WO2021078175A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021078175A1
WO2021078175A1 PCT/CN2020/122624 CN2020122624W WO2021078175A1 WO 2021078175 A1 WO2021078175 A1 WO 2021078175A1 CN 2020122624 W CN2020122624 W CN 2020122624W WO 2021078175 A1 WO2021078175 A1 WO 2021078175A1
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Prior art keywords
auxiliary cathode
electrode
cathode
substrate
display
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PCT/CN2020/122624
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English (en)
French (fr)
Inventor
徐攀
林奕呈
王玲
王国英
韩影
张星
Original Assignee
京东方科技集团股份有限公司
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Priority to EP20879238.2A priority Critical patent/EP4050660A4/en
Priority to US17/297,088 priority patent/US20220037615A1/en
Publication of WO2021078175A1 publication Critical patent/WO2021078175A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • display panels have the advantages of self-luminous, all-solid-state, high contrast, etc., and have become the most promising display panels in recent years.
  • OLED display panels include bottom-emission type and top-emission type, and the top-emission type has a huge advantage due to its high aperture ratio.
  • the top-emission OLED display panel prepared by printing technology has the advantages of long life, high PPI, and less process flow.
  • An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area surrounding the display area, the display area includes: a light-emitting area and a non-light-emitting area, wherein the display substrate includes: a substrate; A first electrode and a first auxiliary cathode arranged in the same layer and spaced apart from each other on the substrate, the first electrode is located in the display area, and the first auxiliary cathode is located in the non-luminous area; A second electrode and a second auxiliary cathode spaced apart from each other are arranged on a side of the first electrode and the first auxiliary electrode away from the substrate, the second electrode is located in the display area, and the second auxiliary cathode Located in the non-emitting area, the orthographic projection of the first auxiliary cathode and the second auxiliary cathode on the substrate is in a mesh structure; the pixel defining layer is located at least in the non-emitting area, the pixel The defining layer is
  • the first auxiliary cathode includes a plurality of first auxiliary cathode wires that are parallel to each other and extend in a first direction
  • the second auxiliary cathode includes a plurality of second auxiliary cathode wires that are parallel to each other and extend in a second direction.
  • the auxiliary cathode line, the first direction and the second direction intersect.
  • the first direction and the second direction are perpendicular.
  • the display substrate further includes a protective layer, the protective layer is located at least in the non-luminous area, and the protective layer is disposed between the first auxiliary cathode and the second auxiliary cathode,
  • the protective layer is provided with a plurality of protective layer via holes in the overlapping area of the plurality of first auxiliary cathode lines and the plurality of second auxiliary cathode lines, and the plurality of first auxiliary cathode lines pass through the plurality of The protective layer via is electrically connected to the plurality of second auxiliary cathode lines.
  • the pixel defining layer includes a plurality of first pixel defining layer openings, and orthographic projections of the plurality of first pixel defining layer openings on the substrate fall into the second auxiliary cathode on the substrate.
  • the cathode is in direct contact with the second auxiliary cathode line through the plurality of first pixel defining layer openings.
  • the first electrode is located in the display area, and the first electrode is located in the source/drain electrode layer; the second electrode is located in the light-emitting area, and the second electrode is an anode.
  • the display substrate further includes: a power line, the power line, the first electrode, and the first auxiliary cathode are arranged in the same layer, and the power line and the first auxiliary cathode are spaced apart from each other .
  • the protective layer includes: an insulating sublayer and a flat sublayer that are sequentially disposed away from the substrate.
  • the display substrate further includes: a power supply electrode disposed on the substrate and located in the non-display area, the power supply electrode is used to supply power to the cathode;
  • the interlayer dielectric layer, the third auxiliary cathode, the isolation layer and the fourth auxiliary cathode, the power supply electrode, the interlayer dielectric layer, the third auxiliary cathode, the isolation layer and the fourth auxiliary cathode are arranged away from the substrate in turn, the The third auxiliary cathode and the fourth auxiliary cathode are both located in the non-display area, the power supply electrode is electrically connected to the transparent electrode through the third auxiliary cathode and the fourth auxiliary cathode, and the third auxiliary cathode is electrically connected to the transparent electrode.
  • the first auxiliary cathode is arranged in the same layer, and the fourth auxiliary cathode and the second auxiliary cathode are arranged in the same layer.
  • the pixel defining layer has a second pixel defining layer opening
  • the orthographic projection of the second pixel defining layer opening on the substrate falls into the fourth auxiliary cathode on the substrate.
  • the isolation layer has an isolation layer via hole penetrating the isolation layer
  • the interlayer dielectric layer has an interlayer dielectric layer via hole penetrating the interlayer dielectric layer
  • the cathode passes through the The opening of the second pixel defining layer is in direct contact with the fourth auxiliary cathode; the fourth auxiliary cathode is electrically connected to the third auxiliary cathode through the isolation layer via hole; the third auxiliary cathode passes through the layer
  • the inter-dielectric layer via is electrically connected to the power supply electrode.
  • the display substrate further includes: a power line, the power line, the first electrode, and the first auxiliary cathode are arranged in the same layer, and the power line and the first auxiliary cathode are spaced apart from each other
  • the power line extends from the display area to the non-display area
  • the power line and the third auxiliary cathode are arranged in the same layer and are spaced apart from each other
  • the power line and the fourth auxiliary cathode are in the The orthographic projections on the substrate do not overlap each other.
  • the display substrate further includes a protective layer, the protective layer is located at least in the non-luminous area, and the protective layer is disposed between the first auxiliary cathode and the second auxiliary cathode;
  • the isolation layer and the protection layer are provided in the same layer.
  • Some embodiments of the present disclosure provide a display panel including the display substrate described in the foregoing embodiments.
  • Some embodiments of the present disclosure provide a method for manufacturing a display substrate, wherein the display substrate is divided into a display area and a non-display area surrounding the display area.
  • the display area includes a light-emitting area and a non-light-emitting area.
  • the preparation method of the display substrate includes: forming a first electrode and a first auxiliary cathode spaced from each other on a substrate through a single patterning process, wherein the first electrode is located in the display area, and the first auxiliary cathode is located in the Non-light-emitting area; a second electrode and a second auxiliary cathode spaced apart from each other are formed by one patterning process, and the second electrode and the second auxiliary cathode are formed on one of the first electrode and the first auxiliary electrode away from the substrate Side, the second electrode is located in the display area, and the second auxiliary cathode is located in the non-luminous area; the projections of the first auxiliary cathode and the second auxiliary cathode on the substrate are in a mesh shape Structure; a pixel defining layer is formed on the side of the second electrode and the second auxiliary cathode away from the substrate, and the pixel defining layer is located at least in the non-light-emitting area; the pixel defining
  • the forming the first electrode and the first auxiliary cathode spaced from each other on the substrate through a single patterning process includes: forming the first electrode and the first auxiliary cathode spaced from each other on the substrate by a printing process.
  • the forming the second electrode and the second auxiliary cathode spaced from each other through a single patterning process includes: forming the second electrode and the second auxiliary cathode spaced from each other through a printing process.
  • FIG. 1 is a schematic diagram of the structure of an OLED display panel provided by related technologies
  • Figure 2 is a schematic diagram showing the area division of the substrate
  • FIG. 3 is a schematic structural diagram of a first auxiliary cathode and a second auxiliary cathode provided by an embodiment of the disclosure
  • Fig. 4 is a schematic cross-sectional view along the CC' direction in Fig. 3 when no transparent cathode is provided;
  • Fig. 5 is a schematic cross-sectional view taken along the CC' direction in Fig. 3 after setting a transparent cathode
  • FIG. 6 is a schematic diagram of a layout structure of a display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a layout structure of a display substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • Fig. 9 is a schematic cross-sectional view taken along the DD' direction in Fig. 8;
  • FIG. 10 is a schematic flowchart of a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • the “upper” and “lower” in the embodiments of the present disclosure are based on the order of forming the layer structure, the layer structure formed first is on the bottom, and the layer structure formed later is on the top.
  • the “first” and “second” in the embodiments of the present disclosure are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • auxiliary cathodes to reduce cathode impedance and meet the voltage drop requirements required for display.
  • the current technology mostly uses a newly added film to set the auxiliary cathode, which undoubtedly increases the complexity of the manufacturing process.
  • the cathode adopts a transparent conductive material.
  • the impedance of the transparent cathode itself is relatively large, which will produce a relatively large voltage drop (IR Drop).
  • IR Drop relatively large voltage drop
  • large-size top-emission OLED display panels often use auxiliary cathodes to reduce cathode impedance and meet the voltage drop requirements required for display.
  • the OLED display panel includes a cover plate and a back plate for the box.
  • the back plate in this document refers to the OLED display substrate.
  • the cover plate includes a cover substrate 101 and a cover substrate 101 formed on the cover substrate.
  • ITO Indium Tin Oxide, for example
  • the backplane includes the backplane substrate 112 and the pixel defining layer 111, the light-emitting layer 110 and the cathode 109 formed on the backplane substrate 112 (of course, the backplane is also formed on the substrate There are anodes, thin film transistors and other structures), the cover plate and the back plate are boxed together by the sealant 107.
  • the auxiliary cathode 105 is designed on the cover substrate 101, and the connecting electrode 106 is overlapped with the cathode 109 to achieve the purpose of reducing the impedance of the cathode.
  • the connecting electrode 106 is overlapped with the cathode 109 to achieve the purpose of reducing the impedance of the cathode.
  • the display substrate is divided into a display area (also called Active Area, AA) 20 and a non-display area 21 surrounding the display area 20.
  • the display area 20 includes : Light-emitting area 201 and non-light-emitting area 202.
  • the above-mentioned display area refers to the area used to realize display; the light-emitting area refers to the area where the OLED unit is arranged.
  • the OLED unit includes an anode (Anode), an organic light-emitting functional layer and a cathode (Cathode); the non-light-emitting area is Refers to the area other than the light-emitting area in the display area.
  • a pixel defining layer and pixel circuit wiring may be provided.
  • the pixel circuit wiring may include gate lines, data lines, and the like.
  • the display substrate includes: a first electrode and a first auxiliary cathode arranged in the same layer and spaced apart on a substrate, the first electrode is located in the display area, and the first auxiliary cathode is located in the non-luminous area; A second electrode and a second auxiliary cathode, the second electrode is located in the display area and disposed on the first electrode, and the second auxiliary cathode is located in the non-luminous area and disposed on the first electrode.
  • the second electrode and the second auxiliary cathode are arranged on the side of the first electrode and the first auxiliary electrode away from the substrate, and the first auxiliary cathode and the second auxiliary cathode
  • the orthographic projection of the cathode on the substrate of the display substrate is in a mesh structure;
  • the pixel defining layer is located in a region other than the light-emitting area, for example, at least in the non-light-emitting area and arranged on the second electrode
  • the second auxiliary cathode the transparent cathode, the transparent cathode covers at least the display area, for example, it can cover the display area and the non-display area, and is arranged on the pixel defining layer; wherein, the transparent cathode and the first auxiliary cathode It is electrically connected to the three second auxiliary cathodes.
  • the above-mentioned arrangement of the first electrode and the first auxiliary cathode in the same layer refers to the use of the same material to form the first electrode and the first auxiliary cathode through a patterning process, and the mutual spacing means that there is a gap between the first electrode and the first auxiliary cathode, and there is no formation. Electrical pathways.
  • the above-mentioned first electrode is an indispensable conductive structure for forming a display substrate. It can be a source and drain, a gate, an anode, etc., or a metal line, such as a gate line, a data line, etc., which is not specifically limited here.
  • the first electrode is located in the display area, that is, the specific area of the first electrode in the display area is not limited, and it needs to be determined according to the specific structure of the first electrode. For example, if the first electrode is a data line located in the source and drain electrode layers, the first electrode may be located in the non-light-emitting area of the display area; if the first electrode is an anode, the first electrode may be located in the light-emitting area of the display area.
  • the above-mentioned first auxiliary cathode is located in the non-light-emitting area, and a pixel defining layer is arranged on it, that is, the first auxiliary cathode is located under the pixel defining layer.
  • the above-mentioned pixel definition layer (PDL) is located in an area other than the light-emitting area, that is, the pixel definition layer is provided with an opening at a position corresponding to the light-emitting area to facilitate the arrangement of the organic light-emitting functional layer.
  • the above-mentioned arrangement of the second electrode and the second auxiliary cathode in the same layer refers to the use of the same material to form the second electrode and the second auxiliary cathode through a patterning process, and the mutual spacing means that there is a gap between the second electrode and the second auxiliary cathode, and there is no formation. Electrical pathways.
  • the above-mentioned second electrode is an indispensable conductive structure for forming a display substrate. It can be a source and drain, a gate, an anode, etc., or a metal line, such as a gate line, a data line, etc., which is not specifically limited here.
  • the above-mentioned second electrode is located in the display area, that is, the specific area of the second electrode in the display area is not limited, and it needs to be determined according to the specific structure of the second electrode. For example, if the second electrode is an anode, the second electrode may be located in the light-emitting area of the display area.
  • the first electrode may be a data line located in the source and drain electrode layer, which may be located in the non-light-emitting area of the display area. If the second electrode is a data line located in the source and drain electrode layers, the second electrode may be located in the non-light-emitting area of the display area. In this case, the first electrode may be a gate line, which may be located in the non-light-emitting area of the display area.
  • the shape and number of the second auxiliary cathodes are not limited here.
  • the transparent cathode, the first auxiliary cathode and the second auxiliary cathode are electrically connected. The specific method of electrical connection is not limited here.
  • first auxiliary cathode and the second auxiliary cathode are not limited here, as long as the projection of the first auxiliary cathode and the second auxiliary cathode on the substrate of the display substrate is a mesh structure.
  • the above-mentioned display substrate also includes other structures or film layers.
  • the above-mentioned display substrate also includes a substrate, and the first electrode and the first auxiliary cathode are formed on the substrate; the above-mentioned display substrate also It may include TFT and so on.
  • TFT time division multiple access
  • the above-mentioned display substrate may also include an anode. If the anode is formed of an opaque material, the display substrate can be used in a top-emission OLED display panel, which is a display panel in which light is emitted from the cathode side. If the anode is formed of a transparent material, the display substrate can be used in an OLED display panel with double-sided display.
  • the double-sided OLED display panel is a display panel in which light is emitted from both sides of the cathode and anode at the same time.
  • the above-mentioned display substrate can also form other types of display panels, which are not limited here.
  • the above-mentioned display substrate can be used as a back plate, and a display panel is formed after being boxed with the cover plate.
  • the supply method of the transparent cathode in the display substrate is not limited here.
  • the above display substrate can be supplied with power to the transparent cathode in a vertical supply mode, or in a left-right supply mode.
  • other supply modes can also be used.
  • the pixel circuit structure and transparent cathode driving mode included in the display substrate are also not limited here.
  • the transparent cathode may adopt a bilateral driving mode or a unilateral driving mode, which is not specifically limited here.
  • each film layer can be formed in a full-printing manner.
  • the embodiment of the present disclosure provides a display substrate.
  • the first auxiliary cathode is located in the non-luminous area, and is arranged in the same layer as the first electrode and spaced apart from each other, so that the first auxiliary cathode can be made at the same time when the first electrode is made.
  • the cathode does not need to add a new film layer;
  • the second auxiliary cathode is located in the non-light-emitting area, and is arranged in the same layer as the second electrode and separated from each other, so that the second auxiliary cathode can be made at the same time when the second electrode is made, and there is no need to add a new layer.
  • the film layer; the transparent cathode, the first auxiliary cathode and the second auxiliary cathode are electrically connected, which can further reduce the impedance of the transparent cathode, thereby reducing the voltage drop more effectively, thereby improving the display effect; the first auxiliary cathode and the second auxiliary cathode
  • the two auxiliary cathodes form a network structure, which can greatly reduce the voltage drop of the transparent cathode, and at the same time greatly reduce the Cross Talk (crosstalk) problem, thereby significantly improving the display effect and improving the product quality.
  • the display substrate provided by the embodiments of the present disclosure can be provided with a first auxiliary cathode and a second auxiliary cathode without adding a new film layer, which can further reduce the impedance of the transparent cathode, thereby more effectively reducing the voltage drop, and further improving The display effect; at the same time, compared with the process in the related technology, the electrode layer in the backplane process is adopted, and there is no new process layer, which greatly reduces the complexity of the manufacturing process and improves the productivity.
  • the above-mentioned display substrate further includes: a protective layer, and the protective layer may be located at least in the non-light-emitting area and arranged between the first auxiliary cathode and the second auxiliary cathode.
  • the first auxiliary cathode 31 includes a plurality of parallel first auxiliary cathode lines 311, the plurality of first auxiliary cathode lines 311 extend in a first direction, and the second auxiliary cathode 32 includes: There are two parallel second auxiliary cathode lines 321, and a plurality of second auxiliary cathode lines 321 extend along the second direction.
  • the first direction and the second direction intersect, for example, perpendicular.
  • the orthographic projections of the first auxiliary cathode 31 and the second auxiliary cathode 32 on the substrate of the display substrate are in a mesh structure (ie Mesh structure).
  • a plurality of parallel first auxiliary cathode lines 311 and a plurality of The projection of the parallel second auxiliary cathode lines 321 on the substrate of the display substrate has a mesh structure.
  • the projections of the plurality of parallel first auxiliary cathode lines and the plurality of parallel second auxiliary cathode lines on the substrate of the display substrate are in a mesh structure, which is simple to manufacture and easy to implement. At the same time, this structure can greatly reduce the voltage drop of the transparent cathode, and at the same time greatly reduce the Cross Talk (crosstalk) problem, thereby significantly improving the display effect and improving the product quality.
  • the protective layer 30 is provided with a protective layer via 37 in the overlapping area corresponding to the first auxiliary cathode line 311 and the second auxiliary cathode line 321, and the first auxiliary cathode line 311 It is electrically connected to the second auxiliary cathode line 321 through the protective layer via 37; as shown in FIG. 4 and FIG.
  • the pixel defining layer 33 is non-overlapping with the first auxiliary cathode line 311 in the second auxiliary cathode line 321
  • the first pixel defining layer opening 330 is arranged in the region, and the orthographic projection of the first pixel defining opening 330 on the substrate falls within the orthographic projection of the second auxiliary cathode on the substrate.
  • the transparent cathode 34 The first pixel defining layer opening 330 directly contacts the second auxiliary cathode line 321.
  • FIG. 6 only rectangular frames are used to indicate the positions of the protective layer via 37 and the first pixel defining layer opening 330 in the schematic plan view.
  • the number and size of the openings of the first pixel defining layer are not limited here, and can be specifically determined according to actual needs.
  • 3 and FIG. 6 both show an example where the pixel defining layer is provided with three first pixel defining layer openings in a region corresponding to the second auxiliary cathode line that does not overlap with the first auxiliary cathode line.
  • FIGS. 3 and 6 both illustrate an example in which the protective layer is provided with a protective layer via hole in an overlapping area corresponding to the second auxiliary cathodic line and the first auxiliary cathodic line.
  • the number and thickness of the protective layer are not limited here.
  • the protective layer includes two sub-layers as an example for drawing.
  • the above structure can realize the electrical connection of the first auxiliary cathode line and the second auxiliary cathode line, the transparent cathode and the second auxiliary cathode line, and further realize the electrical connection of the transparent cathode, the first auxiliary cathode line and the second auxiliary cathode line.
  • the structure design is simple and easy to realize.
  • the first electrode may be a data line located in the source and drain electrode layer; if the second electrode is located in the light-emitting area, the second electrode may be an anode.
  • the thin film transistor includes three electrodes, a source, a drain, and a gate, and the above-mentioned source and drain refer to the source and the drain.
  • the layer where the source and drain are located is generally called the source and drain electrode layer (SD layer).
  • the first auxiliary cathode can be fabricated while the source and drain are being fabricated; while the anode is fabricated, the second auxiliary cathode can be fabricated; thus, the fabrication process can be greatly simplified and the fabrication difficulty can be reduced.
  • the above-mentioned display substrate further includes: a power line (VDD Line) 35 located in the non-light-emitting area; the power line, the first electrode, and the first auxiliary cathode are arranged in the same layer, and the power line 35 is in the same layer as the The first auxiliary cathodes 311 are spaced apart from each other. If the first auxiliary cathode and the power line are short-circuited, it will cause the display panel including the display substrate to fail to light up, and even more seriously, it will burn the screen. Therefore, the first auxiliary cathodes of the power line are arranged on the same layer and spaced apart from each other. As shown in FIG.
  • FIG. 7 is a layout design diagram, which only exemplarily depicts a schematic diagram of the structure of a display substrate.
  • Each pixel unit (including three sub-pixels R, G, B) in FIG. 7 is provided by a power line 35 Drive, of course, can also be other drive methods in practice, so I won’t go into details here.
  • the first auxiliary cathode lines are all arranged along the OB direction, that is, the first direction
  • the second auxiliary cathode lines are all arranged along the OA direction, that is, the second direction.
  • the protective layer 30 includes an insulating sublayer (for example, a PVX layer) 302 and a flat sublayer (for example, a Resin layer) 301 on the insulating sublayer 302.
  • the material of the flat sub-layer may be an organic material, and the thickness of the flat sub-layer may be set to be thicker; the material of the insulating sub-layer may be an inorganic material.
  • a flat sub-layer and an insulating sub-layer are arranged in the middle, which can effectively isolate the power line and the second auxiliary cathode to ensure that there is no short circuit between the two, thereby further improving the inclusion of the The yield rate of the display panel of the display substrate.
  • the above-mentioned display substrate further includes: a power supply electrode 41 disposed on the substrate 10 and located in a non-display area, and the power supply electrode 41 is used to supply power to the transparent cathode 34.
  • the Inter Level Dielectric (ILD) 42, the third auxiliary cathode 43, the isolation layer 40, and the fourth auxiliary cathode 44 are arranged on the power supply electrode 41.
  • the third auxiliary cathode 43 and the fourth auxiliary cathode 44 are all located In the non-display area 21, it can be understood that the power supply electrode 41, the interlayer dielectric layer 42, the third auxiliary cathode 43, the isolation layer 40 and the fourth auxiliary cathode 44 are arranged away from the substrate 10 in sequence.
  • the pixel defining layer 33 has a second pixel defining layer opening 331, and the orthographic projection of the second pixel defining layer opening 331 on the substrate 10 falls into the fourth auxiliary cathode 44 on the substrate 10.
  • the isolation layer 40 has an isolation layer via 403 penetrating the isolation layer 40
  • the interlayer dielectric layer 42 has an interlayer dielectric layer via 421 penetrating the interlayer dielectric layer.
  • the transparent cathode 34 directly contacts the fourth auxiliary cathode 44 through the second pixel defining layer opening 331 of the pixel defining layer 33; the fourth auxiliary cathode 44 is electrically connected to the third auxiliary cathode 43 through the isolation layer via 403 of the isolation layer 40 The third auxiliary cathode 43 is electrically connected to the power supply electrode 41 through the interlayer dielectric layer via 421 of the interlayer dielectric layer 42.
  • the third auxiliary cathode and the first auxiliary cathode are arranged in the same layer and spaced apart from each other, and the fourth auxiliary cathode and the second auxiliary cathode are arranged in the same layer and spaced apart from each other.
  • the above-mentioned power supply electrode can be provided in the same layer as the gate line of the display area, or of course, can also be provided in the same layer as other conductive film layers.
  • the power supply electrode can be electrically connected to the external power supply structure (Vss Power) 38 shown in FIG. Power is supplied to the transparent cathode.
  • the external power supply structure 38 can be a cathode power supply chip or a power supply, of course, it can also be other structures, which will not be listed here.
  • the above-mentioned arrangement of the third auxiliary cathode and the first auxiliary cathode in the same layer refers to the use of the same material to form the third auxiliary cathode and the first auxiliary cathode through a patterning process.
  • the above-mentioned arrangement of the fourth auxiliary cathode and the second auxiliary cathode in the same layer refers to the use of the same material to form the fourth auxiliary cathode and the second auxiliary cathode through one patterning process.
  • the isolation layer 40 may include a first isolation sublayer 401 and a second isolation sublayer 402.
  • the first isolation sublayer may be a flat sublayer of the protection layer.
  • the layers are arranged in the same layer, and the second isolation sub-layer can be arranged in the same layer as the insulating sub-layer of the protective layer, which can reduce the manufacturing process steps and save the cost.
  • FIG. 9 shows an example in which the isolation layer 40 includes a first isolation sub-layer 401 and a second isolation sub-layer 402.
  • the transparent cathode, the fourth auxiliary cathode, the third auxiliary cathode, and the power supply electrode are electrically connected, and power can be supplied to the transparent cathode through the power supply electrode.
  • the third auxiliary cathode and the first auxiliary cathode are arranged in the same layer
  • the fourth auxiliary cathode and the second auxiliary cathode are arranged in the same layer, and no additional film layer is required, which reduces the manufacturing cost.
  • the above-mentioned display substrate further includes a power line located in the non-luminous area; the power line, the first electrode and the first auxiliary cathode are arranged in the same layer, and the power line and the first electrode are all arranged spaced apart from the first auxiliary cathode.
  • the power line extends to the non-display area, and is arranged on the same layer as the third auxiliary cathode and spaced apart from each other.
  • the orthographic projections of the power line and the fourth auxiliary cathode on the substrate of the display substrate do not overlap each other.
  • the third auxiliary cathode and the first auxiliary cathode are arranged in the same layer and spaced apart from each other, and the power line, the first auxiliary cathode and the third auxiliary cathode are all arranged in the same layer and spaced apart from each other. In this way, in the non-display area, there is no crossover or overlap between the third auxiliary cathode and the power line, which can prevent the two from being short-circuited.
  • the orthographic projections of the power line and the fourth auxiliary cathode on the substrate of the display substrate do not overlap each other.
  • Some embodiments of the present disclosure provide a display panel including the display substrate provided in the foregoing embodiments.
  • the display panel may also include a cover plate.
  • the cover plate and the above-mentioned display substrate are combined to form an OLED display panel.
  • the display substrate can also be referred to as a back plate.
  • the display substrate included in the display panel can be provided with auxiliary cathodes without adding a new film layer, thereby reducing the complexity of the manufacturing process and improving the productivity.
  • the display panel may be a display device such as an OLED display and any product or component with a display function, such as a TV, a digital camera, a mobile phone, a tablet computer, and the like including these display devices.
  • the display panel can be a large-size Monitor (display) or TV (television) series.
  • Some embodiments of the present disclosure provide a method for preparing a display substrate.
  • the display substrate is divided into a display area (also called Active Area, AA) 20 and a non-display area 21 surrounding the display area 20.
  • the area 20 includes: a light-emitting area 201 and a non-light-emitting area 202; as shown in FIG. 10, the preparation method of the display substrate includes:
  • the specific process method used in the patterning process is not limited, and as an example, it can be formed by a printing process.
  • S02. Form a second electrode and a second auxiliary cathode spaced from each other through a patterning process; the second electrode is located in the display area and formed on the first electrode, and the second auxiliary cathode is located in the non-light emitting area and is formed in the first auxiliary cathode.
  • the second electrode and the second auxiliary cathode are formed on the side of the first electrode and the first auxiliary electrode away from the substrate, and the first auxiliary cathode and the second auxiliary cathode are on the display substrate.
  • the projection on the substrate is a mesh structure.
  • a pixel defining layer is formed on the second electrode and the second auxiliary cathode.
  • the pixel defining layer is located in an area other than the light-emitting area, for example, the pixel defining layer is located at least in the non-light-emitting area.
  • a transparent cathode is formed on the pixel defining layer.
  • the transparent cathode covers at least the display area, such as covering the display area and the non-display area; wherein the transparent cathode, the first auxiliary cathode and the second auxiliary cathode are electrically connected.
  • the specific formation methods of the first electrode, the first auxiliary cathode, the second electrode, the second auxiliary cathode, the pixel defining layer, and the transparent cathode are not limited, and can be determined according to actual conditions.
  • the first electrode, the first auxiliary cathode, the second electrode, the second auxiliary cathode, the pixel defining layer, and the transparent cathode can all be formed by a printing process, that is, the display substrate can be produced by a full printing process.
  • the display substrate produced by the full printing process has the advantages of long life, high PPI, and less process flow.
  • the above-mentioned display area refers to the area used to realize display; the light-emitting area refers to the area where the OLED unit is arranged.
  • the OLED unit includes an anode (Anode), an organic light-emitting functional layer and a cathode (Cathode); the non-light-emitting area is Refers to the area other than the light-emitting area in the display area.
  • a pixel defining layer and a pixel circuit unit may be provided.
  • the pixel circuit unit may include a TFT (Thin Film Transistor, thin film transistor), a gate line, a data line, and the like.
  • the above-mentioned first electrode is an indispensable conductive structure for forming a display substrate. It can be a source and drain, a gate, an anode, etc., or a metal line, such as a gate line, a data line, etc., which is not specifically limited here.
  • the first electrode is located in the display area, that is, the specific area of the first electrode in the display area is not limited, and it needs to be determined according to the specific structure of the first electrode. For example, if the first electrode is a data line located in the source and drain electrode layers, the first electrode may be located in the non-light-emitting area of the display area; if the first electrode is an anode, the first electrode may be located in the light-emitting area of the display area.
  • the above-mentioned transparent cathode, the first auxiliary cathode and the second auxiliary cathode are electrically connected.
  • the specific method of electrical connection is not limited here.
  • the material of the above-mentioned transparent cathode may be a magnesium-silver alloy, of course, it may also be other materials, as long as it has transparent and conductive properties.
  • the above-mentioned second electrode is an indispensable conductive structure for forming a display substrate. It can be a source and drain, a gate, an anode, etc., or a metal line, such as a gate line, a data line, etc., which is not specifically limited here.
  • the above-mentioned second electrode is located in the display area, that is, the specific area of the second electrode in the display area is not limited, and it needs to be determined according to the specific structure of the second electrode. For example, if the second electrode is an anode, the second electrode may be located in the light-emitting area of the display area.
  • the first electrode may be a data line located in the source and drain electrode layer, which may be located in the non-light-emitting area of the display area. If the second electrode is a data line located in the source and drain electrode layers, the second electrode may be located in the non-light-emitting area of the display area. In this case, the first electrode may be a gate line, which may be located in the non-light-emitting area of the display area.
  • the embodiment of the present disclosure provides a method for preparing a display substrate.
  • a first electrode and a first auxiliary cathode spaced apart from each other are formed on a substrate through a patterning process, and a first electrode and a first auxiliary cathode are formed on the substrate through a patterning process.
  • the second electrode and the second auxiliary cathode spaced apart from each other are formed on the bottom, without changing the existing process flow, thereby reducing the complexity of the manufacturing process and improving the productivity.
  • the display substrate formed by the preparation method can be provided with an auxiliary cathode without adding a new film layer, thereby simplifying the design of the auxiliary cathode and reducing the manufacturing difficulty.
  • S01 forming the first electrode and the first auxiliary cathode spaced apart on the substrate through a single patterning process includes:
  • a first electrode and a first auxiliary cathode spaced apart from each other are formed on the substrate through a printing process, the first electrode is located in the display area, and the first auxiliary cathode is located in the non-light emitting area.
  • the first electrode and the first auxiliary cathode are formed by the printing process, the process is simple, and the operability is strong.
  • S02 forming a second electrode and a second auxiliary cathode spaced from each other through a single patterning process includes:
  • the second electrode and the second auxiliary cathode spaced apart from each other are formed through a printing process.
  • the above-mentioned formation of the second electrode and the second auxiliary cathode through the printing process has a simple process and strong operability.

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Abstract

一种显示基板及其制备方法、显示面板，所述显示基板，包括显示区和围绕所述显示区的非显示区，所述显示区包括：发光区和非发光区，其中，所述显示基板包括：衬底；位于所述衬底上的同层设置且相互间隔的第一电极和第一辅助阴极，所述第一电极位于所述显示区，所述第一辅助阴极位于所述非发光区；同层设置且相互间隔的第二电极和第二辅助阴极，设置在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第二电极位于所述显示区，所述第二辅助阴极位于所述非发光区，所述第一辅助阴极和所述第二辅助阴极在所述衬底上的正投影呈网状结构；像素界定层，至少位于所述非发光区中，所述像素界定层设置在所述第二电极和所述第二辅助阴极远离所述衬底的一侧；阴极，所述阴极至少覆盖所述显示区，所述阴极设置在所述像素界定层远离所述衬底的一侧；其中，所述阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。

Description

显示基板及其制备方法、显示面板
相关申请的交叉引用
本申请要求2019年10月24日提交中国专利局的专利申请201911019818.7的优先权，其全部内容通过引用合并于本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示面板。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板具有自发光、全固态、高对比度等优点，成为近年来最具潜力的显示面板。
OLED显示面板包括底发射型和顶发射型，顶发射型由于具有高开口率而有着巨大的优势。采用打印技术制备的顶发射OLED显示面板具有高寿命，高PPI，工艺流程少等优点。
公开内容
本公开的实施例提供一种显示基板，包括显示区和围绕所述显示区的非显示区，所述显示区包括：发光区和非发光区，其中，所述显示基板包括：衬底；位于所述衬底上的同层设置且相互间隔的第一电极和第一辅助阴极，所述第一电极位于所述显示区，所述第一辅助阴极位于所述非发光区；同层设置且相互间隔的第二电极和第二辅助阴极，设置在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第二电极位于所述显示区，所述第二辅助阴极位于所述非发光区，所述第一辅助阴极和所述第二辅助阴极在所述衬底上的正投影呈网状结构；像素界定层，至少位于所述非发光区中，所述像素界定层设置在所述第二电极和所述第二辅助阴极远离所述衬底的一侧；阴极，所述阴极至少覆盖所述显示区，所述阴极设置在所述像素界定层远离所述衬底的一侧；其中，所述阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。
在一些实施例中，所述第一辅助阴极包括多条相互平行且沿第一方向延伸的第一辅助阴极线，所述第二辅助阴极包括多条相互平行且沿第二方向延伸的第二辅助阴极线，所述第一方向和第二方向相交。
在一些实施例中，所述第一方向和第二方向垂直。
在一些实施例中，所述显示基板还包括：保护层，所述保护层至少位于所述非发光区，所述保护层设置在所述第一辅助阴极和所述第二辅助阴极之间，所述保护层在所述多条第一辅助阴极线和所述多条第二辅助阴极线的交叠区域设置多个保护层过孔，所述多条第一辅助阴极线通过所述多个保护层过孔与所述多条第二辅助阴极线电连接。
在一些实施例中，所述像素界定层包括多个第一像素界定层开口，所述多个第一像素界定层开口在衬底上的正投影落入所述第二辅助阴极在衬底上的正投影内，所述阴极通过所述多个第一像素界定层开口与所述第二辅助阴极线直接接触。
在一些实施例中，所述第一电极位于所述显示区，所述第一电极位于源漏电极层中；所述第二电极位于所述发光区，所述第二电极为阳极。
在一些实施例中，所述显示基板还包括：电源线，所述电源线、所述第一电极和所述第一辅助阴极同层设置，所述电源线与所述第一辅助阴极相互间隔。
在一些实施例中，所述保护层包括：依次远离所述衬底设置的绝缘子层和平坦子层。
在一些实施例中，所述显示基板还包括：设置在衬底上且位于所述非显示区的供电电极，所述供电电极用于向所述阴极供电；设置在所述供电电极之上的层间介质层、第三辅助阴极、隔离层和第四辅助阴极，所述供电电极、层间介质层、第三辅助阴极、隔离层和第四辅助阴极依次远离所述衬底设置，所述第三辅助阴极和所述第四辅助阴极均位于所述非显示区，所述供电电极通过第三辅助阴极、第四辅助阴极与所述透明电极电连接，所述第三辅助阴极与所述第一辅助阴极同层设置，所述第四辅助阴极与所述第二辅助阴极同层设置。
在一些实施例中，所述像素界定层具有第二像素界定层开口，所述第二像素界定层开口在所述衬底上的正投影落入所述第四辅助阴极在所述衬底上的正投影内，所述隔离层具有穿透所述隔离层的隔离层过孔，所述层间介质层具有穿透所述层间介质层的层间介质层过孔，所述阴极通过所述第二像素界定层开口与所述第四辅助阴极直接接触；所述第四辅助阴极通过所述隔离层过孔与所述第三辅助阴极电连接；所述第三辅助阴极通过所述层间介质层过孔与所述供电电极电连接。
在一些实施例中，所述显示基板还包括：电源线，所述电源线、所述第一电 极和所述第一辅助阴极同层设置，所述电源线与所述第一辅助阴极相互间隔；所述电源线自所述显示区延伸至所述非显示区，所述电源线与所述第三辅助阴极同层设置且相互间隔，所述电源线与所述第四辅助阴极在所述衬底上的正投影互不交叠。
在一些实施例中，所述显示基板还包括：保护层，所述保护层至少位于所述非发光区，所述保护层设置在所述第一辅助阴极和所述第二辅助阴极之间；所述隔离层与所述保护层同层设置。
本公开一些实施例提供一种显示面板，包括前述实施例所述的显示基板。
本公开一些实施例提供一种显示基板的制备方法，其中，所述显示基板划分为显示区和围绕所述显示区的非显示区，所述显示区包括：发光区和非发光区，所述显示基板的制备方法包括：通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极，其中，所述第一电极位于所述显示区，所述第一辅助阴极位于所述非发光区；通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极，所述第二电极和第二辅助阴极形成在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第二电极位于所述显示区，所述第二辅助阴极位于所述非发光区；所述第一辅助阴极和所述第二辅助阴极在所述衬底上的投影呈网状结构；在所述第二电极和所述第二辅助阴极远离所述衬底一侧形成像素界定层，所述像素界定层至少位于所述非发光区中；在所述像素界定层远离所述衬底一侧形成阴极，所述阴极至少覆盖所述显示区，其中，所述阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。
在一些实施例中，所述通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极包括：通过打印工艺在衬底上形成相互间隔的第一电极和第一辅助阴极。
在一些实施例中，所述通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极包括：通过打印工艺形成相互间隔的第二电极和第二辅助阴极。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种OLED显示面板结构示意图；
图2为显示基板的区域划分示意图；
图3为本公开实施例提供的第一辅助阴极和第二辅助阴极的结构示意图；
图4为未设置透明阴极时沿图3中CC’方向的剖面示意图；
图5为设置透明阴极后沿图3中CC’方向的剖面示意图；
图6为本公开实施例提供的一种显示基板的版图结构示意图；
图7为本公开实施例提供的一种显示基板的版图结构示意图；
图8为本公开实施例提供的一种显示基板的结构示意图；
图9为沿图8中DD’方向的剖面示意图；
图10为本公开实施例提供的一种显示基板的制备方法的流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本公开实施例中所述“上”、“下”以形成层结构的顺序为依据，在先形成的层结构即在下，在后形成的层结构即在上。本公开实施例中所述“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
目前，打印顶发射OLED显示面板技术正逐渐成为开发OLED显示面板的主流。全打印技术是打印OLED显示面板的技术之一，主要面向大尺寸的Monitor(显示器)或者TV(电视)系列。该技术是指OLED显示面板的所有层都通过打印方式完成，EL(Emitting layer，发光层)只存在于发光区域。
大尺寸的顶发射OLED显示面板多采用辅助阴极，以降低阴极阻抗，满足显示所需的压降要求。但是，目前的技术多采用新增膜层来设置辅助阴极，这样无疑增加了制作工艺的复杂性。
顶发射OLED显示面板中，阴极采用透明导电材料。当电流流经阴极时，由于透明阴极本身的阻抗比较大，因而会产生比较大的压降(IR Drop)。而且，随着显示面板尺寸的增加，阴极的电压降显著增加，从而导致显示的亮度不均匀。因此，大尺寸的顶发射OLED显示面板多采用辅助阴极，以降低阴极阻抗，满足 显示所需的压降要求。
在相关技术中，OLED显示面板包括对盒的盖板和背板，本文中的背板指的是OLED显示基板，参考图1所示，盖板包括盖板衬底101以及形成在盖板衬底101上的黑矩阵102、彩膜层103、平坦层104、辅助阴极105、连接电极106、隔垫物113和填充层108等膜层，其中，连接电极106例如采用ITO(IndiumTin Oxide，氧化铟锡)材料；背板包括背板的衬底112以及形成在背板的衬底112上的像素界定层111、发光层110和阴极109等膜层(当然，背板的衬底上还形成有阳极、薄膜晶体管等其它结构)，盖板和背板通过框胶107对盒在一起。
辅助阴极105设计在盖板衬底101上，通过连接电极106与阴极109搭接，实现降低阴极阻抗的目的。但是，在盖板衬底101上制作辅助阴极105，需要新增层别，从而增加了工艺的复杂性；同时搭接的方式对OLED显示面板容易造成比较大的损伤，从而提高了制作难度。
本公开一些实施例提供了一种显示基板，参考图2所示，该显示基板划分为显示区(亦称为Active Area，AA)20和围绕显示区20的非显示区21，显示区20包括：发光区201和非发光区202。
上述显示区是指用于实现显示的区域；发光区是指设置有OLED单元的区域，根据相关技术可知，OLED单元包括阳极(Anode)、有机发光功能层和阴极(Cathode)；非发光区是指显示区中除发光区以外的区域，在该区域，可以设置像素界定层、像素电路布线，该像素电路布线可以包括栅线、数据线等。
该显示基板包括：设置在衬底上的同层设置且相互间隔的第一电极和第一辅助阴极，第一电极位于显示区，第一辅助阴极位于非发光区；同层设置且相互间隔的第二电极和第二辅助阴极，所述第二电极位于所述显示区，且设置在所述第一电极之上，所述第二辅助阴极位于所述非发光区，且设置在所述第一辅助阴极之上，可以理解为第二电极和第二辅助阴极设置在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第一辅助阴极和所述第二辅助阴极在所述显示基板的衬底上的正投影呈网状结构；像素界定层，像素界定层位于除发光区之外的区域，例如至少位于所述非发光区中，且设置在第二电极和第二辅助阴极之上；透明阴极，透明阴极至少覆盖显示区，例如可以覆盖显示区和非显示区，且设置在像素界定层之上；其中，所述透明阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。
上述第一电极和第一辅助阴极同层设置是指采用相同材料通过一次构图工艺形成第一电极和第一辅助阴极，相互间隔是指第一电极和第一辅助阴极之间存在间隔，没有形成电通路。
上述第一电极是形成显示基板必不可少的导电结构。其可以是源漏极、栅极、阳极等，还可以是金属线，例如栅线、数据线等，这里具体不限定。第一电极位于显示区，即不限定第一电极在显示区的具体区域，需要根据第一电极的具体结构而定。示例的，若第一电极是位于源漏电极层的数据线，则第一电极可以位于显示区的非发光区；若第一电极是阳极，则第一电极可以位于显示区的发光区。
上述第一辅助阴极位于非发光区，其上设置有像素界定层，即第一辅助阴极位于像素界定层的下方。这里对于第一辅助阴极的形状、数量均不做限定。上述像素界定层(Pixel Definition Layer，PDL)位于除发光区之外的区域，即像素界定层在对应于发光区的位置设置有开口，以利于设置有机发光功能层。
上述第二电极和第二辅助阴极同层设置是指采用相同材料通过一次构图工艺形成第二电极和第二辅助阴极，相互间隔是指第二电极和第二辅助阴极之间存在间隔，没有形成电通路。
上述第二电极是形成显示基板必不可少的导电结构。其可以是源漏极、栅极、阳极等，还可以是金属线，例如栅线、数据线等，这里具体不限定。上述第二电极位于显示区，即不限定第二电极在显示区的具体区域，需要根据第二电极的具体结构而定。示例的，若第二电极是阳极，则第二电极可以位于显示区的发光区，此时，第一电极可以是位于源漏电极层的数据线，其可以位于显示区的非发光区。若第二电极是位于源漏电极层的数据线，则第二电极可以位于显示区的非发光区，此时，第一电极可以是栅线，其可以位于显示区的非发光区。
需要说明的是，这里对第二辅助阴极的形状、数量均不做限定。另外，透明阴极、第一辅助阴极和第二辅助阴极三者实现电连接。这里对于电连接的具体方式不做限定。
这里对于第一辅助阴极和第二辅助阴极的具体结构不做限定，只要满足第一辅助阴极和第二辅助阴极在显示基板的衬底上的投影呈网状结构即可。
当然，上述显示基板还包括其它结构或者膜层，示例的，与相关技术类似的，上述显示基板还包括衬底，第一电极和第一辅助阴极形成在该衬底之上；上述显示基板还可以包括TFT等。这里仅描述与发明点相关的结构或者膜层，本领域技 术人员可以通过相关技术和公知常识获知显示基板包括的其它结构或者膜层。
上述显示基板还可以包括阳极，若阳极为不透明材料形成，则该显示基板可用于顶发射型的OLED显示面板中，顶发射型的OLED显示面板即光线从阴极侧射出的显示面板。若阳极为透明材料形成，则该显示基板可用于双面显示的OLED显示面板中，双面显示的OLED显示面板即光线从阴极和阳极两侧同时射出的显示面板。当然，上述显示基板还可以形成其它类型的显示面板，这里不做限定。
上述显示基板可以作为背板，与盖板对盒后形成显示面板。这里对于该显示基板中透明阴极的供给方式不做限定，示例的，上述显示基板可以采用上下供给方式给透明阴极供电，也可以采用左右供给方式给透明阴极供电，当然还可以采用其它供给方式。这里对于显示基板中包括的像素电路结构和透明阴极驱动方式也不做限定，示例的，透明阴极可以采用双边驱动方式，或者单边驱动方式，这里不做具体限定。
这里对于上述显示基板的制作方法不做限定。示例的，可以采用全打印的方式形成各膜层。
本公开的实施例提供了一种显示基板，该显示基板中，第一辅助阴极位于非发光区，与第一电极同层设置且相互间隔，这样在制作第一电极时可同时制作第一辅助阴极，不需要新增膜层；第二辅助阴极位于非发光区，与第二电极同层设置且相互间隔，这样在制作第二电极时可同时制作第二辅助阴极，同样也不需要新增膜层；透明阴极、第一辅助阴极和第二辅助阴极三者实现电连接，可以更多地降低透明阴极的阻抗，从而更有效地降低压降，进而提升显示效果；第一辅助阴极和第二辅助阴极形成网状结构，可以极大降低透明阴极的压降，同时极大减轻Cross Talk(串扰)问题，从而显著提高了显示效果，提升了产品质量。即本公开实施例提供的显示基板能够在不新增膜层的前提下设置第一辅助阴极和第二辅助阴极，可以更进一步降低透明阴极阻抗，从而更有效地降低压降，进而更进一步提升显示效果；同时，跟相关技术中的工艺相比，采用背板工艺中的电极层别，没有新增工艺层别，极大降低了制作工艺的复杂性，提高了生产率。
进一步可选的，上述显示基板还包括：保护层，保护层可以至少位于非发光区，且设置在第一辅助阴极和第二辅助阴极之间。
可选的，参考图3所示，第一辅助阴极31包括：多条平行的第一辅助阴极线311，多条第一辅助阴极线311沿第一方向延伸，第二辅助阴极32包括：多条 平行的第二辅助阴极线321，多条第二辅助阴极线321沿第二方向延伸。第一方向与第二方向相交，例如为垂直。第一辅助阴极31和第二辅助阴极32在显示基板的衬底上的正投影呈网状结构(即Mesh结构)，参考图8所示，多条平行的第一辅助阴极线311和多条平行的第二辅助阴极线321在显示基板的衬底上的投影呈网状结构。
多条平行的第一辅助阴极线和多条平行的第二辅助阴极线在显示基板的衬底上的投影呈网状结构，该结构制作简单，容易实现。同时，该种结构可以极大降低透明阴极的压降，同时极大减轻Cross Talk(串扰)问题，从而显著提高了显示效果，提升了产品质量。
进一步可选的，参考图5和图6所示，保护层30在对应于第一辅助阴极线311和第二辅助阴极线321的交叠区域设置保护层过孔37，第一辅助阴极线311通过保护层过孔37与第二辅助阴极线321电连接；参考图4和图6所示，像素界定层33在对应于第二辅助阴极线321中与第一辅助阴极线311非交叠的区域设置的第一像素界定层开口330，第一像素界定开口330在衬底上的正投影落入所述第二辅助阴极在衬底上的正投影内，参考图5所示，透明阴极34通过第一像素界定层开口330与第二辅助阴极线321直接接触。本领域技术人员可以理解的是，在图6中仅仅采用矩形框来表示保护层过孔37和第一像素界定层开口330在平面示意图中的位置。
这里对于第一像素界定层开口的数量、大小均不作限定，具体可以根据实际需要确定。图3和图6均以像素界定层在对应于第二辅助阴极线中与第一辅助阴极线非交叠的区域设置三个第一像素界定层开口为例进行绘示。
这里对于保护层过孔的数量、大小均不作限定，具体可以根据实际需要确定。图3和图6均以保护层在对应于第二辅助阴极线中与第一辅助阴极线的一个交叠区域设置一个保护层过孔为例进行绘示。
另外，这里对于保护层的层数和厚度不做限定，图4和图5中，均以保护层包括两个子层为例进行绘示。
上述结构可以实现第一辅助阴极线和第二辅助阴极线电连接、透明阴极与第二辅助阴极线电连接，进而实现透明阴极、第一辅助阴极线和第二辅助阴极线三者电连接。该结构设计简单，容易实现。
可选的，若第一电极位于非发光区，第一电极可以为位于源漏电极层中的数 据线；若第二电极位于发光区，第二电极可以为阳极。
需要说明的是，薄膜晶体管包括源极、漏极和栅极三个电极，上述源漏极是指源极和漏极。一般将源漏极所在层称为源漏电极层(SD层)。
这样，在制作源漏极的同时，可以制作第一辅助阴极；在制作阳极的同时，可以制作第二辅助阴极；从而可以极大地简化制作工艺，降低制作难度。
进一步可选的，参考图7所示，上述显示基板还包括：位于非发光区的电源线(VDD Line)35；电源线、第一电极和第一辅助阴极同层设置，且电源线35与第一辅助阴极311相互间隔。若第一辅助阴极与电源线出现短路，会造成包括该显示基板的显示面板无法点亮的情况，更严重的会烧坏屏幕，因此，将电源线第一辅助阴极同层设置且相互间隔，参考图7所示，第一辅助阴极线311与电源线35平行设置且相距较远，这样可以基本杜绝第一辅助阴极和电源线出现短路的情况，从而极大提高了包括该显示基板的显示面板的良率。需要说明的是，图7是版图设计图，仅示例性地绘示出一种显示基板的结构示意图，图7中每一个像素单元(包括三个子像素R、G、B)由一条电源线35驱动，当然实际中还可以是其它驱动方式，这里不再赘述。另外，本公开设置有辅助阴极的附图中，第一辅助阴极线均是沿OB方向，即第一方向设置，第二辅助阴极线均是沿OA方向，即第二方向设置。
可选的，参考图5所示，保护层30包括：绝缘子层(例如为PVX层)302和位于绝缘子层302之上的平坦子层(例如为Resin层)301。该平坦子层的材料可以是有机材料，平坦子层的厚度可以设置地较厚；该绝缘子层的材料可以是无机材料。这样，电源线与第二辅助阴极出现交叠的区域中，中间设置有平坦子层和绝缘子层，可以有效隔离电源线与第二辅助阴极，确保两者不发生短路，从而更进一步提高包括该显示基板的显示面板的良率。
可选的，参考图9所示，上述显示基板还包括：设置在衬底10上位于非显示区的供电电极41，供电电极41用于向透明阴极34供电。
设置在供电电极41之上的层间介质层(Inter Level Dielectric，ILD)42、第三辅助阴极43、隔离层40和第四辅助阴极44，第三辅助阴极43和第四辅助阴极44均位于非显示区21中，可以理解为供电电极41、层间介质层42、第三辅助阴极43、隔离层40和第四辅助阴极44依次远离衬底10设置。
所述像素界定层33具有第二像素界定层开口331，所述第二像素界定层开口 331在所述衬底10上的正投影落入所述第四辅助阴极44在所述衬底10上的正投影内，所述隔离层40具有穿透所述隔离层40的隔离层过孔403，所述层间介质层42具有穿透所述层间介质层的层间介质层过孔421。
其中，透明阴极34通过像素界定层33的第二像素界定层开口331与第四辅助阴极44直接接触；第四辅助阴极44通过隔离层40的隔离层过孔403与第三辅助阴极43电连接；第三辅助阴极43通过层间介质层42的层间介质层过孔421与供电电极41电连接。
第三辅助阴极与第一辅助阴极同层设置且相互间隔，第四辅助阴极与第二辅助阴极同层设置且相互间隔。
上述供电电极可以是与显示区的栅线同层设置，当然也可以与其它导电膜层同层设置，该供电电极可以与图8所示的外部供电结构(Vss Power)38电连接，用于向透明阴极供电。该外部供电结构38可以是阴极供电芯片或者电源，当然还可以是其它结构，这里不再列举。
上述第三辅助阴极与第一辅助阴极同层设置是指采用相同材料通过一次构图工艺形成第三辅助阴极与第一辅助阴极。
上述第四辅助阴极与第二辅助阴极同层设置是指采用相同材料通过一次构图工艺形成第四辅助阴极与第二辅助阴极。
上述隔离层可以是和保护层同层设置，参考图9所示，隔离层40可以包括第一隔离子层401和第二隔离子层402，第一隔离子层可以是和保护层的平坦子层同层设置，第二隔离子层可以是和保护层的绝缘子层同层设置，这样可以减少制作工艺步骤，节约成本。图9是以隔离层40包括第一隔离子层401和第二隔离子层402为例进行绘示。
这样，在非显示区，透明阴极、第四辅助阴极、第三辅助阴极、供电电极四者实现电连接，进而可以通过供电电极向透明阴极供电。该透明阴极的供电结构中，第三辅助阴极与第一辅助阴极同层设置，第四辅助阴极与第二辅助阴极同层设置，不用额外设置新的膜层，降低了制作成本。
进一步的，上述显示基板还包括位于非发光区的电源线；电源线、第一电极和第一辅助阴极同层设置，且电源线、第一电极均与第一辅助阴极间隔设置。该电源线延伸至非显示区，且与第三辅助阴极同层设置且相互间隔。电源线与第四辅助阴极在显示基板的衬底上的正投影互不交叠。
一方面，由于第三辅助阴极与第一辅助阴极同层设置且相互间隔，且电源线、第一辅助阴极和第三辅助阴极均同层设置，且相互间隔。这样，在非显示区内，第三辅助阴极和电源线不存在跨接或者交叠，可以避免两者发生短路。另一方面，电源线与第四辅助阴极在显示基板的衬底上的正投影互不交叠。这样，在非显示区内，第四辅助阴极和电源线也不存在跨接或者交叠，可以避免两者发生短路。那么，在非显示区内，第三辅助阴极、第四辅助阴极分别与电源线不存在跨接或者交叠，从而避免短路发生，更有效地避免不良的发生，进而保证面板的良率。
本公开一些实施例提供了一种显示面板，该显示面板包括前述实施例提供的显示基板。
该显示面板还可以包括盖板。盖板与上述显示基板对盒后形成OLED显示面板，此时，显示基板还可称为背板。该显示面板包括的显示基板能够在不新增膜层的前提下设置辅助阴极，从而降低了制作工艺的复杂性，提高了生产率。该显示面板可以是OLED显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。该显示面板可以是大尺寸的Monitor(显示器)或者TV(电视)系列。
本公开实施例一些提供了一种显示基板的制备方法，参考图1所示，该显示基板划分为显示区(亦称为Active Area，AA)20和围绕显示区20的非显示区21，显示区20包括：发光区201和非发光区202；参考图10所示，该显示基板的制备方法包括：
S01、通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极，其中，第一电极位于显示区，第一辅助阴极位于非发光区。
这里对于构图工艺具体采用的工艺方法不做限定，示例的，可以采用打印工艺形成。
S02、通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极；第二电极位于显示区，且形成在第一电极之上，第二辅助阴极位于非发光区，且形成在第一辅助阴极之上，可以理解为所述第二电极和第二辅助阴极形成在所述第一电极和第一辅助电极远离所述衬底的一侧，第一辅助阴极和第二辅助阴极在显示基板的衬底上的投影呈网状结构。
S03、在第二电极和第二辅助阴极之上形成像素界定层，像素界定层位于除发光区之外的区域，例如像素界定层至少位于非发光区中。
S04、在像素界定层之上形成透明阴极，透明阴极至少覆盖显示区，例如覆盖显示区和非显示区；其中，透明阴极、第一辅助阴极和第二辅助阴极三者电连接。
上述第一电极、第一辅助阴极、第二电极、第二辅助阴极、像素界定层、透明阴极的具体形成方法不做限定，可以根据实际情况确定。示例的，第一电极、第一辅助阴极、第二电极、第二辅助阴极、像素界定层、透明阴极均可采用打印工艺形成，即该显示基板可采用全打印工艺制作。通过全打印工艺制作的显示基板具有高寿命，高PPI，工艺流程少等优点。
上述显示区是指用于实现显示的区域；发光区是指设置有OLED单元的区域，根据相关技术可知，OLED单元包括阳极(Anode)、有机发光功能层和阴极(Cathode)；非发光区是指显示区中除发光区以外的区域，在该区域，可以设置像素界定层、像素电路单元，该像素电路单元可以包括TFT(Thin Film Transistor，薄膜晶体管)、栅线、数据线等。
上述第一电极是形成显示基板必不可少的导电结构。其可以是源漏极、栅极、阳极等，还可以是金属线，例如栅线、数据线等，这里具体不限定。第一电极位于显示区，即不限定第一电极在显示区的具体区域，需要根据第一电极的具体结构而定。示例的，若第一电极是位于源漏电极层的数据线，则第一电极可以位于显示区的非发光区；若第一电极是阳极，则第一电极可以位于显示区的发光区。
上述透明阴极、第一辅助阴极和第二辅助阴极三者实现电连接。这里对于电连接的具体方式不做限定。上述透明阴极的材料可以是镁银合金，当然还可以是其它材料，只要具备透明导电的特性即可。
上述第二电极是形成显示基板必不可少的导电结构。其可以是源漏极、栅极、阳极等，还可以是金属线，例如栅线、数据线等，这里具体不限定。上述第二电极位于显示区，即不限定第二电极在显示区的具体区域，需要根据第二电极的具体结构而定。示例的，若第二电极是阳极，则第二电极可以位于显示区的发光区，此时，第一电极可以是位于源漏电极层的数据线，其可以位于显示区的非发光区。若第二电极是位于源漏电极层的数据线，则第二电极可以位于显示区的非发光区，此时，第一电极可以是栅线，其可以位于显示区的非发光区。
本公开的实施例提供了一种显示基板的制备方法，该显示基板的制备方法中，通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极，通过一次 构图工艺在衬底上形成相互间隔的第二电极和第二辅助阴极，没有改变已有的工艺流程，从而降低了制作工艺的复杂性，提高了生产率。通过该制备方法形成的显示基板能够在不新增膜层的前提下设置辅助阴极，从而简化了辅助阴极的设计，降低了制作难度。
可选的，S01、通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极包括：
通过打印工艺在衬底上形成相互间隔的第一电极和第一辅助阴极，第一电极位于显示区，第一辅助阴极位于非发光区。
上述通过打印工艺形成第一电极和第一辅助阴极，工艺简单，可操作性强。
进一步可选的，S02、通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极包括：
通过打印工艺形成相互间隔的第二电极和第二辅助阴极。
上述通过打印工艺形成第二电极和第二辅助阴极，工艺简单，可操作性强。
需要说明的是，上述显示基板的实施例中，已经对第一电极、第二电极、第一辅助阴极、第二辅助阴极的结构进行了详细的描述，因而此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种显示基板，包括显示区和围绕所述显示区的非显示区，所述显示区包括：发光区和非发光区，其中，所述显示基板包括：
    衬底；
    位于所述衬底上的同层设置且相互间隔的第一电极和第一辅助阴极，所述第一电极位于所述显示区，所述第一辅助阴极位于所述非发光区；
    同层设置且相互间隔的第二电极和第二辅助阴极，设置在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第二电极位于所述显示区，所述第二辅助阴极位于所述非发光区，所述第一辅助阴极和所述第二辅助阴极在所述衬底上的正投影呈网状结构；
    像素界定层，至少位于所述非发光区中，所述像素界定层设置在所述第二电极和所述第二辅助阴极远离所述衬底的一侧；以及
    阴极，所述阴极至少覆盖所述显示区，所述阴极设置在所述像素界定层远离所述衬底的一侧；
    其中，所述阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一辅助阴极包括多条相互平行且沿第一方向延伸的第一辅助阴极线，所述第二辅助阴极包括多条相互平行且沿第二方向延伸的第二辅助阴极线，所述第一方向和第二方向相交。
  3. 根据权利要求2所述的显示基板，其中，所述第一方向和第二方向垂直。
  4. 根据权利要求2所述的显示基板，其中，所述显示基板还包括：
    保护层，所述保护层至少位于所述非发光区，所述保护层设置在所述第一辅助阴极和所述第二辅助阴极之间，
    所述保护层在所述多条第一辅助阴极线和所述多条第二辅助阴极线的交叠区域设置多个保护层过孔，所述多条第一辅助阴极线通过所述多个保护层过孔与所述多条第二辅助阴极线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述像素界定层包括多个第一像素界定层开口，所述多个第一像素界定层开口在衬底上的正投影落入所述第二辅助阴极在衬底上的正投影内，所述阴极通过所述多个第一像素界定层开口与所述第二辅助阴极线直接接触。
  6. 根据权利要求1所述的显示基板，其中，所述第一电极位于所述显示区，所述第一电极位于源漏电极层中；所述第二电极位于所述发光区，所述第二电极为阳极。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：电源线，所述电源线、所述第一电极和所述第一辅助阴极同层设置，所述电源线与所述第一辅助阴极相互间隔。
  8. 根据权利要求4所述的显示基板，其中，所述保护层包括：依次远离所述衬底设置的绝缘子层和平坦子层。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述显示基板还包括：
    设置在衬底上且位于所述非显示区的供电电极，所述供电电极用于向所述阴极供电；
    设置在所述供电电极之上的层间介质层、第三辅助阴极、隔离层和第四辅助阴极，所述供电电极、层间介质层、第三辅助阴极、隔离层和第四辅助阴极依次远离所述衬底设置，所述第三辅助阴极和所述第四辅助阴极均位于所述非显示区，
    所述供电电极通过第三辅助阴极、第四辅助阴极与所述透明电极电连接，
    所述第三辅助阴极与所述第一辅助阴极同层设置，所述第四辅助阴极与所述第二辅助阴极同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述像素界定层具有第二像素界定层开口，所述第二像素界定层开口在所述衬底上的正投影落入所述第四辅助阴极在所述衬底上的正投影内，所述隔离层具有穿透所述隔离层的隔离层过孔， 所述层间介质层具有穿透所述层间介质层的层间介质层过孔，所述阴极通过所述第二像素界定层开口与所述第四辅助阴极直接接触；所述第四辅助阴极通过所述隔离层过孔与所述第三辅助阴极电连接；所述第三辅助阴极通过所述层间介质层过孔与所述供电电极电连接。
  11. 根据权利要求9所述的显示基板，其中，所述显示基板还包括：电源线，所述电源线、所述第一电极和所述第一辅助阴极同层设置，所述电源线与所述第一辅助阴极相互间隔；
    所述电源线自所述显示区延伸至所述非显示区，所述电源线与所述第三辅助阴极同层设置且相互间隔，所述电源线与所述第四辅助阴极在所述衬底上的正投影互不交叠。
  12. 根据权利要求9所述的显示基板，其中，所述显示基板还包括：
    保护层，所述保护层至少位于所述非发光区，所述保护层设置在所述第一辅助阴极和所述第二辅助阴极之间；
    所述隔离层与所述保护层同层设置。
  13. 一种显示面板，包括权利要求1-12任一项所述的显示基板。
  14. 一种显示基板的制备方法，其中，所述显示基板划分为显示区和围绕所述显示区的非显示区，所述显示区包括：发光区和非发光区，所述显示基板的制备方法包括：
    通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极，其中，所述第一电极位于所述显示区，所述第一辅助阴极位于所述非发光区；
    通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极，所述第二电极和第二辅助阴极形成在所述第一电极和第一辅助电极远离所述衬底的一侧，所述第二电极位于所述显示区，所述第二辅助阴极位于所述非发光区；所述第一辅助阴极和所述第二辅助阴极在所述衬底上的投影呈网状结构；
    在所述第二电极和所述第二辅助阴极远离所述衬底一侧形成像素界定层，所述像素界定层至少位于所述非发光区中；以及
    在所述像素界定层远离所述衬底一侧形成阴极，所述阴极至少覆盖所述显示区，
    其中，所述阴极、所述第一辅助阴极和所述第二辅助阴极三者电连接。
  15. 根据权利要求14所述的显示基板的制备方法，其中，所述通过一次构图工艺在衬底上形成相互间隔的第一电极和第一辅助阴极包括：
    通过打印工艺在衬底上形成相互间隔的第一电极和第一辅助阴极。
  16. 根据权利要求14所述的显示基板的制备方法，其中，所述通过一次构图工艺形成相互间隔的第二电极和第二辅助阴极包括：
    通过打印工艺形成相互间隔的第二电极和第二辅助阴极。
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