WO2021051853A1 - 横向双扩散金属氧化物半导体器件及制作方法、电子装置 - Google Patents

横向双扩散金属氧化物半导体器件及制作方法、电子装置 Download PDF

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WO2021051853A1
WO2021051853A1 PCT/CN2020/092201 CN2020092201W WO2021051853A1 WO 2021051853 A1 WO2021051853 A1 WO 2021051853A1 CN 2020092201 W CN2020092201 W CN 2020092201W WO 2021051853 A1 WO2021051853 A1 WO 2021051853A1
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region
ion implantation
type
ion
metal oxide
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PCT/CN2020/092201
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English (en)
French (fr)
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何乃龙
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无锡华润上华科技有限公司
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Priority to US17/639,359 priority Critical patent/US20220302305A1/en
Publication of WO2021051853A1 publication Critical patent/WO2021051853A1/zh

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Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a lateral double-diffused metal oxide semiconductor device, a manufacturing method, and an electronic device.
  • VDMOS vertical double diffused metal oxide semiconductor
  • LDMOS lateral double diffused metal oxide semiconductor
  • VDMOS vertical double diffused metal oxide semiconductor
  • LDMOS lateral double diffused metal oxide semiconductor
  • the lateral double diffused metal oxide semiconductor (LDMOS) has better thermal stability and frequency stability, higher gain and durability, lower feedback capacitance and thermal resistance, as well as constant input impedance and simpler bias current Circuits, therefore, have been widely used at present.
  • a manufacturing method of a lateral double diffused metal oxide semiconductor device including:
  • a drain region is formed in the drift region, a source region is formed in the body region, a gate structure extending to the drift region is formed on the body region, and the drain region and the source region are respectively located in the Both sides of the gate structure;
  • the first type of ion implantation is performed on the drift region region located between the gate structure and the drain region to form an ion implantation at the bottom of the drift region that extends along the direction of the gate structure pointing to the drain region.
  • a plurality of deep trench structures spaced apart and a fin structure located between adjacent deep trench structures are formed above the first ion implantation region, and part of the first ion implantation region is exposed through the deep trench structure ;
  • a second type of ion implantation is performed in the deep trench structure to form a second ion implantation area so that the first ion implantation area and the second ion implantation area are alternately arranged, wherein the first type The ion type is different from the second type of ion.
  • a lateral double diffused metal oxide semiconductor device including:
  • a drain region is formed in the drift region, an active region is formed in the body region, a gate structure extending to the drift region is formed on the body region, and the drain region and the source region are respectively Located on both sides of the gate structure;
  • a number of deep trench isolation structures spaced apart between the gate structure and the drain region and a fin structure located between adjacent deep trench isolation structures are formed in the drift region;
  • the first ion implantation region and the second ion implantation region extend along the direction in which the gate structure points to the drain region, and the ion type of the first ion implantation region is different from the ion type of the second ion implantation region .
  • an electronic device including any of the above-mentioned lateral double diffused metal oxide semiconductor devices.
  • FIG. 1A-1D show a schematic cross-sectional view of a device obtained by sequentially implementing each step in a method for fabricating a lateral double diffused metal oxide semiconductor device according to an embodiment of the present invention
  • FIG. 2A shows a schematic cross-sectional view of the current flow direction of a lateral double-diffused metal oxide semiconductor device according to an embodiment of the present invention
  • FIG. 2B shows a schematic cross-sectional view of the current flow direction of a lateral double-diffused metal oxide semiconductor device according to another embodiment of the present invention
  • FIG. 2C shows a schematic cross-sectional view of the current flow direction of a lateral double diffused metal oxide semiconductor device according to another embodiment of the present invention
  • FIG. 3 shows a flow chart of the manufacturing method of a lateral double diffused metal oxide semiconductor device according to another embodiment of the present invention.
  • the drift region, body region, gate structure, source region, drain region and other structures are all formed by the lateral double diffused metal oxide semiconductor device.
  • the conventional production method of, I will not repeat it here.
  • the following mainly describes the formation process of the super junction of the lateral double diffused metal oxide semiconductor device proposed by the present invention.
  • the manufacturing method of the lateral double diffused metal oxide semiconductor device includes:
  • Step S1 providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate;
  • Step S2 forming a drain region in the drift region, forming a source region in the body region, forming a gate structure extending to the drift region on the body region, the drain region and the source region respectively Located on both sides of the gate structure;
  • Step S3 Perform a first type of ion implantation on the drift region located between the gate structure and the drain region, so as to form at the bottom of the drift region a direction toward the drain region along the gate structure.
  • a first ion implantation area extending in a direction;
  • Step S4 forming a plurality of mutually spaced deep trench structures and fin structures located between adjacent deep trench structures above the first ion implantation region, through the deep trench structures to expose part of the first Ion implantation area;
  • Step S5 Perform a second type of ion implantation in the deep trench structure to form a second ion implantation area, so that the first ion implantation area and the second ion implantation area are alternately arranged, wherein the The ion type of the first type is different from the ion type of the second type.
  • the above-mentioned manufacturing method further includes:
  • Step S6 Perform a second type of ion implantation on the sidewall of the fin structure to form a sidewall ion implantation area on the sidewall of the fin structure.
  • step S1 a semiconductor substrate 101 is provided, and a drift region 102 and a body region 109 are formed in the semiconductor substrate, and the drift region 102 and the body region 109 are in lateral contact with each other.
  • the semiconductor substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI) ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the semiconductor substrate is a P-type semiconductor substrate.
  • the drift region 102 is an N-type drift region
  • the body region 109 is a P-type body region
  • the formation method of the drift region 102 and the body region 109 may be ion implantation or the like.
  • a drain region 104 is formed in the drift region 102, a source region is formed in the body region, a gate structure 108 extending to the drift region is formed on the body region, the drain region 104 and The source regions are located on both sides of the gate structure 108 respectively.
  • a local oxide isolation structure 105 (ie, field oxygen, field oxygen, field oxygen) is formed in the drift region between the body region 109 and the position where the drain region 104 is to be subsequently formed.
  • oxide or FOX used for isolation.
  • the specific implementation method is to form an oxide isolation structure 105 with a thickness greater than 0.5 microns between the body region 109 and the location where the drain region 104 is to be formed subsequently through high-temperature treatment, and then through high-energy
  • the implantation forms an N-type implantation region and a P-type implantation region to form a drain region, a source region, and a body lead-out region 110, etc., respectively.
  • the local oxide layer isolation structure 105 needs to be etched to open a window exposing the lower drift region 102 on the local oxide layer isolation structure 105.
  • the window defined area is the area where the first ion implantation area is subsequently formed.
  • the device further includes a gate structure 108, where the gate structure 108 may be a polysilicon gate or a metal gate.
  • the preparation method of the gate structure 108 may include depositing a gate material layer and patterning to form a gate.
  • source-drain implantation is then performed to form the source and drain regions 104.
  • An N-type buffer zone 103 is also formed in the drift region, and the drain region 104 is formed in the buffer zone 103.
  • step S3 as shown in FIG. 1A, a first type of ion implantation is performed in the region between the gate structure and the drain region in the drift region 102, so as to form at the bottom of the drift region.
  • the first ion implantation region 106 extends along the direction in which the gate structure points to the drain region.
  • the method of forming the first ion implantation region 106 in this step includes the following steps:
  • Step S31 A mask layer is formed on the drift region 102 to define a region where the first ion implantation region and the second ion implantation region are alternately formed subsequently.
  • the mask layer can be a conventional mask layer, for example, a photoresist layer can be selected, which is easier to remove.
  • Step S32 Perform ion implantation using the mask layer as a mask to form a first ion implantation region 106 at the bottom of the drift region.
  • the extension direction of the first ion implantation region 106 extends along the direction of the gate structure pointing to the drain region.
  • the first type of ions are N-type, so the first ion implantation region 106 is N-type.
  • the depth of the first ion implantation region 106 is controlled by controlling the energy of the first type of ion implantation, so as to ensure that the first ion implantation region 106 is located at the bottom region of the drift region, for example, from the bottom of the drift region.
  • the length of is within one-third of the depth of the entire drift zone.
  • the first type of ion implantation is continued to form a well region 107 for the first type of ion above the first ion implantation region.
  • step S4 a plurality of deep trench structures spaced apart from each other and a fin structure located between adjacent deep trench structures are formed above the first ion implantation region, and a part of the deep trench structure is exposed through the deep trench structure.
  • the first ion implantation area is formed above the first ion implantation region.
  • a mask layer is first formed to define the region where the second ion implantation region is formed.
  • the mask layer can be a conventional mask layer, for example, a photoresist layer can be selected, which is easier to remove.
  • the well region 107 above the first ion implantation region is etched using the mask layer as a mask to form a plurality of deep trench structures, wherein the plurality of deep trench structures are directed toward the drain region along the gate structure. Extending in the direction, and a plurality of the deep trench structures are arranged at intervals.
  • a protruding fin structure is formed in the well region 107 between the deep trench structure, wherein the sidewall of the fin structure defines the deep trench Structure outline.
  • step S5 a second type of ion implantation is performed in the deep trench structure to form a second ion implantation area, so that the first ion implantation area and the second ion implantation area are alternately arranged, wherein, The ion type of the first type is different from the ion type of the second type.
  • ion implantation is performed using the fin structure as a mask to form a second ion implantation region 111 at the bottom of the deep trench structure, as shown in FIG. 1D.
  • the extension direction of the second ion implantation region 111 extends along the direction from the gate structure to the drain region.
  • the direction of the second type of ion implantation is vertical downward, and the first ion implantation region exposed at the bottom of the deep trench structure will be inverted so as to be in the drift region.
  • the second ion implantation region 111 is formed at the bottom of the, wherein the height of the first ion implantation region and the second ion implantation region are the same, so that the first ion implantation region and the second ion implantation region Alternate settings.
  • the second type of ions are P-type, so the second ion implantation region 111 is P-type, and thus an ion implantation region with alternately N-P-N-P is formed.
  • the surface of the second ion implantation region 111 at the bottom of the deep trench structure is controlled by controlling the energy of the second type of ion implantation.
  • a large area of the first type of ion implantation is performed first, and then a spaced deep trench structure and a fin structure are formed, and the second type of ion implantation is performed in the deep trench structure to form an alternating pattern at the bottom of the drift region.
  • the first ion implantation area and the second ion implantation area are arranged so as to form a super junction at the bottom of the drift area.
  • step S6 a second type of ion implantation is performed on the sidewall of the fin structure to form a sidewall ion implantation region 112 on the sidewall of the fin structure.
  • a second type of ion implantation is performed on the sidewalls of the fin structure to form an additional sidewall ion implantation region 112.
  • the second type of ion implantation is performed on the sidewalls of the fin structure to form sidewall ion implantation regions on the sidewalls of the fin structure, and the well regions between the deep trench structures withstand voltage therebetween
  • the concentration of the well region is much higher than that of the drift region, so that the on-resistance is further reduced on the basis of super junction LDMOS.
  • This structure has a super junction (super junction) and a sidewall ion implantation zone (sidewall) acting on the drift zone at the same time, reducing the surface electric field, improving the conduction capability, and forming a trench-type 3D RESURF LDMOS.
  • the oblique angle implantation in the present invention refers to performing the second type of ion implantation on the sidewalls of the fin structure at an oblique implantation angle.
  • the ion implantation direction is different from that of the fin.
  • the angle between the sidewalls of the structure is an acute angle, less than 90 degrees, so as to form the sidewall ion implantation area more effectively.
  • a dielectric is filled in the deep trench structure to form a deep trench isolation structure.
  • the LDMOS device described in the present invention may be one of Single Resurf (SR, Resurf means reduce surface field reduction technology), Double Resurf (DR), Triple Resurf (TR), and muti Resurf LDMOS device,
  • SR Single Resurf
  • DR Double Resurf
  • TR Triple Resurf
  • muti Resurf LDMOS device muti Resurf LDMOS device
  • SR Single Resurf
  • DR Double Resurf
  • TR Triple Resurf
  • muti Resurf LDMOS device muti Resurf LDMOS device
  • the top injection area is formed on the top of the fin structure.
  • the current density becomes smaller and smaller from top to bottom, and most of the current flows through the surface channel.
  • Making the surface into a fin shape is equivalent to increasing the surface channel path and correspondingly reducing the on-resistance.
  • the lateral double diffused metal oxide semiconductor device as shown in FIGS. 1C and 1D, includes:
  • a drain region 104 is formed in the drift region, an active region is formed in the body region, a gate structure 108 extending to the drift region 102 is formed on the body region 109, the drain region 104 and The source regions are respectively located on both sides of the gate structure 108;
  • a number of deep trench isolation structures spaced apart between the gate structure and the drain region and a fin structure located between adjacent deep trench isolation structures are formed in the drift region;
  • the first ion implantation region and the second ion implantation region extend along the direction in which the gate structure points to the drain region, and the ion type of the first ion implantation region is different from the ion type of the second ion implantation region .
  • the above-mentioned device may further include a sidewall ion implantation region 112 on the sidewall of the fin structure, and the ion type of the sidewall ion implantation region 112 is the same as that of the second ion implantation region 111 .
  • an N-type drift region 102 is formed on the semiconductor substrate 101, and a P-type well region is formed in the semiconductor substrate 101 to serve as a P-body region 109 (P-body).
  • a P+ implantation region and an N+ implantation region are formed in the body region 109, the P+ implantation region is used as the body lead-out region 110, and the N+ implantation region is used as the source region.
  • An N+ drain region 104 is also formed in the N-type drift region 102 and is spaced apart from the P-type well region.
  • An N-type buffer zone 103 is also formed in the drift region, and the drain region 104 is formed in the buffer zone 103.
  • a gate structure 108 is also formed on the body region.
  • the gate structure 108 may be a polysilicon gate or a metal gate.
  • a local oxide isolation structure 105 (ie, field oxide or FOX) with a thickness greater than 0.5 microns is formed in the drift region between the gate structure 108 and the drain region 104 for isolation.
  • the local oxide isolation structure 105 is provided with a window exposing the drift region 102 below.
  • the super junction includes a first ion implantation region 106 and a second ion implantation region 111 alternately arranged, wherein the first ion implantation region 106 is an N-type implantation region, and the second ion implantation region 111 is a P-type implantation region.
  • the P-type implantation region and the N-type implantation region extend along the direction in which the gate structure points to the drain region.
  • the P-type implantation region and the N-type implantation region are mutually depleted to achieve high voltage resistance, so that the on-resistance can be reduced by simultaneously increasing the doping concentration of the P-type implantation region and the N-type implantation region.
  • a deep trench isolation structure (DTI) and a fin structure are formed in the N-type drift region 102, wherein the bottom of the fin structure is the first ion implantation region 106.
  • the bottom of the deep trench isolation structure is the second ion implantation region 111.
  • the length of the first ion implantation region from the bottom of the drift region is within one third of the depth of the drift region, and the height of the first ion implantation region and the second ion implantation region are the same.
  • an N-type well region is formed in the N-type drift region 102 above the first ion implantation region, and the deep trench isolation structure and the fin structure are formed in the N-type well region.
  • a sidewall ion implantation region 112 is formed on the sidewall of the fin structure, wherein the ion type of the first ion implantation region is different from the ion type of the second ion implantation region, and the ions of the sidewall ion implantation region 112 The type is the same as the ion type of the second ion implantation region 111.
  • a sidewall ion implantation area is formed on the sidewall of the fin structure, and the well region between the deep trench isolation structure is completely depleted by the sidewall ion implantation area on both sides when the well region between the deep trench isolation structure is withstand voltage.
  • the concentration of the well region It is much higher than the drift region, so that the on-resistance is further reduced on the basis of super junction LDMOS.
  • This structure has a super junction (super junction) and a sidewall ion implantation zone (sidewall) acting on the drift zone at the same time, reducing the surface electric field, improving the conduction capability, and forming a trench-type 3D RESURF LDMOS.
  • the LDMOS device described in the present invention may be one of Single Resurf (SR, Resurf means reduce surface field reduction technology), Double Resurf (DR), Triple Resurf (TR), and muti Resurf LDMOS device,
  • SR Single Resurf
  • DR Double Resurf
  • TR Triple Resurf
  • muti Resurf LDMOS device muti Resurf LDMOS device
  • SR Single Resurf
  • DR Double Resurf
  • TR Triple Resurf
  • muti Resurf LDMOS device muti Resurf LDMOS device
  • the top injection area is formed on the top of the fin structure.
  • the current density becomes smaller and smaller from top to bottom, and most of the current flows through the surface channel.
  • Making the surface into a fin shape is equivalent to increasing the surface channel path and correspondingly reducing the on-resistance.

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Abstract

本发明提供了一种横向双扩散金属氧化物半导体器件及制作方法、电子装置。所述方法包括：提供半导体衬底，在所述半导体衬底中形成漂移区和体区；在所述漂移区中形成漏区，在所述体区中形成源区，在所述体区上形成延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；执行第一类型的离子注入，以在所述漂移区的底部形成沿所述栅极结构指向所述漏区的方向延伸的第一离子注入区；在所述第一离子注入区上方形成若干相互间隔的深沟槽结构和位于相邻深沟槽结构之间的鳍片结构，通过所述深沟槽结构以露出部分所述第一离子注入区；在所述深沟槽结构中执行第二类型的离子注入，形成第二离子注入区，以使所述第一离子注入区和所述第二离子注入区交替设置，其中，所述第一类型的离子与第二类型的离子类型不同。

Description

横向双扩散金属氧化物半导体器件及制作方法、电子装置
相关申请
本申请要求于2019年9月19日提交中国专利局的、申请号为201910884490.9、申请名称为“横向双扩散金属氧化物半导体器件及制作方法、电子装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，具体而言涉及一种横向双扩散金属氧化物半导体器件及制作方法、电子装置。
背景技术
在高压MOS管的发展过程中，主要有垂直双扩散金属氧化物半导体(VDMOS)和横向双扩散金属氧化物半导体(LDMOS)两种类型。虽然垂直双扩散金属氧化物半导体(VDMOS)导通电阻小，占用版图面积也小，但是它是纵向结构，不易和低压CMOS电路兼容。而横向双扩散金属氧化物半导体(LDMOS)具有更好的热稳定性和频率稳定性、更高的增益和耐久性、更低的反馈电容和热阻，以及恒定的输入阻抗和更简单的偏流电路，因此，在目前得到了比较广泛的应用。
在目前的高压LDMOS器件中，常规结构Single Resurf(SR，Resurf即reduce surface field降低表面电场技术)、Double Resurf(DR)、Triple Resurf(TR)以及muti Resurf LDMOS器件已经广泛的应用。想要在同等耐压基础上得到更低的导通电阻，则需要使用super-junction(SJ，超结)技术。然而， 目前为止SJ技术仅被成熟应用在垂直分离晶体管(vertical discrete transistor)，譬如VDMOS或IGBT中。在横向晶体管(例如LDMOS)中使用SJ技术时，会遇到很多问题，首先比如如何使导通电阻变得更低，而且工艺更加简单、兼容。
因此有必要提出一种横向双扩散金属氧化物半导体器件及其制作方法，以至少部分解决上述问题。
发明内容
根据本申请的各种实施例提供一种横向双扩散金属氧化物半导体器件的制作方法，所述制作方法包括：
提供半导体衬底，在所述半导体衬底中形成漂移区和体区；
在所述漂移区中形成漏区，在所述体区中形成源区，在所述体区上形成延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；
对位于所述栅极结构和所述漏区之间的漂移区区域执行第一类型的离子注入，以在所述漂移区的底部形成沿所述栅极结构指向所述漏区的方向延伸的第一离子注入区；
在所述第一离子注入区上方形成若干相互间隔的深沟槽结构和位于相邻深沟槽结构之间的鳍片结构，通过所述深沟槽结构以露出部分所述第一离子注入区；
在所述深沟槽结构中执行第二类型的离子注入，形成第二离子注入区，以使所述第一离子注入区和所述第二离子注入区交替设置，其中，所述第一类型离子与第二类型的离子类型不同。
根据本申请的各种实施例还提供一种横向双扩散金属氧化物半导体器件，包括：
半导体衬底，在所述半导体衬底中形成有漂移区和体区；
在所述漂移区中形成有漏区，在所述体区中形成有源区，在所述体区上 形成有延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；
在所述漂移区中形成有位于所述栅极结构和所述漏区之间若干相互间隔的深沟槽隔离结构和位于相邻深沟槽隔离结构之间的鳍片结构；
位于所述鳍片结构下方的第一离子注入区；
位于所述深沟槽隔离结构下方的第二离子注入区；
其中，所述第一离子注入区和所述第二离子注入区沿所述栅极结构指向所述漏区的方向延伸，第一离子注入区的离子类型与第二离子注入区的离子类型不同。
根据本申请的各种实施例还提供一种电子装置，包括上述任一种横向双扩散金属氧化物半导体器件。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1A-图1D示出了根据本发明一实施方式的横向双扩散金属氧化物半导体器件的制作方法依次实施各步骤所获得器件的剖面示意图；
图2A示出了根据本发明一实施方式的横向双扩散金属氧化物半导体器件的电流流通方向的横截面示意图；
图2B示出了根据本发明另一实施方式的横向双扩散金属氧化物半导体器件的电流流通方向的横截面示意图；
图2C示出了根据本发明又一实施方式的横向双扩散金属氧化物半导体器件的电流流通方向的横截面示意图；
图3示出根据本发明另一实施方式的横向双扩散金属氧化物半导体器件的制作方法的步骤流程图。
具体实施方式
为了彻底理解本发明，将在下列的描述中提出详细的结构及步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
下面结合图1A～图1D对本发明提出的横向双扩散金属氧化物半导体器件的制作方法进行说明。
需要说明的是，对于本发明的提出的横向双扩散金属氧化物半导体器件，其漂移区，体区、栅极结构，源区、漏区等结构的形成均采用横向双扩散金属氧化物半导体器件的常规的制作方法，在此不再赘述。下面主要对本发明的提出的横向双扩散金属氧化物半导体器件的超结的形成过程进行说明。
如图3以及图1A～图1D所示，横向双扩散金属氧化物半导体器件的制作方法包括：
步骤S1：提供半导体衬底，在所述半导体衬底中形成漂移区和体区；
步骤S2：在所述漂移区中形成漏区，在所述体区中形成源区，在所述体区上形成延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；
步骤S3：对位于所述栅极结构和所述漏区之间的漂移区区域执行第一类型的离子注入，以在所述漂移区的底部形成沿所述栅极结构指向所述漏区的方向延伸的第一离子注入区；
步骤S4：在所述第一离子注入区上方形成若干相互间隔的深沟槽结构和位于相邻深沟槽结构之间的鳍片结构，通过所述深沟槽结构以露出部分所述第一离子注入区；
步骤S5：在所述深沟槽结构中执行第二类型的离子注入，形成第二离子注入区，以使所述第一离子注入区和所述第二离子注入区交替设置，其中， 所述第一类型的离子与第二类型的离子类型不同。
在一实施例中，上述制作方法还包括：
步骤S6：对鳍片结构的侧壁执行第二类型的离子注入，以在所述鳍片结构的侧壁上形成侧墙离子注入区。
下面结合附图图1A～图1D对所述方法作进一步详细的说明。
首先，在步骤S1中，如图1A所示，提供半导体衬底101，在所述半导体衬底中形成漂移区102和体区109，漂移区102和体区109侧面相互接触。
具体地，所述半导体衬底101可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本发明的一示例中，其中所述半导体衬底为P型半导体衬底。
其中，所述漂移区102为N型漂移区，所述体区109为P型体区，所述漂移区102和所述体区109的形成方法可以为离子注入等。
在步骤S2中，在所述漂移区102形成漏区104，在所述体区中形成源区，在所述体区上形成延伸至漂移区处的栅极结构108，所述漏区104和所述源区分别位于所述栅极结构的108两侧。
具体地，如图1A所示，在所述漂移区中在体区109和后续欲形成漏区104的位置之间的区域形成厚度大于0.5微米的局部氧化层隔离结构105(即场氧，field oxide或FOX)，用于起到隔离作用，其具体实现方法为通过高温处理在体区109和后续欲形成漏区104的位置之间形成厚度大于0.5微米的氧化层隔离结构105，之后通过高能注入形成N型注入区和P型注入区以分别形成漏区、源区以及体引出区110等。所述局部氧化层隔离结构105还要经过刻蚀，以在局部氧化层隔离结构105上开设暴露出下方漂移区102的窗口，该窗口限定区域即为后续形成第一离子注入区的区域。
所述器件还包括栅极结构108，其中，栅极结构108可以为多晶硅栅极 或者金属栅极，栅极结构108的制备方法可以包括沉积栅极材料层并图案化，以形成栅极。
在形成栅极结构108之后，然后执行源漏注入，进而形成源区和漏区104。在所述漂移区中还形成有N型缓冲区103，漏区104形成于缓冲区103中。
在步骤S3中，如图1A所示，在所述漂移区102中位于所述栅极结构和所述漏区之间的区域执行第一类型的离子注入，以在所述漂移区的底部形成沿所述栅极结构指向所述漏区的方向延伸的第一离子注入区106。
具体地，如图1A所示，在该步骤中形成所述第一离子注入区106的方法包括以下步骤：
步骤S31：在所述漂移区102上形成掩膜层，以用于定义后续交替形成第一离子注入区和第二离子注入区的区域。
其中，所述掩膜层可以选用常规的掩膜层，例如可以选用光刻胶层，其更加容易去除。
步骤S32：以所述掩膜层为掩膜执行离子注入，以在所述漂移区的底部形成第一离子注入区106。
其中，在该步骤中，所述第一离子注入区106的延伸方向为沿栅极结构指向所述漏区的方向延伸。
在本发明的一具体实施方式中，所述第一类型的离子为N型，因此第一离子注入区106为N型。
通过控制所述第一类型的离子注入的能量来控制所述第一离子注入区106的深度，以保证所述第一离子注入区106位于所述漂移区的底部区域，例如距离漂移区的底部的长度为整个漂移区深度的三分之一以内。
可选地，继续执行第一类型的离子注入，以在所述第一离子注入区的上方形成第一类型离子的阱区107。
在步骤S4中，在所述第一离子注入区上方形成相互间隔的若干深沟槽结 构和位于相邻深沟槽结构之间的鳍片结构，通过所述深沟槽结构以露出部分所述第一离子注入区。
如图1B和图1C所示，在该步骤中首先形成掩膜层，以用于定义形成第二离子注入区的区域。
其中，所述掩膜层可以选用常规的掩膜层，例如可以选用光刻胶层，其更加容易去除。
然后以所述掩膜层为掩膜蚀刻第一离子注入区的上方的阱区107，以形成若干深沟槽结构，其中，所述若干深沟槽结构沿栅极结构指向所述漏区的方向延伸，并且若干所述深沟槽结构相互间隔设置。
可选地，在形成所述深沟槽结构的同时，在深沟槽结构之间的阱区107中形成了凸出的鳍片结构，其中鳍片结构的侧壁定义了所述深沟槽结构轮廓。
在步骤S5中，在所述深沟槽结构中执行第二类型的离子注入，形成第二离子注入区，以使所述第一离子注入区和所述第二离子注入区交替设置，其中，所述第一类型的离子与第二类型的离子类型不同。
在该步骤中，以所述鳍片结构为掩膜执行离子注入，以在所述深沟槽结构的底部形成第二离子注入区111，如图1D所示。
其中，在该步骤中，所述第二离子注入区111的延伸方向为沿自栅极结构指向所述漏区的方向延伸。
在本发明的一具体实施方式中，所述第二类型的离子注入的方向为竖直向下，所述深沟槽结构底部露出的第一离子注入区会反型，以在所述漂移区的底部形成所述第二离子注入区111，其中，所述第一离子注入区和所述第二离子注入区的高度相同，以使所述第一离子注入区和所述第二离子注入区交替设置。
其中，第二类型的离子为P型，因此第二离子注入区111为P型，因此形成N-P-N-P交替设置的离子注入区。
在该步骤中通过控制所述第二类型的离子注入的能量来控制所述第二离 子注入区111位于所述深沟槽结构的底部的表面。在本申请中先执行大面积的第一类型的离子注入，再形成间隔的深沟槽结构和鳍片结构，并且在深沟槽结构执行第二类型的离子注入，在漂移区的底部形成交替设置的第一离子注入区和所述第二离子注入区，从而形成位于漂移区底部的超结。
在步骤S6中，对鳍片结构的侧壁执行第二类型的离子注入，以在所述鳍片结构的侧壁上形成侧墙离子注入区112。
在该步骤中，对所述鳍片结构的侧壁执行第二类型的离子注入，形成额外的侧墙离子注入区112。斜角注入、对鳍片结构的侧壁执行第二类型的离子注入，以在所述鳍片结构的侧壁上形成侧墙离子注入区，深沟槽结构之间的阱区在其间耐压的时候通过两边的侧墙离子注入区来完全耗尽，阱区的浓度比漂移区高很多，使得导通电阻在超结(super junction)LDMOS的基础上进一步降低。这种结构有超结(super junction)和侧墙离子注入区(sidewall)同时作用于漂移区，降低表面电场，提升导通能力，形成为沟槽型3D RESURF LDMOS。
在发明中所述斜角注入是指以倾斜的注入角度对鳍片结构的侧壁执行第二类型的离子注入，例如在本发明的一具体实施例中所述离子注入方向与所述鳍片结构的侧壁之间的夹角为锐角，小于90度，以更有效的形成所述侧墙离子注入区。
最后，在所述深沟槽结构中填充介质，形成深沟槽隔离结构。
可选地，本发明中所述LDMOS器件可以为Single Resurf(SR，Resurf即reduce surface field降低表面电场技术)、Double Resurf(DR)、Triple Resurf(TR)以及muti Resurf LDMOS器件中的一种，例如当所述器件为SR器件时，其并没有顶部注入层，其电流的流向如图2A所示，从表面到体内电流密度越来越小，电流主要在表面流动，由于电流密度由上而下越来越小，电流大部分都从表面通道流过，如果将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。当所述器件为DR器件时，如图2B所示，所 述鳍片结构的顶部形成顶部注入区，同理，电流密度由上而下越来越小，电流大部分都从表面通道流过，将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。当所述器件为TR器件时，如图2C所示，所述鳍片结构的顶部以下形成埋层注入区，埋层注入区打入漂移区内，电流有上方和下方两个通路，同样的，电流接近一半是走埋层注入区(Pbury)上方，埋层注入区(Pbury)下方的电流也是大部分集中在离埋层注入区(Pbury)比较近的区域，将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。
下面对本发明所述横向双扩散金属氧化物半导体器件的结构进行详细的说明。
所述横向双扩散金属氧化物半导体器件，如图1C和1D所示，包括：
半导体衬底101，在所述半导体衬底上形成有漂移区102和体区109；
在所述漂移区中形成有漏区104，在所述体区中形成有源区，在所述体区109上形成有延伸至漂移区102处的栅极结构108，所述漏区104和所述源区分别位于所述栅极结构108的两侧；
在所述漂移区中形成有位于所述栅极结构和所述漏区之间相互间隔的若干深沟槽隔离结构和位于相邻深沟槽隔离结构之间的鳍片结构；
位于所述鳍片结构下方的第一离子注入区106；
位于所述深沟槽隔离结构下方的第二离子注入区111；
其中，所述第一离子注入区和所述第二离子注入区沿所述栅极结构指向所述漏区的方向延伸，第一离子注入区的离子类型与第二离子注入区的离子类型不同。
在一实施例中，上述器件还可包括位于所述鳍片结构侧壁上的侧墙离子注入区112，所述侧墙离子注入区112的离子类型与第二离子注入区111的离子类型相同。
具体地，在半导体衬底101上形成有N型漂移区102，在半导体衬底101 中形成有P型阱区用作P型体区109(P-body)。在体区109中形成有P+注入区和N+注入区，P+注入区用作体引出区110，N+注入区用作源区。
在N型漂移区102中还形成有与所述P型阱区间隔设置的N+漏区104。在所述漂移区中还形成有N型缓冲区103，漏区104形成于缓冲区103中。
在所述体区上还形成有栅极结构108。其中，栅极结构108可以为多晶硅栅极或者金属栅极。
在所述漂移区中在栅极结构108和漏区104之间的区域形成厚度大于0.5微米的局部氧化层隔离结构105(即场氧，field oxide或FOX)，用于起到隔离作用。该局部氧化层隔离结构105开设有暴露出下方漂移区102的窗口。
超结包括交替设置的第一离子注入区106和第二离子注入区111，其中，第一离子注入区106为N型注入区，第二离子注入区111为P型注入区。P型注入区和N型注入区沿栅极结构指向漏区的方向延伸。器件在关断状态下，P型注入区和N型注入区互相耗尽实现耐高压，从而可以通过同时提高P型注入区和N型注入区的掺杂浓度来降低导通电阻的目的。
为了使用超结技术进一步降低导通电阻，在N型漂移区102中形成有深沟槽隔离结构(DTI)和鳍片结构，其中所述鳍片结构底部为第一离子注入区106，所述深沟槽隔离结构底部为第二离子注入区111。所述第一离子注入区距离所述漂移区底部的长度为漂移区深度的三分之一以内，所述第一离子注入区和所述第二离子注入区的高度相同。
进一步，所述N型漂移区102中位于第一离子注入区的上方形成有N型的阱区，所述深沟槽隔离结构和鳍片结构形成于所述N型的阱区中。
其中，在所述鳍片结构的侧壁上形成有侧墙离子注入区112，其中，第一离子注入区的离子类型与第二离子注入区的离子类型不同，侧墙离子注入区112的离子类型与第二离子注入区111的离子类型相同。
在所述鳍片结构的侧壁上形成侧墙离子注入区，深沟槽隔离结构之间的阱区在其间耐压的时候通过两边的侧墙离子注入区来完全耗尽，阱区的浓度比漂移区高很多，使得导通电阻在超结(super junction)LDMOS的基础上进 一步降低。这种结构有超结(super junction)和侧墙离子注入区(sidewall)同时作用于漂移区，降低表面电场，提升导通能力，形成为沟槽型3D RESURF LDMOS。
可选地，本发明中所述LDMOS器件可以为Single Resurf(SR，Resurf即reduce surface field降低表面电场技术)、Double Resurf(DR)、Triple Resurf(TR)以及muti Resurf LDMOS器件中的一种，例如当所述器件为SR器件时，其并没有顶部注入层，其电流的流向如图2A所示，从表面到体内电流密度越来越小，电流主要在表面流动，由于电流密度由上而下越来越小，电流大部分都从表面通道流过，如果将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。当所述器件为DR器件时，如图2B所示，所述鳍片结构的顶部形成顶部注入区，同理，电流密度由上而下越来越小，电流大部分都从表面通道流过，将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。当所述器件为TR器件时，如图2C所示，所述鳍片结构的顶部以下形成埋层注入区，埋层注入区打入漂移区内，电流有上方和下方两个通路，同样的，电流接近一半是走埋层注入区(Pbury)上方，埋层注入区(Pbury)下方的电流也是大部分集中在离埋层注入区(Pbury)比较近的区域，将表面做成鳍片状，相当于增加了表面通道路径，相应的减小导通阻抗。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向双扩散金属氧化物半导体器件的制作方法，所述制作方法包括：
    步骤S1，提供半导体衬底，在所述半导体衬底中形成漂移区和体区；
    步骤S2，在所述漂移区中形成漏区，在所述体区中形成源区，在所述体区上形成延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；
    步骤S3，对位于所述栅极结构和所述漏区之间的漂移区区域执行第一类型的离子注入，以在所述漂移区的底部形成沿所述栅极结构指向所述漏区的方向延伸的第一离子注入区；
    步骤S4，在所述第一离子注入区上方形成若干相互间隔的深沟槽结构和位于相邻深沟槽结构之间的鳍片结构，通过所述深沟槽结构以露出部分所述第一离子注入区；
    步骤S5，在所述深沟槽结构中执行第二类型的离子注入，形成第二离子注入区，以使所述第一离子注入区和所述第二离子注入区交替设置，其中，所述第一类型的离子与第二类型的离子类型不同。
  2. 根据权利要求1所述的制作方法，其中，所述制作方法还包括：
    步骤S6，对鳍片结构的侧壁执行第二类型的离子注入，以在所述鳍片结构的侧壁上形成侧墙离子注入区。
  3. 根据权利要求1所述的制作方法，其中，所述第一类型的离子为N型，所述第二类型的离子为P型。
  4. 根据权利要求1所述的制作方法，其中，在形成所述第一离子注入区的过程中包括：
    在所述栅极结构和所述漏区之间的所述漂移区上形成掩膜层，以定义所述第一离子注入区的区域；
    执行第一类型的离子注入，以形成所述第一离子注入区；
    继续执行第一类型的离子注入，以在所述第一离子注入区的上方形成第一类型离子的阱区。
  5. 根据权利要求1所述的制作方法，其中，所述制作方法还包括：
    对所述鳍片结构的顶部执行第二类型的离子注入，以在所述鳍片结构的顶部形成顶部注入区或在所述鳍片结构的顶部以下形成埋层注入区。
  6. 根据权利要求2所述的制作方法，其中，形成所述侧墙离子注入区的过程包括：以倾斜的注入角度对鳍片结构的侧壁执行所述第二类型的离子注入。
  7. 一种横向双扩散金属氧化物半导体器件，包括：
    半导体衬底，在所述半导体衬底中形成有漂移区和体区；
    在所述漂移区中形成有漏区，在所述体区中形成有源区，在所述体区上形成有延伸至漂移区处的栅极结构，所述漏区和所述源区分别位于所述栅极结构的两侧；
    在所述漂移区中形成有位于所述栅极结构和所述漏区之间若干相互间隔的深沟槽隔离结构和位于相邻深沟槽隔离结构之间的鳍片结构；
    位于所述鳍片结构下方的第一离子注入区；
    位于所述深沟槽隔离结构下方的第二离子注入区；其中，所述第一离子注入区和所述第二离子注入区沿所述栅极结构指向所述漏区的方向延伸，第一离子注入区的离子类型与第二离子注入区的离子类型不同。
  8. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，还包括位于所述鳍片结构侧壁上的侧墙离子注入区，所述侧墙离子注入区的离子类型与第二离子注入区的离子类型相同。
  9. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，第一离子注入区和所述侧墙离子注入区为N型，所述第二离子注入区为P型。
  10. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，还包括位于所述鳍片结构顶部的顶部注入区或位于所述鳍片结构的顶部以下的埋层注入区，顶部注入区或埋层注入区为P型。
  11. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，所述第一离子注入区的上方形成有N型的阱区，所述鳍片结构形成于N型的阱区中。
  12. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，还包括位于所述漂移区上的局部氧化层隔离结构，位于栅极结构与漏区之间的区域。
  13. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，所述第一离子注入区距离所述漂移区底部的长度为漂移区深度的三分之一以内，所述第一离子注入区和所述第二离子注入区的高度相同。
  14. 根据权利要求7所述的横向双扩散金属氧化物半导体器件，其中，所述漂移区内还形成有缓冲区，所述漏区形成于所述缓冲区内。
  15. 一种电子装置，其中，所述电子装置包括权利要求7至14之一所述的横向双扩散金属氧化物半导体器件。
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