WO2021036379A1 - 电路板及其制造方法、电路板组件的制造方法 - Google Patents

电路板及其制造方法、电路板组件的制造方法 Download PDF

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Publication number
WO2021036379A1
WO2021036379A1 PCT/CN2020/093452 CN2020093452W WO2021036379A1 WO 2021036379 A1 WO2021036379 A1 WO 2021036379A1 CN 2020093452 W CN2020093452 W CN 2020093452W WO 2021036379 A1 WO2021036379 A1 WO 2021036379A1
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WIPO (PCT)
Prior art keywords
circuit
layer
substrate
electrically connected
circuit board
Prior art date
Application number
PCT/CN2020/093452
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English (en)
French (fr)
Inventor
韦文竹
何明展
沈芾云
郭宏艳
Original Assignee
鹏鼎控股(深圳)股份有限公司
庆鼎精密电子（淮安）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 鹏鼎控股(深圳)股份有限公司, 庆鼎精密电子（淮安）有限公司 filed Critical 鹏鼎控股(深圳)股份有限公司
Priority to US17/289,035 priority Critical patent/US12063752B2/en
Priority to CN202080005336.0A priority patent/CN112753289B/zh
Publication of WO2021036379A1 publication Critical patent/WO2021036379A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1121—Cooling, e.g. specific areas of a PCB being cooled during reflow soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Definitions

  • the application relates to a circuit board, a manufacturing method thereof, and a manufacturing method of a circuit board assembly.
  • the transmission line manufactured by the hot press bonding process is usually welded to the main board by hot press welding.
  • the conductive paste in the transmission line has poor thermal conductivity and is easy to form a sintered interface (IMC) with the copper layer, resulting in the connection between the transmission line and the main board. Reliability is reduced.
  • a method for manufacturing a circuit board comprising the steps of: providing a first circuit substrate.
  • the first circuit substrate includes a first substrate layer, a first circuit layer, and a plurality of The first conductive body is formed by an electroplating process.
  • the first circuit layer includes an etching line, and the etching line divides the first circuit layer into a hot pressing area located inside the etching line and a non-heat pressing area located outside the etching line .
  • the hot pressing zone includes a plurality of the first conductive bodies, and the first conductive bodies include a first end portion and a second end portion opposite to the first end portion, and the first conductive body includes a first end portion and a second end portion opposite to the first end portion. The end is electrically connected to the hot pressing zone.
  • a second circuit substrate includes a second base material layer, a second circuit layer, and a plurality of second conductive bodies, and the second conductive bodies include conductive paste.
  • the second conductive body includes a third end and a fourth end opposite to the third end, and the third end is electrically connected to the second circuit layer.
  • the first circuit substrate and the second circuit substrate are stacked so that the second end corresponds to the fourth end to obtain an intermediate body, and the intermediate body is pressed together so that the first The two ends are electrically connected to the fourth end to obtain the circuit board.
  • providing the first circuit substrate includes the step of: providing a double-sided copper-clad substrate, the double-sided copper-clad substrate including the first substrate layer, a first copper foil layer, and a second copper foil
  • the first copper foil layer and the second copper foil layer are arranged on two opposite surfaces of the first substrate layer.
  • a plurality of first via holes are opened in the double-sided copper clad substrate, and the first via holes penetrate the second copper foil layer and the first substrate layer.
  • Electroplating is performed on the second copper foil layer to form an electroplating layer, and part of the electroplating layer is filled in the first via hole to form the first via. And etching the first copper foil layer to obtain the first circuit layer, and etching the second copper foil layer and the electroplating layer to obtain a third circuit layer to obtain the first circuit substrate.
  • the third circuit layer includes a signal line and a plurality of first ground pads electrically isolated from the signal line, and a side of the first ground pad close to the first circuit layer passes through
  • the first conductive body is electrically connected to the first circuit layer, and the side of the first ground pad away from the first circuit layer is electrically connected to the second circuit layer through the second conductive body ,
  • the first circuit layer, the first conductive body, the first ground pad, the second conductive body, and the second circuit layer that are electrically connected form a shielding shell, the The signal line is located in the shielding shell.
  • the plurality of first ground pads includes two electrically conductive first ground pads, and the two electrically conductive first ground pads pass through the two first ground pads.
  • the body is electrically connected to the hot pressing zone and the non-hot pressing zone respectively, so that the hot pressing zone and the non-hot pressing zone are electrically connected.
  • the hot pressing zone includes a copper skin, and the copper skin is electrically connected to the non-hot pressing zone, and a second ground pad and a first signal pad are provided in the copper skin, so The second ground pad and the first ground pad are electrically connected through the first conductive body, the second ground pad and the copper skin are electrically connected through a plurality of microstructures, the The first signal pad and the signal line are electrically connected through the first conductive body, and the first signal pad is electrically separated from the copper skin.
  • providing the second circuit substrate includes the step of: providing a single-sided copper-clad substrate, the single-sided copper-clad substrate including a second substrate layer and a third substrate layer formed on the surface of the second substrate layer. Copper foil layer. The third copper foil layer is etched to form the second circuit layer. A plurality of second via holes are opened in the second substrate layer, and the second via holes penetrate the second substrate layer. Filling the second via hole with conductive paste to obtain the second conductive body, thereby obtaining the second circuit substrate.
  • the second circuit layer includes at least one second signal pad and at least one third ground pad electrically separated from the second signal pad, and the third ground pad of the second conductive body The end is electrically connected to the second signal pad or the third ground pad.
  • the second signal pad corresponds to the signal circuit
  • the third ground pad corresponds to the first ground pad.
  • both the first circuit substrate and the second circuit substrate are flexible circuit substrates.
  • a circuit board includes: at least one first circuit substrate and at least one second circuit substrate overlapped with the first circuit substrate.
  • Each of the first circuit substrates includes a first substrate layer, a first circuit layer, and a plurality of first conductive bodies arranged in the first substrate layer, and the first conductive bodies are electroplated Process formation; wherein, the first circuit layer includes an etching line, the etching line divides the first circuit layer into a hot press area located in the etching line and a non-etching area outside the etching line Hot pressing zone; the projection of the first conductive body on the first circuit layer is located in the hot pressing zone, the first conductive body includes a first end and the first end An opposite second end, and the first end is electrically connected to the hot pressing zone.
  • Each of the second circuit substrates includes a second base material layer, a second circuit layer, and a plurality of second conductive bodies.
  • the second conductive bodies include conductive paste; wherein, the second conductive bodies It includes a third end and a fourth end opposite to the third end, and the third end is electrically connected to the second circuit layer. The second end is electrically connected to the fourth end.
  • the first circuit substrate further includes a third circuit layer provided on the second surface, and the third circuit layer includes a signal circuit and a plurality of first grounds electrically isolated from the signal line Pad, the side of the first ground pad close to the first circuit layer is electrically connected to the first circuit layer through the first conductive body, and the first ground pad is far away from the first circuit layer.
  • One side of the circuit layer is electrically connected to the second circuit layer through the second conductive body, and the first circuit layer, the first conductive body, the first ground pad, The second conductive body and the second circuit layer form a shielding shell, and the signal line is located in the shielding shell.
  • the first substrate layer is exposed in the etching line, the etching line is in the shape of a semi-closed frame, and the etching line divides the first circuit layer into the hot pressing zone and the hot pressing zone in the frame.
  • the non-hot press area outside the frame.
  • the hot pressing zone includes a copper skin, and the copper skin is electrically connected to the non-hot pressing zone.
  • a second ground pad and a first signal pad are arranged in the copper skin.
  • the second The ground pad and the first ground pad are electrically connected through the first conductive body, the second ground pad and the copper skin are electrically connected through a plurality of microstructures, and the first signal The pad and the signal line are electrically connected through the first conductive body, and the first signal pad is electrically separated from the copper skin.
  • a method for manufacturing a circuit board assembly includes the steps:
  • a first circuit board is provided, and the first circuit board is the upper circuit board.
  • a second circuit board is provided, the second circuit board includes a connection area, and the connection area is provided with solder paste.
  • the first circuit board is stacked on the second circuit board, and the connection area is opposite to the hot nip.
  • Heating the hot nip of the first circuit the heat of the hot nip is conducted to the first circuit board and the second circuit board through the first conductive body and the second conductive body And melting the solder paste and cooling to obtain the circuit board assembly.
  • the circuit board and the manufacturing method thereof provided in this application include at least the following advantages:
  • a hot press area is divided on the circuit board, and the first conductive body formed by electroplating in the hot press area is electrically connected to adjacent layers.
  • the heat conduction efficiency along the thickness of the circuit board Can be improved, thereby reducing the risk of brittle sintering interface formation.
  • the etching line on the first circuit layer By setting the etching line on the first circuit layer to divide the hot pressing zone and the non-hot pressing zone, the first substrate layer is exposed from the etching line.
  • the etching line can reduce the heat conduction from the hot pressing zone to The non-hot-pressed area makes the heat in the hot-pressed area concentrated, which facilitates welding at a lower temperature.
  • the grounding pad in the hot pressing area is connected to the copper skin through a microstructure, which is beneficial to reduce the heat conduction from the grounding pad to the copper skin, so that the heat of the grounding pad is concentrated, and it is convenient to complete the welding at a lower temperature.
  • FIG. 1 is a schematic diagram of a double-sided copper clad substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the double-sided copper clad substrate shown in FIG. 1 after a first via hole is drilled.
  • FIG. 3 is a schematic diagram of the first via hole shown in FIG. 2 after the first via is electroplated and filled.
  • FIG. 4 is a schematic diagram of the first circuit substrate obtained by etching FIG. 3.
  • FIG. 5 is a bottom view of the circuit substrate shown in FIG. 4.
  • FIG. 5 is a bottom view of the circuit substrate shown in FIG. 4.
  • Fig. 6 is a top view of the circuit substrate shown in Fig. 4.
  • FIG. 7 is a schematic diagram of a single-sided copper clad substrate provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram after etching the single-sided copper-clad substrate shown in FIG. 7 to obtain a second circuit layer.
  • FIG. 9 is a schematic diagram of FIG. 8 after drilling the second via hole.
  • FIG. 10 is a schematic diagram of the second via hole shown in FIG. 9 being filled with conductive paste to obtain a second circuit substrate.
  • FIG. 11 is a top view of the second circuit substrate shown in FIG. 10.
  • FIG. 12 is a schematic diagram of a circuit board provided by an embodiment of the application.
  • Circuit board 100 first via 143
  • First circuit layer 12 Single-sided copper-clad substrate 15
  • the first signal pad 1213 The second circuit substrate 20
  • Microstructure 1214 Third surface 211
  • the first conductive body 13 The second signal pad 221
  • the embodiment of the present application provides a method for manufacturing the circuit board 100, which includes the steps:
  • the first circuit substrate 10 includes a first base material layer 11, a first circuit layer 12, and a plurality of first conductive bodies 13.
  • the first conductive body 13 is formed by an electroplating process
  • the first substrate layer 11 includes a first surface 111 and a second surface 112 opposite to the first surface 111, and the first circuit layer 12 is disposed on the first surface 111;
  • the first circuit layer 12 includes an etching line 123, and the etching line 123 divides the first circuit layer 12 into a hot pressing area 121 located in the etching line 123 and a hot pressing area 121 located outside the etching line 123.
  • a non-hot pressing zone 122, the hot pressing zone 121 includes a plurality of the first conductive bodies 13;
  • the first conductive body 13 includes a first end 131 and a second end 132 opposite to the first end 131.
  • the first end 131 is electrically connected to the hot pressing zone 121,
  • the second end 132 is exposed on the second surface 112.
  • the second circuit substrate 20 includes a second base material layer 21, a second circuit layer 22, and a plurality of second conductive bodies 23.
  • the second conductive body 23 includes conductive paste;
  • the second substrate layer 21 includes a third surface 211 and a fourth surface 212 opposite to the third surface 211, and the second circuit layer 22 is disposed on the third surface 211;
  • the second conductive body 23 includes a third end 231 and a fourth end 232 opposite to the third end 231, and the third end 231 is electrically connected to the second circuit layer 22 , The fourth end 232 is exposed on the fourth surface 212.
  • solder paste needs to be placed on the connection area (not shown) of the main board.
  • the connection area Corresponding to the hot pressing area 121 of the first circuit layer 12, and then bonding the second circuit layer 22 of the circuit board 100 to the solder paste in the connection area, and a hot pressing head is pressed against it.
  • the hot pressing head heats the hot pressing zone 121, and the heat of the hot pressing zone 121 passes through the first conductive body 13 and the hot pressing zone 121
  • the second conductive body 23 is conducted to the second circuit layer 22, and then the solder paste directly in contact with the second circuit layer 22 is heated and melted, and at the same time the thermal head applies to the circuit board 100 Under pressure, the molten solder paste fully contacts the connection area between the second circuit layer 22 and the main board. After cooling, the circuit board 100 and the main board are soldered.
  • step S1 providing the first circuit substrate 10 includes:
  • FIG. 1 Please refer to FIG. 1 to provide a double-sided copper clad substrate 14 which includes a first substrate layer 11, a first copper foil layer 141, and a second copper foil layer 142.
  • the first substrate layer 11 includes a first surface 111 and a second surface 112 opposite to the first surface 111, the first copper foil layer 141 is disposed on the first surface 111, and the second The copper foil layer 142 is disposed on the second surface 112.
  • the double-sided copper clad substrate 14 is a flexible substrate.
  • a plurality of first via holes 143 are drilled on the double-sided copper-clad substrate 14, and the first via holes 143 penetrate the second copper foil layer 142 and the first The first surface 111 and the second surface 112 of the substrate layer 11, and the side of the first copper foil layer 141 close to the second copper foil layer 142 is exposed at the first via hole 143.
  • electroplating is performed on the second copper foil layer 142 to form an electroplating layer 144, and a part of the electroplating layer 144 is filled in the first via 143 to form the first conductive Whole body 13.
  • the hot nip 121 and the non-hot nip 122 both form the first conductive body 13 in the first via 143 by electroplating.
  • the hot pressing zone 121 forms the first conductive body 13 in the first via hole 143 by electroplating
  • the non-hot pressing zone 122 is filled with conductive
  • the electroplated conductive body (not shown) is formed in the first conductive hole 143 by a paste method.
  • step S13 the first substrate layer 11 is exposed in the etching line 123, and the etching line 123 is in the shape of a semi-enclosed frame.
  • the first circuit layer 12 is divided into the hot pressing area 121 inside the frame and the non-hot pressing area 122 outside the frame.
  • the etching line 123 By arranging the etching line 123 in the shape of a semi-enclosed frame, it is possible to effectively reduce the heat conduction from the hot pressing zone 121 (that is, inside the frame of the etching line 123) to the non-hot pressing zone 122, so that the hot pressing
  • the main heat in the region 121 is conducted to the second circuit layer 22 through the first conductive body 13 and the second conductive body 23, so that the hot nip region 121 can withstand a lower temperature.
  • the hot-press welding is completed, thereby reducing the risk of forming a brittle sintering interface at the end of the second conductive body 23 due to high temperature conditions, which is beneficial to improve the reliability of the product.
  • the third circuit layer 145 includes a signal circuit 1451 and a plurality of first ground pads 1452 electrically isolated from the signal circuit 1451.
  • the side of the first ground pad 1452 close to the first circuit layer 12 is electrically connected to the first circuit layer 12 through the first conductive body 13, and the first ground pad 1452 is far away from the
  • One side of the first circuit layer 12 is electrically connected to the second circuit layer 22 through the second conductive body 23, and the first circuit layer 12, the first conductive body 13, and the electrical connection are electrically connected.
  • the first ground pad 1452, the second conductive body 23, and the second circuit layer 22 form a shielding shell (not shown), the signal line 1451 is located in the shielding shell, and the The shielding shell is used for shielding the high-frequency electrical signals in the signal line 1451.
  • the hot pressing zone 121 includes a copper sheet 1211, and the copper sheet 1211 is electrically connected to the non-hot pressing zone 122, and the copper sheet 1211 is provided with The second ground pad 1212 and the first signal pad 1213, the second ground pad 1212 and the first ground pad 1452 are electrically connected by the first conductive body 13, and the second ground pad
  • the disk 1212 and the copper skin 1211 are electrically connected through a plurality of microstructures 1214, the first signal pad 1213 and the signal line 1451 are electrically connected through the first conductive body 13, and the first The signal pad 1213 is electrically separated from the copper skin 1211.
  • the copper skin 1211 can shield the second signal pad 1211.
  • a part of the electrical signal in a signal pad 1213, and the second ground pad 1212 and the copper skin 1211 are connected through the microstructure 1214, which can reduce the amount of heat generated by the second ground pad 1212 during the thermal compression welding process. Conducted to the copper skin 1211, so that the heat on the second ground pad 1212 is more concentratedly conducted to the second circuit layer 22, so that the second ground pad 1212 can complete the heat at a lower temperature.
  • Pressure welding further reduces the risk of brittle sintering interface formed at the end of the second conductive body 23 due to high temperature conditions, and improves the reliability of the product.
  • the plurality of first ground pads 1452 includes two electrically conductive first ground pads 1452, and the two electrically conductive first ground pads 1452 pass through
  • the two first conductive bodies 13 are electrically connected to the copper skin 1211 and the non-hot pressing zone 122, respectively, so that the hot pressing zone 121 and the non-hot pressing zone 122 have electrical circuits. It is beneficial to improve the shielding effect of the copper skin 1211 on the first signal pad 1213.
  • the first ground pad 1452 and the second ground pad 1212 correspond to each other, and the first ground pad 1452 and the second ground pad 1212 pass through One of the first conductive bodies 13 is electrically connected, the signal line 1451 corresponds to the first signal pad 1213, and the first signal pad 1213 is connected to the first conductive body 13 through one The signal line 1451 is electrically connected.
  • the first ground pad 1452 and the second ground pad 1212 may not correspond to each other, and there is a gap between the first ground pad 1452 and the second ground pad 1212 It can be electrically connected through a plurality of the first conductive bodies 13.
  • the positional relationship between the signal line 1451 and the first signal pad 1213 and the connection between the signal line 1451 and the first signal solder The number of the first conductive bodies 13 of the disk 1213 is not limited to one, either.
  • step S2 providing the second circuit substrate 20 includes:
  • the single-sided copper-clad substrate 15 includes a second substrate layer 21 and a third copper foil layer 151.
  • the second substrate layer 21 includes a third surface 211 and a fourth surface 212 opposite to the third surface 211, and the third copper foil layer 151 is disposed on the third surface 211;
  • the single-sided copper clad substrate 15 is a flexible substrate.
  • S21 Please refer to FIG. 8 to form the second circuit layer 22 by etching on the third copper foil layer 151. Please refer to FIG. 9 to drill a plurality of second conductive lines on the second substrate layer 21 Hole 213.
  • the second via hole 213 penetrates the third surface 211 and the fourth surface 212, so that part of the second circuit layer 22 near the third surface 211 is on the first surface. The inside of the second via hole 213 is exposed.
  • a conductive paste is filled into the second conductive hole 213, and the conductive paste becomes the second conductive body 23 after being cured.
  • the three ends 231 are electrically connected to the second circuit layer 22, and the fourth end 232 of the second conductive body 23 is exposed from the second substrate layer 21.
  • the second circuit layer 22 includes at least one second signal pad 221 and at least one that is electrically isolated from the second signal pad 221
  • the third ground pad 222, and the third end 231 of the second via body 23 is electrically connected to the second signal pad 221 or the third ground pad 222.
  • step S3 before bonding the first circuit substrate 10 and the second circuit substrate 20, it includes:
  • the second signal pad 221 and the signal line 1451 may not overlap with each other but are electrically connected, and the third ground pad 222 is connected to the first signal line 1451.
  • the ground pads 1452 may not overlap the holes but are electrically connected, that is, the positions of the second end portion 132 and the fourth end portion 232 may be alternately corresponding and electrically connected.
  • the present application provides a circuit board 100, referring to FIG. 12, which includes: at least one first circuit substrate 10 and at least one second circuit substrate 20 overlapped with the first circuit substrate 10.
  • Each of the first circuit substrates 10 includes: a first base material layer 11, a first circuit layer 12, and a plurality of first conductive bodies 13 disposed in the first base material layer 11.
  • a conductive body 13 is formed by an electroplating process; wherein, the first circuit layer 12 includes an etching line 123, and the etching line 123 divides the first circuit layer 12 into a heat located in the etching line 123 The nip 121 and a non-thermal nip 122 located outside the etching line 123; the hot nip 121 includes a plurality of the first conductive bodies 13, and the first conductive bodies 13 include a first An end 131 and a second end 132 opposite to the first end 131, the first end 131 is electrically connected to the hot pressing zone 121;
  • Each of the second circuit substrates 20 includes a second base material layer 21, a second circuit layer 22, and a plurality of second conductive bodies 23, and the second conductive bodies 23 include conductive paste; wherein, the The second conductive body 23 includes a third end 231 and a fourth end 232 opposite to the third end 231, and the third end 231 is electrically connected to the second circuit layer 22;
  • the second end 132 and the fourth end 232 are electrically connected.
  • the first circuit substrate 10 further includes a third circuit layer 145 disposed on the second surface 112, and the third circuit layer 145 includes a signal circuit 1451 and a plurality of first ground pads 1452 electrically isolated from the signal line 1451.
  • the first ground pad 1452 is close to the first circuit layer 12 through the first conductive body 13 Is electrically connected to the first circuit layer 12, and the first ground pad 1452 is electrically connected to the second circuit layer 22 through the second conductive body 23 on the side far away from the first circuit layer 12.
  • the first circuit layer 12, the first conductive body 13, the first ground pad 1452, the second conductive body 23, and the second circuit layer 22 that are sexually connected form a shielding shell
  • the signal line 1451 is located in the shielding shell, and the shielding shell is used to shield high-frequency electrical signals in the signal line 1451.
  • the first substrate layer 11 is exposed in the etching line 123, the etching line 123 is in the shape of a semi-closed frame, and the etching line 123 divides the first circuit layer 12 into frames.
  • the hot pressing zone 121 includes a copper skin 1211, the copper skin 1211 is electrically connected to the non-hot pressing zone 122, and the copper skin 1211 is provided with a second ground pad 1212 and a first signal solder
  • the second grounding pad 1212 and the first grounding pad 1452 are electrically connected through the first conductive body 13
  • the second grounding pad 1212 and the copper sheet 1211 are electrically connected through a plurality of
  • the microstructure 1214 is electrically connected
  • the first signal pad 1213 and the signal line 1451 are electrically connected through the first conductive body 13
  • the first signal pad 1213 is electrically connected to the copper sheet 1211.
  • the application also provides a method for manufacturing a circuit board assembly (not shown), including the steps:
  • connection area (not shown), and the connection area is provided with solder paste;
  • the first circuit board may be a mobile phone high frequency signal transmission line
  • the second circuit board may be a mobile phone main board
  • this application includes at least the following advantages:
  • a hot press area is divided on the circuit board, and the first conductive body formed by electroplating in the hot press area is electrically connected to adjacent layers.
  • the heat conduction efficiency along the thickness of the circuit board Can be improved, thereby reducing the risk of brittle sintering interface formation.
  • the etching line on the first circuit layer By setting the etching line on the first circuit layer to divide the hot pressing zone and the non-hot pressing zone, the first substrate layer is exposed from the etching line.
  • the etching line can reduce the heat conduction from the hot pressing zone to The non-hot-pressed area makes the heat in the hot-pressed area concentrated, which facilitates welding at a lower temperature.
  • the grounding pad in the hot pressing area is connected to the copper skin through a microstructure, which is beneficial to reduce the heat conduction from the grounding pad to the copper skin, so that the heat of the grounding pad is concentrated, and it is convenient to complete the welding at a lower temperature.

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Abstract

一种电路板（100），包括至少一第一线路基板（10）及与第一线路基板（10）相叠合的至少一第二线路基板（20）；每一第一线路基板（10）包括：一第一基材层（11）、设置于所述第一基材层（11）上的一第一线路层（12）及多个第一导通体（13），第一导通体（13）通过电镀工艺形成；第一线路层（12）包括一热压区（121）及除热压区（121）外的一非热压区（122）；第一导通体（13）一端部电性连接热压区（121）另一端部露出于第一基材层（11）；每一第二线路基板（20）包括：一第二基材层（21）、设置于第二基材层（21）上的一第二线路层（22）及多个第二导通体（23），第二导通体（23）包括导电膏；第二导通体（23）一端电性连接第二线路层（22），另一端露出于第二基材层（21）；第一导通体（13）于第二导通体（23）电性导通。还提供一种电路板（100）的制造方法及一种电路板组件的制造方法。

Description

电路板及其制造方法、电路板组件的制造方法 技术领域
本申请涉及一种电路板及其制造方法、电路板组件的制造方法。
背景技术
终端电子设备中，高频传输线需要与主板进行连接。热压合工艺制造的传输线通常采用热压焊接的方法与主板焊接，但是，焊接过程中，传输线中的导电膏导热性能差、易于与铜层形成烧结界面(IMC)，导致传输线与主板连接的信赖性降低。
发明内容
有鉴于此，有必要提供一种电路板，该电路板可以通过焊接的方式与主板形成信赖的连接。
另，还有必要提供一种电路的制造方法。
另，还有必要提供一种电路板组件的制造方法。
一种电路板的制造方法，包括步骤：提供第一线路基板，所述第一线路基板包括一第一基材层、一第一线路层及设置于所述第一基材层中的多个第一导通体，所述第一导通体通过电镀工艺形成。其中，所述第一线路层包括一蚀刻线，所述蚀刻线将所述第一线路层划分为位于所述蚀刻线内的一热压区及位于所述蚀刻线外的一非热压区。所述热压区内包括多个所述第一导通体，所述第一导通体包括一第一端部及与所述第一端部相对的一第二端部， 所述第一端部电性连接所述热压区。
提供第二线路基板，所述第二线路基板包括一第二基材层、一第二线路层及多个第二导通体，所述第二导通体包括导电膏。其中，所述第二导通体包括一第三端部及与所述第三端部相对的一第四端部，所述第三端部电性连接所述第二线路层。
层叠所述第一线路基板及所述第二线路基板，使得所述第二端部与所述第四端部位置对应，得到一中间体，以及压合所述中间体，以使所述第二端部与所述第四端部电性导通，得到所述电路板。
进一步的，提供所述第一线路基板包括步骤：提供一双面覆铜基板，所述双面覆铜基板包括一所述第一基材层、一第一铜箔层及一第二铜箔层，所述第一铜箔层和所述第二铜箔层设置于所述第一基材层相对的两个表面。于所述双面覆铜基板中开设多个第一导通孔，所述第一导通孔贯穿所述第二铜箔层及所述第一基材层。于所述第二铜箔层上进行电镀以形成一电镀层，部分所述电镀层填充于所述第一导通孔中以形成所述第一导通体。以及蚀刻所述第一铜箔层以获得所述第一线路层，以及蚀刻所述第二铜箔层及所述电镀层以获得一第三线路层，获得所述第一线路基板。
进一步的，所述第三线路层包括一信号线路及与所述信号线电性隔离的多个第一接地焊盘，所述第一接地焊盘靠近所述第一线路层的一侧通过所述第一导通体电性连接所述第一线路层，所述第一接地焊盘远离所述第一线路层的一侧通过所述第二导通体电性连接所述第二线路层，电性连通的所述第一线路层、所述第一导通体、所述第一接地焊盘、所述第二导通体及所述第 二线路层形成一屏蔽壳体，所述信号线位于所述屏蔽壳体内。
进一步的，多个所述第一接地焊盘中包括两个电性导通的第一接地焊盘，所述两个电性导通的第一接地焊盘通过两个所述第一导通体分别电性连接于所述热压区及所述非热压区，使得所述热压区与所述非热压区电性导通。
进一步的，所述热压区内包括一铜皮，所述铜皮与所述非热压区电性导通，所述铜皮内设置有第二接地焊盘及第一信号焊盘，所述第二接地焊盘与所述第一接地焊盘通过所述第一导通体电性连接，所述第二接地焊盘与所述铜皮通过多个微结构电性导通，所述第一信号焊盘与所述信号线路通过所述第一导通体电性连接，所述第一信号焊盘与所述铜皮电性隔断。
进一步的，提供所述第二线路基板包括步骤：提供一单面覆铜基板，所述单面覆铜基板包括一第二基材层及形成于所述第二基材层表面的一第三铜箔层。蚀刻所述第三铜箔层以形成所述第二线路层。于所述第二基材层中开设多个第二导通孔，所述第二导通孔贯穿所述第二基材层。向所述第二导通孔内填充导电膏，得到所述第二导通体，从而获得所述第二线路基板。
进一步的，所述第二线路层包括至少一第二信号焊盘及与所述第二信号焊盘电性隔断的至少一第三接地焊盘，所述第二导通体的所述第三端部电性连接所述第二信号焊盘或所述第三接地焊盘。
进一步的，层叠所述第一线路基板及所述第二线路基板时，所述第二信号焊盘与所述信号线路相对应，所述第三接地焊盘与所述第一接地焊盘相对应。
进一步的，所述第一线路基板及所述第二线路基板都为柔性电路基板。
一种电路板，包括：至少一第一线路基板及与所述第一线路基板相叠合的至少一第二线路基板。每一所述第一线路基板包括一第一基材层、一第一线路层及设置于所述第一基材层中的多个第一导通体，所述第一导通体通过电镀工艺形成；其中，所述第一线路层包括一蚀刻线，所述蚀刻线将所述第一线路层划分为位于所述蚀刻线内的一热压区及位于所述蚀刻线外的一非热压区；所述第一导通体在所述第一线路层上的投影位于所述热压区内，所述第一导通体包括一第一端部及与所述第一端部相对的一第二端部，所述第一端部电性连接所述热压区。每一所述第二线路基板包括一第二基材层、一第二线路层及多个第二导通体，所述第二导通体包括导电膏；其中，所述第二导通体包括一第三端部及与所述第三端部相对的一第四端部，所述第三端部电性连接所述第二线路层。所述第二端部与所述第四端部电性导通。
进一步的，所述第一线路基板还包括设于所述第二表面的一第三线路层，所述第三线路层包括一信号线路及与所述信号线电性隔离的多个第一接地焊盘，所述第一接地焊盘靠近所述第一线路层的一侧通过所述第一导通体电性连接所述第一线路层，所述第一接地焊盘远离所述第一线路层的一侧通过所述第二导通体电性连接所述第二线路层，电性连通的所述第一线路层、所述第一导通体、所述第一接地焊盘、所述第二导通体及所述第二线路层形成一屏蔽壳体，所述信号线位于所述屏蔽壳体内。
进一步的，所述第一基材层于所述蚀刻线内露出，所述蚀刻线呈半封闭框状，所述蚀刻线将所述第一线路层划分为框内的所述热压区及框外的非热 压区。所述热压区内包括一铜皮，所述铜皮与所述非热压区电性导通，所述铜皮内设置有第二接地焊盘及第一信号焊盘，所述第二接地焊盘与所述第一接地焊盘通过所述第一导通体电性连接，所述第二接地焊盘与所述铜皮通过多个微结构电性导通，所述第一信号焊盘与所述信号线路通过所述第一导通体电性连接，所述第一信号焊盘与所述铜皮电性隔断。
一种电路板组件的制造方法，包括步骤：
提供一第一电路板，所述第一电路板为上所述电路板。
提供一第二电路板，所述第二电路板包括一连接区域，所述连接区域设置有锡膏。
将所述第一电路板叠设在所述第二电路板上，并使得所述连接区域与所述热压区相对。
加热所述第一电路的热压区，所述热压区的热量通过所述第一导通体及所述第二导通体传导至所述第一电路板与所述第二电路板贴合的一侧，并熔化所述锡膏，冷却获得所述电路板组件。
与现有技术相比，本申请提供的电路板及其制造方法至少包括以下优点：
(一)在电路板上划分出一热压区，在热压区内通过电镀形成的第一导通体电性连接相邻层，热压焊接过程中，热量沿电路板厚度方向的传导效率得以提高，进而降低形成脆性烧结界面的风险。
(二)通过在第一线路层上设置蚀刻线划分热压区及非热压区，第一基材层从蚀刻线露出，热压焊接过程中，蚀刻线可以减少热量由热压区传导至 非热压区域，使得热压区的热量集中，便于在较低的温度下完成焊接。
(三)热压区内的接地焊盘通过微结构与铜皮连接，有利于减少热量由接地焊盘传导至铜皮，使得接地焊盘的热量集中，便于在较低温度下完成焊接。
附图说明
图1为本申请实施例提供的双面覆铜基板的示意图。
图2为图1所示的双面覆铜基板上钻取第一导通孔后的示意图。
图3为图2所示第一导通孔电镀填充第一导通体后的示意图。
图4为蚀刻图3获得的第一线路基板示意图。
图5为图4所示线路基板的底示图。
图6为图4所示线路基板的俯视图。
图7为本申请实施例提供的单面覆铜基板的示意图。
图8为蚀刻图7所示单面覆铜基板获得第二线路层后的示意图。
图9为图8钻取第二导通孔后的示意图。
图10为图9所示第二导通孔填充导电膏以获得第二线路基板的示意图。
图11为图10所示的第二线路基板的俯视图。
图12为本申请实施例提供的电路板的示意图。
主要元件符号说明
电路板            100    第一导通孔        143
第一线路基板       10     电镀层           144
第一基材层         11     第三线路层       145
第一表面          111    信号线路         1451
第二表面          112    第一接地焊盘     1452
第一线路层        12     单面覆铜基板      15
铜皮             1211    第三铜箔层        151
第二接地焊盘     1212    第二基材层        21
第一信号焊盘     1213    第二线路基板      20
微结构           1214    第三表面          211
热压区            121    第四表面          212
非热压区          122    第二导通孔        213
蚀刻线            123    第二线路层        22
第一导通体         13     第二信号焊盘     221
第一端部          131    第三接地焊盘      222
第二端部          132    第二导通体        23
双面覆铜基板       14     第三端部         231
第一铜箔层        141    第四端部          232
第二铜箔层        142
如下具体实施方式将结合上述附图进一步说明本申请。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用 的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
本申请实施例提供一种电路板100的制造方法，包括步骤：
S1:请参见图4，提供至少一第一线路基板10，所述第一线路基板10包括一第一基材层11、一第一线路层12及多个第一导通体13，所述第一导通体13通过电镀工艺形成；
所述第一基材层11包括一第一表面111及与所述第一表面111相对的一第二表面112，所述第一线路层12设置于所述第一表面111；
所述第一线路层12包括一蚀刻线123，所述蚀刻线123将所述第一线路层12划分为位于所述蚀刻线123内的一热压区121及位于所述蚀刻线123外的一非热压区122，所述热压区121内包括多个所述第一导通体13；
所述第一导通体13包括一第一端部131及与所述第一端部131相对的一第二端部132，所述第一端部131电性连接所述热压区121，所述第二端部132露出于所述第二表面112。
S2:请参见图10，提供至少一第二线路基板20，所述第二线路基板20包括一第二基材层21、一第二线路层22及多个第二导通体23，所述第二导通体23包括导电膏；
所述第二基材层21包括一第三表面211及与所述第三表面211相对的一第四表面212，所述第二线路层22设置于所述第三表面211；
所述第二导通体23包括一第三端部231及与所述第三端部231相对的一第四端部232，所述第三端部231电性连接所述第二线路层22，所述第四端部232露出于所述第四表面212。
S3:层叠每一所述第一线路基板10及每一所述第二线路基板20，并使得所述第二端部132与所述第四端部232位置对应，得到一中间体(图未示)。
S4:请参见图12，压合所述中间体以得到所述电路板100，所述第二端部132与所述第四端部232电性导通。
在本实施例中，具体将所述电路板100与一主板(图未示)通过热压发生焊接时，首先需要在所述主板的连接区域(图未示)设置锡膏，所述连接区域与所述第一线路层12的所述热压区121相对应，然后将所述电路板100的所述第二线路层22贴合在所述连接区域的锡膏上，一热压头抵压在所述第一线路层12的所述热压区121内，所述热压头加热所述热压区121，所述热压区121的热量通过所述第一导通体13与所述第二导通体23传导至所述第二线路层22，然后与所述第二线路层22直接接触的所述锡膏被加热熔化，同时所述热压头向所述电路板100施加压力，熔化的所述锡膏充分接触所述第二线路层22与所述主板的连接区域，冷却后，所述电路板100与所述主板完成焊接。
在本实施例中，步骤S1中，提供所述第一线路基板10包括：
S10:请参见图1，提供一双面覆铜基板14，所述双面覆铜基板14包括一第一基材层11、一第一铜箔层141及一第二铜箔层142，所述第一基材层11包括一第一表面111及与所述第一表面111相对的一第二表面112，所述第一铜箔层141设置于所述第一表面111，所述第二铜箔层142设置于所述第二表面112。
在本实施例中，所述双面覆铜基板14为柔性基板。
S11:请参见图2，于所述双面覆铜基板14上钻取多个第一导通孔143，所述第一导通孔143贯穿所述第二铜箔层142及所述第一基材层11的第一表面111和第二表面112，所述第一铜箔层141靠近所述第二铜箔层142的一侧于所述第一导通孔143露出。
S12:请参见图3，于所述第二铜箔层142上进行电镀以形成一电镀层144，部分所述电镀层144填充于所述第一导通孔143中以形成所述第一导通体13。
在本实施例中，步骤S12中，所述热压区121及所述非热压区122均通过电镀的方式在所述第一导通孔143内形成所述第一导通体13。在本申请的其他实施例中，所述热压区121通过电镀的方式在所述第一导通孔143内形成所述第一导通体13，所述非热压区122通过填入导电膏的方式在所述第一导通孔143内形成所述电镀导通体(图未示)。
S13:请参见图4，蚀刻所述第一铜箔层141以获得所述第一线路层12，以及蚀刻所述第二铜箔层142及所述电镀层144以获得一第三线路层145。
在本实施例中，请参见图5，步骤S13中，所述第一基材层11于所述蚀刻线123内露出，所述蚀刻线123呈半封闭框状，所述蚀刻线123将所述第一线路层12划分为框内的所述热压区121及框外的非热压区122。通过设置半封闭框状的所述蚀刻线123可以有效地减少热量由所述热压区121(即所述蚀刻线123的框内)传导至所述非热压区122，使得所述热压区121内的主要热量通过所述第一导通体13与所述第二导通体23传导至所述第二线路层22，使得所述热压区121可以在承受较低温度的情况下完成热压焊接，从 而可以降低所述第二导通体23的端部因高温情况下形成易脆烧结界面的风险，有利于提高产品的信赖性。
在本实施例中，请参见图6及图12，步骤S13中，所述第三线路层145包括一信号线路1451及与所述信号线路1451电性隔离的多个第一接地焊盘1452，所述第一接地焊盘1452靠近所述第一线路层12的一侧通过所述第一导通体13电性连接所述第一线路层12，所述第一接地焊盘1452远离所述第一线路层12的一侧通过所述第二导通体23电性连接所述第二线路层22，电性连通的所述第一线路层12、所述第一导通体13、所述第一接地焊盘1452、所述第二导通体23及所述第二线路层22形成一屏蔽壳体(图未示)，所述信号线路1451路位于所述屏蔽壳体内，所述屏蔽壳体用于屏蔽所述信号线路1451内的高频电信号。
在本实施例中，请参见图5，所述热压区121内包括一铜皮1211，所述铜皮1211与所述非热压区122电性导通，所述铜皮1211内设置有第二接地焊盘1212及第一信号焊盘1213，所述第二接地焊盘1212与所述第一接地焊盘1452通过所述第一导通体13电性连接，所述第二接地焊盘1212与所述铜皮1211通过多个微结构1214电性导通，所述第一信号焊盘1213与所述信号线路1451通过所述第一导通体13电性连接，所述第一信号焊盘1213与所述铜皮1211电性隔断。通过将所述第二接地焊盘1212导通所述铜皮1211，并在所述铜皮1211与所述第一信号焊盘1213之间做隔断设计，所述铜皮1211可以屏蔽所述第一信号焊盘1213内的部分电信号，而且，通过微结构1214连接所述第二接地焊盘1212与所述铜皮1211，可减少在热压焊接 的过程中热量由第二接地焊盘1212传导至铜皮1211上，使得所述第二接地焊盘1212上的热量更加集中地传导至所述第二线路层22，使得所述第二接地焊盘1212可以在更低温度情况下完成热压焊接，从而进一步的降低所述第二导通体23的端部因高温情况下形成易脆烧结界面的风险，提高产品的信赖性。
进一步地，请参见图6，多个所述第一接地焊盘1452中包括两个电性导通的第一接地焊盘1452，所述两个电性导通的第一接地焊盘1452通过两个所述第一导通体13分别电性连接于所述铜皮1211及所述非热压区122，从而使得所述热压区121及所述非热压区122电性线路，有利于提高所述铜皮1211对所述第一信号焊盘1213屏蔽的效果。
在本实施例中，请参见图12，所述第一接地焊盘1452及所述第二接地焊盘1212相对应，且所述第一接地焊盘1452与所述第二接地焊盘1212通过一个所述第一导通体13电性相连，所述信号线路1451与所述第一信号焊盘1213相对应，且所述第一信号焊盘1213通过一个所述第一导通体13与所述信号线路1451电性相连。在本申请的其他实施例中，所述第一接地焊盘1452与所述第二接地焊盘1212可以不对应，且所述第一接地焊盘1452及所述第二接地焊盘1212之间可以通过多个所述第一导通体13电性相连，同理，所述信号线路1451与所述第一信号焊盘1213的位置关系及连接所述信号线路1451及所述第一信号焊盘1213的第一导通体13的数量也不限于一个。
在本实施例中，步骤S2中，提供所述第二线路基板20包括：
S20:请参见图7，提供一单面覆铜基板15，所述单面覆铜基板15包括一第二基材层21及一第三铜箔层151。所述第二基材层21包括一第三表面211及与所述第三表面211相对的一第四表面212，所述第三铜箔层151设置于所述第三表面211上；
在本实施例中，所述单面覆铜基板15为柔性基板。
S21:请参见图8，于所述第三铜箔层151上蚀刻形成所述第二线路层22，请参见图9，于所述第二基材层21上钻取多个第二导通孔213，所述第二导通孔213贯穿所述第三表面211及所述第四表面212，以使得部分所述第二线路层22靠近所述第三表面211的一侧于所述第二导通孔213内露出。
S22:请参见图10，向所述第二导通孔213内填入导电膏，所述导电膏固化后成为所述第二导通体23，所述第二导通体23的所述第三端部231电性连接于所述第二线路层22，所述第二导通体23的第四端部232露出于所述第二基材层21。
在本实施例中，请参见图11，步骤S21及步骤S22中，所述第二线路层22包括至少一第二信号焊盘221及与所述第二信号焊盘221电性隔断的至少一第三接地焊盘222，所述第二导通体23的所述第三端部231电性连接所述第二信号焊盘221或所述第三接地焊盘222。
在本实施例中，步骤S3中，贴合所述第一线路基板10及所述第二线路基板20之前包括：
S30:设置所述第一线路基板10的所述第三线路层145朝向所述第二线路基板20的所述第二基材层21；
S31:贴合所述第二线路基板20及所述第二基材层21，并使得所述第二信号焊盘221与所述信号线路1451相对应，所述第三接地焊盘222与所述第一接地焊盘1452相对应；
在本申请的其他实施例中，步骤S31中，所述第二信号焊盘221与所述信号线路1451可以不叠孔对应但电性连通，所述第三接地焊盘222与所述第一接地焊盘1452可以不叠孔对应但电性连通，即，所述第二端部132与所述第四端部232位置可以交错对应并电性连通。
本申请提供一种电路板100，请参见图12，包括：至少一第一线路基板10及与所述第一线路基板10相叠合的至少一第二线路基板20。
每一所述第一线路基板10包括：一第一基材层11、一第一线路层12及设置于所述第一基材层11中的多个第一导通体13，所述第一导通体13通过电镀工艺形成；其中，所述第一线路层12包括一蚀刻线123，所述蚀刻线123将所述第一线路层12划分为位于所述蚀刻线123内的一热压区121及位于所述蚀刻线123外的一非热压区122；所述热压区121内包括多个所述第一导通体13，所述第一导通体13包括一第一端部131及与所述第一端部131相对的一第二端部132，所述第一端部131电性连接所述热压区121；
每一所述第二线路基板20包括一第二基材层21、一第二线路层22及多个第二导通体23，所述第二导通体23包括导电膏；其中，所述第二导通体23包括一第三端部231及与所述第三端部231相对的一第四端部232，所述第三端部231电性连接所述第二线路层22；
所述第二端部132与所述第四端部232电性导通。
在本实施例中，请参见图1至图12，所述第一线路基板10还包括设于所述第二表面112的一第三线路层145，所述第三线路层145包括一信号线路1451及与所述信号线路1451电性隔离的多个第一接地焊盘1452，所述第一接地焊盘1452靠近所述第一线路层12的一侧通过所述第一导通体13电性连接所述第一线路层12，所述第一接地焊盘1452远离所述第一线路层12的一侧通过所述第二导通体23电性连接所述第二线路层22，电性连通的所述第一线路层12、所述第一导通体13、所述第一接地焊盘1452、所述第二导通体23及所述第二线路层22形成一屏蔽壳体，所述信号线路1451位于所述屏蔽壳体内，所述屏蔽壳体用于屏蔽所述信号线路1451内的高频电信号。
在本实施例中，所述第一基材层11于所述蚀刻线123内露出，所述蚀刻线123呈半封闭框状，所述蚀刻线123将所述第一线路层12划分为框内的所述热压区121及框外的非热压区122。
所述热压区121内包括一铜皮1211，所述铜皮1211与所述非热压区122电性导通，所述铜皮1211内设置有第二接地焊盘1212及第一信号焊盘1213，所述第二接地焊盘1212与所述第一接地焊盘1452通过所述第一导通体13电性连接，所述第二接地焊盘1212与所述铜皮1211通过多个微结构1214电性导通，所述第一信号焊盘1213与所述信号线路1451通过所述第一导通体13电性连接，所述第一信号焊盘1213与所述铜皮1211电性隔断。
本申请还提供一种电路板组件(图未示)的制造方法，包括步骤：
(一)提供一第一电路板(图未示)，所述第一电路板为以上所述电路 板100；
(二)提供一第二电路板(图未示)，所述第二电路板包括一连接区域(图未示)，所述连接区域设置有锡膏；
(三)将所述第一电路板叠设在所述第二电路板上，并使得所述连接区域与所述热压区121相对；
(四)加热所述第一电路板的热压区121，所述热压区121的热量通过所述第一导通体13及所述第二导通体23传导至所述第一电路板与所述第二电路板贴合的一侧，并熔化所述锡膏，冷却获得所述电路板组件。
在本实施例中，步骤(二)中，所述第一电路板可以为手机高频信号传输线，所述第二电路板可以为手机主板。
与现有技术相比，本申请至少包括以下优点：
(一)在电路板上划分出一热压区，在热压区内通过电镀形成的第一导通体电性连接相邻层，热压焊接过程中，热量沿电路板厚度方向的传导效率得以提高，进而降低形成脆性烧结界面的风险。
(二)通过在第一线路层上设置蚀刻线划分热压区及非热压区，第一基材层从蚀刻线露出，热压焊接过程中，蚀刻线可以减少热量由热压区传导至非热压区域，使得热压区的热量集中，便于在较低的温度下完成焊接。
(三)热压区内的接地焊盘通过微结构与铜皮连接，有利于减少热量由接地焊盘传导至铜皮，使得接地焊盘的热量集中，便于在较低温度下完成焊接。
另外，对于本领域的普通技术人员来说，可以根据本申请的技术构思做 出其它各种相应的改变与变形，而所有这些改变与变形都应属于本申请的保护范围。

Claims (13)

  1. 一种电路板的制造方法，其特征在于，包括步骤：
    提供第一线路基板，所述第一线路基板包括一第一基材层、一第一线路层及设置于所述第一基材层中的多个第一导通体，所述第一导通体通过电镀工艺形成；其中，所述第一线路层包括一蚀刻线，所述蚀刻线将所述第一线路层划分为位于所述蚀刻线内的一热压区及位于所述蚀刻线外的一非热压区；所述热压区内包括多个所述第一导通体，所述第一导通体包括一第一端部及与所述第一端部相对的一第二端部，所述第一端部电性连接所述热压区；
    提供第二线路基板，所述第二线路基板包括一第二基材层、一第二线路层及多个第二导通体，所述第二导通体包括导电膏；其中，所述第二导通体包括一第三端部及与所述第三端部相对的一第四端部，所述第三端部电性连接所述第二线路层；
    层叠所述第一线路基板及所述第二线路基板，使得所述第二端部与所述第四端部位置对应，得到一中间体，以及
    压合所述中间体，以使所述第二端部与所述第四端部电性导通，得到所述电路板。
  2. 如权利要求1所述的电路板的制造方法，其特征在于，提供所述第一线路基板包括步骤：
    提供一双面覆铜基板，所述双面覆铜基板包括一所述第一基材层、一第一铜箔层及一第二铜箔层，所述第一铜箔层和所述第二铜箔层设置于所述第 一基材层相对的两个表面；
    于所述双面覆铜基板中开设多个第一导通孔，所述第一导通孔贯穿所述第二铜箔层及所述第一基材层；
    于所述第二铜箔层上进行电镀以形成一电镀层，部分所述电镀层填充于所述第一导通孔中以形成所述第一导通体；以及
    蚀刻所述第一铜箔层以获得所述第一线路层，以及蚀刻所述第二铜箔层及所述电镀层以获得一第三线路层，获得所述第一线路基板。
  3. 如权利要求2所述的电路板的制造方法，其特征在于，所述第三线路层包括一信号线路及与所述信号线电性隔离的多个第一接地焊盘，所述第一接地焊盘靠近所述第一线路层的一侧通过所述第一导通体电性连接所述第一线路层，所述第一接地焊盘远离所述第一线路层的一侧通过所述第二导通体电性连接所述第二线路层，电性连通的所述第一线路层、所述第一导通体、所述第一接地焊盘、所述第二导通体及所述第二线路层形成一屏蔽壳体，所述信号线位于所述屏蔽壳体内。
  4. 如权利要求3所述的电路板的制造方法，其特征在于，多个所述第一接地焊盘中包括两个电性导通的第一接地焊盘，所述两个电性导通的第一接地焊盘通过两个所述第一导通体分别电性连接于所述热压区及所述非热压区，使得所述热压区与所述非热压区电性导通。
  5. 如权利要求4所述的电路板的制造方法，其特征在于，所述热压区内包括一铜皮，所述铜皮与所述非热压区电性导通，所述铜皮内设置有第二接地焊盘及第一信号焊盘，所述第二接地焊盘与所述第一接地焊盘通过所述第 一导通体电性连接，所述第二接地焊盘与所述铜皮通过多个微结构电性导通，所述第一信号焊盘与所述信号线路通过所述第一导通体电性连接，所述第一信号焊盘与所述铜皮电性隔断。
  6. 如权利要求4所述的电路板的制造方法，其特征在于，提供所述第二线路基板包括步骤：
    提供一单面覆铜基板，所述单面覆铜基板包括一第二基材层及形成于所述第二基材层表面的一第三铜箔层；
    蚀刻所述第三铜箔层以形成所述第二线路层；
    于所述第二基材层中开设多个第二导通孔，所述第二导通孔贯穿所述第二基材层；
    向所述第二导通孔内填充导电膏，得到所述第二导通体，从而获得所述第二线路基板。
  7. 如权利要求6所述的电路板的制造方法，其特征在于，所述第二线路层包括至少一第二信号焊盘及与所述第二信号焊盘电性隔断的至少一第三接地焊盘，所述第二导通体的所述第三端部电性连接所述第二信号焊盘或所述第三接地焊盘。
  8. 如权利要求7所述的电路板的制造方法，其特征在于，层叠所述第一线路基板及所述第二线路基板时，所述第二信号焊盘与所述信号线路相对应，所述第三接地焊盘与所述第一接地焊盘相对应。
  9. 如权利要求1所述的电路板的制造方法，其特征在于，所述第一线路基板及所述第二线路基板都为柔性电路基板。
  10. 一种电路板，其特征在于，包括：至少一第一线路基板及与所述第一线路基板相叠合的至少一第二线路基板；
    每一所述第一线路基板包括一第一基材层、一第一线路层及设置于所述第一基材层中的多个第一导通体，所述第一导通体通过电镀工艺形成；其中，所述第一线路层包括一蚀刻线，所述蚀刻线将所述第一线路层划分为位于所述蚀刻线内的一热压区及位于所述蚀刻线外的一非热压区；所述热压区内包括多个所述第一导通体，所述第一导通体包括一第一端部及与所述第一端部相对的一第二端部，所述第一端部电性连接所述热压区；
    每一所述第二线路基板包括一第二基材层、一第二线路层及多个第二导通体，所述第二导通体包括导电膏；其中，所述第二导通体包括一第三端部及与所述第三端部相对的一第四端部，所述第三端部电性连接所述第二线路层；
    所述第二端部与所述第四端部电性导通。
  11. 如权利要求10所述的电路板，其特征在于，所述第一线路基板还包括与所述第一线路层相对的一第三线路层，所述第三线路层包括一信号线路及与所述信号线电性隔离的多个第一接地焊盘，所述第一接地焊盘靠近所述第一线路层的一侧通过所述第一导通体电性连接所述第一线路层，所述第一接地焊盘远离所述第一线路层的一侧通过所述第二导通体电性连接所述第二线路层，电性连通的所述第一线路层、所述第一导通体、所述第一接地焊盘、所述第二导通体及所述第二线路层形成一屏蔽壳体，所述信号线位于所述屏蔽壳体内。
  12. 如权利要求11所述的电路板，其特征在于，所述第一基材层于所述蚀刻线内露出，所述蚀刻线呈半封闭框状，所述蚀刻线将所述第一线路层划分为框内的所述热压区及框外的非热压区；
    所述热压区内包括一铜皮，所述铜皮与所述非热压区电性导通，所述铜皮内设置有第二接地焊盘及第一信号焊盘，所述第二接地焊盘与所述第一接地焊盘通过所述第一导通体电性连接，所述第二接地焊盘与所述铜皮通过多个微结构电性导通，所述第一信号焊盘与所述信号线路通过所述第一导通体电性连接，所述第一信号焊盘与所述铜皮电性隔断。
  13. 一种电路板组件的制造方法，其特征在于，包括步骤：
    提供一第一电路板，所述第一电路板为权利要求10至12中任意一项所述电路板；
    提供一第二电路板，所述第二电路板包括一连接区域，所述连接区域设置有锡膏；
    将所述第一电路板叠设在所述第二电路板上，并使得所述连接区域与所述热压区相对；
    加热所述第一电路的热压区，所述热压区的热量通过所述第一导通体及所述第二导通体传导至所述第一电路板与所述第二电路板贴合的一侧，并熔化所述锡膏，冷却获得所述电路板组件。
PCT/CN2020/093452 2019-08-31 2020-05-29 电路板及其制造方法、电路板组件的制造方法 WO2021036379A1 (zh)

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