WO2021027007A1 - 一种液晶显示面板及其制备方法 - Google Patents

一种液晶显示面板及其制备方法 Download PDF

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Publication number
WO2021027007A1
WO2021027007A1 PCT/CN2019/106211 CN2019106211W WO2021027007A1 WO 2021027007 A1 WO2021027007 A1 WO 2021027007A1 CN 2019106211 W CN2019106211 W CN 2019106211W WO 2021027007 A1 WO2021027007 A1 WO 2021027007A1
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Prior art keywords
substrate
liquid crystal
layer
display panel
crystal display
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Ceased
Application number
PCT/CN2019/106211
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English (en)
French (fr)
Inventor
仇梦禹
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US16/617,810 priority Critical patent/US11156889B1/en
Publication of WO2021027007A1 publication Critical patent/WO2021027007A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13398—Spacer materials; Spacer properties
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • This application relates to the field of liquid crystal display technology, and in particular to a liquid crystal display panel and a preparation method thereof.
  • Thin Film Transistor-Liquid Crystal Display is generally composed of a first substrate, a second substrate, and a liquid crystal layer (Liquid Crystal Display) arranged between the two substrates. Crystal, referred to as LC).
  • the first substrate and the second substrate are fabricated separately, the first substrate may be a color filter (CF) substrate, the second substrate may be a thin film transistor (TFT) array substrate, and the first and second substrates are paired After grouping, a liquid crystal cell is formed.
  • CF color filter
  • TFT thin film transistor
  • VA(Vertical Alignment, vertical alignment) mode and TN (Twisted Nematic, twisted nematic) mode is very important two liquid crystal display modes, VA mode and TN mode liquid crystal display panel, the liquid crystal capacitor is composed of the pixel electrode (Pixel Electrode) and the CF substrate side common electrode (CF-COM) are formed, and the deflection of liquid crystal molecules is controlled according to the voltage loaded on both ends of the liquid crystal capacitor.
  • CF-COM CF substrate side common electrode
  • the common voltage (COM) signal on the CF substrate side of the VA mode and TN mode liquid crystal display panels in the prior art is given by the driver IC on the TFT array substrate side by bonding, and then enters the circuit on the TFT array substrate , And then through the transfer pad (Transfer Pad) and gold ball (Au Ball) conduction to the CF substrate side.
  • the transfer pad Transfer Pad
  • Au Ball gold ball
  • Figure 1 is an equivalent circuit diagram of a pixel in a VA mode or TN mode display panel
  • Figure 2 is a cross-sectional view of the film structure of an existing liquid crystal display panel
  • Figure 3 is an existing liquid crystal display
  • Fig. 4 is a schematic diagram of the conduction structure of two substrates of a conventional liquid crystal display panel
  • Fig. 5 is a schematic plan view of the peripheral arrangement of the liquid crystal display panel shown in Fig. 4.
  • the storage capacitor Cst and the liquid crystal capacitor Clc are the two most important capacitors of the pixel.
  • the two electrodes of the liquid crystal capacitor Clc are pixel electrodes (which are connected to the source of the thin film transistor T1 of the pixel).
  • the two electrodes of the storage capacitor Cst are the pixel electrode and the TFT array substrate side common electrode (Array-COM, hereinafter referred to as A-COM) 12 respectively.
  • the drain of the thin film transistor T1 is connected to the data signal line (Data) 13, and the gate of the thin film transistor T1 is connected to the scan signal line (Scan) 14.
  • the function of the storage capacitor Cst is generally to maintain the stability of the potential of the pixel electrode, and the function of the liquid crystal capacitor Clc is to control the rotation of the liquid crystal molecules according to the voltage loaded on both ends of the capacitor.
  • the film structure of the existing liquid crystal display panel includes: a CF substrate 21, a TFT array substrate 22, and a liquid crystal layer 23 disposed between the two substrates.
  • the CF substrate 21 includes: a CF-side substrate 211 and a first transparent conductive layer 212 disposed on the CF-side substrate 211.
  • the TFT array substrate 22 includes: a TFT-side base substrate 221, a first metal layer, a gate insulating layer (GI) 223, and an active layer 224 sequentially disposed on the TFT-side base substrate 221 , A second metal layer, a passivation layer (PAV/PFA) 226, and a second transparent conductive layer (ITO) 227.
  • PAV/PFA passivation layer
  • ITO transparent conductive layer
  • Pattern processing is performed on the first metal layer to form a gate 2221 of a thin film transistor, an A-COM 2222, and a common voltage signal line 2223 on the CF substrate side (shown in FIG. 4);
  • the second metal layer is patterned to form the drain 2251 and the source 2252 of the thin film transistor;
  • the first transparent conductive layer 212 includes a CF-COM 2122;
  • the second transparent conductive layer 227 includes a pixel electrode 2271
  • the pixel electrode 2271 and the source electrode 2252 are connected through a through hole 2261 provided on the passivation layer 226.
  • the storage capacitor Cst is formed between the A-COM 2222 and the pixel electrode 2271, and the liquid crystal capacitor Clc is formed between the pixel electrode 2271 and the CF-COM 2122 (indicated by a dotted line in the figure).
  • the two substrates of the liquid crystal display panel are paired to form a liquid crystal cell.
  • the outer circle of the liquid crystal display panel is made of sealant material to form a sealed ring pattern (Pattern) of the sealant layer 31 ,
  • the liquid crystal layer 23 is enclosed therein.
  • a chip on film (COF) 32 is used to bond a PCBA board 33 provided with a driver IC to the TFT array substrate 22 of the liquid crystal display panel. Since the driver IC is directly connected to the TFT array substrate 22, its output signal also enters the wiring on the TFT array substrate 22 first.
  • the common voltage signal line 2223 on the CF substrate side of the TFT array substrate 22 is connected to the driver IC (not shown in the figure), and the Au Ball 41 is outside the frame sealant layer 31,
  • the second transparent conductive layer 227 connected to the common voltage signal line 2223 on the CF substrate side is exposed.
  • the CF substrate-side common voltage signal given by the driver IC first enters the CF substrate-side common voltage signal line 2223 of the TFT array substrate 22, and then the CF substrate is transferred through the second transparent conductive layer 227 and a gold ball 41.
  • the side common voltage signal is conducted to the CF-COM 2122 of the CF substrate 21.
  • the width of the frame sealant layer 31 is d1
  • the center of the frame sealant layer 31 and the center of the golden ball 41 are staggered by a distance ⁇ d, so that The golden ball 41 will exceed the frame sealing glue layer 31 by a distance d2.
  • the total width occupied by the frame-sealing adhesive layer 31 and the golden ball 41 is d1+d2.
  • this width is above 1mm. This width is comparable to splicing wall products. Larger ones will make it difficult to compress the panel frame, which is not conducive to the realization of narrow-frame panels.
  • a display area (AA area) 51 often has a large number of patterned transparent conductive layers (ITO Pattern) is used for crossovers between different layers. These ITO patterns are generally connected to different signal lines. These ITO patterns cannot enter the area of the frame sealant layer 31, otherwise the golden ball 41 in the frame sealant layer 31 will conduct these ITO patterns with the CF-COM 2122, causing input The panel signal is short-circuited with CF-COM, causing the screen display to be abnormal. Therefore, the frame sealing adhesive layer 31 needs to maintain a safe distance d3 from the AA area of the panel. The existence of this distance will also make it difficult to continue to compress the frame of the display panel in the VA mode and the TN mode.
  • ITO Pattern transparent conductive layers
  • the purpose of the present application is to provide a liquid crystal display panel and a manufacturing method thereof in view of the problems existing in the prior art, which can optimize the structure of the peripheral area of the panel and realize a narrower frame.
  • the present application provides a liquid crystal display panel, the liquid crystal display panel comprising a first substrate, a second substrate disposed opposite to each other, and is disposed between the first substrate and the second substrate A liquid crystal layer, a non-display area of the liquid crystal display panel is provided with a sealant layer that encloses the liquid crystal layer;
  • the first substrate includes a first transparent conductive layer, and the first transparent conductive layer includes A first common electrode;
  • the second substrate includes: a second base substrate, a first metal layer, a gate insulating layer, a passivation layer, and a first base substrate disposed on the second base substrate
  • Two transparent conductive layers, the first metal layer includes a second common voltage signal line, the second transparent conductive layer and the second common voltage signal line are connected by a through hole, wherein the non-display Area, a second conductive material is provided between the first substrate and the second substrate, and the second conductive material is in contact with the first transparent conductive layer and the second transparent conductive layer, respectively;
  • the present application also provides a liquid crystal display panel.
  • the liquid crystal display panel includes a first substrate, a second substrate, and a first substrate and a second substrate disposed opposite to each other.
  • a liquid crystal layer between, a non-display area of the liquid crystal display panel is provided with a sealant layer that encloses the liquid crystal layer;
  • the first substrate includes a first transparent conductive layer, the first transparent conductive layer Including a first common electrode;
  • the liquid crystal display panel also includes a side bonding pad, the side bonding pad is provided on the side of the first substrate and the second substrate and the frame sealant layer On the side away from the liquid crystal layer, the side bonding pads are in contact with the first transparent conductive layer; and a side surface of the liquid crystal display panel where the side bonding pads are provided is bonded with a chip-on-chip film ,
  • the first transparent conductive layer is electrically connected to a third common voltage signal line on the chip on film through the side bonding pads, so that the first common electrode receives
  • the present application also provides a method for manufacturing a liquid crystal display panel, which includes the following steps: (1) On the sides of a first substrate and a second substrate, and a sealant layer away from a liquid crystal layer The first conductive material is printed on one side of the substrate to prepare a side bonding pad.
  • the side bonding pad is in contact with a first transparent conductive layer of the first substrate, and the first transparent conductive layer includes a first common Electrode; and (2) a flip chip film is attached to the side of the liquid crystal display panel where the side bonding pad is provided, and the first transparent conductive layer is connected to the cover through the side bonding pad A third common voltage signal line on the chip film is electrically connected, so that the first common electrode receives a common voltage signal transmitted by the chip on film.
  • the present application improves the peripheral structure of the display panel, which not only realizes the transmission of the common voltage signal on the CF substrate side to the CF substrate, but also saves the process of golden ball, and effectively compresses the peripheral space of the panel, which effectively improves the product quality of the liquid crystal display panel. Rate, improve product production efficiency and enhance product competitiveness.
  • FIG. 2 is a cross-sectional view of the film structure of a conventional liquid crystal display panel
  • FIG. 3 is a schematic diagram of joining of a conventional liquid crystal display panel
  • FIG. 4 is a schematic diagram of the conduction structure of two substrates of a conventional liquid crystal display panel
  • FIG. 5 is a schematic plan view of the peripheral arrangement of the liquid crystal display panel shown in FIG. 4;
  • FIG. 6 is a schematic diagram of joining the liquid crystal display panel of the present application.
  • FIG. 7 is a schematic diagram of the conduction structure of two substrates of the first embodiment of the liquid crystal display panel of the present application.
  • FIG. 8 is a schematic plan view of the peripheral arrangement of the liquid crystal display panel shown in FIG. 7;
  • FIG. 9 is a schematic diagram of the conduction structure of the two substrates of the second embodiment of the liquid crystal display panel of the present application.
  • FIG. 10 is a schematic plan view of the peripheral arrangement of the liquid crystal display panel shown in FIG. 9.
  • the "on” or “under” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the liquid crystal display panel of the present application includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.
  • a non-display area of the liquid crystal display panel is provided There is a sealant layer for enclosing the liquid crystal layer;
  • the first substrate includes a first transparent conductive layer, the first transparent conductive layer includes a first common electrode;
  • the liquid crystal display panel further includes a side edge Bonding pad Pad), the side bonding pads are provided on the sides of the first substrate and the second substrate and the side of the frame sealant layer away from the liquid crystal layer, and the side bonding pads are
  • the first transparent conductive layer is in contact with each other; a chip on film (COF) is attached to a side of the liquid crystal display panel provided with the side bonding pads, and the first transparent conductive layer passes through the side bonding pads It is electrically connected to a third common voltage signal line on the chip on film, so that the first common electrode receives a common voltage signal transmitted by the chip on film.
  • the present application combines the structure of side bonding (Bonding), and combines the sealant layer (Sealant) and the transfer pad (Transfer Pad) is improved by setting the side bonding pads so that the first transparent conductive layer is electrically connected to the third common voltage signal line on the flip chip film through the side bonding pads, and the first common electrode can directly receive the data transmitted by the flip chip film Common voltage signal. It not only realizes the transmission of the common voltage signal to the first substrate, but also saves the external pin bonding (Outer Lead Bonding (hereinafter referred to as OLB) area can effectively compress the frame of the liquid crystal display panel, which is very beneficial to the narrowing of the frame of the VA mode and TN mode display panel.
  • OLB Outer Lead Bonding
  • FIG. 6 is a schematic diagram of the bonding of the liquid crystal display panel of the present application
  • FIG. 7 is a schematic diagram of the conduction structure of the two substrates of the first embodiment of the liquid crystal display panel of the present application
  • FIG. 8 is the liquid crystal shown in FIG. A schematic plan view of the periphery of the display panel.
  • the liquid crystal display panel includes a first substrate 61, a second substrate 62, and a liquid crystal layer 63 disposed between the two substrates.
  • the two substrates are combined to form a liquid crystal cell.
  • a ring (non-display area) of the liquid crystal display panel is a sealant layer 64 formed by a sealant in a closed ring pattern, and the liquid crystal layer 63 is enclosed therein.
  • a side bonding pad 65 is provided on one side surface of the liquid crystal display panel for bonding a chip on film 69.
  • the chip on film 69 is used to connect a PCBA board 68 provided with a driver IC to two substrates through the side bonding pads 65 respectively.
  • the liquid crystal display panel adopts a structure in which the COF is attached to the side of the panel and the side edges are joined.
  • the side joining method saves space in the OLB area, so that the frame of the liquid crystal display panel can be effectively compressed.
  • the first substrate 61 includes: a first base substrate 611, a first transparent conductive layer (ITO) 612 disposed on the first base substrate 611, the first transparent
  • the conductive layer 612 includes a first common electrode.
  • the second substrate 62 includes: a second base substrate 621, a gate insulating layer 622 and a passivation layer 623 disposed on the second base substrate 621.
  • the liquid crystal display panel further includes the side bonding pads 65, which are provided on the sides of the first substrate 61 and the second substrate 62, and the distance from the frame sealant layer 64 On one side of the liquid crystal layer 63, the side bonding pad 65 is in contact with the first transparent conductive layer 612; the side of the liquid crystal display panel where the side bonding pad 65 is attached
  • the chip on film 69, the first transparent conductive layer 612 is electrically connected to a third common voltage signal line (not shown in the figure) on the chip on film 69 through the side bonding pads 65, so that The first common electrode receives a common voltage signal transmitted by the chip on film 69.
  • the first substrate 61 is a color filter (CF) substrate
  • the second substrate 62 is a thin film transistor (TFT) array substrate
  • the first common electrode is a color filter substrate side common electrode (CF).
  • CF color filter substrate side common electrode
  • the first base substrate 611 may be a glass substrate. It should be noted that other components of the color filter substrate required for display are also prepared on the first base substrate 611, such as a black matrix (BM) and a color resist. Layers (R/G/B) and a photoresist layer (PS), etc., for the arrangement and preparation methods of the layers, please refer to the existing manufacturing process, and will not be repeated here.
  • the second base substrate 621 may be a glass substrate, and the passivation layer 623 may be made of PAV/PFA; it should be noted that the second base substrate 621 is prepared with other components of the array substrate required for display. For example: a first metal layer, an active layer, a second metal layer, and a second transparent conductive layer.
  • Pattern processing is performed on the first metal layer to form a gate of at least one thin film transistor and a second common electrode (ie, the common electrode A-COM on the TFT array substrate side);
  • the active layer includes a channel Region and a source/drain contact region, the source/drain contact region is located at both ends of the channel region;
  • the second metal layer is patterned to form the drain and source of the thin film transistor
  • the second transparent conductive layer includes a pixel electrode, and the pixel electrode and the source electrode are connected through a through hole.
  • a storage capacitor Cst is formed between the A-COM and the pixel electrode, and a liquid crystal capacitor Clc is formed between the pixel electrode and the CF-COM; the arrangement and preparation methods of the components on the array substrate can be referred to The existing manufacturing process will not be repeated here.
  • the first substrate 61 may also be an array substrate, and correspondingly, the second substrate 62 is a color filter substrate.
  • the side bonding pad 65 is formed by printing a first conductive material on the sides of the first substrate 61 and the second substrate 62, and the sealant layer 64 away from the liquid crystal layer 63 Made on one side.
  • the first conductive material is silver (Ag).
  • the edge positions of the two substrates of the display panel are printed with Ag material in advance to form side bonding pads to increase the contact area of the circuit on the COF.
  • the common voltage signal line on the COF is electrically connected to the transparent conductive layer (ITO) on the CF substrate side, the transparent conductive layer (CF-ITO) on the CF substrate side, the side bonding pad 65 and the COF
  • the common voltage signal line forms a path from which the driver IC can input common voltage signals into the plane.
  • the common voltage signal is directly connected to the CF-ITO through the COF by the driving IC, there is no need to provide a common voltage signal line on the TFT array substrate. Since there is no need to set the common voltage signal line on the TFT array substrate, it is no longer necessary to pass the gold ball (Au Ball) Connecting the signal to the CF substrate can reduce the gold ball dotting process, avoid the gold ball dotting offset, glue rejection and other undesirable phenomena, and save the gold ball material cost. Compared with the existing and display panel panel design, the cost The application effectively compresses the peripheral space of the display panel, which is very beneficial to the narrowing of the frame of the VA mode and TN mode display panel.
  • the gold ball will exceed the frame sealant layer for a certain distance, that is, the distance d2 in Figure 5 in this implementation In the example, it is not needed, which can effectively compress the peripheral space of the panel. And because there is no conductive material in the frame sealant layer, the frame sealant layer will not cause the signal short circuit of the two substrates after covering the display area (AA area) of the liquid crystal display panel. The distance can be further reduced.
  • the distance d3' between the frame sealant layer 64 and the corresponding AA area 81 is smaller than the distance d3 between the frame sealant layer 31 and the corresponding AA area 51 in the prior art (shown in FIG. 5). That is, the liquid crystal display panel of the present application not only realizes the transmission of the common voltage signal on the CF substrate side to the CF substrate, but also saves the material cost of the golden ball, and is very beneficial and effective for the narrowing of the frame of the VA mode and TN mode display panel. Improved the yield rate of liquid crystal display panel products, improved product production efficiency, and enhanced product competitiveness.
  • FIG. 9 is a schematic diagram of the conduction structure of the two substrates of the second embodiment of the liquid crystal display panel of this application
  • FIG. 10 is a schematic plan view of the periphery of the liquid crystal display panel shown in FIG.
  • the common voltage signal line on the COF is electrically connected to the transparent conductive layer (CF-ITO) on the CF substrate side, and is also electrically connected to the TFT array substrate side.
  • the common voltage signal line is connected, and the driver IC can simultaneously input the common voltage signal into the plane through the CF-ITO and the common voltage signal line on the side of the TFT array substrate.
  • a CF substrate 91 includes: a first base substrate 911, a first transparent conductive layer (ITO) 912 disposed on the first base substrate 911, and the first transparent conductive layer 912 includes a The first common electrode (CF-COM).
  • a TFT array substrate 92 includes: a second base substrate 921, a first metal layer, a gate insulating layer 923, a passivation layer 924, and a second transparent substrate disposed on the second base substrate 921
  • the conductive layer 925, the first metal layer includes a second common voltage signal line 9221, and the second transparent conductive layer 925 and the second common voltage signal line 9221 are connected through a through hole 9222.
  • the liquid crystal display panel further includes a side bonding pad 95, which is provided on the sides of the CF substrate 91 and the TFT array substrate 92, and the sealant layer 94 is away from a liquid crystal layer.
  • the side bonding pad 95 is in contact with the first transparent conductive layer 912.
  • a chip-on-chip film 99 is attached to one side of the liquid crystal display panel where the side bonding pads 95 are provided.
  • a second conductive material 96 is provided between the CF substrate 91 and the TFT array substrate 92, and the second conductive material 96 is connected to the first
  • the transparent conductive layer 912 is in contact with the second transparent conductive layer 925.
  • the first transparent conductive layer 912 is electrically connected to a third common voltage signal line (not shown in the figure) on the chip on film 99 through the side bonding pads 95; at the same time, the first transparent conductive layer
  • the layer 912 is also electrically connected to the third common voltage signal line through the second conductive material 96, the second transparent conductive layer 925, and the second common voltage signal line 9221.
  • the first common electrode may receive a common voltage signal through the path formed by the first transparent conductive layer 912, the side bonding pad 95, and the third common voltage signal line; and may also receive a common voltage signal through the first transparent conductive layer.
  • the path formed by the layer 912, the second conductive material 96, the second transparent conductive layer 925, the second common voltage signal line 9221, and the third common voltage signal line receives a common voltage signal.
  • the second conductive material 96 is added to the frame sealant material for preparing the frame sealant layer 94.
  • the frame sealant layer 94 containing the second conductive material 96 can be prepared by a one-time coating process, which is relatively simple.
  • the second conductive material is a gold ball. That is, in this embodiment, the Au In Sealant method is adopted. By adding gold ball material to the frame sealant material, in the One Drop Filling (ODF) process, only one frame sealant is required. The coating process is sufficient, no additional movement of transferring the gold ball to the pad is required, and the process is relatively simple.
  • ODF One Drop Filling
  • the frame sealant layer 94 is provided with a conductive material, in order to prevent the frame sealant layer 94 from covering the peripheral circuits of the display area (AA area) 101 of the liquid crystal display panel, the signals of the two substrates are short-circuited. There is a first distance d3 between the frame sealant layer 94 and the display area 101.
  • the liquid crystal display panel of the present application not only realizes the transmission of the common voltage signal from the CF substrate side to the CF substrate, but also saves the golden ball manufacturing process, and effectively compresses the peripheral space of the panel, which effectively improves the yield rate of the liquid crystal display panel.
  • Product production efficiency has improved product competitiveness.
  • this application also provides a method for manufacturing a liquid crystal display panel.
  • the preparation method includes the following steps: (1) Print the first conductive material on the sides of a first substrate and a second substrate and the side of the sealant layer away from a liquid crystal layer to prepare one side Side bonding pads, the side bonding pads are in contact with a first transparent conductive layer of the first substrate, and the first transparent conductive layer includes a first common electrode; (2) on the liquid crystal display panel A side surface with the side bonding pads is attached to a flip chip film, and the first transparent conductive layer is electrically connected to a third common voltage signal line on the flip chip through the side bonding pads , So that the first common electrode receives a common voltage signal transmitted by the chip on film.
  • the prepared liquid crystal display panel can be referred to as shown in FIG. 7.
  • the liquid crystal display panel prepared by the preparation method described in this application not only realizes the transmission of the common voltage signal from the CF substrate side to the CF substrate, but also saves the material cost of the golden ball. And it is very beneficial to the narrowing of the frame of the VA mode and TN mode display panel, which effectively improves the yield rate of liquid crystal display panels, improves product production efficiency, and enhances product competitiveness.
  • the second substrate in step (1) is further prepared by the following steps: providing a second base substrate; forming a first metal layer on the second base substrate, and The first metal layer is patterned to form a second common voltage signal line; a gate insulating layer, a passivation layer, and a second transparent conductive layer are sequentially formed on the first metal layer, and the second transparent conductive layer The layer is connected with the second common voltage signal line through a through hole.
  • step (1) further includes: in a non-display area of the liquid crystal display panel, a second conductive material is disposed between the first substrate and the second substrate, and the second conductive material is The first transparent conductive layer and the second transparent conductive layer are in contact.
  • step (2) may further include: passing the first transparent conductive layer through the second conductive material, the second transparent conductive layer, and the second common voltage signal line and the third common The voltage signal line is electrically connected so that the first common electrode receives the common voltage signal. That is, the first common electrode may receive the common voltage signal through the path formed by the first transparent conductive layer, the side bonding pad, and the third common voltage signal line; and may also pass through the first The path formed by the transparent conductive layer, the second conductive material, the second transparent conductive layer, the second common voltage signal line, and the third common voltage signal line receives the common voltage signal.
  • the second conductive material can be added to the frame sealant material, and the frame sealant layer containing the second conductive material is prepared through a one-time coating process.
  • the prepared liquid crystal display panel can be referred to as shown in FIG. 9.
  • the liquid crystal display panel prepared by the preparation method described in this application not only realizes the transmission of the common voltage signal on the CF substrate side to the CF substrate, but also saves the golden ball manufacturing process, and Effectively compress the peripheral space of the panel, effectively improve the yield of liquid crystal display panel products, improve product production efficiency, and enhance product competitiveness.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

一种液晶显示面板及其制备方法，通过在第一基板（61）、第二基板（62）的侧边以及封框胶层（64）的远离液晶层（63）的一侧设置侧边接合垫（65），侧边接合垫（65）与第一基板（61）的第一透明导电层（612）相接触，覆晶薄膜（69）采用侧边接合方式贴合在侧边接合垫（65）上，既实现了第一基板（61）侧公共电压信号向第一基板（61）的传递，也节省了点金球的制程，且有效的压缩面板的外围空间。

Description

一种液晶显示面板及其制备方法 技术领域
本申请涉及液晶显示技术领域，尤其涉及一种液晶显示面板及其制备方法。
 背景技术
在TV和商用显示面板市场，窄边框的产品已经越来越普及，压缩显示面板的边框宽度在设计中是一个非常重要的课题。
薄膜晶体管液晶显示面板(Thin Film Transistor-Liquid Crystal Display，简称TFT-LCD)一般由一第一基板、一第二基板以及一配置于两基板间的液晶层(Liquid Crystal，简称LC) 所构成。所述第一基板及所述第二基板分别制作，所述第一基板可以为彩膜(CF)基板，所述第二基板可以为薄膜晶体管(TFT)阵列基板，第一、第二基板对组后形成一液晶盒。VA(Vertical Alignment，垂直配向)模式和TN(Twisted Nematic，扭转式向列型)模式是非常重要的两种液晶显示模式，VA模式和TN模式的液晶显示面板，液晶电容是由像素电极(Pixel Electrode)和CF基板侧公共电极(CF-COM)形成，根据加载在液晶电容两端的电压控制液晶分子偏转。
 技术问题
现有技术中的VA模式以及TN模式的液晶显示面板的CF基板侧公共电压(COM)信号是通过接合(Bonding)在TFT阵列基板侧的驱动IC给出，然后进入TFT阵列基板上的线路中，再通过传送垫(Transfer Pad)和金球(Au Ball)导通至CF基板侧。通常面板在制作时，传送垫和金球的中心位置会错开一段距离，这样两者相加就会占用比较大的外围空间，对于面板边框的压缩是非常不利的。
请参阅图1-图5，其中，图1为VA模式或TN模式显示面板中像素的等效电路图，图2为现有液晶显示面板的膜层结构的剖面图，图3为现有液晶显示面板的接合示意图，图4为现有液晶显示面板的两基板导通结构示意图，图5为图4所示液晶显示面板外围设置的平面示意图。
如图1所示，存储电容Cst和液晶电容Clc是像素的最重要的两个电容，其中所述液晶电容Clc的两个电极分别是像素电极(其连接到像素的薄膜晶体管T1的源极)和CF基板侧公共电极(CF-COM)11，所述存储电容Cst的两个电极分别是像素电极和TFT阵列基板侧公共电极(Array-COM，以下简称A-COM)12。所述薄膜晶体管T1的漏极接入数据信号线(Data)13，其栅极接入扫描信号线(Scan)14。所述存储电容Cst的作用一般是维持像素电极电位的稳定，所述液晶电容Clc的作用是根据加载在其两端的电压控制液晶分子的转动。
如图2所示，现有液晶显示面板的膜层结构包括：一CF基板21、一TFT阵列基板22以及一配置于两基板间的液晶层23。所述CF基板21包括：一CF侧衬底基板(substrate)211，设置在所述CF侧衬底基板211上的一第一透明导电层212。所述TFT阵列基板22包括：一TFT侧衬底基板221，依次设置在所述TFT侧衬底基板221上的一第一金属层、一栅极绝缘层(GI)223、一有源层224、一第二金属层、一钝化层(PAV/PFA)226以及一第二透明导电层(ITO)227。对所述第一金属层进行图形化(Pattern)处理形成至少一薄膜晶体管的栅极2221、一A-COM 2222以及一CF基板侧公共电压信号线2223(示于图4中)；对所述第二金属层进行图形化处理形成所述薄膜晶体管的漏极2251和源极2252；所述第一透明导电层212包括一CF-COM 2122；所述第二透明导电层227包括一像素电极2271，所述像素电极2271与所述源极2252之间通过设于所述钝化层226上的一通孔2261连接。所述A-COM 2222和所述像素电极2271之间形成所述存储电容Cst，所述像素电极2271和所述CF-COM 2122之间形成所述液晶电容Clc(图中以虚线示意出)。
如图3所示，液晶显示面板的两基板对组后形成一液晶盒，液晶显示面板外围一圈是由封框胶材料(Sealant)形成一个封闭的环形图案(Pattern)的封框胶层31，将液晶层23封闭在其中。采用一覆晶薄膜(Chip On Film，简称COF)32将设有驱动(Driver)IC的一PCBA板33与液晶显示面板的所述TFT阵列基板22接合(Bonding)。由于驱动IC是直接与所述TFT阵列基板22接合，其输出信号也是首先进入到所述TFT阵列基板22上的走线中。
如图4所示，所述TFT阵列基板22上的CF基板侧公共电压信号线2223与驱动IC(未示于图中)连接，金球(Au Ball)41在封框胶层31的外侧，此处有连接CF基板侧公共电压信号线2223的第二透明导电层227裸露出来。驱动IC给出的CF基板侧公共电压信号首先是进入到TFT阵列基板22的所述CF基板侧公共电压信号线2223中，再通过所述第二透明导电层227、一金球41将CF基板侧公共电压信号导通至所述CF基板21的所述CF-COM 2122中。
如图5所示，假设所述封框胶层31的宽度为d1，为了制程的需求，通常所述封框胶层31的中心和所述金球41的中心会错开一段距离Δd，这样所述金球41会超出所述封框胶层31一段距离d2。在整个面板外围的设计中，所述封框胶层31和所述金球41所占用的总宽度是d1+d2，一般这个宽度都在1mm以上，这个宽度对于拼接墙的产品来讲是比较大的，这会造成面板边框难以继续压缩，不利于窄边框面板的实现。且在面板设计中，一显示区(AA区)51的外围部分往往都会有大量图形化的透明导电层(ITO Pattern)用于不同层别之间的跨线，这些ITO Pattern一般都会和不同的信号线连接。这些ITO Pattern是不能进入到所述封框胶层31的区域里面，否则所述封框胶层31中的所述金球41会将这些ITO Pattern和所述CF-COM 2122导通，导致输入面板的信号与CF-COM短路，引起画面显示异常。因此所述封框胶层31距离面板的AA区需要保持一个安全的距离d3，这个距离的存在也会使得VA模式以及TN模式的显示面板边框难以继续压缩。
 技术解决方案
本申请的目的在于，针对现有技术存在的问题，提供一种液晶显示面板及其制备方法，可以优化面板外围区域的结构，实现更窄的边框。
为实现上述目的，本申请提供了一种液晶显示面板，所述液晶显示面板包括相对设置的一第一基板、一第二基板，以及配置于所述第一基板与所述第二基板之间的一液晶层，所述液晶显示面板的一非显示区设有封闭所述液晶层的一封框胶层；所述第一基板包括一第一透明导电层，所述第一透明导电层包括一第一公共电极；所述第二基板包括：一第二衬底基板，设置在所述第二衬底基板上的一第一金属层、一栅极绝缘层、一钝化层以及一第二透明导电层，所述第一金属层包括一第二公共电压信号线，所述第二透明导电层与所述第二公共电压信号线之间通过一通孔连接，其中，在所述非显示区，所述第一基板与所述第二基板之间设有第二导电材料，所述第二导电材料分别与所述第一透明导电层以及所述第二透明导电层接触；所述液晶显示面板还包括一侧边接合垫，所述侧边接合垫设于所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧，所述侧边接合垫与所述第一透明导电层相接触，其中，所述侧边接合垫通过将第一导电材料印刷在所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧制成；以及所述液晶显示面板的设有所述侧边接合垫的一侧面贴合有一覆晶薄膜，所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号；所述第一透明导电层还通过所述第二导电材料、所述第二透明导电层以及所述第二公共电压信号线与所述第三公共电压信号线电连接，以使所述第一公共电极接收所述公共电压信号。
为实现上述目的，本申请还提供了一种液晶显示面板，所述液晶显示面板包括相对设置的一第一基板、一第二基板，以及配置于所述第一基板与所述第二基板之间的一液晶层，所述液晶显示面板的一非显示区设有封闭所述液晶层的一封框胶层；所述第一基板包括一第一透明导电层，所述第一透明导电层包括一第一公共电极；所述液晶显示面板还包括一侧边接合垫，所述侧边接合垫设于所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧，所述侧边接合垫与所述第一透明导电层相接触；以及所述液晶显示面板的设有所述侧边接合垫的一侧面贴合有一覆晶薄膜，所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。
为实现上述目的，本申请还提供了一种液晶显示面板的制备方法，包括如下步骤：(1) 在一第一基板和一第二基板的侧边以及一封框胶层的远离一液晶层的一侧印刷第一导电材料，制备一侧边接合垫，所述侧边接合垫与所述第一基板的一第一透明导电层相接触，所述第一透明导电层包括一第一公共电极；以及(2) 在所述液晶显示面板的设有所述侧边接合垫的一侧面贴合一覆晶薄膜，将所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。
 有益效果
本申请通过改进了显示面板外围结构，既实现了CF基板侧公共电压信号向CF基板的传递，也节省点金球的制程，且有效的压缩面板的外围空间，有效提升了液晶显示面板产品良率，提升了产品生产效率，提升了产品竞争力。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1，VA模式或TN模式显示面板中像素的等效电路图；
图2，现有液晶显示面板的膜层结构的剖面图；
图3，现有液晶显示面板的接合示意图；
图4，现有液晶显示面板的两基板导通结构示意图；
图5为图4所示液晶显示面板外围设置的平面示意图；
图6，本申请液晶显示面板的接合示意图；
图7，本申请液晶显示面板第一实施例的两基板导通结构示意图；
图8为图7所示液晶显示面板外围设置的平面示意图；
图9，本申请液晶显示面板第二实施例的两基板导通结构示意图；
图10为图9所示液晶显示面板外围设置的平面示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
本申请的说明书和权利要求书以及附图中的术语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，应当理解，这样描述的对象在适当情况下可以互换。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请液晶显示面板包括相对设置一第一基板、一第二基板，以及配置于所述第一基板与所述第二基板之间的一液晶层，所述液晶显示面板的一非显示区设有封闭所述液晶层的一封框胶层；所述第一基板包括一第一透明导电层，所述第一透明导电层包括一第一公共电极；所述液晶显示面板还包括一侧边接合垫(Bonding Pad)，所述侧边接合垫设于所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧，所述侧边接合垫与所述第一透明导电层相接触；所述液晶显示面板的设有所述侧边接合垫的一侧面贴合有一覆晶薄膜(COF)，所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。即，本申请结合侧边接合(Bonding)的结构，并对封框胶层(Sealant)以及传送垫(Transfer Pad)进行改善，通过设置侧边接合垫，使得第一透明导电层通过侧边接合垫与覆晶薄膜上的第三公共电压信号线电连接，第一公共电极可以直接接收覆晶薄膜传送的公共电压信号。既实现了公共电压信号向第一基板的传递，也节省了外引脚接合(Outer Lead Bonding，以下简称OLB)区域的空间，从而可以有效压缩液晶显示面板边框，对VA模式以及TN模式显示面板边框的缩窄非常有利。
请参阅图6-图8，其中，图6为本申请液晶显示面板的接合示意图，图7为本申请液晶显示面板第一实施例的两基板导通结构示意图，图8为图7所示液晶显示面板外围设置的平面示意图。
如图6所示，所述液晶显示面板包括一第一基板61、一第二基板62，以及一配置于两基板间的液晶层63，两基板对组后形成一液晶盒。所述液晶显示面板外围一圈(非显示区)是由封框胶材料(Sealant)形成一个封闭的环形图案(Pattern)的一封框胶层64，将所述液晶层63封闭在其中。所述液晶显示面板上用于贴合一覆晶薄膜69的一侧面设有一侧边接合垫65。采用所述覆晶薄膜69通过所述侧边接合垫65将设有驱动(Driver)IC的一PCBA板68分别与两基板接合。由于驱动IC是分别直接与两基板接合，其输出信号也是分别直接进入到两基板上的走线中。即，所述液晶显示面板采用将COF贴合在面板的侧面的侧边接合的架构，侧边接合方式节省了OLB区域的空间，从而可以有效压缩液晶显示面板边框。
如图7所示，所述第一基板61包括：一第一衬底基板611，设置在所述第一衬底基板611上的一第一透明导电层(ITO)612，所述第一透明导电层612包括一第一公共电极。所述第二基板62包括：一第二衬底基板621，设置在所述第二衬底基板621上的一栅极绝缘层622以及一钝化层623。所述液晶显示面板还包括所述侧边接合垫65，所述侧边接合垫65设于所述第一基板61和所述第二基板62的侧边以及所述封框胶层64的远离所述液晶层63的一侧，所述侧边接合垫65与所述第一透明导电层612相接触；所述液晶显示面板的设有所述侧边接合垫65的一侧面贴合有所述覆晶薄膜69，所述第一透明导电层612通过所述侧边接合垫65与所述覆晶薄膜69上的一第三公共电压信号线(未示于图中)电连接，以使所述第一公共电极接收所述覆晶薄膜69传送的一公共电压信号。
在本实施例中，所述第一基板61为彩膜(CF)基板，所述第二基板62为薄膜晶体管(TFT)阵列基板，所述第一公共电极为彩膜基板侧公共电极(CF-COM)。所述第一衬底基板611可以为玻璃基板，需要说明的是，所述第一衬底基板611上还制备有显示所需彩膜基板其它组件，例如：一黑色矩阵(BM)、一色阻层(R/G/B)以及一光阻层(PS)等，其设置方式及制备方法可参考现有制程，此处不再赘述。所述第二衬底基板621可以为玻璃基板，所述钝化层623可以采用PAV/PFA制备；需要说明的是，所述第二衬底基板621上制备有显示所需阵列基板其它组件，例如：一第一金属层、一有源层、一第二金属层以及一第二透明导电层。对所述第一金属层进行图形化(Pattern)处理形成至少一薄膜晶体管的栅极以及一第二公共电极(即TFT阵列基板侧公共电极A-COM)；所述有源层包括一沟道区和一源/漏极接触区，所述源/漏极接触区位于所述沟道区的两端；对所述第二金属层进行图形化处理形成所述薄膜晶体管的漏极和源极；所述第二透明导电层包括一像素电极，所述像素电极与所述源极之间通过一通孔连接。所述A-COM和所述像素电极之间形成一存储电容Cst，所述像素电极和所述CF-COM之间形成一液晶电容Clc；上述阵列基板上各组件的设置方式及制备方法可参考现有制程，此处不再赘述。在其它实施例中，所述第一基板61也可以为阵列基板，相应的，所述第二基板62为彩膜基板。
优选地，所述侧边接合垫65通过将第一导电材料印刷在所述第一基板61和所述第二基板62的侧边以及所述封框胶层64的远离所述液晶层63的一侧制成。优选地，所述第一导电材料为银(Ag)。在显示面板两基板边缘位置预先用Ag材料印刷成侧边接合垫，增大COF上线路的接触面积。在完成COF接合之后，COF上的公共电压信号线和CF基板侧的透明导电层(ITO)电连接，CF基板侧的透明导电层(CF-ITO)、所述侧边接合垫65与COF上的公共电压信号线形成通路，驱动IC可以从这个通路向面内输入公共电压信号。
由于公共电压信号是由驱动IC通过COF直接与CF-ITO连接，TFT阵列基板上可以无需设置公共电压信号线。由于在TFT阵列基板上无需设置公共电压信号线的走线，因此不再需要通过金球(Au Ball)将信号导通至CF基板，可以减少金球打点工序，避免金球打点偏移、甩胶等不良现象，并节省了金球材料成本，相比现有的以及显示面板面板设计，本申请有效的压缩了显示面板的外围空间，对VA模式以及TN模式显示面板边框的缩窄非常有利。
如图8所示，由于不再需要通过金球(Au Ball)将信号导通至CF基板，因此不存在金球会超出封框胶层一段距离的限制，即图5中的距离d2本实施例中是不需要的，从而可以有效的压缩面板的外围空间。且由于封框胶层中没有导电材料存在，因此，封框胶层覆盖液晶显示面板的显示区(AA区)外围线路后也不会导致两基板的信号短路，封框胶层距离AA区的距离可以进一步降低。本实施例中，所述封框胶层64距离相应的AA区81的距离d3’小于现有技术中的封框胶层31距离相应的AA区51的距离d3(示于图5中)。也即，本申请液晶显示面板，既实现了CF基板侧公共电压信号向CF基板的传递，也节省了金球的材料成本，且对VA模式以及TN模式显示面板边框的缩窄非常有利，有效提升了液晶显示面板产品良率，提升了产品生产效率，提升了产品竞争力。
请参阅图9-图10，其中，图9为本申请液晶显示面板第二实施例的两基板导通结构示意图，图10为图9所示液晶显示面板外围设置的平面示意图。与图7所示实施例的不同之处在于，在本实施例中，COF上的公共电压信号线和CF基板侧的透明导电层(CF-ITO)电连接，同时也和TFT阵列基板侧的公共电压信号线连接，驱动IC可以同时通过CF-ITO以及TFT阵列基板侧的公共电压信号线向面内输入公共电压信号。
具体的，一CF基板91包括：一第一衬底基板911，设置在所述第一衬底基板911上的一第一透明导电层(ITO)912，所述第一透明导电层912包括一第一公共电极(CF-COM)。一TFT阵列基板92包括：一第二衬底基板921，设置在所述第二衬底基板921上的一第一金属层、一栅极绝缘层923、一钝化层924以及一第二透明导电层925，所述第一金属层包括一第二公共电压信号线9221，所述第二透明导电层925与所述第二公共电压信号线9221之间通过一通孔9222连接。所述液晶显示面板还包括一侧边接合垫95，所述侧边接合垫95设于所述CF基板91和所述TFT阵列基板92的侧边以及一封框胶层94的远离一液晶层93的一侧，所述侧边接合垫95与所述第一透明导电层912相接触。所述液晶显示面板的设有所述侧边接合垫95的一侧面贴合有一覆晶薄膜99。
具体的，在所述液晶显示面板的一非显示区，所述CF基板91与所述TFT阵列基板92之间设有第二导电材料96，所述第二导电材料96分别与所述第一透明导电层912以及所述第二透明导电层925接触。所述第一透明导电层912通过所述侧边接合垫95与所述覆晶薄膜99上的一第三公共电压信号线(未示于图中)电连接；同时，所述第一透明导电层912还通过所述第二导电材料96、所述第二透明导电层925以及所述第二公共电压信号线9221与所述第三公共电压信号线电连接。所述第一公共电极可以通过所述第一透明导电层912、所述侧边接合垫95、所述第三公共电压信号线形成的通路接收公共电压信号；还可以通过所述第一透明导电层912、所述第二导电材料96、所述第二透明导电层925、所述第二公共电压信号线9221、所述第三公共电压信号线形成的通路接收公共电压信号。
优选地，所述第二导电材料96添加在制备所述封框胶层94的封框胶材料中。包含所述第二导电材料96的所述封框胶层94可以通过一次涂布制程制备，制程相对比较简单。
优选地，所述第二导电材料为金球。也即，本实施例采用了Au In Sealant的方式，通过在封框胶材料中添加金球材料，在滴入式注入法(One Drop Filling，简称ODF)制程中，只需要进行一次封框胶涂布制程即可，不需要再进行额外的传送垫点金球的动作，制程相对比较简单。
如图10所示，由于不再需要单独的点金球的操作，因此不存在金球会超出封框胶层一段距离的限制，即图5中的距离d2本实施例中是不需要的，从而可以有效的压缩面板的外围空间。但由于所述封框胶层94中设有导电材料，为了避免所述封框胶层94覆盖所述液晶显示面板的显示区(AA区)101外围线路后导致两基板的信号短路，所述封框胶层94与所述显示区101之间有一第一距离d3。本申请液晶显示面板，既实现了CF基板侧公共电压信号向CF基板的传递，也节省点金球的制程，且有效的压缩面板的外围空间，有效提升了液晶显示面板产品良率，提升了产品生产效率，提升了产品竞争力。
基于同一申请构思，本申请还提供了一种液晶显示面板的制备方法。具体的，所述制备方法包括如下步骤：(1) 在一第一基板和一第二基板的侧边以及一封框胶层的远离一液晶层的一侧印刷第一导电材料，制备一侧边接合垫，所述侧边接合垫与所述第一基板的一第一透明导电层相接触，所述第一透明导电层包括一第一公共电极；(2) 在所述液晶显示面板的设有所述侧边接合垫的一侧面贴合一覆晶薄膜，将所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。制备出的液晶显示面板可参考图7所示，采用本申请所述制备方法制备的液晶显示面板，既实现了CF基板侧公共电压信号向CF基板的传递，也节省了金球的材料成本，且对VA模式以及TN模式显示面板边框的缩窄非常有利，有效提升了液晶显示面板产品良率，提升了产品生产效率，提升了产品竞争力。
在一实施例中，步骤(1)中的所述第二基板进一步通过以下步骤制备：提供一第二衬底基板；在所述第二衬底基板上制作一第一金属层，对所述第一金属层进行图形化处理形成一第二公共电压信号线；在所述第一金属层上依次制作一栅绝缘层、一钝化层以及一第二透明导电层，所述第二透明导电层与所述第二公共电压信号线之间通过一通孔连接。相应的，步骤(1)进一步包括：在所述液晶显示面板的一非显示区，在所述第一基板与所述第二基板之间设置第二导电材料，所述第二导电材料分别与所述第一透明导电层以及所述第二透明导电层接触。通过上述制程，步骤(2)可以进一步包括：将所述第一透明导电层通过所述第二导电材料、所述第二透明导电层以及所述第二公共电压信号线与所述第三公共电压信号线电连接，以使所述第一公共电极接收所述公共电压信号。即，所述第一公共电极可以通过所述第一透明导电层、所述侧边接合垫、所述第三公共电压信号线形成的通路接收所述公共电压信号；还可以通过所述第一透明导电层、所述第二导电材料、所述第二透明导电层、所述第二公共电压信号线、所述第三公共电压信号线形成的通路接收所述公共电压信号。
优选地，可以将所述第二导电材料添加在封框胶材料中，通过一次涂布制程制备包含所述第二导电材料的所述封框胶层。制备出的液晶显示面板可参考图9所示，采用本申请所述制备方法制备的液晶显示面板，既实现了CF基板侧公共电压信号向CF基板的传递，也节省点金球的制程，且有效的压缩面板的外围空间，有效提升了液晶显示面板产品良率，提升了产品生产效率，提升了产品竞争力。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种液晶显示面板，所述液晶显示面板包括相对设置的一第一基板、一第二基板，以及配置于所述第一基板与所述第二基板之间的一液晶层，所述液晶显示面板的一非显示区设有封闭所述液晶层的一封框胶层；其中，所述第一基板包括一第一透明导电层，所述第一透明导电层包括一第一公共电极；所述第二基板包括：一第二衬底基板，设置在所述第二衬底基板上的一第一金属层、一栅极绝缘层、一钝化层以及一第二透明导电层，所述第一金属层包括一第二公共电压信号线，所述第二透明导电层与所述第二公共电压信号线之间通过一通孔连接，并且其中，在所述非显示区，所述第一基板与所述第二基板之间设有第二导电材料，所述第二导电材料分别与所述第一透明导电层以及所述第二透明导电层接触；所述液晶显示面板还包括一侧边接合垫，所述侧边接合垫设于所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧，所述侧边接合垫与所述第一透明导电层相接触，并且其中，所述侧边接合垫通过将第一导电材料印刷在所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧制成；以及所述液晶显示面板的设有所述侧边接合垫的一侧面贴合有一覆晶薄膜，所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号；所述第一透明导电层还通过所述第二导电材料、所述第二透明导电层以及所述第二公共电压信号线与所述第三公共电压信号线电连接，以使所述第一公共电极接收所述公共电压信号。
  2. 如权利要求1所述的液晶显示面板，其中，所述第一导电材料为银。
  3. 如权利要求1所述的液晶显示面板，其中，所述第二导电材料添加在制备所述封框胶层的封框胶材料中。
  4. 如权利要求1所述的液晶显示面板，其中，所述第二导电材料为金球。
  5. 如权利要求1所述的液晶显示面板，其中，包含所述第二导电材料的所述封框胶层通过一次涂布制程制备。
  6. 如权利要求1所述的液晶显示面板，其中，所述封框胶层与所述液晶显示面板的一显示区之间有一第一距离。
  7. 一种液晶显示面板，所述液晶显示面板包括相对设置的一第一基板、一第二基板，以及配置于所述第一基板与所述第二基板之间的一液晶层，所述液晶显示面板的一非显示区设有封闭所述液晶层的一封框胶层；其中，所述第一基板包括一第一透明导电层，所述第一透明导电层包括一第一公共电极；所述液晶显示面板还包括一侧边接合垫，所述侧边接合垫设于所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧，所述侧边接合垫与所述第一透明导电层相接触；以及所述液晶显示面板的设有所述侧边接合垫的一侧面贴合有一覆晶薄膜，所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。
  8. 如权利要求7所述的液晶显示面板，其中，所述侧边接合垫通过将第一导电材料印刷在所述第一基板和所述第二基板的侧边以及所述封框胶层的远离所述液晶层的一侧制成。
  9. 如权利要求8所述的液晶显示面板，其中，所述第一导电材料为银。
  10. 如权利要求7所述的液晶显示面板，其中，所述第二基板包括：一第二衬底基板，设置在所述第二衬底基板上的一第一金属层、一栅极绝缘层、一钝化层以及一第二透明导电层，所述第一金属层包括一第二公共电压信号线，所述第二透明导电层与所述第二公共电压信号线之间通过一通孔连接；在所述非显示区，所述第一基板与所述第二基板之间设有第二导电材料，所述第二导电材料分别与所述第一透明导电层以及所述第二透明导电层接触；所述第一透明导电层还通过所述第二导电材料、所述第二透明导电层以及所述第二公共电压信号线与所述第三公共电压信号线电连接，以使所述第一公共电极接收所述公共电压信号。
  11. 如权利要求10所述的液晶显示面板，其中，所述第二导电材料添加在制备所述封框胶层的封框胶材料中。
  12. 如权利要求10所述的液晶显示面板，其中，所述第二导电材料为金球。
  13. 如权利要求10所述的液晶显示面板，其中，包含所述第二导电材料的所述封框胶层通过一次涂布制程制备。
  14. 如权利要求7所述的液晶显示面板，其中，所述封框胶层与所述液晶显示面板的一显示区之间有一第一距离。
  15. 一种液晶显示面板的制备方法，其中，包括如下步骤： (1) 在一第一基板和一第二基板的侧边以及一封框胶层的远离一液晶层的一侧印刷第一导电材料，制备一侧边接合垫，所述侧边接合垫与所述第一基板的一第一透明导电层相接触，所述第一透明导电层包括一第一公共电极；以及 (2) 在所述液晶显示面板的设有所述侧边接合垫的一侧面贴合一覆晶薄膜，将所述第一透明导电层通过所述侧边接合垫与所述覆晶薄膜上的一第三公共电压信号线电连接，以使所述第一公共电极接收所述覆晶薄膜传送的一公共电压信号。
  16. 如权利要求15所述的制备方法，其中，所述第一导电材料为银。
  17. 如权利要求15所述的制备方法，其中，步骤(1)中的所述第二基板进一步通过以下步骤制备：提供一第二衬底基板；在所述第二衬底基板上制作一第一金属层，并对所述第一金属层进行图形化处理形成一第二公共电压信号线；以及在所述第一金属层上依次制作一栅绝缘层、一钝化层以及一第二透明导电层，所述第二透明导电层与所述第二公共电压信号线之间通过一通孔连接；步骤(1)进一步包括：在所述液晶显示面板的一非显示区，在所述第一基板与所述第二基板之间设置第二导电材料，所述第二导电材料分别与所述第一透明导电层以及所述第二透明导电层接触；以及步骤(2)进一步包括：将所述第一透明导电层通过所述第二导电材料、所述第二透明导电层以及所述第二公共电压信号线与所述第三公共电压信号线电连接，以使所述第一公共电极接收所述公共电压信号。
  18. 如权利要求15所述的制备方法，其中，步骤(1)中的所述封框胶层进一步通过以下步骤制备：将所述第二导电材料添加在封框胶材料中，通过一次涂布制程制备包含所述第二导电材料的所述封框胶层。
  19. 如权利要求18所述的制备方法，其中，所述第二导电材料为金球。
  20. 如权利要求15所述的制备方法，其中，所述封框胶层与所述液晶显示面板的一显示区之间有一第一距离。
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