WO2021018014A1 - Structure de boîtier multipuce sur la base de tsv et son procédé de fabrication - Google Patents

Structure de boîtier multipuce sur la base de tsv et son procédé de fabrication Download PDF

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Publication number
WO2021018014A1
WO2021018014A1 PCT/CN2020/103959 CN2020103959W WO2021018014A1 WO 2021018014 A1 WO2021018014 A1 WO 2021018014A1 CN 2020103959 W CN2020103959 W CN 2020103959W WO 2021018014 A1 WO2021018014 A1 WO 2021018014A1
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WO
WIPO (PCT)
Prior art keywords
chip
packaging
interconnection
board
adapter board
Prior art date
Application number
PCT/CN2020/103959
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English (en)
Chinese (zh)
Inventor
曹立强
李恒甫
Original Assignee
上海先方半导体有限公司
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Filing date
Publication date
Application filed by 上海先方半导体有限公司 filed Critical 上海先方半导体有限公司
Publication of WO2021018014A1 publication Critical patent/WO2021018014A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne le domaine de l'encapsulation de puces, spécifiquement une structure de boîtier multipuce sur la base de TSV et son procédé de fabrication. La structure de boîtier multipuce comprend une structure d'interconnexion; une première puce disposée sur la structure d'interconnexion; une carte d'adaptateur disposée sur la structure d'interconnexion, ladite carte d'adaptateur étant disposée sur le même côté de la structure d'interconnexion que la première puce et ayant une épaisseur supérieure à celle de la première puce; une seconde puce agencée sur la carte d'adaptateur et disposée à l'opposé de la structure d'interconnexion ; et une couche d'encapsulation. La disposition de la structure d'interconnexion et de la carte d'adaptation, la plaque d'adaptation ayant une certaine épaisseur, et la seconde puce étant montée sur la carte d'adaptateur, permet de placer la première puce et la seconde puce sur deux plans de différentes hauteurs, ce qui permet d'obtenir une encapsulation tridimensionnelle de multiples puces. Par rapport à l'état de la technique, la somme des dimensions de la première puce et de la seconde puce dans la structure de boîtier obtenue par la présente invention n'a pas besoin d'être limitée aux dimensions du plan de la structure d'interconnexion, ce qui permet d'étendre le développement diversifié de structures de boîtiers de puces.
PCT/CN2020/103959 2019-07-29 2020-07-24 Structure de boîtier multipuce sur la base de tsv et son procédé de fabrication WO2021018014A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910689442.4 2019-07-29
CN201910689442.4A CN110335859B (zh) 2019-07-29 2019-07-29 一种基于tsv的多芯片的封装结构及其制备方法

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Publication Number Publication Date
WO2021018014A1 true WO2021018014A1 (fr) 2021-02-04

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WO (1) WO2021018014A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335859B (zh) * 2019-07-29 2024-04-05 上海先方半导体有限公司 一种基于tsv的多芯片的封装结构及其制备方法
CN111415927A (zh) * 2020-05-19 2020-07-14 华进半导体封装先导技术研发中心有限公司 封装结构及其制备方法
CN112911798B (zh) * 2021-01-18 2023-04-25 维沃移动通信有限公司 主板结构和电子设备
CN113192924A (zh) * 2021-04-27 2021-07-30 维沃移动通信有限公司 电路板封装结构、封装方法和电子设备
CN114937633B (zh) * 2022-07-25 2022-10-18 成都万应微电子有限公司 一种射频芯片系统级封装方法及射频芯片系统级封装结构

Citations (6)

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CN103839894A (zh) * 2012-11-21 2014-06-04 台湾积体电路制造股份有限公司 形成叠层封装结构的方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN206618883U (zh) * 2016-03-10 2017-11-07 颖飞公司 通过混合多芯片集成的紧凑型光收发器
US20180068937A1 (en) * 2012-03-23 2018-03-08 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
CN110335859A (zh) * 2019-07-29 2019-10-15 上海先方半导体有限公司 一种基于tsv的多芯片的封装结构及其制备方法
CN210120135U (zh) * 2019-07-29 2020-02-28 上海先方半导体有限公司 一种基于tsv的多芯片封装结构

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Publication number Priority date Publication date Assignee Title
US9548251B2 (en) * 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
CN108598046B (zh) * 2018-04-19 2020-03-27 苏州通富超威半导体有限公司 芯片的封装结构及其封装方法
CN208923115U (zh) * 2018-11-30 2019-05-31 华进半导体封装先导技术研发中心有限公司 一种微波多芯片组件的封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180068937A1 (en) * 2012-03-23 2018-03-08 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
CN103839894A (zh) * 2012-11-21 2014-06-04 台湾积体电路制造股份有限公司 形成叠层封装结构的方法
CN206618883U (zh) * 2016-03-10 2017-11-07 颖飞公司 通过混合多芯片集成的紧凑型光收发器
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN110335859A (zh) * 2019-07-29 2019-10-15 上海先方半导体有限公司 一种基于tsv的多芯片的封装结构及其制备方法
CN210120135U (zh) * 2019-07-29 2020-02-28 上海先方半导体有限公司 一种基于tsv的多芯片封装结构

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