WO2021009882A1 - 電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機 - Google Patents

電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機 Download PDF

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Publication number
WO2021009882A1
WO2021009882A1 PCT/JP2019/028158 JP2019028158W WO2021009882A1 WO 2021009882 A1 WO2021009882 A1 WO 2021009882A1 JP 2019028158 W JP2019028158 W JP 2019028158W WO 2021009882 A1 WO2021009882 A1 WO 2021009882A1
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Prior art keywords
current
power conversion
converter
conversion device
unit
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Ceased
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PCT/JP2019/028158
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English (en)
French (fr)
Japanese (ja)
Inventor
憲嗣 岩崎
貴昭 ▲高▼原
有澤　浩一
卓也 下麥
智 一木
啓介 植村
元哉 鈴木
厚司 土谷
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2021532625A priority Critical patent/JP7138796B2/ja
Priority to PCT/JP2019/028158 priority patent/WO2021009882A1/ja
Publication of WO2021009882A1 publication Critical patent/WO2021009882A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/23—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power converter that converts an AC voltage output from an AC power source into a DC voltage, a motor drive device including the power converter, a blower and a compressor equipped with the motor drive device, and the blower or the blower.
  • the present invention relates to an air conditioner equipped with the compressor.
  • one converter circuit is provided with two backflow prevention diodes, two switching elements, and two current detectors, and the negative terminal of the converter circuit is AC via a bypass circuit outside the converter circuit.
  • An interleaved power converter connected to a power source is disclosed.
  • Patent Document 1 has a configuration in which the entire power supply current flows into an AC power supply via a bypass circuit. Therefore, it is not necessary to provide a large-capacity terminal in the converter circuit, and it is said that the power conversion device including the converter circuit can be miniaturized.
  • Patent Document 1 has a configuration in which each switching element has a current detector, and the same number of current detectors as the switching element is required. Therefore, if the number of switching elements is increased in order to increase the number of interleaved phases, the number of current detectors is also increased accordingly. For this reason, there arises a problem that the size of the device becomes large. Further, as the number of parts increases, the cost increases and the reliability of the device also decreases.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a power conversion device capable of detecting a current flowing through a converter circuit while suppressing the number of current detectors.
  • the power conversion device has a plurality of unit converters having one reactor and at least one switching element, and has an AC voltage output from an AC power supply. Is provided with a converter circuit that converts the voltage into a DC voltage. Further, the power conversion device includes one or a plurality of current detectors for detecting the current flowing through the converter circuit. At least one of the one or more current detectors is a first current flowing through the first reactor of the first unit converter of the two unit converters and a second of the second unit converters. The combined current with the second current flowing in the reactor of the above is detected.
  • the power conversion device According to the power conversion device according to the present invention, there is an effect that the current flowing through the converter circuit can be detected while suppressing the number of current detectors.
  • the figure which shows the structure of the power conversion apparatus which concerns on Embodiment 1. A time chart showing an example of waveforms of a main part when the power conversion device according to the first embodiment operates.
  • a block diagram showing a configuration example of a control device according to the first embodiment. A block diagram showing a configuration example of the reference duty calculation unit shown in FIG.
  • a block diagram showing a configuration example of the correction duty calculation unit shown in FIG. A block diagram showing a configuration example of the gate signal calculation unit shown in FIG.
  • a block diagram showing a configuration example of the reference duty calculation unit shown in FIG. A block diagram showing a configuration example of the correction duty calculation unit shown in FIG.
  • Block diagram showing a configuration example of the control device according to the third embodiment A block diagram showing a configuration example of the gate signal calculation unit shown in FIG.
  • FIG. 1 is a diagram showing a configuration of a power conversion device 120 according to the first embodiment.
  • the power conversion device 120 according to the first embodiment includes a converter circuit 10, a smoothing capacitor 6, voltage detectors 71 and 72, a current detector 73, and a control device 200.
  • the converter circuit 10 converts the AC voltage output from the AC power supply 1 into a DC voltage.
  • the smoothing capacitor 6 smoothes and holds the DC voltage converted by the converter circuit 10.
  • the current detector 73 detects the current flowing through the converter circuit 10.
  • the voltage detector 71 detects the output voltage of the AC power supply 1.
  • the voltage detector 72 detects the voltage of the smoothing capacitor 6.
  • the converter circuit 10 includes unit converters 100a and 100b and a rectifier circuit 20.
  • the rectifier circuit 20 has four diodes D21, D22, D23, and D24 that are bridge-connected.
  • the rectifier circuit 20 rectifies the AC voltage output from the AC power supply 1 and applies the rectified voltage to the unit converters 100a and 100b.
  • the unit converter 100a includes a reactor 4a, a backflow blocking diode 5a, and a switching element 3a.
  • the unit converter 100b includes a reactor 4b, a backflow blocking diode 5b, and a switching element 3b.
  • the converter circuit 10 is configured by connecting the unit converter 100a and the unit converter 100b in parallel to each other.
  • the reactor 4a may be referred to as a "first reactor” and the reactor 4b may be referred to as a "second reactor".
  • the converter circuit 10 has a connection point 12 to which one end of the reactor 4a of the unit converter 100a and one end of the reactor 4b of the unit converter 100b, that is, the terminals on the AC power supply 1 side in each of the reactors 4a and 4b are connected. .. Further, the converter circuit 10 has a connection point 14 in which the cathode of the backflow blocking diode 5a of the unit converter 100a and the cathode of the backflow blocking diode 5b of the unit converter 100b, that is, the cathodes of the backflow blocking diodes 5a and 5b are connected to each other. Have.
  • the current detector 73 is arranged between the rectifier circuit 20 and the connection point 12.
  • the location of the current detector 73 shown in FIG. 1 is an example, and the present invention is not limited to this. Variations regarding the arrangement location of the current detector 73 will be described later.
  • the other end of the reactor 4a is connected to the anode of the backflow blocking diode 5a.
  • the cathode of the backflow blocking diode 5a is connected to the positive electrode side terminal of the smoothing capacitor 6.
  • the connection point between the reactor 4a and the backflow blocking diode 5a is connected to one end of the switching element 3a.
  • the unit converter 100b is also configured in the same manner as the unit converter 100a. Further, in the unit converters 100a and 100b, the other ends of the switching elements 3a and 3b are also connected to each other.
  • switching elements 3a and 3b are the illustrated metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET). Insulated gate bipolar transistors (Insulated Gate Bipolar Transistors: IGBTs) may be used instead of the MOSFETs.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • IGBTs Insulated Gate Bipolar Transistors
  • Each of the switching elements 3a and 3b is provided with a diode connected in antiparallel between the drain and the source.
  • the anti-parallel connection means that the drain of the MOSFET and the cathode of the diode are connected, and the source of the MOSFET and the anode of the diode are connected.
  • a parasitic diode that the MOSFET itself has inside may be used. Parasitic diodes are also called body diodes.
  • At least one of the switching elements 3a and 3b is not limited to the MOSFET formed of silicon, and may be a MOSFET formed of a wide bandgap semiconductor such as silicon carbide, gallium nitride, gallium oxide or diamond.
  • wide bandgap semiconductors have higher withstand voltage and heat resistance than silicon semiconductors. Therefore, by using a wide bandgap semiconductor for at least one of the switching elements 3a and 3b, the withstand voltage resistance and the allowable current density of the switching element are increased, and the semiconductor module incorporating the switching element can be miniaturized.
  • the current flowing through the reactor 4a flows through the current detector 73.
  • the current flowing through the reactor 4b flows through the current detector 73.
  • the current detector 73 receives a combined current of the current flowing through the reactor 4a and the current flowing through the reactor 4b.
  • the current flowing through the reactor 4a may be referred to as a "first current”
  • the current flowing through the reactor 4b may be referred to as a "second current”.
  • the control device 200 includes a processor 200a and a memory 200b.
  • the control device 200 receives the detected value of the combined current iac detected by the current detector 73.
  • the control device 200 receives the detected value of the AC voltage vac detected by the voltage detector 71.
  • the control device 200 receives the detection value of the capacitor voltage Vdc, which is the voltage of the smoothing capacitor 6 detected by the voltage detector 72.
  • the control device 200 obtains a gate signal Gate_3a for controlling the switching element 3a and a gate signal Gate_3b for controlling the switching element 3b based on the detected values of the combined current iac, the AC voltage vac, and the capacitor voltage Vdc. Generate.
  • the unit converters 100a and 100b have a gate drive circuit (not shown).
  • the gate drive circuit of the unit converter 100a generates a drive pulse using the gate signal Gate_3a output from the control device 200, and applies the generated drive pulse to the gate of the switching element 3a to drive the switching element 3a.
  • the gate drive circuit of the unit converter 100b generates a drive pulse using the gate signal Gate_3b output from the control device 200, and applies the generated drive pulse to the gate of the switching element 3b to drive the switching element 3b.
  • control device 200 The internal configuration of the control device 200 and the detailed operation of the control device 200 will be described later.
  • the detected value of the AC voltage vac detected by the voltage detector 71 is used for improving the distortion of the current flowing through the converter circuit 10. Therefore, the control regarding the basic operation of the converter circuit 10 is established even if the voltage detector 71 is not provided.
  • the processor 200a is an arithmetic unit such as an arithmetic unit, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor).
  • the memory 200b is a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Project ROM), or an EEPROM (registered trademark) (Electrically EPROM).
  • the memory 200b stores a program that executes the functions of the control device 200 described above and the functions of the control device 200 described later.
  • the processor 200a sends and receives necessary information via an interface including an analog-to-digital converter (not shown) and a digital-to-analog converter, and the processor 200a executes a program stored in the memory 200b to perform a required process.
  • the calculation result by the processor 200a is stored in the memory 200b.
  • the control device 200 controls the switching elements 3a and 3b to be switched with a predetermined duty so that the voltage output from the converter circuit 10 becomes a desired voltage.
  • the unit converters 100a and 100b operate in order according to a predetermined period. This cycle is called the "interleaved cycle". Further, the combination of one reactor and one switching element is counted as one phase.
  • the number of booster circuits defined in the first embodiment matches the number of phases defined here.
  • FIG. 1 is an example of two phases, and is a two-phase interleaved configuration.
  • the second embodiment described later exemplifies the configuration of the four-phase interleaving system
  • the fourth embodiment described later exemplifies the configuration of the three-phase interleaving system.
  • a configuration of a two-phase interleaving system in which one reactor and two switching elements are combined will be illustrated.
  • the present invention is not limited to these examples.
  • N is an integer of 1 or more
  • the number of phases of the power converter according to the present invention may be 2N or 2N + 1.
  • FIG. 2 is a time chart showing a waveform example of a main part when the power conversion device 120 according to the first embodiment operates.
  • FIG. 2A shows the waveforms of the first current i_4a flowing through the reactor 4a and the second current i_4b flowing through the reactor 4b.
  • FIG. 2B shows the waveform of the combined current iac flowing through the current detector 73. The waveform shown in FIG. 2B is a waveform obtained by adding the first current i_4a and the second current i_4b shown in FIG. 2A.
  • FIG. 2C shows the waveform of the carrier signal Car_3a used for generating the gate signal Gate_3a to the switching element 3a.
  • FIG. 2D shows the waveform of the carrier signal Car_3b used to generate the gate signal Gate_3b to the switching element 3b.
  • the period from time t1 to t3 is a carrier cycle.
  • the carrier cycle is equal to the switching cycle Ts, which is a repeating cycle when switching control of the switching elements 3a and 3b.
  • the switching cycle Ts is equal to the reciprocal of the switching frequency fsw that controls the switching elements 3a and 3b.
  • the carrier signal Car_3a is a reverse sawtooth wave that rises sharply at time t1 and falls with a slope at times t1 to t3.
  • the carrier signal Car_3b is a reverse sawtooth wave that rises sharply at time t2 and falls with a slope at times t2 to t4.
  • the time t2 is a time obtained by dividing the period of the times t1 to t3, which is the switching cycle Ts of the carrier signal Car_3a, into two. That is, the time t2 is a time set so that the period of the time t1 to t2 and the period of the time t2 to t3 are equal to each other.
  • time t1 is the gate of the switching element 3a. It is a mountain of carrier signal Car_3a used for signal calculation. Further, the time t2 is a peak of the carrier signal Car_3b used for the gate signal calculation of the switching element 3b.
  • the ripple component of the combined current iac flowing through the current detector 73 has a frequency component twice the switching frequency fsw. Further, both the detected value iac (t1) of the combined current iac at the time t1 and the detected value iac (t2) of the combined current iac at the time t2 are maximum values.
  • the detected value iac (t1) is larger than the detected value iac (t2). That is, there is a deviation between the detected value iac (t1) and the detected value iac (t2). This deviation is the difference in the inductance value of each reactor between each unit converter, the impedance difference between each unit converter due to wiring, etc., and the difference in time lag between the detection timing of each detector in the control device 200 and the reflection timing of the detected value. Due to such factors.
  • FIG. 3 is a block diagram showing a configuration example of the control device 200 according to the first embodiment.
  • the control device 200 shown in FIG. 3 has a component that controls to reduce the deviation between the combined currents iac as shown in FIG.
  • the control device 200 includes an input phase calculation unit 210, a low-pass filter (LPF) 220, a reference duty calculation unit 230, a correction duty calculation unit 240, and a gate signal calculation unit 250. ..
  • LPF low-pass filter
  • the input phase calculation unit 210 calculates the phase of the AC voltage vac based on the detected value of the AC voltage vac, and generates a sinusoidal signal sin ( ⁇ t) synchronized with the phase of the AC voltage vac.
  • the low-pass filter 220 removes a noise frequency component or a switching frequency component from the detected value of the combined current iac.
  • the reference duty calculation unit 230 performs constant output voltage control and high power factor control of the input current.
  • the output voltage referred to here is the voltage output by the converter circuit 10, and the input current is the current flowing in and out of the converter circuit 10.
  • the reference duty calculation unit 230 calculates the reference duty Dreff based on the detected value of the capacitor voltage Vdc and the output of the low-pass filter 220. It should be noted that constant output voltage control and high power factor control of input current are known, and detailed description thereof will be omitted here.
  • the correction duty calculation unit 240 controls to suppress the current imbalance between the single-phase converters.
  • the current non-equilibrium referred to here refers to a state in which a deviation occurs between the combined currents iac at time t1 and time t2, which are two consecutive detection times.
  • the correction duty calculation unit 240 calculates the correction duty Dbal based on the detected value of the combined current iac.
  • the gate signal calculation unit 250 calculates the gate signal Gate_3a and the gate signal Gate_3b based on the reference duty Dref which is the output of the reference duty calculation unit 230 and the correction duty Dbal which is the output of the correction duty calculation unit 240. ..
  • FIG. 4 is a block diagram showing a configuration example of the reference duty calculation unit 230 shown in FIG.
  • the reference duty calculation unit 230 includes a differential device 231, a proportional integral (PI) controller 232, a multiplier 233, a differential device 234, and a PI controller 235.
  • PI proportional integral
  • the diffifier 231 calculates the deviation ⁇ Vdc between the predetermined command value Vdc * of the capacitor voltage and the detected value of the capacitor voltage Vdc.
  • the amplitude command value ⁇ 2Iac * of the combined current iac is generated by PI controlling the deviation ⁇ Vdc.
  • the multiplier 233 the amplitude command value ⁇ 2Iac * is multiplied by the absolute value
  • the diffifier 234 the deviation ⁇ iac between the combined current command value iac *, which is the output of the multiplier 233, and the output of the combined current iac passed through the low-pass filter 220 is calculated.
  • the reference duty Dref is generated by controlling the deviation ⁇ iac by PI.
  • FIG. 5 is a block diagram showing a configuration example of the correction duty calculation unit 240 shown in FIG. As shown in FIG. 5, the correction duty calculation unit 240 has a difference device 241,242 and a PI controller 243.
  • the differencer 241 calculates the deviation ⁇ iac between the detected value iac (t1) of the combined current iac at time t1 and the detected value iac (t2) of the combined current iac at time t2.
  • the times t1 and t2 when the carrier signal is a reverse sawtooth wave are as shown in FIG.
  • the carrier signal does not have to be a reverse sawtooth wave, and may be a triangular wave or a sawtooth wave.
  • the differencer 242 calculates the deviation ⁇ iac between the deviation ⁇ iac, which is the output of the differencer 241 and the theoretical value ⁇ iac * of the amount of change in the current at time t1 and time t2.
  • the theoretical value ⁇ iac * of the amount of change in the current is a difference value between iac (t1) and iac (t2) that can occur depending on the phase of the alternating current, and in the control device 200, , Preset.
  • the correction duty Dbal is generated by controlling the deviation ⁇ iac by PI.
  • FIG. 6 is a block diagram showing a configuration example of the gate signal calculation unit 250 shown in FIG. As shown in FIG. 6, the gate signal calculation unit 250 includes a difference device 251, an adder 252, and a comparator 253, 254.
  • the difference value obtained by subtracting the correction duty Dbal from the reference duty Dref is calculated.
  • the adder 252 the added value of the reference duty Dref and the correction duty Dbal is calculated.
  • the comparator 253 the difference value and the amplitude value of the carrier signal Car_3a are compared, and the comparison result is output.
  • the comparator 254 the added value and the amplitude value of the carrier signal Car_3b are compared, and the comparison result is output. As shown in the figure, the output of the comparator 253 becomes the gate signal Gate_3a to the switching element 3a, and the output of the comparator 254 becomes the gate signal Gate_3b to the switching element 3b.
  • the value of the correction duty Dbal which is the output of the correction duty calculation unit 240 shown in FIG. 5, becomes positive.
  • the output of the diffifier 251 input to the + terminal of the comparator 253 of FIG. 6 is smaller than that when the value of the correction duty Dbal is zero.
  • the output of the adder 252 input to the + terminal of the comparator 254 of FIG. 6 is larger than that when the value of the correction duty Dbal is zero.
  • the time for which the gate signal Gate_3b is output is longer than the time for which the gate signal Gate_3a is output.
  • the detection value iac (t1) becomes smaller
  • the detected value iac (t2) becomes larger
  • the deviation ⁇ iac becomes smaller.
  • the current flowing through each reactor can be equalized, and the temperature rise of each reactor can be equalized.
  • the eddy current loss and the hysteresis loss which are iron losses caused by the change in the current flowing through the reactor, can be reduced. As a result, the efficiency of the device equipped with the power conversion device can be improved.
  • the low-pass filter 220 for removing the noise frequency component or the switching frequency component from the output of the current detector 73 is provided, but the low-pass filter 220 is omitted in an environment where the influence of these frequency components is small. You may.
  • the input phase calculation unit 210 may generate a sine wave signal whose phase is synchronized with the AC power supply 1 based on the output voltage of the rectifier circuit 20. In this case, since the positive half wave and the negative half wave cannot be distinguished, the sine wave signal is
  • the reference duty calculation unit 230 may control each of the combined current iac and the combined current command value iac * between the two unit converters by multiplying them by 1/2 as the input current of the converter circuit of one phase. ..
  • the combined current iac is detected at the time when each carrier signal rises, but the detection timing is arbitrary. As an example of the detection timing, the combined current iac may be detected at the timing when the current flows through the rectifier circuit 20. Alternatively, the combined current iac may be detected at the timing when the current flows through the switching elements 3a and 3b.
  • one current detector 73 flows into the first reactor of the first unit converter of the two unit converters 100a and 100b.
  • the combined current of the first current and the second current flowing through the second reactor of the second unit converter is detected.
  • the current flowing through the converter circuit 10 can be detected while suppressing the number of current detectors.
  • the cost can be reduced.
  • the power conversion device 120 when the power conversion device 120 according to the first embodiment detects the combined current, the detection result of the first combined current detected at one of the two consecutive detection times and the other time are used.
  • the correction duty is calculated based on the detection result of the detected second combined current. Then, control is performed to correct the current non-equilibrium between the unit converters by the calculated correction duty. This makes it possible to correct the deviation between the current flowing in the first reactor and the current flowing in the second reactor even when one current detector is used. Therefore, it is possible to reduce the cost by suppressing the number of current detectors. In addition, it is possible to reduce the cost of sorting, such as searching for a reactor within the range of inductance variation according to the product specifications.
  • the current flowing in each of the two reactors 4a and 4b is equalized by the control for correcting the current imbalance between the unit converters 100a and 100b. It is possible to make the temperature rise of each reactor uniform. As a result, the temperature range that the reactor itself must deal with can be narrowed as compared with the conventional one, and the cost of the reactor itself can be reduced. Further, since the current flowing through each reactor can be equalized, the iron loss generated in the reactor can be reduced. As a result, the efficiency of the device equipped with the power conversion device can be improved.
  • FIG. 7 is a diagram showing a configuration of a power conversion device 120-1 according to a first modification of the first embodiment.
  • the current detector 73 is connected to the output terminal on the high potential side of the rectifier circuit 20, but as shown in FIG. 7, the current detector 73 is connected to the output terminal on the low potential side of the rectifier circuit 20. You may.
  • the control device 200 described above can be used.
  • FIG. 8 is a diagram showing the configuration of the power conversion device 120-2 according to the second modification of the first embodiment.
  • the current detector 73 is connected to the terminal on the output side of the rectifier circuit 20, but as shown in FIG. 8, the current detector 73 may be connected to the terminal on the input side of the rectifier circuit 20. ..
  • the control device 200A is used.
  • FIG. 9 is a block diagram showing a configuration example of the control device 200A in the second modification of the first embodiment.
  • the polarity of the current detected by the current detector 73 may be positive electrode or negative electrode. Therefore, the absolute value calculator 260 is provided in front of the low-pass filter 220. The absolute value calculator 260 calculates the absolute value of the combined current iac so that the detected value of the input combined current iac becomes positive, that is, a positive value, and the calculation result is calculated by the low pass filter 220 and the correction duty calculation. Output to unit 240A.
  • FIG. 10 is a block diagram showing a configuration example of the reference duty calculation unit 230A shown in FIG.
  • the difference device 234 in the reference duty calculation unit 230A in the second modification, is replaced with the difference device 234A in the configuration of the reference duty calculation unit 230 shown in FIG.
  • Other configurations are the same or equivalent to the configuration shown in FIG. 4, and the same or equivalent components are designated by the same reference numerals.
  • the absolute value of the combined current iac is calculated by the absolute value calculator 260. Therefore, the signals input to the diffifier 234A are the absolute value
  • FIG. 11 is a block diagram showing a configuration example of the correction duty calculation unit 240A shown in FIG.
  • the difference device 241 is replaced with the difference device 241A
  • the difference device 242 is replaced by the difference device 242A. It has been replaced.
  • Other configurations are the same as or equivalent to the configuration shown in FIG. 5, and the same or equivalent components are designated by the same reference numerals.
  • the absolute value of the combined current iac is calculated by the absolute value calculator 260. Therefore, the signals input to the diffifier 241A are the absolute value
  • FIG. 12 is a diagram showing a configuration of the power conversion device 120A according to the second embodiment.
  • the power conversion device 120 according to the first embodiment shown in FIG. 1 has a two-phase interleaving system configuration, whereas the power conversion device 120A according to the second embodiment shown in FIG. 12 has a four-phase interleaving system configuration.
  • the converter circuit 10 is replaced by the converter circuit 10A, and the control device 200 is replaced by the control device 200A.
  • a current detector 74 is added between the rectifier circuit 20 and the converter circuit 10A.
  • the unit converter 100c includes a reactor 4c, a backflow blocking diode 5c, and a switching element 3c.
  • the unit converter 100d includes a reactor 4d, a backflow blocking diode 5d, and a switching element 3d.
  • the connection of each reactor, each switching element, and each backflow prevention diode in the unit converters 100c and 100d is the same as that of the unit converters 100a and 100b, and the description thereof is omitted here.
  • the converter circuit 10A has a connection point 12a to which one end of the reactor 4a of the unit converter 100a and one end of the reactor 4b of the unit converter 100b are connected.
  • the converter circuit 10A has a connection point 12b to which one end of the reactor 4c of the unit converter 100c and one end of the reactor 4d of the unit converter 100d are connected.
  • the converter circuit 10A has a connection point 14a to which the cathode of the backflow blocking diode 5a of the unit converter 100a and the cathode of the backflow blocking diode 5b of the unit converter 100b are connected.
  • the converter circuit 10A has a connection point 14b to which the cathode of the backflow blocking diode 5c of the unit converter 100c and the cathode of the backflow blocking diode 5d of the unit converter 100d are connected. Further, the converter circuit 10A has a connection point 14c to which the connection point 14a and the connection point 14b are connected.
  • the combined current iac2 is input to the control device 200A.
  • the combined current iac1 is a current flowing through the current detector 73
  • the combined current iac2 is a current flowing through the current detector 74.
  • the control device 200A has a gate signal Gate_3c for controlling the switching element 3c and a switching element 3d in addition to the gate signals Gate_3a and Gate_3b based on the detected values of the combined currents iac1 and iac2, the AC voltage vac and the capacitor voltage Vdc.
  • a gate signal Gate_3d and a gate signal for controlling the above are generated.
  • the unit converters 100c and 100d have a gate drive circuit (not shown).
  • the gate drive circuit of the unit converter 100c generates a drive pulse using the gate signal Gate_3c output from the control device 200A, and applies the generated drive pulse to the gate of the switching element 3c to drive the switching element 3c.
  • the gate drive circuit of the unit converter 100d generates a drive pulse using the gate signal Gate_3d output from the control device 200A, and applies the generated drive pulse to the gate of the switching element 3d to drive the switching element 3d.
  • the internal configuration of the control device 200A can be realized by using two sets of those shown in the first embodiment.
  • the control device 200A can suppress the current non-equilibrium between the unit converter 100a and the unit converter 100b and the current non-equilibrium between the unit converter 100c and the unit converter 100d.
  • a common sine wave is used by sharing the input phase calculation unit 210 or the like.
  • Each unit converter may be controlled using a wave signal.
  • the carrier phase between the unit converters is, for example, 180 degrees between the unit converter 100a and the unit converter 100b, and 180 degrees between the unit converter 100c and the unit converter 100d.
  • the phase relationship between the unit converter 100a and the unit converter 100c or the unit converter 100d and the phase relationship between the unit converter 100b and the unit converter 100c or the unit converter 100d may be arbitrarily set.
  • the phase relationship between the unit converter 100a and the unit converter 100c and the phase relationship between the unit converter 100b and the unit converter 100d may be matched.
  • the carrier phase may be shifted by 90 degrees between the unit converter 100a and the unit converter 100c, and the carrier phase may be shifted by 90 degrees between the unit converter 100b and the unit converter 100d. In this case, the carrier phases of each unit converter are shifted by 90 degrees.
  • control for suppressing the current imbalance between the unit converters has been described in the second embodiment, the control for correcting the current imbalance between the current detectors may be performed.
  • the correction duty may be generated based on the deviation.
  • a 2N phase converter circuit can be configured by a group of N units of unit converters by forming one set of two unit converters.
  • the number of current detectors can be N or more and 2N-1 or less. If the number of current detectors is 2N-1 or less, at least one current detector is the first current flowing through the first reactor of the first unit converter of the two unit converters and the second unit. The combined current with the second current flowing through the second reactor of the converter can be detected. This has the effect of reducing the number of current detectors.
  • FIG. 13 is a diagram showing a configuration of the power conversion device 120B according to the third embodiment.
  • the converter circuit 10 is replaced with the converter circuit 10B in the configuration of the power conversion device 120 according to the first embodiment shown in FIG. 1, and the control device 200 It has been replaced by the control device 200B.
  • one current detector 73 is arranged between the AC power supply 1 and the connection point 12.
  • the rectifier circuit 20 of the full bridge connection is replaced with the rectifier circuit 22 of the half bridge connection.
  • the unit converter 100a is replaced with the unit converter 100a'
  • the unit converter 100b is replaced with the unit converter 100b'.
  • the backflow blocking diode 5a is replaced with the switching element 3a'
  • the backflow blocking diode 5b is replaced with the switching element 3b'.
  • the connection of each reactor and each switching element in the unit converters 100a'and 100b' is the same as that of the unit converters 100a and 100b, and the description thereof is omitted here.
  • the detected values of the combined current iac and the AC voltage vac are input to the control device 200B.
  • the control device 200B receives a gate signal Gate_3a for controlling the switching element 3a and a gate signal Gate_3b for controlling the switching element 3b based on the detected values of the combined current iac, the AC voltage vac, and the capacitor voltage Vdc. Generate. Further, the control device 200B controls the gate signal Gate_3a'for controlling the switching element 3a'and the switching element 3b' based on the detected values of the combined current iac, the AC voltage vac and the capacitor voltage Vdc. Generates a gate signal Gate_3b'.
  • the unit converter 100a' has a first and second gate drive circuits (not shown), and the unit converter 100b'has a third and fourth gate drive circuits (not shown).
  • the first gate drive circuit generates a drive pulse using the gate signal Gate_3a output from the control device 200B, and applies the generated drive pulse to the gate of the switching element 3a to drive the switching element 3a.
  • the second gate drive circuit generates a drive pulse using the gate signal Gate_3a'output from the control device 200B, and applies the generated drive pulse to the gate of the switching element 3a'to drive the switching element 3a'. ..
  • the third gate drive circuit generates a drive pulse using the gate signal Gate_3b output from the control device 200B, and applies the generated drive pulse to the gate of the switching element 3b to drive the switching element 3b.
  • the fourth gate drive circuit generates a drive pulse using the gate signal Gate_3b'output from the control device 200B, and applies the generated drive pulse to the gate of the switching element 3b'to drive the switching element 3b'. ..
  • FIG. 14 is a block diagram showing a configuration example of the control device 200B according to the third embodiment.
  • the gate signal calculation unit 250 is replaced with the gate signal calculation unit 250B in the configuration of the control device 200A shown in FIG. Further, the AC voltage vac detected by the voltage detector 71 is input to the gate signal calculation unit 250B in addition to the input phase calculation unit 210A. The AC voltage vac is input to the gate signal calculation unit 250B by switching between a switching pattern that controls the switching elements 3a and 3a'according to the polarity of the AC power supply 1 and a switching pattern that controls the switching elements 3b and 3b'. Because. Other configurations are the same as or equivalent to the configuration shown in FIG. 9, and the same or equivalent components are designated by the same reference numerals, and redundant description will be omitted.
  • FIG. 15 is a block diagram showing a configuration example of the gate signal calculation unit 250B shown in FIG.
  • the polarity inversion device 255, 256, the dead time imparting device 257, and the signal selector 261,262 , 263, 264 and the comparator 265 have been added.
  • Other configurations are the same as or equivalent to the configuration shown in FIG. 6, and the same or equivalent components are designated by the same reference numerals.
  • the processing up to the comparators 253 and 254 is the same as in FIG.
  • Each signal selector has an S terminal, an A terminal, a B terminal, and a Y terminal.
  • the output of the comparator 253 is input to the A terminal of the signal selector 261 and the inverting output of the comparator 253 is input to the B terminal of the signal selector 261 via the polarity inverter 255.
  • the output of the comparator 253 is input to the B terminal of the signal selector 262, and the inverted output of the comparator 253 is input to the A terminal of the signal selector 262 via the polarity reversing device 255.
  • the output of the comparator 254 is input to the A terminal of the signal selector 263, and the inverted output of the comparator 254 is input to the B terminal of the signal selector 263 via the polarity inverter 256.
  • the output of the comparator 254 is input to the B terminal of the signal selector 264, and the inverted output of the comparator 254 is input to the A terminal of the signal selector 264 via the polarity reversing device 256.
  • the output of the comparator 265 is input to the S terminal of each signal selector. As shown in the table at the lower right of FIG. 15, if the signal input to the S terminal is logic "1", the signal input to the A terminal is selected and output from the Y terminal. If the signal input to the S terminal is logic "0", the signal input to the B terminal is selected and output from the Y terminal. As a result, each gate signal that is switched according to the switching pattern according to the polarity of the AC power supply 1 is applied to the corresponding switching element.
  • a signal that has passed through the dead time giver 257 is input to the A terminal and the B terminal.
  • the relationship between the switching element 3a and the switching element 3a'and the relationship between the switching element 3b and the switching element 3b' are the relations of the upper and lower arms in the bridge circuit. Therefore, a dead time imparting device 257 is provided so that these switching elements are not turned on at the same time. In the dead time giver 257, the dead time Td is given.
  • the power converter 120B according to the third embodiment is configured as described above, and one current detector 73 is the first unit converter of the two unit converters 100a'and 100b'. The combined current of the first current flowing through the reactor and the second current flowing through the second reactor of the second unit converter can be detected. Further, the power conversion device 120B according to the third embodiment has a control device 200B.
  • the control device 200B has the same function as the control device 200 in the first embodiment. Therefore, as in the first embodiment, control for correcting the current imbalance between the unit converters can be performed. As a result, the same effect as that of the first embodiment can be obtained.
  • FIG. 16 is a diagram showing a configuration of the power conversion device 120C according to the fourth embodiment.
  • the power conversion device 120A according to the second embodiment shown in FIG. 12 has a four-phase interleaving system configuration, whereas the power conversion device 120C according to the fourth embodiment shown in FIG. 16 has a three-phase interleaving system configuration. Is. Specifically, in FIG. 16, in the configuration of FIG. 12, the converter circuit 10A is replaced with the converter circuit 10C.
  • the unit converter 100d is omitted in the configuration of the converter circuit 10A shown in FIG. Therefore, only the unit converter 100c is connected to the current detector 74. Further, the cathode of the backflow blocking diode 5c is connected to the connection point 14a. Further, in FIG. 16, the components corresponding to the control device 200A and the voltage detectors 71 and 72 of FIG. 12 are not shown. Other configurations are the same as or equivalent to the configuration shown in FIG. 12, and the same or equivalent components are designated by the same reference numerals, and redundant description will be omitted.
  • the current detector 74 is connected only to the unit converter 100c, but the current detector 73 is connected to the two unit converters 100a and 100b. Therefore, the current detector 73 has a first current flowing through the first reactor of the first unit converter of the two unit converters 100a and 100b and a second current flowing through the second reactor of the second unit converter. The combined current with the current can be detected. Therefore, the same effect as that of the first embodiment and the second embodiment can be obtained.
  • FIG. 16 describes the case where the number of interleaved phases is 3, but the present invention is not limited to this.
  • N is a natural number and the number of interleaved phases is 2N + 1
  • N is a natural number and the number of interleaved phases is 2N + 1
  • the number of current detectors in this case is N + 1. If the unit converter group is at least one, the effect of reducing the number of current detectors can be obtained. Therefore, a configuration having one unit converter group having two unit converters and a unit converter having 2N-1 is also included in the gist of the present invention.
  • FIG. 17 is a diagram showing a configuration example of the motor drive device 150 according to the fifth embodiment.
  • an inverter 7a and a motor 7b are added to the configuration of the power conversion device 120 shown in FIG.
  • a motor 7b is connected to the output side of the inverter 7a.
  • the motor 7b is an example of a load device.
  • the inverter 7a drives the motor 7b by converting the DC power stored in the smoothing capacitor 6 into AC power and supplying the converted AC power to the motor 7b.
  • the motor drive device 150 shown in FIG. 17 can be applied to products such as blowers, compressors and air conditioners.
  • the power conversion device 120 according to the first embodiment is applied to configure the motor drive device 150, but the present invention is not limited to this.
  • any of the power conversion devices 120-1 and 120-2 according to the first embodiment may be applied.
  • any of the power conversion device 120A according to the second embodiment, the power conversion device 120B according to the third embodiment, or the power conversion device 120C according to the fourth embodiment may be applied.
  • FIG. 18 is a diagram showing an example in which the motor drive device 150 shown in FIG. 17 is applied to an air conditioner.
  • a motor 7b is connected to the output side of the motor drive device 150, and the motor 7b is connected to the compression element 504.
  • the compressor 505 includes a motor 7b and a compression element 504.
  • the refrigeration cycle unit 506 is configured to include a four-way valve 506a, an indoor heat exchanger 506b, an expansion valve 506c, and an outdoor heat exchanger 506d.
  • the flow path of the refrigerant circulating inside the air conditioner is from the compression element 504 via the four-way valve 506a, the indoor heat exchanger 506b, the expansion valve 506c, the outdoor heat exchanger 506d, and again via the four-way valve 506a. , It is configured to return to the compression element 504.
  • the motor drive device 150 receives electric power from the AC power supply 1 and rotates the motor 7b.
  • the compression element 504 executes a compression operation of the refrigerant by rotating the motor 7b, and the refrigerant can be circulated inside the refrigeration cycle unit 506.
  • the power conversion device according to the first to fourth embodiments is provided.
  • products such as blowers, compressors, and air conditioners to which the motor drive device according to the fifth embodiment is applied, the effects described in the first to fourth embodiments can be obtained.
  • the configuration shown in the above-described embodiment shows an example of the content of the present invention, can be combined with another known technique, and is configured without departing from the gist of the present invention. It is also possible to omit or change a part of.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Inverter Devices (AREA)
  • Dc-Dc Converters (AREA)
PCT/JP2019/028158 2019-07-17 2019-07-17 電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機 Ceased WO2021009882A1 (ja)

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PCT/JP2019/028158 WO2021009882A1 (ja) 2019-07-17 2019-07-17 電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機

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WO2025100551A1 (ja) * 2023-11-11 2025-05-15 国立大学法人神戸大学 ４相フローティングインターリーブ方式双方向ｄｃ－ｄｃコンバータ

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JP2013135516A (ja) * 2011-12-26 2013-07-08 Mitsubishi Heavy Ind Ltd 電力変換装置及び空気調和機
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