WO2020249024A1 - 一种显示基板、显示面板及显示装置 - Google Patents

一种显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2020249024A1
WO2020249024A1 PCT/CN2020/095445 CN2020095445W WO2020249024A1 WO 2020249024 A1 WO2020249024 A1 WO 2020249024A1 CN 2020095445 W CN2020095445 W CN 2020095445W WO 2020249024 A1 WO2020249024 A1 WO 2020249024A1
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Prior art keywords
transistor
pixel driving
driving circuit
doped region
active pattern
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PCT/CN2020/095445
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English (en)
French (fr)
Inventor
赵洪浩
廖文骏
鲁晏廷
张陶然
周炟
王建波
黄雯锦
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/260,659 priority Critical patent/US11903272B2/en
Publication of WO2020249024A1 publication Critical patent/WO2020249024A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light-Emitting Diode
  • a display substrate including: a substrate having a display area; a plurality of data lines arranged on the substrate and located in the display area; and a plurality of columns of pixel driving circuits arranged on the substrate And is located in the display area; a column of pixel drive circuits in the multiple columns of pixel drive circuits is connected to a corresponding one of the multiple data lines, and each pixel drive circuit in the column of pixel drive circuits includes a drive A transistor and a first transistor electrically connected to the driving transistor, the driving transistor is a P-type transistor; the first transistor includes: a first active pattern, having a first channel region and being located in the first channel region The first doped region and the second doped region on opposite sides of the first gate, the orthographic projection of the first gate on the substrate and the first channel region on the substrate The orthographic projections overlap; the first insulating block is arranged on the side of the first active pattern away from the substrate, the first insulating block is the part of the insulating layer in the region
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the first via holes in the pixel driving circuit group have the same size, In addition, the sizes of the first via holes in different pixel driving circuit groups are different.
  • the display substrate further includes: a plurality of first voltage lines disposed on the substrate and located in the display area; the plurality of first voltage lines all extend along the first direction The plurality of first voltage lines and the plurality of data lines are arranged in the same layer;
  • the pixel driving circuit further includes a second transistor, the second transistor includes: a second active pattern having a second channel region And a third doped region and a fourth doped region located on opposite sides of the second channel region; the second active pattern is located in the fourth doped region and the first active region The part of the pattern located in the second doped region is connected as a whole; the second gate, the orthographic projection of the second gate on the substrate and the second channel region on the substrate The orthographic projection overlaps; the second insulating block, the second insulating block is the part of the insulating layer in the area where the second transistor is located, and the second insulating block has a second via hole; and the column pixel driving circuit A connected first voltage line is electrically connected to the portion of the second active pattern located
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the second via holes in the pixel driving circuit group have the same size, Moreover, the sizes of the second via holes in different pixel driving circuit groups are different.
  • the pixel driving circuit further includes a storage capacitor;
  • the storage capacitor includes: a first storage electrode; a second storage electrode, arranged between the first storage electrode and the plurality of data lines and the Between the layers where the first voltage lines are located;
  • the driving transistor includes: a third active pattern having a third channel region and fifth doped regions located on opposite sides of the third channel region and A sixth doped region; the part of the third active pattern located in the fifth doped region and the part of the first active pattern located in the second doped region are connected as a whole;
  • a third gate Multiplexed with the first storage electrode, the orthographic projection of the third gate on the substrate overlaps the orthographic projection of the third channel region on the substrate;
  • the insulating layer It includes a first insulating sublayer, a second insulating sublayer, and a third insulating sublayer that are stacked in sequence, the first insulating sublayer is located between the third active pattern and the first storage electrode, and the second insulating sublayer Located between the first storage electrode and
  • the pixel driving circuit further includes: a fourth transistor, the fourth transistor includes: a fourth active pattern having a fourth channel region and located on opposite sides of the fourth channel region The seventh doped region and the eighth doped region; the portion of the fourth active pattern located in the seventh doped region and the portion of the third active pattern located in the sixth doped region are connected as One body; a fourth grid, the orthographic projection of the fourth grid on the substrate overlaps the orthographic projection of the fourth channel region on the substrate; a fourth insulating block, the fourth The insulating block is a part of the insulating layer located in the region where the fourth transistor is located, and the fourth insulating block has a fourth via; a first auxiliary pattern is connected to the plurality of data lines and the plurality of first The voltage lines are arranged in the same layer; the first auxiliary pattern is electrically connected to the part of the fourth active pattern located in the eighth doped region through the fourth via hole; wherein, all the pixel driving circuits in the column The size of the fourth via hole gradually increases
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the fourth via holes in the pixel driving circuit group have the same size, In addition, the sizes of the fourth via holes in different pixel driving circuit groups are different.
  • the display substrate further includes: a plurality of enable signal lines arranged on the substrate and located in the display area; the plurality of enable signal lines all extend along the second direction, so The second direction crosses the first direction; the multiple enable signal lines are arranged in the same layer as the first storage electrode; each enable signal line is connected to a row of pixel drive circuits in a plurality of rows of pixel drive circuits , The part of an enable signal line connected to the pixel driving circuit in the area where the fourth transistor is located and the part in the area where the second transistor is located are used as the fourth gate and The second gate.
  • the pixel driving circuit further includes: at least one fifth transistor, and each fifth transistor includes: a fifth active pattern having a fifth channel region and an opposite side located in the fifth channel region.
  • the ninth doped region and the tenth doped region on both sides; the fifth gate, the orthographic projection of the fifth gate on the substrate and the fifth channel region on the substrate The front projection overlaps; wherein the fifth active pattern in the at least one fifth transistor is located in the ninth doped region and the third active pattern in the driving transistor is located in the first
  • the six doped regions are connected as a whole; the second auxiliary pattern is arranged in the same layer as the first auxiliary pattern; the second auxiliary pattern passes through the fifth insulating sublayer and the fifth insulating sublayer.
  • the via hole is electrically connected to the first storage electrode, and is electrically connected to a portion of the fifth active pattern located in the tenth doped region through a sixth via hole penetrating the insulating layer.
  • the display substrate further includes: a plurality of gate lines disposed on the substrate and located in the display area; the plurality of gate lines all extend along the second direction, and the A plurality of gate lines and the plurality of enable signal lines are arranged in the same layer; each gate line is connected to a row of pixel driving circuits in a plurality of rows of pixel driving circuits, and a gate line connected to the pixel driving circuit is located at all The part in the area where the first transistor is located and the part in the area where the fifth transistor is located are used as the first gate and the fifth gate, respectively.
  • the display substrate further includes: a plurality of initialization signal lines arranged on the substrate and located in the display area; the plurality of initialization signal lines all extend along the second direction, and The plurality of initialization signal lines and the second storage electrode are arranged in the same layer; each initialization signal line is connected to a row of pixel driving circuits in a plurality of rows of pixel driving circuits; the pixel driving circuit further includes: at least one sixth transistor , Each sixth transistor includes: a sixth active pattern having a sixth channel region and an eleventh doped region and a twelfth doped region located on opposite sides of the sixth channel region; Gate, the orthographic projection of the sixth gate on the substrate overlaps the orthographic projection of the sixth channel region on the substrate; wherein the at least one sixth transistor in the The portion of the sixth active pattern located in the twelfth doped region is integrated with the portion of the fifth active pattern in the at least one fifth transistor located in the tenth doped region; a third auxiliary The pattern is provided in the same layer
  • the pixel driving circuit further includes: a seventh transistor; the seventh transistor includes: a seventh active pattern having a seventh channel region and located on opposite sides of the seventh channel region The thirteenth doped region and the fourteenth doped region; the seventh active pattern is located in the fourteenth doped region and the fourth active pattern is located in the eighth doped region Parts are connected as a whole; a seventh grid, the orthographic projection of the seventh grid on the substrate overlaps the orthographic projection of the seventh channel region on the substrate; a fourth auxiliary pattern, and The third auxiliary pattern is arranged in the same layer; the fourth auxiliary pattern is electrically connected to the portion of the seventh active pattern located in the thirteenth doped region through a ninth via hole penetrating the insulating layer, and An initialization signal line corresponding to the next row of pixel driving circuits adjacent to the pixel driving circuit is electrically connected through the tenth via hole penetrating the third sub-insulating layer.
  • the display substrate further includes: a plurality of reset signal lines disposed on the substrate and located in the display area; the plurality of reset signal lines all extend along the second direction, and The plurality of reset signal lines and the plurality of gate lines are arranged in the same layer; a part of the reset signal line connected to the pixel driving circuit in the region where the sixth transistor is located serves as a sixth gate, The portion of the reset signal line connected to the pixel drive circuit of the next row adjacent to the pixel drive circuit located in the region where the seventh transistor is located serves as the gate of the seventh transistor.
  • the display substrate further includes: a plurality of light-emitting devices disposed on the substrate; each pixel driving circuit is electrically connected to one of the plurality of light-emitting devices, and the pixel driving The circuit is configured to drive the light emitting device to emit light.
  • the display substrate further includes: a flat layer disposed between the pixel driving circuit and the light emitting device; the flat layer has a plurality of eleventh via holes; wherein the pixel driving circuit
  • the circuit includes a fourth transistor and a first auxiliary pattern; the light-emitting device includes an anode, a light-emitting functional layer, and a cathode that are sequentially stacked along the thickness direction of the substrate, and the anode of the light-emitting device is connected to at least one eleventh via hole.
  • the first auxiliary pattern is electrically connected; wherein, the size of all the eleventh via holes in the pixel driving circuit of the column gradually increases along the first direction.
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the eleventh vias in the pixel driving circuit group have the same size , And the sizes of the eleventh via holes in different pixel drive circuit groups are different.
  • the display substrate further includes: a pixel defining layer disposed on the side of the anode away from the substrate; the pixel defining layer has a plurality of openings, and each light emitting device is disposed in a corresponding opening Wherein, the size of all the openings corresponding to the pixel drive circuit of the column gradually increase along the first direction.
  • the multiple light-emitting devices include multiple red light-emitting devices, multiple green light-emitting devices, and multiple blue light-emitting devices; for light-emitting devices of the same color, sizes of openings corresponding to light-emitting devices of different colors are different.
  • a display panel which includes the above-mentioned display substrate and an encapsulation layer.
  • a display device including the above-mentioned display panel and a data drive chip arranged on one side of the display panel, and the side where the data drive chip is located is the signal input of the data line in the display panel end.
  • a display substrate including: a substrate having a display area; a plurality of data lines arranged on the substrate and located in the display area; and a plurality of columns of pixel driving circuits arranged on the substrate Above and located in the display area; one column of pixel drive circuits in the multiple columns of pixel drive circuits is connected to a corresponding one of the multiple data lines, and each pixel drive circuit in the column of pixel drive circuits includes A driving transistor and a first transistor electrically connected to the driving transistor, the driving transistor is an N-type transistor; the first transistor includes: a first active pattern having a first channel region and a first transistor located in the first channel The first doped region and the second doped region on opposite sides of the region; the first gate, the orthographic projection of the first gate on the substrate and the first channel region on the liner The orthographic projections on the bottom overlap; the first insulating block is arranged on the side of the first active pattern away from the substrate, and the first insulating block is the part of the
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the first via holes in the pixel driving circuit group have the same size, In addition, the sizes of the first via holes in different pixel driving circuit groups are different.
  • the display substrate further includes: a plurality of first voltage lines disposed on the substrate and located in the display area; the plurality of first voltage lines all extend along the first direction The plurality of first voltage lines and the plurality of data lines are arranged in the same layer;
  • the pixel driving circuit further includes a second transistor, the second transistor includes: a second active pattern having a second channel region And a third doped region and a fourth doped region located on opposite sides of the second channel region; the second active pattern is located in the fourth doped region and the first active region The part of the pattern located in the second doped region is connected as a whole; the second gate, the orthographic projection of the second gate on the substrate and the second channel region on the substrate The orthographic projection overlaps; the second insulating block, the second insulating block is the part of the insulating layer in the area where the second transistor is located, and the second insulating block has a second via hole; and the column pixel driving circuit A connected first voltage line is electrically connected to the portion of the second active pattern located
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the second via holes in the pixel driving circuit group have the same size, Moreover, the sizes of the second via holes in different pixel driving circuit groups are different.
  • the pixel driving circuit further includes a storage capacitor;
  • the storage capacitor includes: a first storage electrode; a second storage electrode, arranged between the first storage electrode and the plurality of data lines and the Between the layers where the first voltage lines are located;
  • the driving transistor includes: a third active pattern having a third channel region and fifth doped regions located on opposite sides of the third channel region and A sixth doped region; the part of the third active pattern located in the fifth doped region and the part of the first active pattern located in the second doped region are connected as a whole;
  • a third gate Multiplexed with the first storage electrode, the orthographic projection of the third gate on the substrate overlaps the orthographic projection of the third channel region on the substrate;
  • the insulating layer It includes a first insulating sublayer, a second insulating sublayer, and a third insulating sublayer that are stacked in sequence, the first insulating sublayer is located between the third active pattern and the first storage electrode, and the second insulating sublayer Located between the first storage electrode and
  • the pixel driving circuit further includes: a fourth transistor, the fourth transistor includes: a fourth active pattern having a fourth channel region and located on opposite sides of the fourth channel region The seventh doped region and the eighth doped region; the portion of the fourth active pattern located in the seventh doped region and the portion of the third active pattern located in the sixth doped region are connected as One body; a fourth grid, the orthographic projection of the fourth grid on the substrate overlaps the orthographic projection of the fourth channel region on the substrate; a fourth insulating block, the fourth The insulating block is a part of the insulating layer located in the region where the fourth transistor is located, and the fourth insulating block has a fourth via; a first auxiliary pattern is connected to the plurality of data lines and the plurality of first The voltage lines are arranged in the same layer; the first auxiliary pattern is electrically connected to the part of the fourth active pattern located in the eighth doped region through the fourth via hole; wherein, all the pixel driving circuits in the column The size of the fourth via hole gradually decrease
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the fourth via holes in the pixel driving circuit group have the same size, In addition, the sizes of the fourth via holes in different pixel driving circuit groups are different.
  • the display substrate further includes: a plurality of enable signal lines arranged on the substrate and located in the display area; the plurality of enable signal lines all extend along the second direction, so The second direction crosses the first direction; the multiple enable signal lines are arranged in the same layer as the first storage electrode; each enable signal line is connected to a row of pixel drive circuits in a plurality of rows of pixel drive circuits , The part of an enable signal line connected to the pixel driving circuit in the area where the fourth transistor is located and the part in the area where the second transistor is located are used as the fourth gate and The second gate.
  • the pixel driving circuit further includes: at least one fifth transistor, and each fifth transistor includes: a fifth active pattern having a fifth channel region and an opposite side located in the fifth channel region.
  • the ninth doped region and the tenth doped region on both sides; the fifth gate, the orthographic projection of the fifth gate on the substrate and the fifth channel region on the substrate The front projection overlaps; wherein the fifth active pattern in the at least one fifth transistor is located in the ninth doped region and the third active pattern in the driving transistor is located in the first
  • the six doped regions are connected as a whole; the second auxiliary pattern is arranged in the same layer as the first auxiliary pattern; the second auxiliary pattern passes through the fifth insulating sublayer and the fifth insulating sublayer.
  • the via hole is electrically connected to the first storage electrode, and is electrically connected to a portion of the fifth active pattern located in the tenth doped region through a sixth via hole penetrating the insulating layer.
  • the display substrate further includes: a plurality of gate lines disposed on the substrate and located in the display area; the plurality of gate lines all extend along the second direction, and the A plurality of gate lines and the plurality of enable signal lines are arranged in the same layer; each gate line is connected to a row of pixel driving circuits in a plurality of rows of pixel driving circuits, and a gate line connected to the pixel driving circuit is located at all The part in the area where the first transistor is located and the part in the area where the fifth transistor is located are used as the first gate and the fifth gate, respectively.
  • the display substrate further includes: a plurality of initialization signal lines arranged on the substrate and located in the display area; the plurality of initialization signal lines all extend along the second direction, and The plurality of initialization signal lines and the second storage electrode are arranged in the same layer; each initialization signal line is connected to a row of pixel driving circuits in a plurality of rows of pixel driving circuits; the pixel driving circuit further includes: at least one sixth transistor , Each sixth transistor includes: a sixth active pattern having a sixth channel region and an eleventh doped region and a twelfth doped region located on opposite sides of the sixth channel region; Gate, the orthographic projection of the sixth gate on the substrate overlaps the orthographic projection of the sixth channel region on the substrate; wherein the at least one sixth transistor in the The portion of the sixth active pattern located in the twelfth doped region is integrated with the portion of the fifth active pattern in the at least one fifth transistor located in the tenth doped region; a third auxiliary The pattern is provided in the same layer
  • the pixel driving circuit further includes: a seventh transistor; the seventh transistor includes: a seventh active pattern having a seventh channel region and located on opposite sides of the seventh channel region The thirteenth doped region and the fourteenth doped region; the seventh active pattern is located in the fourteenth doped region and the fourth active pattern is located in the eighth doped region Parts are connected as a whole; a seventh grid, the orthographic projection of the seventh grid on the substrate overlaps the orthographic projection of the seventh channel region on the substrate; a fourth auxiliary pattern, and The third auxiliary pattern is arranged in the same layer; the fourth auxiliary pattern is electrically connected to the portion of the seventh active pattern located in the thirteenth doped region through a ninth via hole penetrating the insulating layer, and An initialization signal line corresponding to the next row of pixel driving circuits adjacent to the pixel driving circuit is electrically connected through the tenth via hole penetrating the third sub-insulating layer.
  • the display substrate further includes: a plurality of reset signal lines disposed on the substrate and located in the display area; the plurality of reset signal lines all extend along the second direction, and The plurality of reset signal lines and the plurality of gate lines are arranged in the same layer; a part of the reset signal line connected to the pixel driving circuit in the region where the sixth transistor is located serves as a sixth gate, The portion of the reset signal line connected to the pixel drive circuit of the next row adjacent to the pixel drive circuit located in the region where the seventh transistor is located serves as the gate of the seventh transistor.
  • the display substrate further includes: a plurality of light-emitting devices disposed on the substrate; each pixel driving circuit is electrically connected to one of the plurality of light-emitting devices, and the pixel driving The circuit is configured to drive the light emitting device to emit light.
  • the display substrate further includes: a flat layer disposed between the pixel driving circuit and the light emitting device; the flat layer has a plurality of eleventh via holes; wherein the pixel driving circuit
  • the circuit includes a fourth transistor and a first auxiliary pattern; the light-emitting device includes an anode, a light-emitting functional layer, and a cathode that are sequentially stacked along the thickness direction of the substrate, and the anode of the light-emitting device is connected to at least one eleventh via hole.
  • the first auxiliary pattern is electrically connected; wherein the size of all the eleventh via holes in the pixel driving circuit of the column gradually decreases along the first direction.
  • the column of pixel driving circuits is divided into a plurality of pixel driving circuit groups, each pixel driving circuit group includes a plurality of pixel driving circuits, and all the eleventh vias in the pixel driving circuit group have the same size , And the sizes of the eleventh via holes in different pixel drive circuit groups are different.
  • the display substrate further includes: a pixel defining layer disposed on the side of the anode away from the substrate; the pixel defining layer has a plurality of openings, and each light emitting device is disposed in a corresponding opening Wherein, the size of all the openings corresponding to the pixel drive circuit of the column gradually decreases along the first direction.
  • the multiple light-emitting devices include multiple red light-emitting devices, multiple green light-emitting devices, and multiple blue light-emitting devices; for light-emitting devices of the same color, sizes of openings corresponding to light-emitting devices of different colors are different.
  • a display panel which includes the above-mentioned display substrate and an encapsulation layer.
  • a display device including the above-mentioned display panel and a data drive chip arranged on one side of the display panel, and the side where the data drive chip is located is the signal input of the data line in the display panel end.
  • FIG. 1 is a schematic structural diagram of a display device provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of area division of a display panel provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural diagram of an electroluminescent display panel provided by some embodiments of the present disclosure.
  • FIG. 4 is a plan view of an electroluminescent display panel provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit provided by some embodiments of the disclosure.
  • FIG. 6 is a schematic structural diagram of another pixel driving circuit provided by some embodiments of the disclosure.
  • FIG. 7 is a schematic structural diagram of a first transistor provided by some embodiments of the disclosure.
  • FIG. 8 is a schematic diagram of the size distribution of a first via hole provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of the size distribution of another first via hole provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of uneven long-range display brightness of a display panel in the related art
  • FIG. 11 is a circuit layout diagram corresponding to the pixel driving circuit in FIG. 6 provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a first transistor and a second transistor provided by some embodiments of the present disclosure.
  • FIG. 13 is a schematic diagram of the size distribution of a second via hole provided by some embodiments of the present disclosure.
  • FIG. 14 is a schematic diagram of the size distribution of another second via provided by some embodiments of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a second transistor and a driving transistor provided by some embodiments of the present disclosure.
  • 16 is a schematic structural diagram of a fourth transistor and a seventh transistor provided by some embodiments of the present disclosure.
  • FIG. 17 is a schematic diagram of the size distribution of a fourth via hole provided by some embodiments of the present disclosure.
  • FIG. 18 is a schematic diagram of the size distribution of another fourth via hole provided by some embodiments of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a driving transistor, a fifth transistor, and a sixth transistor provided by some embodiments of the present disclosure.
  • 20 is a schematic structural diagram of a fourth transistor and an anode of a light emitting device provided by some embodiments of the present disclosure
  • FIG. 21 is a schematic diagram of the size distribution of an eleventh via provided by some embodiments of the present disclosure.
  • 22 is a schematic diagram of the size distribution of another eleventh via provided by some embodiments of the present disclosure.
  • FIG. 23 is a schematic diagram of the size distribution of an opening provided by some embodiments of the present disclosure.
  • FIG. 24 is a schematic diagram of the size distribution of another opening provided by some embodiments of the present disclosure.
  • first, second and similar words used in the specification and claims of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • connection may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “connected” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • Some embodiments of the present disclosure provide a display device, which can be used as a mobile phone, a tablet computer, a personal digital assistant (personal digital assistant, PDA), a vehicle-mounted computer, etc.
  • the embodiments of the present disclosure do not make use of the display device. Special restrictions.
  • the display device may be an organic electroluminescence display device or a quantum dot electroluminescence display device.
  • the display device includes a frame 1, a cover plate 2, a display panel 3, a circuit board 4, a flexible circuit board 5, and other electronic accessories such as a camera.
  • the frame 1 is a U-shaped frame
  • the circuit board 4 and the flexible circuit board 5 are arranged in a cavity enclosed by the frame 1 and the cover plate 2.
  • the flexible circuit board 5 is arranged on the edge of the display panel 3, and the circuit board 4 is connected to the flexible circuit board 5 and arranged on the side of the display panel 3 away from the cover 2.
  • the flexible circuit board 5 includes a flexible circuit board body and at least one driver chip provided on the flexible circuit board body, and the driver chip may be a driver IC (Integrate Circuit, integrated circuit).
  • the at least one driving IC includes at least one data driving IC.
  • the circuit board 4 is configured to provide the display panel 3 with signals required for display.
  • the circuit board 4 is a printed circuit board assembly (Printed Circuit Board Assembly, PCBA), and the PCBA includes a printed circuit board (Printed Circuit Board, PCB) and a timing controller (TCON) set on the PCB and power management Integrated circuits (Power Management IC, PMIC) and other ICs or circuits, etc.
  • PCBA printed circuit board Assembly
  • TCON timing controller
  • the display panel 3 has a display area 31 and a peripheral area 32 for wiring.
  • the peripheral area 32 is arranged in a circle around the display area 31.
  • the peripheral area 32 is only located on one side of a part of the edge of the display area 31, for example, located on opposite sides of the display area 31.
  • FIG. 2 illustrates an example in which the peripheral area 32 is arranged in a circle around the display area 31.
  • the display area 31 includes a plurality of sub-pixel areas 33, and the plurality of sub-pixel areas 33 at least include a plurality of red sub-pixel areas, a plurality of green sub-pixel areas, and a plurality of blue sub-pixel areas.
  • the display panel 3 is an electroluminescence display panel.
  • the electroluminescent display panel includes a display substrate 34 and an encapsulation layer 35 for encapsulating the display substrate 34.
  • the packaging layer 35 can be a packaging film or a packaging substrate.
  • the display substrate 34 includes a substrate 340, a plurality of pixel driving circuits 30 and a plurality of light emitting devices L disposed on the substrate 340 and located in the display area 31.
  • Each pixel driving circuit 30 is correspondingly disposed in a sub-pixel area 33, and each light-emitting device L is correspondingly disposed in a sub-pixel area 33 and is electrically connected to the pixel driving circuit 30 located in the sub-pixel area 33.
  • the pixel driving circuit 30 is configured to drive the corresponding light emitting device L to emit light.
  • the circuit structure of the pixel driving circuit 30 is 2T1C, and its equivalent circuit is shown in FIG. 5.
  • the pixel driving circuit 30 includes a first transistor T1, a driving transistor Td, and a storage capacitor Cst.
  • the gate of the first transistor T1 is electrically connected to the gate line Vgate
  • the first electrode of the first transistor T1 is electrically connected to the data line Vdata
  • the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor Td
  • the driving transistor Td The first pole of the light emitting device L is electrically connected to the first voltage line Vdd
  • the second pole of the driving transistor Td is electrically connected to the anode of the light emitting device L
  • the cathode of the light emitting device L is electrically connected to the second voltage line Vss.
  • the first storage electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the second storage electrode of the storage capacitor Cst is electrically connected to the second electrode of the driving transistor Td. It should be noted that, for each transistor, one of the first electrode and the second electrode is the source, and the other is the drain.
  • the circuit structure of the pixel driving circuit 30 is 7T1C, and its equivalent circuit is shown in FIG. 6.
  • the pixel driving circuit 30 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor. T4, fifth transistor T5, sixth transistor T6, driving transistor Td, and storage capacitor Cst.
  • the gate of the first transistor T1 is electrically connected to the gate line Vgate, the first electrode of the first transistor T1 is electrically connected to the data line Vdata, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the driving transistor Td.
  • the second electrode of the driving transistor Td is electrically connected to the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5, and the gate of the driving transistor Td is electrically connected to the second electrode of the fifth transistor T5.
  • the gate of the fifth transistor T5 is electrically connected to the gate line Vgate.
  • the gate of the fourth transistor T4 is electrically connected to the enable signal line EM
  • the second electrode of the fourth transistor T4 is electrically connected to the anode of the light emitting device L
  • the cathode of the light emitting device L is electrically connected to the second voltage line Vss.
  • the gate of the second transistor T2 is electrically connected to the enable signal line EM, the first electrode of the second transistor T2 is electrically connected to the first voltage line Vdd, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor Td. connection.
  • the gate of the sixth transistor T6 is electrically connected to the reset signal line Vreset, the first electrode of the sixth transistor T6 is electrically connected to the initialization signal line Vinit, and the second electrode of the sixth transistor T6 is electrically connected to the gate of the driving transistor Td.
  • the gate of the seventh transistor T7 is electrically connected to the reset signal line Vreset connected to the sixth transistor T6 in the pixel driving circuit 30 of the next row, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal line Vinit, and the The second pole is electrically connected to the anode of the light emitting device L.
  • the first storage electrode of the storage capacitor Cst is electrically connected to the first voltage line Vdd, and the second storage electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor Td.
  • the width-to-length ratio of the channel of the driving transistor Td is greater than that of the channels of other switching transistors.
  • the pixel drive circuit 30 is not limited to the structure shown in FIG. 5 and FIG. 6, and it can also be other types of pixel drive circuits, which will not be described here. Enumerate. However, it should be understood that regardless of the structure of the pixel driving circuit 30, it at least includes a driving transistor Td, a switching transistor and a storage capacitor Cst. On this basis, the display substrate 3 includes a gate line Vgate, a data line Vdata, and a first voltage line Vdd connected to the pixel driving circuit 30.
  • the driving transistor Td may be a P-type transistor or an N-type transistor. The following description will be given by taking the driving transistor Td as a P-type transistor as an example.
  • the display substrate 34 includes a substrate 340, a plurality of gate lines Vgate, a plurality of data lines Vdata, a plurality of first voltage lines Vdd, and a plurality of columns disposed on the substrate 340 and located in the display area 31.
  • Pixel driving circuit 30 The plurality of data lines Vdata and the plurality of first voltage lines Vdd all extend in the first direction, and the plurality of gate lines Vgate extend in the second direction.
  • the first direction and the second direction cross each other, for example, are perpendicular to each other.
  • the first direction is the direction in which the signal input end of the data line Vdata points to the opposite far end of the signal input end.
  • each column of pixel drive circuits 30 includes multiple pixel drive circuits 30 arranged along the first direction, and each pixel drive circuit 30 is located in a corresponding sub-pixel area 33. in.
  • the multiple data lines Vdata and the multiple first voltage lines Vdd are arranged in the same layer, and the multiple gate lines Vgate are arranged between the layer where the multiple data lines Vdata and the multiple first voltage lines Vdd are located and the substrate 340.
  • the “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a patterning process.
  • the patterning process may include exposure, development and etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • One column of pixel driving circuits 30 in the plurality of columns of pixel driving circuits 30 arranged along the second direction is connected to a corresponding one of the plurality of data lines Vdata.
  • each column of pixel driving circuit 30 is connected to a corresponding data line Vdata.
  • One column of pixel driving circuits 30 in the plurality of columns of pixel driving circuits 30 arranged in the second direction is connected to a corresponding first voltage line Vdd among the plurality of first voltage lines Vdd.
  • each column of pixel driving circuit 30 is connected to a corresponding first voltage line Vdd.
  • the first voltage line Vdd is configured to provide a first power supply voltage signal to the pixel driving circuit 30, and the first power supply voltage signal is, for example, a high-level signal.
  • a plurality of pixel driving circuits 30 arranged along the second direction in the multi-column pixel driving circuit 30 constitute a row of pixel driving circuits 30.
  • one row of pixel driving circuits 30 in the multi-row pixel driving circuit 30 is connected to a corresponding one of the plurality of gate lines Vgate.
  • each row of pixel driving circuit 30 is connected to a corresponding gate line Vgate.
  • Each pixel driving circuit 30 in the column of pixel driving circuits 30 includes a driving transistor Td and a first transistor T1 electrically connected to the driving transistor Td.
  • the first transistor T1 is a P-type transistor.
  • the first transistor T1 includes a first active pattern 101, a first gate 102 and a first insulating block 103.
  • the first active pattern 101 has a first channel region 1010 and a first doped region 1011 and a second doped region 1012 located on opposite sides of the first channel region 1010.
  • the orthographic projection of the first gate 102 on the substrate 340 overlaps the orthographic projection of the first channel region 1010 on the substrate 340.
  • the gate line Vgate connected to the pixel driving circuit 30 is located at the first transistor T1.
  • the part in the region serves as the first gate 102.
  • the first insulating block 103 is disposed on the side of the first active pattern 101 away from the substrate 340.
  • the first insulating block 103 has a first via 1030, and the data line Vdata passes through the first via 1030 and the first active pattern.
  • the portion 101 located in the first doped region 1011 is electrically connected.
  • the first insulating block 103 is a part of the insulating layer 38 in the area where the first transistor T1 is located.
  • the insulating layer 38 may be composed of multiple insulating sub-layers, and the number of layers needs to be determined according to the structure of the display substrate 34.
  • the first doped region 1011 and the second doped region 1012 are ion-doped, so that the first active pattern 101 is located in the first doped region 1011 and the second doped region 1011.
  • the part of the second doped region 1012 is a conductor.
  • the subsequent doped region it has the same meaning as the doped region here.
  • the size of all the first via holes 1030 gradually decreases along the first direction.
  • Each sub-pixel area in FIG. 8 and FIG. 9 only illustrates the structure of the first via hole 1030.
  • the “size of the via” mentioned in the embodiment of the present disclosure refers to the size of the orthographic projection of the via on the substrate 340.
  • the sizes of all the first via holes 1030 are sequentially decreased along the first direction. That is, in the column of pixel driving circuits 30, the sizes of all the first via holes 1030 are different.
  • the column of pixel driving circuits 30 is divided into a plurality of pixel driving circuit groups 300, each pixel driving circuit group 300 includes a plurality of pixel driving circuits 30, different pixel driving circuit groups 300
  • the number of pixel driving circuits 30 included may be the same or different.
  • the sizes of the first via holes 1030 in the pixel driving circuit group 300 are the same.
  • the size of the first via hole 1030 in different pixel drive circuit groups 300 is different, that is, along the first direction, the first via hole 1030 in the current pixel drive circuit group 300 is relative to the first via hole 1030 in the previous pixel drive circuit group 300.
  • the size of a via hole 1030 is reduced.
  • the display device can input signals to the data line Vdata and the first voltage line Vdd in the display panel through the flexible circuit board 5. As shown in FIG. 10, since the flexible circuit board 5 is arranged on one side of the display panel 3, and the data line Vdata and the first voltage line Vdd have a certain impedance, the signals on the data line Vdata and the first voltage line Vdd are along the first A pressure drop (IR drop) will occur in either direction.
  • the data signal provided by the data line Vdata is written into the gate of the driving transistor Td, and the smaller the voltage value of the data signal provided by the data line Vdata, the lower the voltage value of the light emitting device L The higher the brightness.
  • the first power voltage signal provided by the first voltage line Vdd is input to the source of the driving transistor Td, and the greater the voltage value of the first power voltage signal provided by the first voltage line Vdd, the higher the brightness of the light emitting device L. Regardless of the voltage drop on the first voltage line Vdd, the voltage drop on the data line Vdata causes the brightness of the light emitting device L along the first direction to gradually increase.
  • the brightness of the light emitting device L along the first direction will be reduced.
  • the voltage value of the data signal on the data line Vdata is relatively small, so that the voltage drop of the data signal has a significantly smaller impact on the brightness of the picture than on the first voltage line Vdd.
  • the voltage drop of a power supply voltage signal affects the brightness of the screen. Therefore, as shown in FIG. 10, along the first direction, the brightness of the light-emitting device L connected to the pixel driving circuit 30 of the column is significantly reduced. As a result, the display device has the problem of uneven long-range display brightness.
  • the size of the first via hole 1030 for electrically connecting the data line Vdata and the first transistor T1 is The first direction gradually decreases, and without considering the voltage drop on the data line Vdata, the voltage of the data signal written into the pixel driving circuit 30 of the column gradually decreases. On this basis, due to the existence of the voltage drop on the data line Vdata, the voltage value of the data signal on the data line Vdata is further reduced in the first direction.
  • the voltage value of the data signal provided by the data line Vdata is smaller, the brightness of the light emitting device L is higher, and therefore, the display brightness of the light emitting device L connected to the pixel driving circuit 30 of the column is increased in the first direction. Therefore, the problem of the brightness reduction of the light emitting devices L arranged in the first direction can be improved, and the uniformity of the display brightness can be improved.
  • the display substrate 34 further includes a plurality of enable signal lines EM disposed on the substrate 340 and located in the display area 31, and the enable signal lines EM extend along the second direction.
  • the multiple enable signal lines EM and the multiple gate lines Vgate are arranged in the same layer.
  • the enable signal line EM is configured to output an on signal during the light-emitting phase.
  • FIG. 11 only illustrates the layer structure of one pixel driving structure 30 and the signal lines connected thereto.
  • One row of pixel driving circuits 30 in the plurality of rows of pixel driving circuits 30 arranged in the first direction is connected to a corresponding one of the plurality of enable signal lines EM.
  • each row of pixel driving circuit 30 is connected to a corresponding enable signal line EM.
  • the pixel driving circuit 30 further includes a second transistor T2.
  • the second transistor T2 includes a second active pattern 201, a second gate 202 and a second insulating block 203.
  • the second active pattern 201 has a second channel region 2010, and a third doped region 2011 and a fourth doped region 2012 located on opposite sides of the second channel region 2010.
  • the second active pattern 201 is located in the fourth doped region.
  • the portion of the impurity region 2012 and the portion of the first active pattern 101 in the second doped region 1012 are connected as a whole.
  • the orthographic projection of the second gate 202 on the substrate 340 overlaps the orthographic projection of the second channel region 2010 on the substrate 340.
  • the enable signal line EM connected to the pixel driving circuit 30 is located in the second The part in the region where the transistor T2 is located serves as the second gate 202.
  • the second insulating block 203 is a part of the insulating layer 38 in the region where the second transistor T2 is located.
  • the second insulating block 203 has a second via 2030, and the first voltage line Vdd passes through the second via 2030 and the second active pattern 201 is located in a part of the third doped region 2011 that is electrically connected.
  • the first active pattern 101 and the second active pattern 101 can be fabricated simultaneously.
  • the source pattern 201 can simplify the manufacturing process of the display substrate 34.
  • each sub-pixel region in FIGS. 13 and 14 only illustrates the structure of the second via 2030.
  • the sizes of all the second via holes 2030 increase sequentially along the first direction. That is, in the column of pixel driving circuits 30, the sizes of all the second via holes 2030 are different.
  • the column of pixel driving circuits 30 is divided into a plurality of pixel driving circuit groups 300, each pixel driving circuit group 300 includes a plurality of pixel driving circuits 30, different pixel driving circuit groups 300
  • the number of pixel driving circuits 30 included may be the same or different.
  • All the second via holes 2030 in the pixel driving circuit group 300 have the same size, and the second via holes 2030 in different pixel driving circuit groups 300 have different sizes. That is, along the first direction, the size of the second via 2030 in the current pixel driving circuit group 300 increases relative to the size of the second via 2030 in the previous pixel driving circuit group 300.
  • the size of the second via 2030 for electrically connecting the first voltage line Vdd and the second transistor T2 gradually increases along the first direction. Increase.
  • the gradual increase in the size of the second via 2030 will again The voltage value of the first power supply voltage signal transmitted to the pixel driving circuit 30 of the column gradually increases in the first direction, so that the voltage value of the first power voltage signal transmitted to the pixel driving circuit 30 of the column tends to In balance. In this way, the problem of uneven long-range display brightness can be further improved, thereby improving the display quality of the display panel 3.
  • the pixel driving circuit 30 further includes a storage capacitor Cst.
  • the storage capacitor Cst includes a first storage electrode C1 and a second storage electrode C2.
  • the second storage electrode C2 is located between the first storage electrode C1 and the plurality of data lines Vdata and the plurality of first voltage lines Vdd.
  • the driving transistor Td includes a third active pattern 301 and a third gate 302.
  • the third active pattern 301 has a third channel region 3010, and a fifth doped region 3011 and a sixth doped region 3012 located on opposite sides of the third channel region 3010.
  • the third active pattern 301 is located in the fifth doped region.
  • the portion of the impurity region 3011 is integrated with the portion of the first active pattern 101 in the second doped region 1012 and the portion of the second active pattern 201 in the fourth doped region 2012.
  • the third gate 302 is multiplexed with the first storage electrode C1, and the orthographic projection of the third gate 302 on the substrate 340 overlaps with the orthographic projection of the third channel region 3010 on the substrate 340.
  • the third active pattern 301 is located in the fifth doped region 3011, the first active pattern 101 is located in the second doped region 1012 and the second active pattern 201 is located in the fourth doped region 2012. Therefore, the first active pattern 101, the second active pattern 201 and the third active pattern 301 can be manufactured at the same time, thereby further simplifying the manufacturing process of the display substrate 34.
  • the insulating layer 38 includes a first insulating sublayer 381, a second insulating sublayer 382, and a third insulating sublayer 383 stacked in sequence.
  • the first insulating sublayer 381 is located between the third active pattern 301 and the first storage electrode C1.
  • the second insulating sublayer 382 is located between the first storage electrode C1 and the second storage electrode C2, and the third insulating sublayer 383 is located between the second storage electrode C2 and the plurality of data lines Vdata and the plurality of first voltage lines Vdd.
  • the first voltage line Vdd is electrically connected to the second storage electrode C2 through a third via 303 penetrating the third insulating sublayer 383.
  • the pixel driving circuit 30 further includes a fourth transistor T4 and a first auxiliary pattern 400 provided in the same layer as the plurality of data lines Vdata and the plurality of first voltage lines Vdd.
  • the fourth transistor T4 includes a fourth active pattern 401, a fourth gate 402, and a fourth insulating block 403.
  • the fourth active pattern 401 has a fourth channel region 4010 and a seventh doped region 4011 and an eighth doped region 4012 located on opposite sides of the fourth channel region 4010.
  • the portion of the fourth active pattern 401 located in the seventh doped region 4011 and the portion of the third active pattern 301 located in the sixth doped region 3012 are integrally connected.
  • the orthographic projection of the fourth gate 402 on the substrate 340 overlaps the orthographic projection of the fourth channel region 4010 on the substrate 340.
  • the enable signal line EM connected to the pixel drive circuit 30 is located in the fourth transistor
  • the part in the area where T4 is located serves as the fourth gate 402.
  • the fourth insulating block 403 is a part of the insulating layer 38 in the area where the fourth transistor T4 is located.
  • the fourth insulating block 403 has a fourth via 4030.
  • the first auxiliary pattern 400 is located between the fourth active pattern 401 and the fourth via 4030.
  • Part of the eighth doped region 4012 is electrically connected.
  • electrical connection between the light emitting device L and the portion of the fourth active pattern 401 located in the eighth doped region 4012 is achieved through the first auxiliary pattern 400.
  • the third active pattern 301 and the fourth active pattern 301 can be fabricated at the same time.
  • the source pattern 401 can simplify the manufacturing process of the display substrate 34.
  • the size of all the fourth via holes 4030 in the pixel driving circuit 30 of the column gradually increases along the first direction.
  • Each sub-pixel area in FIG. 17 and FIG. 18 only illustrates the structure of the fourth via 4030.
  • the sizes of all the fourth via holes 4030 are sequentially increased along the first direction. That is, in the column of pixel driving circuits 30, the sizes of all the fourth via holes 4030 are different.
  • the column of pixel driving circuits 30 is divided into a plurality of pixel driving circuit groups 300, each pixel driving circuit group 300 includes a plurality of pixel driving circuits 30, different pixel driving circuit groups 300
  • the number of pixel driving circuits 30 included may be the same or different.
  • the size of the fourth via 4030 in the pixel drive circuit group 300 is the same, and the size of the fourth via 4030 in different pixel drive circuit groups 300 is different. That is, along the first direction, the size of the fourth via 4030 in the current pixel drive circuit group 300 is increased relative to the size of the fourth via 4030 in the previous pixel drive circuit group 300.
  • the size of the fourth via 4030 for electrically connecting the light emitting device L and the pixel drive circuit 30 is along the first direction Gradually increase.
  • the driving current output by the driving transistor Td is transmitted to the light emitting device L through the fourth transistor T4, and the voltage drop of the first voltage line Vdd in the first direction will cause the voltage value of the first power supply voltage signal to gradually decrease, so that the transmission to The driving current of the light emitting device L gradually decreases along the first direction.
  • the size of the fourth via 4030 gradually increases along the first direction, which can reduce the contact resistance between the fourth transistor T4 and the first auxiliary pattern 400, so that the size of the driving current output to the light emitting device L tends to be balanced. In this way, the problem of uneven long-range display brightness can be further improved.
  • the pixel driving circuit 30 further includes at least one fifth transistor T5 and a second auxiliary pattern 500 provided in the same layer as the first auxiliary pattern 400.
  • each fifth transistor T5 includes a fifth active pattern 501 and a fifth gate 502.
  • the fifth active pattern 501 has a fifth channel region 5010 and a ninth doped region 5011 and a tenth doped region 5012 located on opposite sides of the fifth channel region 5010.
  • the orthographic projection of the fifth gate 502 on the substrate 340 overlaps the orthographic projection of the fifth channel region 5010 on the substrate 340.
  • the gate line Vgate connected to the pixel driving circuit 30 is located at the fifth transistor T5. The part in the area serves as the fifth gate 502.
  • the portion of the fifth active pattern 501 in the at least one fifth transistor T5 located in the ninth doped region 5011 is integrated with the portion of the driving transistor Td located in the sixth doped region 3012.
  • the second auxiliary pattern 500 is electrically connected to the first storage electrode C1 through the fifth via hole 304 penetrating the third insulating sublayer 383 and the second insulating sublayer 382, and is electrically connected to the fifth active electrode C1 through the sixth via hole 503 penetrating the insulating layer 38.
  • the portion of the pattern 501 located in the tenth doped region 5012 is electrically connected.
  • the pixel driving circuit 30 includes a plurality of fifth transistors T5
  • the plurality of fifth transistors T5 are connected in series, that is, the fifth active pattern 501 of the first fifth transistor T5 is located in the ninth doped region 5011 Part is connected to the part of the driving transistor Td located in the sixth doped region 3012, the fifth active pattern 5010 of the first fifth transistor T5 is located in the tenth doped region 5012 and the part of the second fifth transistor T5
  • the portions of the fifth active pattern 5010 located in the ninth doped region 5011 are connected as a whole, and so on.
  • the fifth active pattern 5010 of the first fifth transistor T5 is located in the tenth doped region 5012 and the second fifth transistor T5
  • the part of the fifth active pattern 5010 located in the ninth doped region 5011 is connected as a whole, so the two fifth transistors T5 can be regarded as a fifth equivalent transistor, and the fifth active pattern of the fifth equivalent transistor
  • the portion of the pattern 501 located in one of its doped regions is the portion of the fifth active pattern 5010 of the first fifth transistor T5 located in the ninth doped region 5011
  • the portion located in the other doped region is the portion located in the tenth doped region 5012 of the fifth active pattern 5010 of the second fifth transistor T5.
  • the second auxiliary pattern 500 is electrically connected to the portion of the fifth active pattern 501 located in the tenth doped region 5012 through the sixth via 503 penetrating the insulating layer 38, which actually means that the second auxiliary pattern 500 passes through the first via hole 503 penetrating the insulating layer 38.
  • the six via holes 503 are electrically connected to the part of the fifth active pattern 501 of the fifth equivalent transistor in the other doped region.
  • the fifth active pattern 501 in the fifth transistor T5 is integrated with the third active pattern 301 of the driving transistor Td, the third active pattern 301 and the fifth active pattern 501 can be produced at the same time, thereby simplifying the display The manufacturing process of the substrate 34.
  • the display substrate 34 further includes a plurality of initialization signal lines Vinit and a plurality of reset signal lines Vreset disposed on the substrate 340 and located in the display area, and a plurality of initialization signal lines Vinit and
  • the multiple reset signal lines Vreset all extend along the second direction, the multiple reset signal lines Vreset and the multiple gate lines Vgate are arranged in the same layer, and the multiple initialization signal lines Vinit and the second storage electrode C2 are arranged in the same layer.
  • the initialization signal line Vinit is configured to provide an initialization signal
  • the reset signal line Vreset is configured to provide a reset signal.
  • the pixel driving circuit 30 further includes at least one sixth transistor T6 and a third auxiliary pattern 600 provided in the same layer as the first auxiliary pattern 400.
  • each sixth transistor T6 includes a sixth active pattern 601 and a sixth gate 602.
  • the sixth active pattern 601 has a sixth channel region 6010 and an eleventh doped region 6011 and a twelfth doped region 6012 located on opposite sides of the sixth channel region 6010.
  • the orthographic projection of the sixth gate 602 on the substrate 340 overlaps the orthographic projection of the sixth channel region 6010 on the substrate 340.
  • a reset signal line Vreset connected to the pixel drive circuit 30 is located at the sixth The part in the region where the transistor T6 is located serves as the sixth gate 602.
  • At least one sixth active pattern 601 in the sixth transistor T6 is located in a portion of the twelfth doped region 6012 and at least one fifth active pattern 501 in the fifth transistor T5 is located in a portion of the tenth doped region 5012 Connect as one.
  • the third auxiliary pattern 600 is electrically connected to an initialization signal line Vinit connected to the pixel driving circuit 30 through a seventh via 603 penetrating the third insulating sublayer 383, and is electrically connected to at least one first via 604 penetrating the insulating layer 38.
  • the sixth active pattern 601 in the six transistor T6 is electrically connected to the portion of the eleventh doped region 6011 to realize the electrical connection between the sixth transistor T6 and the initialization signal line Vinit.
  • the pixel driving circuit 30 includes a plurality of sixth transistors T6, the plurality of sixth transistors T6 are connected in series, that is, the sixth active pattern 6010 of the first sixth transistor T6 is located in the twelfth doped region 6012
  • the part of the sixth active pattern 6010 of the second sixth transistor T6 is connected to the part of the eleventh doped region 6011, and so on, the sixth active pattern 601 of the last sixth transistor T6 is located in the first
  • the portion of the twelve-doped region 6012 is integrated with the portion of the fifth active pattern 501 of the last fifth transistor T5 in the tenth doped region 5012 of the at least one fifth transistor T5.
  • the sixth active pattern 6010 of the first sixth transistor T6 is located in the portion of the twelfth doped region 6012 and the second sixth transistor T6
  • the part of the sixth active pattern 6010 in the eleventh doped region 6011 is connected as a whole, so the two sixth transistors T6 can be regarded as a sixth equivalent transistor, and the sixth active pattern of the sixth equivalent transistor
  • the portion of the pattern 6010 in one of its doped regions is the sixth active pattern 6010 of the first sixth transistor T6 in the eleventh doped region 6011, and the sixth active pattern 6010 of the sixth equivalent transistor is located in
  • the other part of the doped region is the part where the sixth active pattern 6010 of the second sixth transistor T6 is located in the twelfth doped region 6012.
  • the third auxiliary pattern 600 is electrically connected to the portion of the sixth active pattern 601 in the at least one sixth transistor T6 in the eleventh doped region 6011 through the eighth via 604 penetrating the insulating layer 38, which actually refers to the third auxiliary
  • the pattern 600 is electrically connected to a portion of the sixth active pattern 601 of the sixth equivalent transistor located in a doped region thereof through the eighth via 604 penetrating the insulating layer 38.
  • the pixel driving circuit 30 further includes a seventh transistor T7 and a fourth auxiliary pattern 700 provided in the same layer as the third auxiliary pattern 600.
  • the seventh transistor T7 includes a seventh active pattern 701 and a seventh gate 702.
  • the seventh active pattern 701 has a seventh channel region 7010 and a thirteenth doped region 7011 and a fourteenth doped region 7012 located on opposite sides of the seventh channel region 7010.
  • the portion of the seventh active pattern 701 located in the fourteenth doped region 7012 and the portion of the fourth active pattern 401 located in the eighth doped region 4012 are integrated.
  • the orthographic projection of the seventh gate 702 on the substrate 340 overlaps the orthographic projection of the seventh channel region 7010 on the substrate 340.
  • the reset of the pixel driving circuit 30 in the next row adjacent to the pixel driving circuit 30 The portion of the signal line Vreset(n+1) located in the region where the seventh transistor T7 is located serves as the gate 702 of the seventh transistor T7.
  • the fourth auxiliary pattern 700 is electrically connected to the portion of the seventh active pattern 701 in the thirteenth doped region 7011 through the ninth via 703 penetrating the insulating layer 38, and through the tenth via 704 penetrating the third insulating sub-layer 383
  • An initialization signal line Vinit connected to the pixel driving circuit 30 of the next row adjacent to the pixel driving circuit 30 is electrically connected.
  • the fourth active pattern 401 and the seventh active pattern 401 can be fabricated simultaneously.
  • the active pattern 701 can simplify the manufacturing process of the display substrate 34.
  • the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors.
  • the light-emitting device L includes an anode 341, a light-emitting functional layer 342 and a cathode 343 that are sequentially stacked along the thickness direction of the substrate 340.
  • the display panel 3 is a top-emission display panel.
  • the anode 341 in the light emitting device L is an opaque electrode
  • the cathode 343 is a transparent electrode or a semi-transparent electrode.
  • the display panel 3 is a bottom emission display panel.
  • the anode 341 in the light emitting device L is a transparent electrode or a semi-transparent electrode
  • the cathode 343 is an opaque electrode.
  • the display panel 3 may also be a double-sided light-emitting display panel.
  • the anode 341 and the cathode 343 in the light-emitting device L are both transparent electrodes or semi-transparent electrodes.
  • the light-emitting functional layer 342 includes a light-emitting layer.
  • the light-emitting functional layer 342 also includes an electron transport layer (election transporting layer, ETL), an electron injection layer (election injection layer, EIL), and a hole transporting layer (hole transporting layer). , HTL for short) and one or more layers of hole injection layer (HIL for short).
  • ETL electron transport layer
  • EIL electron injection layer
  • hole transporting layer hole transporting layer
  • HTL electron transporting layer
  • HIL hole transporting layer
  • the display substrate 34 further includes a flat layer 345 disposed between the pixel driving circuit 30 and the light emitting device L, and the flat layer 345 has a plurality of eleventh via holes 3450.
  • the light emitting device L is electrically connected to the fourth transistor T4 of the pixel driving circuit 30 through the first auxiliary pattern 400.
  • the anode 341 of the light emitting device L is electrically connected to the first auxiliary pattern 400 through at least one eleventh via 3450, that is, the anode 341 of the light emitting device L passes through at least one eleventh via 3450 in the flat layer 345 and the first The auxiliary pattern 400 is electrically connected.
  • the size of all the eleventh via holes 3450 in the pixel driving circuit 30 of the column gradually increases along the first direction.
  • Each sub-pixel area in FIG. 21 and FIG. 22 only illustrates the structure of the eleventh via 3450.
  • the sizes of all the eleventh via holes 3450 are sequentially increased along the first direction. That is, in the column of pixel driving circuits 30, the sizes of all the eleventh via holes 3450 are different.
  • the column of pixel driving circuits 30 is divided into a plurality of pixel driving circuit groups 300, each pixel driving circuit group 300 includes a plurality of pixel driving circuits 30, different pixel driving circuit groups 300
  • the number of pixel driving circuits 30 included may be the same or different.
  • the size of the eleventh via 3450 in the pixel drive circuit group 300 is the same, and the size of the eleventh via 3450 in different pixel drive circuit groups 300 is different. That is, along the first direction, the size of the eleventh via 3450 in the current pixel driving circuit group 300 increases relative to the size of the eleventh via 3450 in the previous pixel driving circuit group 300.
  • the size of the eleventh via 3450 for electrically connecting the anode 341 of the light emitting device L and the first auxiliary pattern 400 is along the first Gradually increase in one direction. Since the voltage drop of the first voltage line Vdd causes the driving current output by the driving transistor Td to gradually decrease in the first direction, the gradual increase in the size of the eleventh via 3450 in the first direction can reduce the first auxiliary pattern 400 and The contact resistance of the anode 341 of the light emitting device L, so that the magnitude of the driving current transmitted to the light emitting device L tends to be balanced. In this way, the problem of uneven long-range display brightness can be further improved.
  • the display substrate 34 further includes a pixel defining layer 344 disposed on the side of the anode 341 away from the substrate 340.
  • the pixel defining layer 344 has a plurality of openings 3440, and each light emitting device L is disposed in a corresponding opening 3440. It should be noted that since only one light emitting device L is shown in FIG. 3, the opening 3440 of the pixel defining layer 344 in FIG. 3 also shows only one.
  • the size of the opening 3440 refers to the size of the orthographic projection of the opening on the substrate 340.
  • the multiple light emitting devices L include multiple red light emitting devices, multiple green light emitting devices and multiple blue light emitting devices, and the sizes of the openings 3440 corresponding to the light emitting devices L of different colors are different. Since the luminous efficiency of the blue light-emitting device, the red light-emitting device and the green light-emitting device increases in sequence, for the same pixel area (including the red sub-pixel area, the green sub-pixel area and the blue sub-pixel area), blue light emission The size of the opening 3440 corresponding to the device, the red light-emitting device, and the green light-emitting device is sequentially reduced.
  • the sizes of all the openings 3440 corresponding to a column of pixel driving circuits 30 connected to the data line Vdata gradually increase along the first direction.
  • Each sub-pixel area in FIG. 23 and FIG. 24 only illustrates the structure of the opening 3440.
  • the sizes of all openings 3440 are sequentially increased along the first direction. That is, in the column of pixel driving circuits 30, the sizes of all the openings 3440 are different.
  • the column of pixel driving circuits 30 is divided into a plurality of pixel driving circuit groups 300, each pixel driving circuit group 300 includes a plurality of pixel driving circuits 30, different pixel driving circuit groups 300
  • the number of pixel driving circuits 30 included may be the same or different.
  • the sizes of the openings 3440 in the pixel driving circuit group 300 are the same, and the sizes of the openings 3440 in different pixel driving circuit groups 300 are different. That is, along the first direction, the size of the opening 3440 in the current pixel driving circuit group 300 increases relative to the size of the opening 3440 in the previous pixel driving circuit group 300.
  • the size of the opening 3440 is not the same, the size of the light emitting device L provided in the opening 3440 is not the same. The larger the size of the light emitting device L, the greater the brightness of the light emitted from the area of the opening 3440.
  • the size of the opening 3440 is designed according to the luminous efficiency of different color light-emitting devices L and the voltage drop phenomenon of the signal line, so as to solve the difference in efficiency of different colors and the color difference or color unevenness caused by uneven long-range display brightness (Discolor) problem.
  • some embodiments of the present disclosure also provide another display substrate.
  • the driving transistor Td is an N-type transistor, and along the first direction, the first via 1030 and the second via
  • the changing trend of the size of the hole 2030, the fourth via 4030, the eleventh via 3450, and the opening 3440 is opposite to the changing trend when the driving transistor Td is a P-type transistor, and will not be repeated here.

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Abstract

一种显示基板、显示面板及显示装置。显示基板包括：多根数据线，设置在衬底上；多列像素驱动电路，设置在衬底上且位于显示区；一列像素驱动电路与对应的一根数据线连接，该列像素驱动电路中的每个像素驱动电路包括驱动晶体管和第一晶体管，驱动晶体管为P型晶体管；第一晶体管包括：第一有源图案，具有第一沟道区以及第一沟道区的相对两侧的第一掺杂区和第二掺杂区；第一栅极，在衬底上的正投影与第一沟道区在衬底上的正投影重叠；第一绝缘块，设置在第一有源图案远离衬底的一侧且具有第一过孔；数据线通过第一过孔与第一有源图案位于第一掺杂区的部分电连接；其中，该列像素驱动电路中的所有第一过孔的尺寸沿第一方向逐渐递减。

Description

一种显示基板、显示面板及显示装置
本申请要求于2019年6月12日提交的、申请号为201910503899.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
随着显示技术的快速发展，诸如有机电致发光(Organic Light-Emitting Diode，简称OLED)显示装置和量子点电致发光(Quantum Dot Light-Emitting Diode，简称QLED)显示装置等自发光型显示装置受到了广泛的关注。
公开内容
一方面，提供一种显示基板，包括：衬底，具有显示区；多根数据线，设置在所述衬底上且位于所述显示区；多列像素驱动电路，设置在所述衬底上且位于所述显示区；所述多列像素驱动电路中的一列像素驱动电路与所述多根数据线中对应的一根数据线连接，该列像素驱动电路中的每个像素驱动电路包括驱动晶体管和与该驱动晶体管电连接的第一晶体管，所述驱动晶体管为P型晶体管；所述第一晶体管包括：第一有源图案，具有第一沟道区以及位于所述第一沟道区的相对两侧的第一掺杂区和第二掺杂区；第一栅极，所述第一栅极在所述衬底上的正投影与所述第一沟道区在所述衬底上的正投影重叠；第一绝缘块，设置在所述第一有源图案远离所述衬底的一侧，所述第一绝缘块为绝缘层位于所述第一晶体管所在区域的部分，且所述第一绝缘块具有第一过孔；所述数据线通过所述第一过孔与所述第一有源图案位于所述第一掺杂区的部分电连接；其中，该列像素驱动电路中的所有第一过孔的尺寸沿第一方向逐渐递减；所述第一方向为所述数据线的信号输入端指向该信号输入端相对的远端的方向。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第一过孔的尺寸相同，且不同像素驱动电路组中的所述第一过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：多根第一电压线，设置在所述衬底上且位于所述显示区；所述多根第一电压线均沿所述第一方向延伸；所述多根第一电压线与所述多根数据线同层设置；所述像素驱动电路还包括第 二晶体管，所述第二晶体管包括：第二有源图案，具有第二沟道区以及位于所述第二沟道区的相对两侧的第三掺杂区和第四掺杂区；所述第二有源图案位于所述第四掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；第二栅极，所述第二栅极在所述衬底上的正投影与所述第二沟道区在所述衬底上的正投影重叠；第二绝缘块，所述第二绝缘块为所述绝缘层位于所述第二晶体管所在区域的部分，且所述第二绝缘块具有第二过孔；与该列像素驱动电路连接的一根第一电压线通过所述第二过孔与所述第二有源图案位于所述第三掺杂区的部分电连接；其中，该列像素驱动电路中的所有第二过孔的尺寸沿所述第一方向逐渐递增。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第二过孔的尺寸相同，且不同像素驱动电路组中的所述第二过孔的尺寸不相同。
在一些实施例中，所述像素驱动电路还包括存储电容器；所述存储电容器包括：第一存储电极；第二存储电极，设置在所述第一存储电极与所述多根数据线和所述多根第一电压线所在的层之间；所述驱动晶体管包括：第三有源图案，具有第三沟道区以及位于所述第三沟道区的相对两侧的第五掺杂区和第六掺杂区；所述第三有源图案位于所述第五掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；第三栅极，与所述第一存储电极复用，所述第三栅极在所述衬底上的正投影与所述第三沟道区在所述衬底上的正投影重叠；其中，所述绝缘层包括依次层叠设置的第一绝缘子层、第二绝缘子层和第三绝缘子层，所述第一绝缘子层位于所述第三有源图案与所述第一存储电极之间，所述第二绝缘子层位于所述第一存储电极与第二存储电极之间，所述第三绝缘子层位于所述第二存储电极与多根数据线和所述多根第一电压线所在的层之间；所述第一电压线通过贯穿所述第三绝缘子层的第三过孔与所述第二存储电极电连接。
在一些实施例中，所述像素驱动电路还包括：第四晶体管，所述第四晶体管包括：第四有源图案，具有第四沟道区以及位于所述第四沟道区的相对两侧的第七掺杂区和第八掺杂区；所述第四有源图案位于所述第七掺杂区的部分与所述第三有源图案位于所述第六掺杂区的部分连为一体；第四栅极，所述第四栅极在所述衬底上的正投影与所述第四沟道区在所述衬底上的正投影重叠；第四绝缘块，所述第四绝缘块为所述绝缘层位于所述第四晶体管所 在区域的部分，且所述第四绝缘块具有第四过孔；第一辅助图案，与所述多根数据线和所述多根第一电压线同层设置；所述第一辅助图案通过所述第四过孔与所述第四有源图案位于所述第八掺杂区的部分电连接；其中，该列像素驱动电路中的所有第四过孔的尺寸，沿所述第一方向逐渐递增。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第四过孔的尺寸相同，且不同像素驱动电路组中的所述第四过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：多根使能信号线，设置在所述衬底上且位于所述显示区；所述多根使能信号线均沿第二方向延伸，所述第二方向与所述第一方向交叉；所述多根使能信号线与所述第一存储电极同层设置；每根使能信号线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根使能信号线的位于所述第四晶体管所在区域中的部分和位于所述第二晶体管所在区域中的部分，分别用作所述第四栅极和所述第二栅极。
在一些实施例中，所述像素驱动电路还包括：至少一个第五晶体管，每个第五晶体管包括：第五有源图案，具有第五沟道区以及位于所述第五沟道区的相对两侧的第九掺杂区和第十掺杂区；第五栅极，所述第五栅极在所述衬底上的正投影与所述第五沟道区在所述衬底上的正投影重叠；其中，所述至少一个第五晶体管中的所述第五有源图案位于所述第九掺杂区的部分与所述驱动晶体管中的所述第三有源图案位于所述第六掺杂区的部分连为一体；第二辅助图案，与所述第一辅助图案同层设置；所述第二辅助图案通过贯穿所述第三绝缘子层和所述第二绝缘子层的第五过孔与所述第一存储电极电连接，并通过贯穿所述绝缘层的第六过孔与所述第五有源图案位于所述第十掺杂区的部分电连接。
在一些实施例中，所述显示基板还包括：多根栅线，设置在所述衬底上且位于所述显示区；所述多根栅线均沿所述第二方向延伸，且所述多根栅线与所述多根使能信号线同层设置；每根栅线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根栅线的位于所述第一晶体管所在区域中的部分和位于所述第五晶体管所在区域中的部分，分别用作所述第一栅极和所述第五栅极。
在一些实施例中，所述显示基板还包括：多根初始化信号线，设置在所 述衬底上且位于所述显示区；所述多根初始化信号线均沿所述第二方向延伸，且所述多根初始化信号线与所述第二存储电极同层设置；每根初始化信号线与多行像素驱动电路中的一行像素驱动电路连接；所述像素驱动电路还包括：至少一个第六晶体管，每个第六晶体管包括：第六有源图案，具有第六沟道区以及位于所述第六沟道区的相对两侧的第十一掺杂区和第十二掺杂区；第六栅极，所述第六栅极在所述衬底上的正投影与所述第六沟道区在所述衬底上的正投影重叠；其中，所述至少一个第六晶体管中的所述第六有源图案位于所述第十二掺杂区的部分与所述至少一个第五晶体管中的所述第五有源图案位于所述第十掺杂区的部分连为一体；第三辅助图案，与所述第一辅助图案同层设置；所述第三辅助图案通过贯穿所述第三绝缘子层的第七过孔与所述像素驱动电路对应的一根初始化信号线电连接，并通过贯穿所述绝缘层的第八过孔与所述至少一个第六晶体管中的所述第六有源图案位于所述第十一掺杂区的部分电连接。
在一些实施例中，所述像素驱动电路还包括：第七晶体管；所述第七晶体管包括：第七有源图案，具有第七沟道区以及位于所述第七沟道区的相对两侧的第十三掺杂区和第十四掺杂区；所述第七有源图案位于所述第十四掺杂区的部分与所述第四有源图案位于所述第八掺杂区的部分连为一体；第七栅极，所述第七栅极在所述衬底上的正投影与所述第七沟道区在所述衬底上的正投影重叠；第四辅助图案，与所述第三辅助图案同层设置；所述第四辅助图案通过贯穿所述绝缘层的第九过孔与所述第七有源图案位于所述第十三掺杂区的部分电连接，并通过贯穿所述第三子绝缘层的第十过孔和与该像素驱动电路相邻的下一行像素驱动电路对应的一根初始化信号线电连接。
在一些实施例中，所述显示基板还包括：多根复位信号线，设置在所述衬底上且位于所述显示区；所述多根复位信号线均沿所述第二方向延伸，且所述多根复位信号线与所述多根栅线同层设置；与所述像素驱动电路连接的一根复位信号线的位于所述第六晶体管所在区域中的部分用作第六栅极，与所述像素驱动电路相邻的下一行像素驱动电路连接的复位信号线位于所述第七晶体管所在区域中的部分用作第七晶体管的栅极。
在一些实施例中，所述显示基板还包括：多个发光器件，设置在所述衬底上；每个像素驱动电路与所述多个发光器件中的一个发光器件电连接，所述像素驱动电路被配置为驱动所述发光器件发光。
在一些实施例中，所述显示基板还包括：平坦层，设置在所述像素驱动电路与所述发光器件之间；所述平坦层具有多个第十一过孔；其中，所述像素驱动电路包括第四晶体管和第一辅助图案；所述发光器件包括沿所述衬底的厚度方向依次层叠的阳极、发光功能层和阴极，所述发光器件的阳极通过至少一个第十一过孔与所述第一辅助图案电连接；其中，该列像素驱动电路中的所有第十一过孔的尺寸沿所述第一方向逐渐递增。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第十一过孔的尺寸相同，且不同像素驱动电路组中的所述第十一过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：像素界定层，设置在所述阳极远离所述衬底一侧；所述像素界定层具有多个开口，每个发光器件设置在对应的一个开口中；其中，该列像素驱动电路对应的所有开口的尺寸沿所述第一方向逐渐递增。
在一些实施例中，所述多个发光器件包括多个红色发光器件，多个绿色发光器件和多个蓝色发光器件；针对于同一颜色的发光器件，不同颜色的发光器件对应的开口的尺寸不同。
另一方面，提供一种显示面板，包括上述的显示基板以及封装层。
再一方面，提供一种显示装置，包括上述的显示面板以及设置在所述显示面板一侧的数据驱动芯片，所述数据驱动芯片所在的一侧为所述显示面板中的数据线的信号输入端。
又一方面，提供一种显示基板，包括：衬底，具有显示区；多根数据线，设置在所述衬底上且位于所述显示区；多列像素驱动电路，设置在所述衬底上且位于所述显示区；所述多列像素驱动电路中的一列像素驱动电路与所述多根数据线中对应的一根数据线连接，该列像素驱动电路中的每个像素驱动电路包括驱动晶体管和与该驱动晶体管电连接的第一晶体管，所述驱动晶体管为N型晶体管；所述第一晶体管包括：第一有源图案，具有第一沟道区以及位于所述第一沟道区的相对两侧的第一掺杂区和第二掺杂区；第一栅极，所述第一栅极在所述衬底上的正投影与所述第一沟道区在所述衬底上的正投影重叠；第一绝缘块，设置在所述第一有源图案远离所述衬底的一侧，所述第一绝缘块为绝缘层位于所述第一晶体管所在区域的部分，且所述第一绝缘块具有第一过孔；所述数据线通过所述第一过孔与所述第一有源图案位于所 述第一掺杂区的部分电连接；其中，该列像素驱动电路中的所有第一过孔的尺寸沿第一方向逐渐递增；所述第一方向为所述数据线的信号输入端指向该信号输入端相对的远端的方向。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第一过孔的尺寸相同，且不同像素驱动电路组中的所述第一过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：多根第一电压线，设置在所述衬底上且位于所述显示区；所述多根第一电压线均沿所述第一方向延伸；所述多根第一电压线与所述多根数据线同层设置；所述像素驱动电路还包括第二晶体管，所述第二晶体管包括：第二有源图案，具有第二沟道区以及位于所述第二沟道区的相对两侧的第三掺杂区和第四掺杂区；所述第二有源图案位于所述第四掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；第二栅极，所述第二栅极在所述衬底上的正投影与所述第二沟道区在所述衬底上的正投影重叠；第二绝缘块，所述第二绝缘块为所述绝缘层位于所述第二晶体管所在区域的部分，且所述第二绝缘块具有第二过孔；与该列像素驱动电路连接的一根第一电压线通过所述第二过孔与所述第二有源图案位于所述第三掺杂区的部分电连接；其中，该列像素驱动电路中的所有第二过孔的尺寸沿所述第一方向逐渐递减。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第二过孔的尺寸相同，且不同像素驱动电路组中的所述第二过孔的尺寸不相同。
在一些实施例中，所述像素驱动电路还包括存储电容器；所述存储电容器包括：第一存储电极；第二存储电极，设置在所述第一存储电极与所述多根数据线和所述多根第一电压线所在的层之间；所述驱动晶体管包括：第三有源图案，具有第三沟道区以及位于所述第三沟道区的相对两侧的第五掺杂区和第六掺杂区；所述第三有源图案位于所述第五掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；第三栅极，与所述第一存储电极复用，所述第三栅极在所述衬底上的正投影与所述第三沟道区在所述衬底上的正投影重叠；其中，所述绝缘层包括依次层叠设置的第一绝缘子层、第二绝缘子层和第三绝缘子层，所述第一绝缘子层位于所述第三有源图案与所述第一存储电极之间，所述第二绝缘子层位于所述第一存储电极与第二存 储电极之间，所述第三绝缘子层位于所述第二存储电极与多根数据线和所述多根第一电压线所在的层之间；所述第一电压线通过贯穿所述第三绝缘子层的第三过孔与所述第二存储电极电连接。
在一些实施例中，所述像素驱动电路还包括：第四晶体管，所述第四晶体管包括：第四有源图案，具有第四沟道区以及位于所述第四沟道区的相对两侧的第七掺杂区和第八掺杂区；所述第四有源图案位于所述第七掺杂区的部分与所述第三有源图案位于所述第六掺杂区的部分连为一体；第四栅极，所述第四栅极在所述衬底上的正投影与所述第四沟道区在所述衬底上的正投影重叠；第四绝缘块，所述第四绝缘块为所述绝缘层位于所述第四晶体管所在区域的部分，且所述第四绝缘块具有第四过孔；第一辅助图案，与所述多根数据线和所述多根第一电压线同层设置；所述第一辅助图案通过所述第四过孔与所述第四有源图案位于所述第八掺杂区的部分电连接；其中，该列像素驱动电路中的所有第四过孔的尺寸，沿所述第一方向逐渐递减。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第四过孔的尺寸相同，且不同像素驱动电路组中的所述第四过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：多根使能信号线，设置在所述衬底上且位于所述显示区；所述多根使能信号线均沿第二方向延伸，所述第二方向与所述第一方向交叉；所述多根使能信号线与所述第一存储电极同层设置；每根使能信号线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根使能信号线的位于所述第四晶体管所在区域中的部分和位于所述第二晶体管所在区域中的部分，分别用作所述第四栅极和所述第二栅极。
在一些实施例中，所述像素驱动电路还包括：至少一个第五晶体管，每个第五晶体管包括：第五有源图案，具有第五沟道区以及位于所述第五沟道区的相对两侧的第九掺杂区和第十掺杂区；第五栅极，所述第五栅极在所述衬底上的正投影与所述第五沟道区在所述衬底上的正投影重叠；其中，所述至少一个第五晶体管中的所述第五有源图案位于所述第九掺杂区的部分与所述驱动晶体管中的所述第三有源图案位于所述第六掺杂区的部分连为一体；第二辅助图案，与所述第一辅助图案同层设置；所述第二辅助图案通过贯穿所述第三绝缘子层和所述第二绝缘子层的第五过孔与所述第一存储电极电连 接，并通过贯穿所述绝缘层的第六过孔与所述第五有源图案位于所述第十掺杂区的部分电连接。
在一些实施例中，所述显示基板还包括：多根栅线，设置在所述衬底上且位于所述显示区；所述多根栅线均沿所述第二方向延伸，且所述多根栅线与所述多根使能信号线同层设置；每根栅线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根栅线的位于所述第一晶体管所在区域中的部分和位于所述第五晶体管所在区域中的部分，分别用作所述第一栅极和所述第五栅极。
在一些实施例中，所述显示基板还包括：多根初始化信号线，设置在所述衬底上且位于所述显示区；所述多根初始化信号线均沿所述第二方向延伸，且所述多根初始化信号线与所述第二存储电极同层设置；每根初始化信号线与多行像素驱动电路中的一行像素驱动电路连接；所述像素驱动电路还包括：至少一个第六晶体管，每个第六晶体管包括：第六有源图案，具有第六沟道区以及位于所述第六沟道区的相对两侧的第十一掺杂区和第十二掺杂区；第六栅极，所述第六栅极在所述衬底上的正投影与所述第六沟道区在所述衬底上的正投影重叠；其中，所述至少一个第六晶体管中的所述第六有源图案位于所述第十二掺杂区的部分与所述至少一个第五晶体管中的所述第五有源图案位于所述第十掺杂区的部分连为一体；第三辅助图案，与所述第一辅助图案同层设置；所述第三辅助图案通过贯穿所述第三绝缘子层的第七过孔与所述像素驱动电路对应的一根初始化信号线电连接，并通过贯穿所述绝缘层的第八过孔与所述至少一个第六晶体管中的所述第六有源图案位于所述第十一掺杂区的部分电连接。
在一些实施例中，所述像素驱动电路还包括：第七晶体管；所述第七晶体管包括：第七有源图案，具有第七沟道区以及位于所述第七沟道区的相对两侧的第十三掺杂区和第十四掺杂区；所述第七有源图案位于所述第十四掺杂区的部分与所述第四有源图案位于所述第八掺杂区的部分连为一体；第七栅极，所述第七栅极在所述衬底上的正投影与所述第七沟道区在所述衬底上的正投影重叠；第四辅助图案，与所述第三辅助图案同层设置；所述第四辅助图案通过贯穿所述绝缘层的第九过孔与所述第七有源图案位于所述第十三掺杂区的部分电连接，并通过贯穿所述第三子绝缘层的第十过孔和与该像素驱动电路相邻的下一行像素驱动电路对应的一根初始化信号线电连接。
在一些实施例中，所述显示基板还包括：多根复位信号线，设置在所述衬底上且位于所述显示区；所述多根复位信号线均沿所述第二方向延伸，且所述多根复位信号线与所述多根栅线同层设置；与所述像素驱动电路连接的一根复位信号线的位于所述第六晶体管所在区域中的部分用作第六栅极，与所述像素驱动电路相邻的下一行像素驱动电路连接的复位信号线位于所述第七晶体管所在区域中的部分用作第七晶体管的栅极。
在一些实施例中，所述显示基板还包括：多个发光器件，设置在所述衬底上；每个像素驱动电路与所述多个发光器件中的一个发光器件电连接，所述像素驱动电路被配置为驱动所述发光器件发光。
在一些实施例中，所述显示基板还包括：平坦层，设置在所述像素驱动电路与所述发光器件之间；所述平坦层具有多个第十一过孔；其中，所述像素驱动电路包括第四晶体管和第一辅助图案；所述发光器件包括沿所述衬底的厚度方向依次层叠的阳极、发光功能层和阴极，所述发光器件的阳极通过至少一个第十一过孔与所述第一辅助图案电连接；其中，该列像素驱动电路中的所有第十一过孔的尺寸沿所述第一方向逐渐递减。
在一些实施例中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第十一过孔的尺寸相同，且不同像素驱动电路组中的所述第十一过孔的尺寸不相同。
在一些实施例中，所述显示基板还包括：像素界定层，设置在所述阳极远离所述衬底一侧；所述像素界定层具有多个开口，每个发光器件设置在对应的一个开口中；其中，该列像素驱动电路对应的所有开口的尺寸沿所述第一方向逐渐递减。
在一些实施例中，所述多个发光器件包括多个红色发光器件，多个绿色发光器件和多个蓝色发光器件；针对于同一颜色的发光器件，不同颜色的发光器件对应的开口的尺寸不同。
另一方面，提供一种显示面板，包括上述的显示基板以及封装层。
再一方面，提供一种显示装置，包括上述的显示面板以及设置在所述显示面板一侧的数据驱动芯片，所述数据驱动芯片所在的一侧为所述显示面板中的数据线的信号输入端。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将 对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一些实施例提供的一种显示装置的结构示意图；
图2为本公开的一些实施例提供的一种显示面板的区域划分示意图；
图3为本公开的一些实施例提供的一种电致发光显示面板的结构示意图；
图4为本公开的一些实施例提供的一种电致发光显示面板的平面图；
图5为本公开的一些实施例提供的一种像素驱动电路的结构示意图；
图6为本公开的一些实施例提供的另一种像素驱动电路的结构示意图；
图7为本公开的一些实施例提供的第一晶体管的结构示意图；
图8为本公开的一些实施例提供的一种第一过孔的尺寸分布示意图；
图9为本公开的一些实施例提供的另一种第一过孔的尺寸分布示意图；
图10为相关技术中的一种显示面板的长程显示亮度不均的示意图；
图11为本公开的一些实施例提供的一种与图6中的像素驱动电路对应的电路排版图；
图12为本公开的一些实施例提供的一种第一晶体管和第二晶体管的结构示意图；
图13为本公开的一些实施例提供的一种第二过孔的尺寸分布示意图；
图14为本公开的一些实施例提供的另一种第二过孔的尺寸分布示意图；
图15为本公开的一些实施例提供的一种第二晶体管和驱动晶体管的结构示意图；
图16为本公开的一些实施例提供的一种第四晶体管和第七晶体管的结构示意图；
图17为本公开的一些实施例提供的一种第四过孔的尺寸分布示意图；
图18为本公开的一些实施例提供的另一种第四过孔的尺寸分布示意图；
图19为本公开的一些实施例提供的一种驱动晶体管、第五晶体管和第六晶体管的结构示意图；
图20为本公开的一些实施例提供的一种第四晶体管和发光器件的阳极的结构示意图；
图21为本公开的一些实施例提供的一种第十一过孔的尺寸分布示意图；
图22为本公开的一些实施例提供的另一种第十一过孔的尺寸分布示意图；
图23为本公开的一些实施例提供的一种开口的尺寸分布示意图；
图24为本公开的一些实施例提供的另一种开口的尺寸分布示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开说明书以及权利要求书中使用的术语“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。然而，术语“连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本公开的一些实施例提供一种显示装置，该显示装置可以用作手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等，本公开的实施例对显示装置的用途不做特殊限制。
该显示装置可以为有机电致发光显示装置或者量子点电致发光显示装置。如图1所示，显示装置包括框架1、盖板2、显示面板3、电路板4、柔性线路板5、以及摄像头等其它电子配件。示例的，框架1为U型框架，显示面板3、电路板4和柔性线路板5设置于框架1和盖板2围成的腔体内。柔性线路板5设置在显示面板3的边缘，电路板4与柔性线路板5连接，且设置于显示面板3背离盖板2的一侧。
在一些示例中，柔性线路板5包括柔性线路板本体和设置在柔性线路板本体上的至少一个驱动芯片，驱动芯片可以为驱动IC(Integrate Circuit，集成电路)。示例的，至少一个驱动IC包括至少一个数据驱动IC。
在一些示例中，电路板4被配置为向显示面板3提供显示所需的信号。示例的，电路板4为印刷电路板组件(Printed Circuit Board Assembly，PCBA)，PCBA包括印刷电路板(Printed Circuit Board，PCB)和设置于PCB上的时序控制器(Timing Controller，TCON)、电源管理集成电路(Power Management IC，PMIC)以及其它IC或电路等。
如图2所示，显示面板3具有显示区31和用于布线的周边区32。在一些示例中，周边区32围绕显示区31一圈设置。在另一些示例中，周边区32仅位于显示区31的部分边缘一侧，例如位于显示区31的相对两侧。图2以周边区32围绕显示区31一圈设置为例进行示意。显示区31包括多个亚像素区33，多个亚像素区33至少包括多个红色亚像素区、多个绿色亚像素区和多个蓝色亚像素区。
在显示装置为电致发光显示装置(有机电致发光显示装置或者量子点电致发光显示装置)的情况下，显示面板3为电致发光显示面板。如图3所示，该电致发光显示面板包括显示基板34和用于封装显示基板34的封装层35。该封装层35可以为封装薄膜，也可以为封装基板。
本公开的一些实施例提供一种显示基板3。如图4所示，该显示基板34包括衬底340，设置于衬底340上且位于显示区31的多个像素驱动电路30和多个发光器件L。每个像素驱动电路30对应的设置于一个亚像素区33中，每个发光器件L对应的设置于一个亚像素区33中且与位于该亚像素区33中的像素驱动电路30电连接。该像素驱动电路30被配置为驱动对应的发光器件L发光。
在一些示例中，像素驱动电路30的电路结构为2T1C，其等效电路如图5所示，该像素驱动电路30包括第一晶体管T1、驱动晶体管Td和 存储电容器Cst。第一晶体管T1的栅极与栅线Vgate电连接，第一晶体管T1的第一极与数据线Vdata电连接，第一晶体管T1的第二极与驱动晶体管Td的栅极电连接，驱动晶体管Td的第一极与第一电压线Vdd电连接，驱动晶体管Td的第二极与发光器件L的阳极电连接，发光器件L的阴极与第二电压线Vss电连接。存储电容器Cst的第一存储电极与驱动晶体管Td的栅极电连接，存储电容器Cst的第二存储电极与驱动晶体管Td的第二极电连接。需要说明的是，针对每个晶体管，第一极和第二极中的一者为源极，另一者为漏极。
在另一些示例中，像素驱动电路30的电路结构为7T1C，其等效电路如图6所示，该像素驱动电路30包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、驱动晶体管Td和存储电容器Cst。第一晶体管T1的栅极与栅线Vgate电连接，第一晶体管T1的第一极与数据线Vdata电连接，第一晶体管T1的第二极与驱动晶体管Td的第一极电连接。驱动晶体管Td的第二极与第四晶体管T4的第一极和第五晶体管T5的第一极电连接，驱动晶体管Td的栅极与第五晶体管T5的第二极电连接。第五晶体管T5的栅极与栅线Vgate电连接。第四晶体管T4的栅极与使能信号线EM电连接，第四晶体管T4的第二极与发光器件L的阳极电连接，发光器件L的阴极与第二电压线Vss电连接。第二晶体管T2的栅极与使能信号线EM电连接，第二晶体管T2的第一极与第一电压线Vdd电连接，第二晶体管T2的第二极与驱动晶体管Td的第一极电连接。第六晶体管T6的栅极与复位信号线Vreset电连接，第六晶体管T6的第一极与初始化信号线Vinit电连接，第六晶体管T6的第二极与驱动晶体管Td的栅极电连接。第七晶体管T7的栅极与下一行像素驱动电路30中的第六晶体管T6连接的复位信号线Vreset电连接，第七晶体管T7的第一极与初始化信号线Vinit电连接，第七晶体管T7的第二极与发光器件L的阳极电连接。存储电容器Cst的第一存储电极与第一电压线Vdd电连接，存储电容器Cst的第二存储电极与驱动晶体管Td的栅极电连接。
本领域技术人员应当明白，在像素驱动电路30中，驱动晶体管Td的沟道的宽长比大于其它起开关作用的晶体管的沟道的宽长比。
上述仅仅是对像素驱动电路30的举例说明，关于像素驱动电路30的等效电路结构不限于图5和图6所示的结构，其还可以是其它类型的像素驱动电路，这里不再一一列举。但应理解，不管像素驱动电路30是 哪种结构，其至少包括一个驱动晶体管Td、一个起开关作用的晶体管以及一个存储电容器Cst。在此基础上，显示基板3包括与该像素驱动电路30连接的栅线Vgate、数据线Vdata和第一电压线Vdd。
下面结合附图对本公开的一些实施例提供的显示基板34的层结构进行描述。驱动晶体管Td可以为P型晶体管或者N型晶体管，以下以驱动晶体管Td为P型晶体管为例进行说明。
如图4所示，该显示基板34包括衬底340，设置在衬底340上且位于显示区31的多根栅线Vgate、多根数据线Vdata、多根第一电压线Vdd、以及多列像素驱动电路30。多根数据线Vdata和多根第一电压线Vdd均沿第一方向延伸，多根栅线Vgate沿第二方向延伸。第一方向和第二方向相互交叉，例如相互垂直。第一方向为数据线Vdata的信号输入端指向该信号输入端相对的远端的方向。其中，多列像素驱动电路30沿第二方向排布，每列像素驱动电路30包括沿第一方向排布的多个像素驱动电路30，每个像素驱动电路30位于对应的一个亚像素区33中。
示例的，多根数据线Vdata和多根第一电压线Vdd同层设置，多根栅线Vgate设置在多根数据线Vdata和多根第一电压线Vdd所在的层与衬底340之间。这里，“同层”是指采用同一成膜工艺形成用于形成特定图形的膜层，再利用同一掩模板通过构图工艺形成的层结构。其中，构图工艺可能包括曝光、显影和刻蚀工艺，而形成的层结构中的特定图形可以是连续的，也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
沿第二方向排布的多列像素驱动电路30中的一列像素驱动电路30与多根数据线Vdata中对应的一根数据线Vdata连接。示例的，每列像素驱动电路30与对应的一根数据线Vdata连接。
沿第二方向排布的多列像素驱动电路30中的一列像素驱动电路30与多根第一电压线Vdd中对应的一根第一电压线Vdd连接。示例的，每列像素驱动电路30与对应的一根第一电压线Vdd连接。第一电压线Vdd被配置为向像素驱动电路30提供第一电源电压信号，第一电源电压信号例如为高电平信号。
多列像素驱动电路30中沿第二方向排布的多个像素驱动电路30构成一行像素驱动电路30。沿第一方向，多行像素驱动电路30中的一行像素驱动电路30与多根栅线Vgate中对应的一根栅线Vgate连接。示例的，每行像素驱动电路30与对应的一根栅线Vgate连接。
该列像素驱动电路30中的每个像素驱动电路30包括驱动晶体管Td和与该驱动晶体管Td电连接的第一晶体管T1，示例的，第一晶体管T1为P型晶体管。如图7、图11和图12所示，第一晶体管T1包括第一有源图案101、第一栅极102和第一绝缘块103。第一有源图案101具有第一沟道区1010以及位于第一沟道区1010的相对两侧的第一掺杂区1011和第二掺杂区1012。第一栅极102在衬底340上的正投影与第一沟道区1010在衬底340上的正投影重叠，示例的，与像素驱动电路30连接的栅线Vgate的位于第一晶体管T1所在区域中的部分用作第一栅极102。第一绝缘块103设置在第一有源图案101远离衬底340的一侧，第一绝缘块103具有第一过孔1030，且数据线Vdata通过该第一过孔1030与第一有源图案101位于第一掺杂区1011的部分电连接。第一绝缘块103为绝缘层38位于第一晶体管T1所在区域的部分，该绝缘层38可以由多个绝缘子层构成，其层数需根据显示基板34的结构而定。
需要说明的是，相对于第一沟道区1010，第一掺杂区1011和第二掺杂区1012进行了离子掺杂，从而使得第一有源图案101位于第一掺杂区1011和第二掺杂区1012的部分为导体。关于后续的掺杂区，与这里的掺杂区具有相同的意义。
如图8和图9所示，在该列像素驱动电路30中，所有第一过孔1030的尺寸沿第一方向逐渐递减。图8和图9中的每个亚像素区仅示意出了第一过孔1030的结构。需要说明的是，本公开的实施例提及到的“过孔的尺寸”是指过孔在衬底340上的正投影的尺寸。
在一些示例中，如图8所示，在该列像素驱动电路30中，所有第一过孔1030的尺寸沿第一方向依次递减。即，在该列像素驱动电路30中，所有第一过孔1030的尺寸均不相同。
在另一些示例中，如图9所示，该列像素驱动电路30分为多个像素驱动电路组300，每个像素驱动电路组300包括多个像素驱动电路30，不同像素驱动电路组300所包括的像素驱动电路30的数量可以相同，也可以不同。像素驱动电路组300中的第一过孔1030的尺寸相同。不同像素驱动电路组300中的第一过孔1030的尺寸不相同，即，沿第一方向，当前像素驱动电路组300中的第一过孔1030相对于上一个像素驱动电路组300中的第一过孔1030的尺寸减小。
显示装置可以通过柔性线路板5向显示面板中的数据线Vdata和第 一电压线Vdd输入信号。如图10所示，由于柔性线路板5设置在显示面板3的一侧，而数据线Vdata和第一电压线Vdd存在一定的阻抗，导致数据线Vdata和第一电压线Vdd上的信号沿第一方向均会产生压降(IR drop)。
对于包括P型驱动晶体管Td的像素驱动电路30而言，数据线Vdata提供的数据信号会写入驱动晶体管Td的栅极，且数据线Vdata提供的数据信号的电压值越小，发光器件L的亮度越高。第一电压线Vdd提供的第一电源电压信号会输入至驱动晶体管Td的源极，且第一电压线Vdd提供的第一电源电压信号的电压值越大，发光器件L的亮度越高。在不考虑第一电压线Vdd上压降的情况下，数据线Vdata上的压降，使得发光器件L沿第一方向的亮度逐渐升高。但由于第一电压线Vdd上的压降，又会使得发光器件L沿第一方向的亮度有所降低。尤其是在该显示面板显示高灰阶画面时，数据线Vdata上数据信号的电压值相对较小，使得数据信号的电压值的压降对画面的亮度的影响明显小于第一电压线Vdd上第一电源电压信号的压降对画面的亮度的影响，因此，如图10所示，沿第一方向，与该列像素驱动电路30连接的发光器件L的亮度出现了明显的降低。从而导致显示装置出现长程显示亮度不均的问题。
在本公开的一些实施例所提供的显示基板34中，与数据线Vdata连接的一列像素驱动电路30中，用于使数据线Vdata与第一晶体管T1电连接的第一过孔1030的尺寸沿第一方向逐渐减小，在不考虑数据线Vdata上压降的情况下，写入该列像素驱动电路30的数据信号的电压逐渐减小。在此基础上，由于数据线Vdata上压降的存在，使得数据线Vdata上的数据信号的电压值沿第一方向进一步的减小。这样，由于数据线Vdata提供的数据信号的电压值越小，发光器件L的亮度越高，因此，沿第一方向增大了与该列像素驱动电路30连接的发光器件L的显示亮度。从而可改善沿第一方向排布的发光器件L的亮度降低的问题，提高了显示亮度的均一性。
在一些实施例中，如图11所示，该显示基板34还包括设置在衬底340上且位于显示区31的多根使能信号线EM，使能信号线EM沿第二方向延伸。多根使能信号线EM与多根栅线Vgate同层设置。使能信号线EM被配置为在发光阶段输出开启信号。
需要说明的是，图11仅为示例了一个像素驱动结构30的层结构以及其连接的各信号线。
沿第一方向排布的多行像素驱动电路30中的一行像素驱动电路30与多根使能信号线EM中对应的一根使能信号线EM连接。示例的，每行像素驱动电路30与对应的一根使能信号线EM连接。
如图11、图12和图15所示，像素驱动电路30还包括第二晶体管T2。如图12和图15所示，第二晶体管T2包括第二有源图案201、第二栅极202和第二绝缘块203。第二有源图案201具有第二沟道区2010以及位于第二沟道区2010的相对两侧的第三掺杂区2011和第四掺杂区2012，第二有源图案201位于第四掺杂区2012的部分与第一有源图案101位于第二掺杂区1012的部分连为一体。第二栅极202在衬底340上的正投影与第二沟道区2010在衬底340上的正投影重叠，示例的，与该像素驱动电路30连接的使能信号线EM的位于第二晶体管T2所在区域中的部分用作第二栅极202。第二绝缘块203为绝缘层38位于第二晶体管T2所在区域的部分，第二绝缘块203具有第二过孔2030，且第一电压线Vdd通过该第二过孔2030与第二有源图案201位于第三掺杂区2011的部分电连接。
由于第二有源图案201位于第四掺杂区2012的部分与第一有源图案101位于第二掺杂区1012的部分连为一体，因此可以同时制作第一有源图案101与第二有源图案201，从而能够简化显示基板34的制作工艺。
如图13和图14所示，在该列像素驱动电路30中，所有第二过孔2030的尺寸沿第一方向逐渐递增。图13和图14中的每个亚像素区仅示意出了第二过孔2030的结构。
在一些示例中，如图13所示，在该列像素驱动电路30中，所有第二过孔2030的尺寸沿第一方向依次递增。即，在该列像素驱动电路30中，所有第二过孔2030的尺寸均不相同。
在另一些示例中，如图14所示，该列像素驱动电路30分为多个像素驱动电路组300，每个像素驱动电路组300包括多个像素驱动电路30，不同像素驱动电路组300所包括的像素驱动电路30的数量可以相同，也可以不同。在像素驱动电路组300中的所有第二过孔2030的尺寸相同，不同像素驱动电路组300中的第二过孔2030的尺寸不相同。即，沿第一方向，当前像素驱动电路组300中的第二过孔2030的尺寸相对于上一个像素驱动电路组300中的第二过孔2030的尺寸增大。
本公开的一些实施例所提供的显示基板34，在该列像素驱动电路30 中，用于使第一电压线Vdd与第二晶体管T2电连接的第二过孔2030的尺寸沿第一方向逐渐增大。这样，虽然第一电压线Vdd上的压降会造成第一电压线Vdd上的第一电源电压信号的电压值沿第一方向逐渐减小，但第二过孔2030的尺寸的逐渐增大又会使得第一电源电压信号在传输到该列像素驱动电路30中的电压值沿第一方向逐渐增大，从而可使传输到该列像素驱动电路30中的第一电源电压信号的电压值趋于平衡。这样，可进一步改善长程显示亮度不均的问题，进而改善了显示面板3的显示品质。
在一些实施例中，如图11所示，像素驱动电路30还包括存储电容器Cst。如图11和图15所示，存储电容器Cst包括第一存储电极C1和第二存储电极C2，第二存储电极C2位于第一存储电极C1与多根数据线Vdata和多根第一电压线Vdd所在的层之间。驱动晶体管Td包括第三有源图案301和第三栅极302。第三有源图案301具有第三沟道区3010以及位于第三沟道区3010的相对两侧的第五掺杂区3011和第六掺杂区3012，第三有源图案301位于第五掺杂区3011的部分与第一有源图案101位于第二掺杂区1012的部分和第二有源图案201位于第四掺杂区2012的部分连为一体。第三栅极302与第一存储电极C1复用，第三栅极302在衬底340上的正投影与第三沟道区3010在衬底340上的正投影重叠。
由于第三有源图案301位于第五掺杂区3011的部分与第一有源图案101位于第二掺杂区1012的部分和第二有源图案201位于第四掺杂区2012的部分连为一体，因此可以同时制作第一有源图案101、第二有源图案201和第三有源图案301，从而进一步简化显示基板34的制作工艺。
如图15所示，绝缘层38包括依次层叠设置的第一绝缘子层381、第二绝缘子层382和第三绝缘子层383，第一绝缘子层381位于第三有源图案301与第一存储电极C1之间，第二绝缘子层382位于第一存储电极C1与第二存储电极C2之间，第三绝缘子层383位于第二存储电极C2与多根数据线Vdata和多根第一电压线Vdd所在的层之间。第一电压线Vdd通过贯穿第三绝缘子层383的第三过孔303与第二存储电极C2电连接。
在一些实施例中，如图11所示，像素驱动电路30还包括第四晶体管T4以及与多根数据线Vdata和多根第一电压线Vdd同层设置的第一辅助图案400。如图11和图16所示，第四晶体管T4包括第四有源图案401、第四栅极402和第四绝缘块403。第四有源图案401具有第四沟道区4010以及位于第四沟道区4010的相对两侧的第七掺杂区4011和第八掺杂区4012。第四有源图案401位于第七掺杂区4011的部分与第三有源图案301位于第六掺杂区 3012的部分连为一体。第四栅极402在衬底340上的正投影与第四沟道区4010在衬底340上的正投影重叠，示例的，与像素驱动电路30连接的使能信号线EM的位于第四晶体管T4所在区域中的部分用作第四栅极402。第四绝缘块403为绝缘层38位于第四晶体管T4所在区域的部分，第四绝缘块403具有第四过孔4030，第一辅助图案400通过第四过孔4030与第四有源图案401位于第八掺杂区4012的部分电连接。这里，通过第一辅助图案400实现发光器件L与第四有源图案401位于第八掺杂区4012的部分的电连接。
由于第四有源图案401位于第七掺杂区4011的部分与第三有源图案301位于第六掺杂区3012的部分连为一体，因此可以同时制作第三有源图案301与第四有源图案401，从而能够简化显示基板34的制作工艺。
如图17和图18所示，该列像素驱动电路30中的所有第四过孔4030的尺寸沿第一方向逐渐递增。图17和图18中的每个亚像素区仅示意出了第四过孔4030的结构。
在一些示例中，如图17所示，在该列像素驱动电路30中，所有第四过孔4030的尺寸沿第一方向依次递增。即，在该列像素驱动电路30中，所有第四过孔4030的尺寸均不相同。
在另一些示例中，如图18所示，该列像素驱动电路30分为多个像素驱动电路组300，每个像素驱动电路组300包括多个像素驱动电路30，不同像素驱动电路组300所包括的像素驱动电路30的数量可以相同，也可以不同。像素驱动电路组300中的第四过孔4030的尺寸相同，不同像素驱动电路组300中的第四过孔4030的尺寸不相同。即，沿第一方向，当前像素驱动电路组300中的第四过孔4030的尺寸相对于上一个像素驱动电路组300中的第四过孔4030的尺寸增大。
基于此，本公开的一些实施例所提供的显示基板34，在该列像素驱动电路30中，用于使发光器件L和像素驱动电路30电连接的第四过孔4030的尺寸沿第一方向逐渐增大。驱动晶体管Td输出的驱动电流会经过第四晶体管T4传输至发光器件L，而第一电压线Vdd沿第一方向的压降会造成第一电源电压信号的电压值逐渐减小，从而使得传输至发光器件L的驱动电流沿第一方向逐渐减小。因此，第四过孔4030的尺寸沿第一方向逐渐增大，能够降低第四晶体管T4与第一辅助图案400的接触电阻，从而使得输出至发光器件L的驱动电流的大小趋于平衡。这样，可进一步改善长程显示亮度不均的问题。
在一些实施例中，如图11所示，像素驱动电路30还包括至少一个第五晶体管T5以及与第一辅助图案400同层设置的第二辅助图案500。如图19所示，每个第五晶体管T5包括第五有源图案501和第五栅极502。第五有源图案501具有第五沟道区5010以及位于第五沟道区5010的相对两侧的第九掺杂区5011和第十掺杂区5012。第五栅极502在衬底340上的正投影与第五沟道区5010在衬底340上的正投影重叠，示例的，与像素驱动电路30连接的栅线Vgate的位于第五晶体管T5所在区域中的部分用作第五栅极502。其中，至少一个第五晶体管T5中的第五有源图案501位于第九掺杂区5011的部分与驱动晶体管Td位于第六掺杂区3012的部分连为一体。第二辅助图案500通过贯穿第三绝缘子层383和第二绝缘子层382的第五过孔304与第一存储电极C1电连接，并通过贯穿绝缘层38的第六过孔503与第五有源图案501位于第十掺杂区5012的部分电连接。
在像素驱动电路30包括多个第五晶体管T5的情况下，该多个第五晶体管T5串联连接，即，第一个第五晶体管T5的第五有源图案501位于第九掺杂区5011的部分与驱动晶体管Td位于第六掺杂区3012的部分连为一体，第一个第五晶体管T5的第五有源图案5010位于第十掺杂区5012的部分与第二个第五晶体管T5的第五有源图案5010位于第九掺杂区5011的部分连为一体，以此类推。以多个第五晶体管T5包括两个第五晶体管T5为例，由于第一个第五晶体管T5的第五有源图案5010的位于第十掺杂区5012的部分与第二个第五晶体管T5的第五有源图案5010的位于第九掺杂区5011的部分连为一体，因此该两个第五晶体管T5可认为是一个第五等效晶体管，该第五等效晶体管的第五有源图案501位于其一个掺杂区的部分即为第一个第五晶体管T5的第五有源图案5010的位于第九掺杂区5011的部分，该第五等效晶体管的第五有源图案501位于其另一掺杂区的部分即为第二个第五晶体管T5的第五有源图案5010的位于第十掺杂区5012的部分。第二辅助图案500通过贯穿绝缘层38的第六过孔503与第五有源图案501位于第十掺杂区5012的部分电连接，实际是指第二辅助图案500通过贯穿绝缘层38的第六过孔503与第五等效晶体管的第五有源图案501位于其另一掺杂区的部分电连接。
由于第五晶体管T5中的第五有源图案501与驱动晶体管Td的第三有源图案301连为一体，因此可以同时制作第三有源图案301与第五有源 图案501，从而能够简化显示基板34的制作工艺。
在一些实施例中，如图11所示，该显示基板34还包括设置在衬底340上且位于显示区的多根初始化信号线Vinit和多根复位信号线Vreset，多根初始化信号线Vinit和多根复位信号线Vreset均沿第二方向延伸，多根复位信号线Vreset与多根栅线Vgate同层设置，多根初始化信号线Vinit与第二存储电极C2同层设置。初始化信号线Vinit被配置为提供初始化信号，复位信号线Vreset被配置为提供复位信号。
如图11所示，像素驱动电路30还包括至少一个第六晶体管T6以及与第一辅助图案400同层设置的第三辅助图案600。如图19所示，每个第六晶体管T6包括第六有源图案601和第六栅极602。第六有源图案601具有第六沟道区6010以及位于第六沟道区6010的相对两侧的第十一掺杂区6011和第十二掺杂区6012。第六栅极602在衬底340上的正投影与第六沟道区6010在衬底340上的正投影重叠，示例的，与像素驱动电路30连接的一根复位信号线Vreset的位于第六晶体管T6所在区域中的部分用作第六栅极602。其中，至少一个第六晶体管T6中的第六有源图案601位于第十二掺杂区6012的部分与至少一个第五晶体管T5中的第五有源图案501位于第十掺杂区5012的部分连为一体。第三辅助图案600通过贯穿第三绝缘子层383的第七过孔603与像素驱动电路30连接的一根初始化信号线Vinit电连接，并通过贯穿绝缘层38的第八过孔604与至少一个第六晶体管T6中的第六有源图案601位于第十一掺杂区6011的部分电连接，以实现第六晶体管T6与初始化信号线Vinit的电连接。
在像素驱动电路30包括多个第六晶体管T6的情况下，该多个第六晶体管T6串联连接，即，第一个第六晶体管T6的第六有源图案6010位于第十二掺杂区6012的部分与第二个第六晶体管T6的第六有源图案6010位于第十一掺杂区6011的部分连为一体，以此类推，最后一个第六晶体管T6的第六有源图案601位于第十二掺杂区6012的部分与至少一个第五晶体管T5中最后一个第五晶体管T5的第五有源图案501位于第十掺杂区5012的部分连为一体。以多个第六晶体管T6包括两个第六晶体管T6为例，由于第一个第六晶体管T6的第六有源图案6010位于第十二掺杂区6012的部分与第二个第六晶体管T6的第六有源图案6010位于第十一掺杂区6011的部分连为一体，因此该两个第六晶体管T6可认为是一个第六等效晶体管，该第六等效晶体管的第六有源图案6010位于其一个掺杂区的部 分为第一个第六晶体管T6的第六有源图案6010位于第十一掺杂区6011的部分，该第六等效晶体管的第六有源图案6010位于其另一掺杂区的部分为第二个第六晶体管T6的第六有源图案6010位于第十二掺杂区6012的部分。第三辅助图案600通过贯穿绝缘层38的第八过孔604与至少一个第六晶体管T6中的第六有源图案601位于第十一掺杂区6011的部分电连接，实际是指第三辅助图案600通过贯穿绝缘层38的第八过孔604与第六等效晶体管的第六有源图案601位于其一个掺杂区的部分电连接。
在一些实施例中，如图11所示，像素驱动电路30还包括第七晶体管T7以及与第三辅助图案600同层设置的第四辅助图案700。如图16所示，第七晶体管T7包括第七有源图案701和第七栅极702。第七有源图案701具有第七沟道区7010以及位于第七沟道区7010的相对两侧的第十三掺杂区7011和第十四掺杂区7012。第七有源图案701位于第十四掺杂区7012的部分与第四有源图案401位于第八掺杂区4012的部分连为一体。第七栅极702在衬底340上的正投影与第七沟道区7010在衬底340上的正投影重叠，示例的，与像素驱动电路30相邻的下一行像素驱动电路30对应的复位信号线Vreset(n+1)位于第七晶体管T7所在区域中的部分用作第七晶体管T7的栅极702。第四辅助图案700通过贯穿绝缘层38的第九过孔703与第七有源图案701位于第十三掺杂区7011的部分电连接，并通过贯穿第三绝缘子层383的第十过孔704和与该像素驱动电路30相邻的下一行像素驱动电路30连接的一根初始化信号线Vinit电连接。
由于第七有源图案701位于第十四掺杂区7012的部分与第四有源图案401位于第八掺杂区4012的部分连为一体，因此可以同时制作第四有源图案401与第七有源图案701，从而能够简化显示基板34的制作工艺。在一些示例中，第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管。
在一些实施例中，如图3所示，发光器件L包括沿衬底340的厚度方向依次层叠设置的阳极341、发光功能层342和阴极343。在一些示例中，该显示面板3是顶发射型显示面板，在此情况下，发光器件L中的阳极341为不透明电极，阴极343为透明电极或半透明电极。在另一些示例中，该显示面板3是底发射型显示面板，在此情况下，发光器件L中的阳极341为透明电极或半透明电极，阴极343为不透明电极。当然，该显示面板3还可以为双面发光型显示面板，在此情况下，发光器件L中 的阳极341和阴极343均为透明电极或半透明电极。
在一些示例中，发光功能层342包括发光层。在另一些示例中，发光功能层342除包括发光层外，还包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)和空穴注入层(hole injection layer，简称HIL)中的一层或多层。在显示面板3为有机电致发光显示面板的情况下，该发光层为有机发光层。在显示面板3为量子点电致发光显示面板的情况下，该发光层为量子点发光层。
在一些实施例中，如图3所示，显示基板34还包括设置在像素驱动电路30和发光器件L之间的平坦层345，该平坦层345具有多个第十一过孔3450。如图16和图20所示，发光器件L与像素驱动电路30的第四晶体管T4通过第一辅助图案400电连接。发光器件L的阳极341通过至少一个第十一过孔3450与第一辅助图案400电连接，即，发光器件L的阳极341穿过平坦层345中的至少一个第十一过孔3450与第一辅助图案400电连接。
如图21和图22所示，该列像素驱动电路30中的所有第十一过孔3450的尺寸沿第一方向逐渐递增。图21和图22中的每个亚像素区仅示意出了第十一过孔3450的结构。
在一些示例中，如图21所示，在该列像素驱动电路30中，所有第十一过孔3450的尺寸沿第一方向依次递增。即，在该列像素驱动电路30中，所有第十一过孔3450的尺寸均不相同。
在另一些示例中，如图22所示，该列像素驱动电路30分为多个像素驱动电路组300，每个像素驱动电路组300包括多个像素驱动电路30，不同像素驱动电路组300所包括的像素驱动电路30的数量可以相同，也可以不同。像素驱动电路组300中的第十一过孔3450的尺寸相同，不同像素驱动电路组300中的第十一过孔3450的尺寸不相同。即，沿第一方向，当前像素驱动电路组300中的第十一过孔3450的尺寸相对于上一个像素驱动电路组300中的第十一过孔3450的尺寸增大。
本公开的一些实施例所提供的显示基板34，在该列像素驱动电路30中，用于实现发光器件L的阳极341与第一辅助图案400电连接的第十一过孔3450的尺寸沿第一方向逐渐增大。由于第一电压线Vdd的压降使得驱动晶体管Td输出的驱动电流沿第一方向逐渐减小，因此，第十一过孔3450的 尺寸沿第一方向逐渐增大能够降低第一辅助图案400与发光器件L的阳极341的接触电阻，从而使得传输至发光器件L的驱动电流的大小趋于平衡。这样，可进一步改善长程显示亮度不均的问题。
在一些实施例中，如图3所示，显示基板34还包括设置在阳极341远离衬底340一侧的像素界定层344。该像素界定层344具有多个开口3440，每个发光器件L设置在对应的一个开口3440中。需要说明的是，图3中由于仅示意了一个发光器件L，因此，图3中的像素界定层344的开口3440也仅示意了一个。
这里，“开口3440的尺寸”是指开口在衬底340上的正投影的尺寸。
示例的，多个发光器件L包括多个红色发光器件，多个绿色发光器件和多个蓝色发光器件，不同颜色的发光器件L对应的开口3440的尺寸不相同。由于蓝色发光器件、红色发光器件和绿色发光器件的发光效率依次升高，因此对于同一个像素区(包括红色亚像素区、绿色亚像素区和蓝色亚像素区)而言，蓝色发光器件、红色发光器件和绿色发光器件对应的开口3440的尺寸依次减小。
而对于不同的像素区而言，如图23和图24所示，与数据线Vdata连接的一列像素驱动电路30对应的所有开口3440的尺寸，沿第一方向逐渐递增。图23和图24中的每个亚像素区仅示意出了开口3440的结构。
在一些示例中，如图23所示，在该列像素驱动电路30中，所有开口3440的尺寸沿第一方向依次递增。即，在该列像素驱动电路30中，所有开口3440的尺寸均不相同。
在另一些示例中，如图24所示，该列像素驱动电路30分为多个像素驱动电路组300，每个像素驱动电路组300包括多个像素驱动电路30，不同像素驱动电路组300所包括的像素驱动电路30的数量可以相同，也可以不同。像素驱动电路组300中的开口3440的尺寸相同，不同像素驱动电路组300中的开口3440的尺寸不相同。即，沿第一方向，当前像素驱动电路组300中的开口3440的尺寸相对于上一个像素驱动电路组300中的开口3440的尺寸增大。
应当理解，开口3440的尺寸不相同，则设置在开口3440内的发光器件L的尺寸不相同。而发光器件L的尺寸越大，从该开口3440的区域发出的光的亮度就越大。
由于多个开口3440的尺寸不完全相同，因而从多个开口3440的区 域发出的光的亮度不完全相同。根据不同颜色的发光器件L的发光效率以及信号线的压降现象来设计开口3440的尺寸，从而可以解决不同颜色的效率差异以及长程显示亮度不均共同产生的色差或颜色不均的(Discolor)问题。
基于以上描述，本公开的一些实施例还提供了另一种显示基板，与上述显示基板的不同在于，驱动晶体管Td为N型晶体管，且沿第一方向，第一过孔1030、第二过孔2030、第四过孔4030、第十一过孔3450、以及开口3440的尺寸的变化趋势与驱动晶体管Td为P型晶体管时的变化趋势相反，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    衬底，具有显示区；
    多根数据线，设置在所述衬底上且位于所述显示区；
    多列像素驱动电路，设置在所述衬底上且位于所述显示区；所述多列像素驱动电路中的一列像素驱动电路与所述多根数据线中对应的一根数据线连接，该列像素驱动电路中的每个像素驱动电路包括驱动晶体管和与该驱动晶体管电连接的第一晶体管，所述驱动晶体管为P型晶体管；所述第一晶体管包括：
    第一有源图案，具有第一沟道区以及位于所述第一沟道区的相对两侧的第一掺杂区和第二掺杂区；
    第一栅极，所述第一栅极在所述衬底上的正投影与所述第一沟道区在所述衬底上的正投影重叠；
    第一绝缘块，设置在所述第一有源图案远离所述衬底的一侧，所述第一绝缘块为绝缘层位于所述第一晶体管所在区域的部分，且所述第一绝缘块具有第一过孔；所述数据线通过所述第一过孔与所述第一有源图案位于所述第一掺杂区的部分电连接；
    其中，该列像素驱动电路中的所有第一过孔的尺寸沿第一方向逐渐递减；所述第一方向为所述数据线的信号输入端指向该信号输入端相对的远端的方向。
  2. 根据权利要求1所述的显示基板，其中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第一过孔的尺寸相同，且不同像素驱动电路组中的所述第一过孔的尺寸不相同。
  3. 根据权利要求1或2所述的显示基板，还包括：
    多根第一电压线，设置在所述衬底上且位于所述显示区；所述多根第一电压线均沿所述第一方向延伸；所述多根第一电压线与所述多根数据线同层设置；
    所述像素驱动电路还包括第二晶体管，所述第二晶体管包括：
    第二有源图案，具有第二沟道区以及位于所述第二沟道区的相对两侧的第三掺杂区和第四掺杂区；所述第二有源图案位于所述第四掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；
    第二栅极，所述第二栅极在所述衬底上的正投影与所述第二沟道区在所述衬底上的正投影重叠；
    第二绝缘块，所述第二绝缘块为所述绝缘层位于所述第二晶体管所在区域的部分，且所述第二绝缘块具有第二过孔；与该列像素驱动电路连接的一根第一电压线通过所述第二过孔与所述第二有源图案位于所述第三掺杂区的部分电连接；
    其中，该列像素驱动电路中的所有第二过孔的尺寸沿所述第一方向逐渐递增。
  4. 根据权利要求3所述的显示基板，其中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第二过孔的尺寸相同，且不同像素驱动电路组中的所述第二过孔的尺寸不相同。
  5. 根据权利要求3或4所述的显示基板，其中，所述像素驱动电路还包括存储电容器；
    所述存储电容器包括：
    第一存储电极；
    第二存储电极，设置在所述第一存储电极与所述多根数据线和所述多根第一电压线所在的层之间；
    所述驱动晶体管包括：
    第三有源图案，具有第三沟道区以及位于所述第三沟道区的相对两侧的第五掺杂区和第六掺杂区；所述第三有源图案位于所述第五掺杂区的部分与所述第一有源图案位于所述第二掺杂区的部分连为一体；
    第三栅极，与所述第一存储电极复用，所述第三栅极在所述衬底上的正投影与所述第三沟道区在所述衬底上的正投影重叠；
    其中，所述绝缘层包括依次层叠设置的第一绝缘子层、第二绝缘子层和第三绝缘子层，所述第一绝缘子层位于所述第三有源图案与所述第一存储电极之间，所述第二绝缘子层位于所述第一存储电极与第二存储电极之间，所述第三绝缘子层位于所述第二存储电极与多根数据线和所述多根第一电压线所在的层之间；所述第一电压线通过贯穿所述第三绝缘子层的第三过孔与所述第二存储电极电连接。
  6. 根据权利要求5所述的显示基板，其中，所述像素驱动电路还包括：
    第四晶体管，所述第四晶体管包括：
    第四有源图案，具有第四沟道区以及位于所述第四沟道区的相对两侧的第七掺杂区和第八掺杂区；所述第四有源图案位于所述第七掺杂区的部分与所述第三有源图案位于所述第六掺杂区的部分连为一体；
    第四栅极，所述第四栅极在所述衬底上的正投影与所述第四沟道区在所述衬底上的正投影重叠；
    第四绝缘块，所述第四绝缘块为所述绝缘层位于所述第四晶体管所在区域的部分，且所述第四绝缘块具有第四过孔；
    第一辅助图案，与所述多根数据线和所述多根第一电压线同层设置；所述第一辅助图案通过所述第四过孔与所述第四有源图案位于所述第八掺杂区的部分电连接；
    其中，该列像素驱动电路中的所有第四过孔的尺寸，沿所述第一方向逐渐递增。
  7. 根据权利要求6所述的显示基板，其中，该列像素驱动电路分为多个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第四过孔的尺寸相同，且不同像素驱动电路组中的所述第四过孔的尺寸不相同。
  8. 根据权利要求6或7所述的显示基板，还包括：
    多根使能信号线，设置在所述衬底上且位于所述显示区；所述多根使能信号线均沿第二方向延伸，所述第二方向与所述第一方向交叉；所述多根使能信号线与所述第一存储电极同层设置；每根使能信号线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根使能信号线的位于所述第四晶体管所在区域中的部分和位于所述第二晶体管所在区域中的部分，分别用作所述第四栅极和所述第二栅极。
  9. 根据权利要求7或8所述的显示基板，其中，所述像素驱动电路还包括：
    至少一个第五晶体管，每个第五晶体管包括：
    第五有源图案，具有第五沟道区以及位于所述第五沟道区的相对两侧的第九掺杂区和第十掺杂区；
    第五栅极，所述第五栅极在所述衬底上的正投影与所述第五沟道区在所述衬底上的正投影重叠；
    其中，所述至少一个第五晶体管中的所述第五有源图案位于所述第九掺杂区的部分与所述驱动晶体管中的所述第三有源图案位于所述第六掺杂区的部分连为一体；
    第二辅助图案，与所述第一辅助图案同层设置；所述第二辅助图案通过贯穿所述第三绝缘子层和所述第二绝缘子层的第五过孔与所述第一存储电极电连接，并通过贯穿所述绝缘层的第六过孔与所述第五有源图案位于所述第十掺杂区的部分电连接。
  10. 根据权利要求9所述的显示基板，还包括：
    多根栅线，设置在所述衬底上且位于所述显示区；所述多根栅线均沿所述第二方向延伸，且所述多根栅线与所述多根使能信号线同层设置；每根栅线与多行像素驱动电路中的一行像素驱动电路连接，与所述像素驱动电路连接的一根栅线的位于所述第一晶体管所在区域中的部分和位于所述第五晶体管所在区域中的部分，分别用作所述第一栅极和所述第五栅极。
  11. 根据权利要求9或10所述的显示基板，还包括：
    多根初始化信号线，设置在所述衬底上且位于所述显示区；所述多根初始化信号线均沿所述第二方向延伸，且所述多根初始化信号线与所述第二存储电极同层设置；每根初始化信号线与多行像素驱动电路中的一行像素驱动电路连接；
    所述像素驱动电路还包括：
    至少一个第六晶体管，每个第六晶体管包括：
    第六有源图案，具有第六沟道区以及位于所述第六沟道区的相对两侧的第十一掺杂区和第十二掺杂区；
    第六栅极，所述第六栅极在所述衬底上的正投影与所述第六沟道区在所述衬底上的正投影重叠；
    其中，所述至少一个第六晶体管中的所述第六有源图案位于所述第十二掺杂区的部分与所述至少一个第五晶体管中的所述第五有源图案位于所述第十掺杂区的部分连为一体；
    第三辅助图案，与所述第一辅助图案同层设置；所述第三辅助图案通过贯穿所述第三绝缘子层的第七过孔与所述像素驱动电路对应的一根初始化信号线电连接，并通过贯穿所述绝缘层的第八过孔与所述至少一个第六晶体管中的所述第六有源图案位于所述第十一掺杂区的部分电连接。
  12. 根据权利要求11所述的显示基板，其中，所述像素驱动电路还包括：
    第七晶体管；所述第七晶体管包括：
    第七有源图案，具有第七沟道区以及位于所述第七沟道区的相对两侧的第十三掺杂区和第十四掺杂区；所述第七有源图案位于所述第十四掺杂区的部分与所述第四有源图案位于所述第八掺杂区的部分连为一体；
    第七栅极，所述第七栅极在所述衬底上的正投影与所述第七沟道区在所述衬底上的正投影重叠；
    第四辅助图案，与所述第三辅助图案同层设置；所述第四辅助图案通过贯穿所述绝缘层的第九过孔与所述第七有源图案位于所述第十三掺杂区的部分电连接，并通过贯穿所述第三子绝缘层的第十过孔和与该像素驱动电路相邻的下一行像素驱动电路对应的一根初始化信号线电连接。
  13. 根据权利要求12所述的显示基板，还包括：
    多根复位信号线，设置在所述衬底上且位于所述显示区；所述多根复位信号线均沿所述第二方向延伸，且所述多根复位信号线与所述多根栅线同层设置；与所述像素驱动电路连接的一根复位信号线的位于所述第六晶体管所在区域中的部分用作第六栅极，与所述像素驱动电路相邻的下一行像素驱动电路连接的复位信号线位于所述第七晶体管所在区域中的部分用作第七晶体管的栅极。
  14. 根据权利要求1-13任一项所述的显示基板，还包括：
    多个发光器件，设置在所述衬底上；每个像素驱动电路与所述多个发光器件中的一个发光器件电连接，所述像素驱动电路被配置为驱动所述发光器件发光。
  15. 根据权利要求14所述的显示基板，还包括：
    平坦层，设置在所述像素驱动电路与所述发光器件之间；所述平坦层具有多个第十一过孔；其中，
    所述像素驱动电路包括第四晶体管和第一辅助图案；所述发光器件包括沿所述衬底的厚度方向依次层叠的阳极、发光功能层和阴极，所述发光器件的阳极通过至少一个第十一过孔与所述第一辅助图案电连接；
    其中，该列像素驱动电路中的所有第十一过孔的尺寸沿所述第一方向逐渐递增。
  16. 根据权利要求15所述的显示基板，其中，该列像素驱动电路分为多 个像素驱动电路组，每个像素驱动电路组包括多个像素驱动电路，所述像素驱动电路组中的所有第十一过孔的尺寸相同，且不同像素驱动电路组中的所述第十一过孔的尺寸不相同。
  17. 根据权利要求15所述的显示基板，还包括：
    像素界定层，设置在所述阳极远离所述衬底一侧；所述像素界定层具有多个开口，每个发光器件设置在对应的一个开口中；
    其中，该列像素驱动电路对应的所有开口的尺寸沿所述第一方向逐渐递增。
  18. 根据权利要求17所述的显示基板，其中，所述多个发光器件包括多个红色发光器件，多个绿色发光器件和多个蓝色发光器件，不同颜色的发光器件对应的开口的尺寸不同。
  19. 一种显示面板，包括如权利要求1-18任一项所述的显示基板以及封装层。
  20. 一种显示装置，包括如权利要求19所述的显示面板以及设置在所述显示面板一侧的数据驱动芯片，所述数据驱动芯片所在的一侧为所述显示面板中的数据线的信号输入端。
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