WO2021103003A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021103003A1
WO2021103003A1 PCT/CN2019/122189 CN2019122189W WO2021103003A1 WO 2021103003 A1 WO2021103003 A1 WO 2021103003A1 CN 2019122189 W CN2019122189 W CN 2019122189W WO 2021103003 A1 WO2021103003 A1 WO 2021103003A1
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WO
WIPO (PCT)
Prior art keywords
sub
auxiliary
display panel
pixel
base substrate
Prior art date
Application number
PCT/CN2019/122189
Other languages
English (en)
French (fr)
Inventor
吴仲远
李永谦
袁粲
袁志东
李蒙
张大成
刘烺
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/122189 priority Critical patent/WO2021103003A1/zh
Priority to US16/976,796 priority patent/US11849617B2/en
Priority to CN201980002714.7A priority patent/CN113196492A/zh
Publication of WO2021103003A1 publication Critical patent/WO2021103003A1/zh
Priority to US18/492,194 priority patent/US20240057418A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to display panels and display devices.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • other electroluminescent diodes have the advantages of self-luminescence, low energy consumption, etc., which are the most important in the application research field of electroluminescent display panels.
  • One of the hot spots has received widespread attention.
  • a plurality of pixel units are arranged in an array on the base substrate, and at least one of the pixel units includes: a plurality of sub-pixels, and at least one of the sub-pixels includes: a sensing transistor and a driving transistor;
  • a plurality of gate line groups each of the gate line groups includes a first gate line and a second gate line located on both sides of the pixel unit;
  • the sensing transistor is located on the side of the sub-pixel closer to the second gate line, and the driving transistor is located The sub-pixel is closer to one side of the first gate line;
  • the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through a first connecting hole, and the first electrode of the driving transistor is electrically connected to the power line through the second connecting hole;
  • At least one signal line in the area enclosed by the first connection hole and the second connection hole of the two sub-pixels has a double-layer routing Line structure, and the double-layer wiring structure of the same signal line is electrically connected to each other.
  • the sub-pixel further includes: an anode, a light-emitting function layer, and a cathode layer that are stacked; wherein, in the same sub-pixel, the second electrode of the driving transistor is electrically connected to the anode. connection;
  • the display panel also includes:
  • a plurality of auxiliary wirings wherein the auxiliary wiring is located in the gap between two adjacent sub-pixel columns, and the cathode layer is electrically connected to the auxiliary wiring through a first via;
  • the detection line is located in the gap between two adjacent sub-pixel columns, and the detection line is insulated from the auxiliary wiring, and the detection line is connected to the first of the sensing transistor Two-pole electrical connection;
  • the signal line includes: at least one of the auxiliary wiring, the detection line, and the power line.
  • the display panel further includes:
  • the pixel defining layer is located between the layer where the anode is located and the light-emitting function layer;
  • a planarization layer located on the side of the pixel defining layer facing the base substrate;
  • a first conductive layer located on the side of the planarization layer facing the base substrate;
  • the first insulating layer is located on the side of the first conductive layer facing the base substrate;
  • a second conductive layer located on the side of the first insulating layer facing the base substrate;
  • the auxiliary wiring includes:
  • the first auxiliary wiring is located on the first conductive layer and extends along the column direction of the sub-pixels;
  • the second auxiliary wiring is located on the second conductive layer
  • the first auxiliary wiring is electrically connected to the second auxiliary wiring through a second via hole penetrating the first insulating layer.
  • the second auxiliary wiring includes a plurality of first auxiliary parts arranged at intervals; wherein, in the same auxiliary wiring, the first auxiliary wiring passes through the The second via hole is electrically connected to the corresponding first auxiliary part.
  • the orthographic projection of the first auxiliary wiring on the base substrate and the corresponding first auxiliary part on the base substrate has overlapping areas.
  • the orthographic projection of the first auxiliary portion on the base substrate covers the orthographic projection of the corresponding second via on the base substrate.
  • one sub-pixel row corresponds to one first auxiliary part.
  • sub-pixel rows separated by at least one sub-pixel row correspond to one first auxiliary portion.
  • each of the first auxiliary parts is electrically connected to the corresponding first auxiliary wiring through at least four second via holes.
  • the first auxiliary part and the first gate line and the second gate line corresponding to the same row of sub-pixels is closer to the second gate line.
  • the orthographic projection of the first via on the base substrate and the orthographic projection of the anode on the base substrate do not overlap.
  • the display panel further includes:
  • a plurality of first connecting parts which are in the same layer as the anode and are insulated;
  • the first via includes: a first sub-via penetrating through the pixel defining layer and a second sub-via penetrating through the planarization layer;
  • the cathode layer is electrically connected to the first connection part through the first sub-via, and the first connection part is electrically connected to the auxiliary wiring through the second sub-via.
  • the orthographic projection of the first sub-via on the base substrate and the orthographic projection of the second sub-via on the base substrate at least partially do not overlap.
  • one auxiliary wiring corresponds to a plurality of first via holes, and one first via corresponds to one sub-pixel row;
  • the orthographic projection of the first sub-via on the base substrate and the second gate line has an overlapping area; and the orthographic projection of the second sub-via on the base substrate is located on the first grid line and the second grid line on the backing Between the orthographic projection of the base substrate.
  • the second sub-vias are located in the The orthographic projection of the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of all the second vias on the base substrate.
  • the width of the portion of the first auxiliary trace that overlaps the orthographic projection of the first auxiliary part along the sub-pixel row direction is the first width, which is the same as the first width.
  • the width of the portion of the orthographic projection of a gate line with the overlapping first auxiliary wiring along the sub-pixel row direction is the second width;
  • the first width is greater than the second width.
  • the portion of the first auxiliary wiring having the second width is close to the second connecting hole.
  • the first auxiliary wiring is located in a gap between two adjacent pixel unit columns.
  • At least two adjacent pixel unit columns are taken as a first column group, one of the first column groups corresponds to one first auxiliary wiring, and the first auxiliary wiring Located in the gap between two adjacent pixel unit columns in the corresponding first column group.
  • the display panel further includes:
  • a second insulating layer located on the side of the second conductive layer facing the base substrate;
  • An active semiconductor layer located on the side of the second insulating layer facing the base substrate;
  • a third insulating layer located on the side of the active semiconductor layer facing the base substrate;
  • a light-shielding metal layer located on the side of the third insulating layer facing the base substrate;
  • the light-shielding metal layer includes: at least one light-shielding electrode; wherein, one of the light-shielding electrodes is located in one of the sub-pixels;
  • the orthographic projection of the light-shielding electrode on the base substrate at least covers the orthographic projection of the channel region of the driving transistor on the base substrate.
  • At least one of the sub-pixels further includes: a storage capacitor; wherein the first electrode of the storage capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the gate of the driving transistor.
  • the two poles are electrically connected to the second pole of the driving transistor;
  • the second electrode of the storage capacitor is also electrically connected to the light-shielding electrode through a third connection hole.
  • the detection line includes:
  • the first detection trace is located in the first conductive layer and extends along the column direction of the sub-pixels;
  • the second detection trace is located on the second conductive layer
  • the first detection trace is electrically connected to the second detection trace through a third via hole penetrating the first insulating layer.
  • the second detection line includes a plurality of second auxiliary parts arranged at intervals; wherein, in the same detection line, the first detection line passes through the first detection line respectively.
  • the three vias are electrically connected to the corresponding second auxiliary part.
  • the orthographic projection of the first detection trace on the base substrate and the corresponding second auxiliary part on the base substrate has overlapping areas.
  • the orthographic projection of the second auxiliary portion on the base substrate covers the orthographic projection of the corresponding third via on the base substrate.
  • one sub-pixel row corresponds to one second auxiliary part.
  • sub-pixel rows separated by at least one sub-pixel row correspond to one second auxiliary part.
  • one second auxiliary part and one first auxiliary part correspond to the same sub-pixel row.
  • the second via hole of the first auxiliary part and the second auxiliary part is misaligned.
  • each of the second auxiliary parts is electrically connected to the corresponding first detection trace through at least three third via holes.
  • the second auxiliary part and the first gate line and the second gate line corresponding to the same row of sub-pixels is closer to the first gate line.
  • the width of the portion of the first detection trace that overlaps the orthographic projection of the second auxiliary part along the sub-pixel row direction is the third width, which is the same as the first detection trace.
  • the width of the portion of the orthographic projection of a gate line with overlapping first detection traces along the sub-pixel row direction is a fourth width;
  • the third width is greater than the fourth width.
  • the portion of the first detection trace having the fourth width is close to the second connection hole.
  • the first auxiliary wiring corresponds to the first detection wiring and the first auxiliary wiring.
  • the orthographic projection of the first sub-via on the base substrate also has an overlapping area with the orthographic projection of the first detection trace on the base substrate.
  • one of the first detection wiring and one of the first auxiliary wiring are both arranged in the gap between the same pixel unit column.
  • the power cord includes:
  • the first power trace is located on the first conductive layer and extends along the column direction of the sub-pixels;
  • the second power trace is located on the second conductive layer
  • the first power trace is electrically connected to the second power trace through a fourth via hole penetrating the first insulating layer.
  • At least one column of pixel units is spaced between the first power trace and the first auxiliary trace.
  • the second power trace includes a plurality of third auxiliary parts arranged at intervals; wherein, in the same power cord, the first power trace respectively passes through the first power cord.
  • the four vias are electrically connected to the corresponding third auxiliary part.
  • the orthographic projection of the first power trace on the base substrate and the corresponding third auxiliary part on the base substrate has overlapping areas.
  • the orthographic projection of the third auxiliary portion on the base substrate covers the orthographic projection of the corresponding fourth via on the base substrate.
  • each of the third auxiliary parts is electrically connected to the corresponding first power trace through at least four fourth via holes.
  • one sub-pixel row corresponds to one third auxiliary part.
  • sub-pixel rows separated by at least one sub-pixel row correspond to one third auxiliary part.
  • one said third auxiliary part and one said first auxiliary part correspond to the same sub-pixel row.
  • the third auxiliary part and the first gate line and the second gate line corresponding to the same row of sub-pixels is closer to the second gate line. Two gate lines.
  • the width of the portion of the first power trace that overlaps the orthographic projection of the third auxiliary portion along the sub-pixel row direction is the fifth width, which is the same as the first power trace.
  • the width of the part of the orthographic projection of a gate line with overlapping first power traces along the direction of the sub-pixel row is the sixth width;
  • the fifth width is greater than the sixth width.
  • the portion of the first power trace having the sixth width is close to the second connection hole.
  • a fourth via hole corresponding to the third auxiliary portion and the first The connecting holes are arranged on a straight line along the sub-pixel row direction.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2a is a schematic top view of the structure of a display panel provided by an embodiment of the disclosure.
  • FIG. 2b is a schematic top view of some display panels provided by the embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of the layout structure of still other display panels provided by the embodiments of the present disclosure.
  • 4a is a schematic cross-sectional structure diagram of the display panel shown in FIG. 3 along the AA' direction;
  • 4b is a schematic cross-sectional structure view of the display panel shown in FIG. 3 along the BB' direction;
  • 4c is a schematic cross-sectional structure view of the display panel shown in FIG. 3 along the CC' direction;
  • FIG. 5a is a schematic diagram of the structure of a light-shielding metal layer in the display panel shown in FIG. 3;
  • FIG. 5b is a schematic diagram of the structure of the active semiconductor layer in the display panel shown in FIG. 3;
  • FIG. 5c is a schematic diagram of the structure of the second conductive layer in the display panel shown in FIG. 3;
  • FIG. 5d is a schematic diagram of the structure of the first conductive layer in the display panel shown in FIG. 3;
  • FIG. 6 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • Electroluminescent diodes are generally current-driven and require a stable current to drive their light.
  • a pixel drive circuit is used in the display panel to drive the electroluminescent diode to emit light.
  • the electroluminescent diode includes an anode, a light-emitting function layer, and a cathode layer that are sequentially stacked on a base substrate.
  • the pixel driving circuit is electrically connected with the anode to load a signal to the anode.
  • a low voltage signal VSS is applied to the cathode layer to cause the electroluminescent diode to emit light.
  • the light-emitting surface of top-emission electroluminescent diodes is on the side of the cathode layer.
  • the cathode is generally made of transparent conductive material or made very thin, which leads to The sheet resistance of the cathode is relatively large. In this way, when the display panel is working, the current flowing through the cathode will be larger, and the voltage drop (IR-Drop) on the cathode will be larger, which leads to the problem of uneven luminous brightness at different positions of the display panel.
  • the display panel may include: a base substrate; a plurality of pixel units arranged in an array on the base substrate, and a plurality of gate line groups.
  • at least one pixel unit includes: a plurality of sub-pixels
  • at least one sub-pixel includes: a sensing transistor and a driving transistor.
  • Each gate line group includes a first gate line and a second gate line located on both sides of the pixel unit; for the first gate line and the second gate line corresponding to the same row of sub-pixels, the sensing transistor is located in the sub-pixel closer to the second gate line
  • the driving transistor is located on the side of the sub-pixel closer to the first gate line; in the same sub-pixel, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through the first connecting hole, and the first electrode of the driving transistor is electrically connected to the second electrode of the driving transistor through the first connecting hole.
  • One pole is electrically connected to the power line through the second connection hole; for two sub-pixels in the same row that are close to each other and not located in the same pixel unit, the area enclosed by the first connection hole and the second connection hole of the two sub-pixels has at least One signal line has a double-layer wiring structure, and the double-layer wiring structure of the same signal line is electrically connected to each other.
  • the resistance of the signal line provided with the double-layer wiring structure can be reduced, thereby reducing the influence of IR Drop on the light-emitting uniformity of the display panel and improving the display effect of the display panel .
  • At least one sub-pixel may include a pixel driving circuit and an electroluminescent diode L.
  • the display panel provided by the embodiment of the present disclosure will be described below in conjunction with the structure of the pixel driving circuit.
  • the pixel driving circuit generally includes: a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst.
  • the gate of the switching transistor T2 is electrically connected to the first gate line G1
  • the first electrode (for example, the source) of the switching transistor T2 is electrically connected to the data line DA
  • the second electrode (for example, the drain) of the switching transistor T2 is electrically connected to the driving
  • the gate of the transistor T1 is electrically connected.
  • the first electrode (for example, the source) of the driving transistor T1 is electrically connected to the power supply line VDD
  • the second electrode (for example, the drain) of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode L
  • the cathode of the electroluminescent diode L is electrically connected to The low voltage signal line VSS is electrically connected.
  • the gate of the sensing transistor T3 is electrically connected to the second gate line G2
  • the first electrode (for example, the source) of the sensing transistor T3 is electrically connected to the second electrode (for example, the drain) of the driving transistor T1
  • the The second electrode (for example, the drain) is electrically connected to the detection line SL.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1
  • the second electrode of the storage capacitor Cst is electrically connected to the second electrode (for example, the drain) of the driving transistor T1.
  • the switching transistor T2 is controlled to be turned on by the signal transmitted on the first gate line G1 to write the data voltage transmitted on the data line DA into the gate of the driving transistor T1, and the driving transistor T1 is controlled to generate a working current to drive the electroluminescent diode L Glow.
  • the sensing transistor T3 is controlled to be turned on by the signal transmitted on the second gate line G2, so as to output the operating current generated by the driving transistor T1 to the detection line SL to charge the detection line SL. Then, by detecting the voltage on each detection line SL, and performing compensation calculation according to the detected voltage, the data voltage for display corresponding to each sub-pixel in the row is obtained.
  • the power supply line VDD may transmit a constant first voltage, the first voltage being a positive voltage; and the low-voltage signal line VSS may transmit a constant second voltage, and the second voltage is a negative voltage.
  • the low voltage signal line VSS may also be grounded.
  • the pixel driving circuit may also be a structure including other numbers of transistors and capacitors, which is not limited in the embodiment of the present disclosure.
  • the display panel may include a plurality of pixel units PX located in the display area AA, for example, a plurality of pixel units PX.
  • At least one pixel unit PX may include a plurality of sub-pixels.
  • each pixel unit may include a plurality of sub-pixels.
  • a pixel unit usually includes a plurality of sub-pixels that can respectively display a single color (for example, red, green or blue), and each sub-pixel is provided with an electroluminescent diode and a pixel driving circuit to pass
  • the light-emitting ratio of the sub-pixels of different colors is controlled to realize the display of different colors, so the above-mentioned sub-pixels may be monochromatic sub-pixels.
  • the pixel unit PX may include: a first color sub-pixel 010, a second color sub-pixel 020, and a third color sub-pixel 030.
  • the first color sub-pixel is configured to emit light of the first color
  • the second color sub-pixel is configured to emit light of the second color
  • the third color sub-pixel is configured to emit light of the third color.
  • the first color, the second color, and the third color can be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue.
  • the pixel unit PX has an arrangement structure of red, green and blue sub-pixels.
  • the embodiments of the present disclosure include but are not limited thereto, and the above-mentioned first color, second color, and third color may also be other colors.
  • the first-color sub-pixels, the second-color sub-pixels, and the third-color sub-pixels are sequentially arranged along the row direction F2, and the colors of the sub-pixels in the same column are the same.
  • the embodiments of the present disclosure include but are not limited to this.
  • the display panel further includes: a plurality of auxiliary wiring 210, a plurality of detection lines SL, and a plurality of data lines DA (DA-010, DA -020, DA-030) and power line VDD.
  • the detection line is insulated from the auxiliary wiring, and the auxiliary wiring 210 is located in the gap between two adjacent sub-pixel columns.
  • the detection line SL is located in the gap between two adjacent sub-pixel columns, and the detection line is electrically connected to the second electrode of the sensing transistor.
  • the first pole of the driving transistor is electrically connected to the power line VDD.
  • Figs. 5a to 5d are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the present disclosure. The positional relationship of the pixel driving circuit on the base substrate will be described below with reference to FIGS. 5a to 5d.
  • the display panel may include: a pixel defining layer 330 located between the layer 500 where the anode is located and the light-emitting function layer 600, and a planarizing layer located on the side of the pixel defining layer 330 facing the base substrate 100 320, the first conductive layer 200 located on the side of the planarization layer facing the base substrate, the first insulating layer 711 located on the side of the first conductive layer 200 facing the base substrate 100; the first insulating layer 711 facing the base substrate 100
  • the second conductive layer 800 on one side, the second insulating layer 712 on the side of the second conductive layer 800 facing the base substrate 100, and the active semiconductor layer 0320 on the side of the second insulating layer 712 facing the base substrate 100 are located
  • the active semiconductor layer 0320 faces the third insulating layer 713 on the side of the base substrate 100, and the light shielding metal layer 0310 is located on the side of the third insulating layer 713 facing the base substrate 100.
  • 3 to 5d also show the first gate line G1, the second gate line G2, the detection line SL, the data lines DA-010, DA-020 and DA-030, and the power supply line VDD connected to the pixel driving circuit. , Auxiliary routing 210.
  • the data line DA-010 is electrically connected to the switching transistor T2 of the pixel driving circuit in the first color sub-pixel 010
  • the data line DA-020 is electrically connected to the switching transistor T2 of the pixel driving circuit in the second color sub-pixel 020
  • the data line DA-030 is electrically connected to the switching transistor T2 of the pixel driving circuit in the third color sub-pixel 030.
  • the light-shielding metal layer 0310 of the pixel driving circuit is located on the base substrate 100.
  • the light-shielding metal layer 0310 includes: a first connection line 0311, a second connection line 0312, and light-shielding electrodes 0313-010, 0313-020, and 0313-030.
  • the first connection trace 0311 and the second connection trace 0312 extend along the row direction F2.
  • the first color sub-pixel 010 includes light-shielding electrodes 0313-010
  • the second color sub-pixel 020 includes light-shielding electrodes 0313-020
  • the third color sub-pixel 030 includes light-shielding electrodes 0313-030.
  • the orthographic projection of the light-shielding electrodes 0313-010, 0313-020, and 0313-030 on the base substrate 100 at least covers the orthographic projection of the channel region of the driving transistor on the base substrate 100.
  • the active semiconductor layer 0320 of the above-mentioned pixel driving circuit is shown, and there is a third insulating layer 713 between the active semiconductor layer 0320 and the light-shielding metal layer 0310.
  • the active semiconductor layer 0320 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 0320 can be used to fabricate the active layers of the driving transistor T1, the switching transistor T2, and the sensing transistor T3 in the first color sub-pixel 010, the second color sub-pixel 020, and the third color sub-pixel 030, each of which has
  • the source layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active semiconductor layer 0320 also includes conductive regions 0323-010, 0323-020, and 0323-030; wherein the conductive regions 0323-010 form the first pole of the storage capacitor Cst in the first color sub-pixel 010, and the conductive region 0323-010 020 forms the first pole of the storage capacitor Cst in the second color sub-pixel 020, and the conductive regions 0323-030 form the first pole of the storage capacitor Cst in the third color sub-pixel 030.
  • the embodiments of the present disclosure include but are not limited to this.
  • the active layer of each transistor is arranged at intervals.
  • the active semiconductor layer 0320 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the aforementioned conductive region may be a conductive region formed after ion doping of the active semiconductor layer 0320. Of course, the embodiments of the present disclosure include but are not limited to this.
  • the pixel driving circuit further includes a second conductive layer 800 located on the side of the active semiconductor layer 0320 away from the base substrate 100.
  • a second insulating layer 720 is formed between the aforementioned active semiconductor layer 0320 and the second conductive layer 800 to protect the aforementioned active semiconductor layer 0320.
  • the second conductive layer 800 is shown.
  • the second conductive layer 800 is disposed on the second insulating layer 712 so as to be insulated from the active semiconductor layer 0320.
  • the second conductive layer 800 may include a plurality of first gate lines G1, a plurality of second gate lines G2, and a plurality of gate portions (for example, gate portions G-010, G-020, and G-030).
  • the gate of the switching transistor T2 may be the overlapping portion of the first gate line G1 and the active semiconductor layer 0320, and the gate of the sensing transistor T3 may be the second gate line G2 overlaps the active semiconductor layer 0320.
  • the gate part G-010 is the gate of the driving transistor T1 in the first color sub-pixel 010
  • the gate part G-020 is the gate of the driving transistor T1 in the second color sub-pixel 020
  • the gate part G-030 It is the gate of the driving transistor T1 in the third color sub-pixel 030.
  • each gate line group includes a first gate line G1 and a second gate line G2; wherein, a row of sub-pixels corresponds to one gate line group, and the first gate line group in the same gate line group A gate line G1 and a second gate line G2 are located on both sides of the row of pixel units.
  • a row of sub-pixels is correspondingly electrically connected to a first gate line G1 and a second gate line G2.
  • the first gate line G1 and the second gate line G2 are arranged along the column direction F1 and extend along the row direction F2.
  • the first pole of the storage capacitor Cst is located between the first gate line G1 and the second gate line G2.
  • each dashed rectangular frame (not labeled) in FIG. 5c shows each part where the second conductive layer 800 and the active semiconductor layer 0320 overlap.
  • the first conductive layer 200 of the pixel driving circuit is shown.
  • the first conductive layer 200 is located on the side of the first insulating layer 711 away from the base substrate 100.
  • the first conductive layer 200 includes: a plurality of data lines (for example, data lines DA-010, DA-020, and DA-030), and capacitor electrode portions Cst-010, Cst-020, and Cst-030.
  • the capacitor electrode portion Cst-010 serves as the second pole of the storage capacitor Cst in the first color sub-pixel 010
  • the capacitor electrode portion Cst-020 serves as the second pole of the storage capacitor Cst in the second color sub-pixel 020
  • the capacitor electrode portion Cst -030 is used as the second pole of the storage capacitor Cst in the third color sub-pixel 030.
  • the data lines DA-010, DA-020, and DA-030 may be extended along the column direction F1 and arranged along the row direction F2.
  • the data lines DA-010, DA-020, and DA-030 are electrically connected to the source of the switching transistor through a portion protruding in the row direction F2, respectively.
  • the pixel defining layer 330 may include a plurality of light-emitting opening regions KB.
  • the display panel may further include: an anode layer 500 located between the planarization layer 320 and the pixel defining layer 330, and a light-emitting function layer 600 located between the anode layer 500 and the cathode layer 400.
  • the layer 500 where the anode is located includes a plurality of independent anodes 510; wherein, one anode 510 corresponds to one light-emitting opening area KB, and the orthographic projection of the anode 510 on the base substrate 100 and the corresponding light-emitting opening area KB are on the base substrate 100.
  • the orthographic projection has overlapping areas. Exemplarily, the orthographic projection of the first via 310 on the base substrate 100 and the orthographic projection of the anode 510 on the base substrate 100 do not overlap. In this way, the influence of the first via 310 on the flatness of the anode 510 can be avoided.
  • planarization layer 320 on the side of the aforementioned first conductive layer 200 away from the base substrate 100 for protecting the aforementioned first conductive layer 200 and achieving a planarization effect.
  • a pixel defining layer 330 on the side of the layer 500 where the anode is located away from the base substrate 100.
  • the pixel defining layer 330 has a plurality of light-emitting opening areas KB.
  • One anode 510 corresponds to one light-emitting opening area KB, so that the corresponding light-emitting opening area KB corresponds to The anode 510 is exposed.
  • the first conductive layer 200 is located on the side of the layer 500 where the anode is located facing the base substrate 100.
  • the first conductive layer 200 will not affect the luminous transmittance, so that the first conductive layer 200 will not be limited by the width and thickness, even if the cathode layer 400 is made of a transparent conductive material or is made of extremely thin thickness, It is also possible to reduce the resistance of the cathode layer 400 by providing the first conductive layer 200, thereby reducing the influence of IR Drop on the light emission uniformity of the display panel, and improving the display effect of the display panel.
  • the anode 510 may be a reflective anode to reflect light.
  • the light-emitting functional layer 600 directly contacts the anode 510 through the light-emitting opening area KB, and the light-emitting functional layer 600 directly contacts the cathode layer 400, so as to drive the light-emitting functional layer through the signal loaded on the anode 510 and the signal loaded on the cathode layer 400 600 glows.
  • the present disclosure includes but is not limited to this.
  • a hole transport layer and a hole injection layer may be further provided between the light-emitting function layer 600 and the anode 510, and film layers such as an electron transport layer and an electron injection layer may also be provided between the light-emitting function layer 600 and the cathode layer 400.
  • the cathode layer 400 generally has a whole-layer structure covering the base substrate 100.
  • the anode 510, the light-emitting function layer 600, and the cathode layer 400 are stacked to form an electroluminescent diode.
  • the orthographic projection of the anode 510 on the base substrate 100 may cover the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100.
  • the area of the orthographic projection of the anode 510 on the base substrate 100 is larger than the area of the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100.
  • the edge of the orthographic projection of the anode 510 on the base substrate 100 and the edge of the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100 can have a certain distance, and the distance can be designed and determined according to the actual application environment. There is no limitation here.
  • FIG. 3 is a schematic diagram of the stacked positional relationship of the light shielding metal layer 0310, the active semiconductor layer 0320, the second conductive layer 800, and the first conductive layer 200 described above.
  • the protruding portion of the data line DA-010 along the row direction F2 passes through at least one via hole (for example, via hole 341-010) of the first insulating layer 711 and the second insulating layer 712 It is electrically connected to the source region of the switching transistor T2 of the first color sub-pixel 010 in the active semiconductor layer 0320.
  • the protruding portion of the data line DA-020 in the row direction F2 passes through at least one of the via holes (for example, via holes 341-220) in the first insulating layer 711 and the second insulating layer 712 and the first in the active semiconductor layer 0320.
  • the source region of the switching transistor T2 of the two-color sub-pixel 020 is electrically connected.
  • the protruding portion of the data line DA-030 in the row direction F2 passes through at least one of the via holes (for example, via holes 341-030) in the first insulating layer 711 and the second insulating layer 712 and the first in the active semiconductor layer 0320.
  • the source region of the switching transistor T2 of the three-color sub-pixel 030 is electrically connected.
  • the present disclosure includes but is not limited to this.
  • the first electrode of the sensing transistor T3 is electrically connected to the second electrode of the driving transistor T1 through the first connection hole 0110.
  • the source region of the sensing transistor T3 in the active semiconductor layer 0320 passes through the first connection hole 0110 that penetrates the first insulating layer 711 and the second insulating layer 712 and the storage capacitor The first pole of Cst is electrically connected.
  • the drain region of the driving transistor T1 in the active semiconductor layer 0320 is electrically connected to the first electrode of the storage capacitor Cst through the fourth connection hole 0140 penetrating the first insulating layer 711 and the second insulating layer 712. In this way, the first electrode of the sensing transistor T3 and the second electrode of the driving transistor T1 can be electrically connected.
  • the first pole of the driving transistor T1 is electrically connected to the power line VDD through the second connection hole 0120.
  • the first conductive layer 200 may further include a plurality of fourth connection portions, and some of the sub-pixels respectively have a fourth connection portion.
  • the second color sub-pixel 020 has a fourth connection portion T1-020
  • the third color sub-pixel 030 has a fourth connection portion T1-030.
  • One end of the fourth connecting portion T1-030 is electrically connected to the corresponding second connection trace 0312 through the via 917 that penetrates the first insulating layer 711, the second insulating layer 712 and the third insulating layer 713, and the other end is electrically connected to the corresponding second connection trace 0312 through the first insulating layer 711, the second insulating layer 712 and the third insulating layer 713.
  • the second connection hole 0120 of the insulating layer 711 and the second insulating layer 712 is electrically connected to the source region of the active layer of the driving transistor.
  • the fourth connecting part T1-020 is arranged in the same way, and will not be repeated here.
  • the second electrode of the storage capacitor is also electrically connected to the light-shielding electrode through the third connection hole.
  • the capacitor electrode portion Cst-030 passes through the third connection hole 0130 and the light shielding electrode 0313- through the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713.
  • 030 is electrically connected to expand the capacitance value of the storage capacitor.
  • the capacitor electrode parts Cst-010 and Cst-020 have the same principle, and will not be repeated here.
  • the orthographic projection of the light-shielding electrode on the base substrate 100 may cover the area enclosed by the first connection via and the second connection via.
  • the cathode layer 400 is electrically connected to the auxiliary wiring 210 through the first via 310.
  • a signal line having a double-layer wiring structure may include auxiliary wiring 210.
  • the auxiliary wiring 210 is provided and the cathode layer 400 is electrically connected to the auxiliary wiring 210 to reduce the resistance of the cathode layer.
  • the influence of IR Drop on the light-emitting uniformity of the display panel can be reduced, and the display effect of the display panel can be improved.
  • the auxiliary wiring 210 may include: a first auxiliary wiring 211 located on the first conductive layer 200, The second auxiliary wiring 212 of the second conductive layer 800.
  • the first auxiliary wiring 211 extends along the column direction F1 of the sub-pixels, and the first auxiliary wiring 211 is arranged along the row direction F2 of the sub-pixels.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first auxiliary wiring 211 may be located in the gap between two adjacent sub-pixel columns, and the cathode layer 400 may pass through the second A via 310 is electrically connected to the first auxiliary wiring 211.
  • one auxiliary wiring 210 is located in the gap between the third color sub-pixel column and the first color sub-pixel column.
  • the first auxiliary wiring 211 may be located in the gap between two adjacent pixel unit columns.
  • the embodiments of the present disclosure include but are not limited to this.
  • At least two adjacent pixel unit columns are regarded as a first column group, and a first column group corresponds to a first column group.
  • the auxiliary wiring 211, the first auxiliary wiring 211 is located in the gap between two adjacent pixel unit columns in the corresponding first column group.
  • two adjacent pixel unit columns are used as a first column group.
  • the first pixel unit column and The second pixel unit column is the first first column group
  • the third pixel unit column and the fourth pixel unit column are the second first column group.
  • the first auxiliary wiring 211 corresponding to the first first column group is located in the gap between the first pixel unit column and the second pixel unit column, and the first auxiliary wiring 211 corresponding to the second first column group is Located in the gap between the third pixel unit column and the fourth pixel unit column.
  • one auxiliary wiring 210 may be provided for every gap between two adjacent pixel unit columns.
  • an auxiliary wiring 210 is provided in the gap between the first pixel unit column and the second pixel unit column, and the second pixel
  • An auxiliary wiring 210 is provided in the gap between the cell column and the third pixel cell column
  • an auxiliary wiring 210 is provided in the gap between the third pixel cell column and the fourth pixel cell column.
  • one detection line SL and one auxiliary wiring 210 are correspondingly arranged in the same gap between the same pixel unit column.
  • the first pixel unit column and the second pixel unit column can be the first first column group, and the third pixel unit column And the fourth pixel unit column is the second first column group.
  • the auxiliary wiring 210 and the detection line SL corresponding to the first first column group are located in the gap between the first pixel unit column and the second pixel unit column, and the auxiliary wiring 210 corresponding to the second first column group is located in the gap between the first pixel unit column and the second pixel unit column.
  • the sum detection line SL is located in the gap between the third pixel unit column and the fourth pixel unit column.
  • the display panel may further include: a plurality of first connection portions 520 arranged in the same layer as the anode 510 and insulated.
  • the first via 310 may include: a first sub-via 311 penetrating the pixel defining layer 330 and a second sub-via 312 penetrating the planarization layer 320; wherein the cathode layer 400 passes through the first sub-via 311 and the second sub-via 311.
  • a connecting portion 520 is electrically connected, and the first connecting portion 520 is electrically connected to the auxiliary wiring 210 through the second sub-via 312, for example, the first connecting portion 520 is electrically connected to the first auxiliary wiring 211 through the second sub-via 312 .
  • the planarization layer 320 achieves a better planarization effect, the planarization layer 320 is thicker than other insulating layers, which results in a thicker film between the cathode layer 400 and the auxiliary wiring 210.
  • a via hole may cause the cathode layer 400 and the auxiliary wiring 210 to be disconnected due to the fact that the cathode layer 400 cannot be electrically connected to the auxiliary wiring 210 due to the deepness of the via hole.
  • the auxiliary wiring 210 can be electrically connected to the first connection portion 520 through the second sub-via 312 first, and then the first The connecting portion 520 is electrically connected to the cathode layer 400 through the first sub-via 311, so that it is possible to avoid the situation that only one via is provided, which causes the actual electrical connection and disconnection.
  • the orthographic projection of the first sub-via 311 on the base substrate 100 and the orthographic projection of the second sub-via 312 on the base substrate 100 can be made.
  • the projections do not overlap at least partially.
  • the orthographic projection of the first sub-via 311 on the base substrate 100 and the orthographic projection of the second sub-via 312 on the base substrate 100 do not overlap. In this way, the problem that the cathode layer 400 and the auxiliary wiring 210 cannot be electrically connected due to the too deep via hole can be further avoided.
  • the first insulating layer 711 may have a second via 720, and the first auxiliary path
  • the wire 211 is electrically connected to the second auxiliary wiring 212 through a second via 720 penetrating the first insulating layer 711.
  • the cathode layer 400 can be further reduced.
  • the resistance Thereby, the influence of IR Drop on the light-emitting uniformity of the display panel can be further reduced, and the display effect of the display panel can be further improved.
  • the second auxiliary wiring 212 includes a plurality of first auxiliary portions 810 arranged at intervals; in the same auxiliary wiring 210 , The first auxiliary wiring 211 is electrically connected to the corresponding first auxiliary portion 810 through the second via 720. Further, in the same auxiliary wiring 210, the orthographic projection of the first auxiliary wiring 211 on the base substrate 100 and the orthographic projection of the corresponding first auxiliary portion 810 on the base substrate 100 have an overlapping area.
  • the orthographic projection of the first auxiliary wiring 211 on the base substrate 100 covers the orthographic projection of the corresponding first auxiliary portion 810 on the base substrate 100.
  • the first auxiliary part 810 can also be arranged between the sub-pixel columns, so as to prevent the first auxiliary part 810 from affecting the light-emitting display.
  • the orthographic projection of the first auxiliary part 810 on the base substrate 100 covers the corresponding second via 720 in the substrate Orthographic projection of the substrate 100.
  • the second via 720 can also be arranged between the sub-pixel columns, so as to avoid affecting the light-emitting display.
  • one first auxiliary wiring 211 may correspond to a plurality of first auxiliary parts 810.
  • the orthographic projection of a first auxiliary part 810 on the base substrate 100 is located between the first gate line G1 and the second gate line G2 electrically connected to the same row of sub-pixels in the orthographic projection of the base substrate 100.
  • one sub-pixel row may correspond to one first auxiliary part 810. That is, each row of sub-pixels can correspond to one first auxiliary part 810 one by one.
  • a first auxiliary part 810 may be provided between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.
  • first auxiliary parts 810 electrically connected to the same first auxiliary wiring 211
  • sub-pixel rows separated by at least one sub-pixel row correspond to one first auxiliary part 810.
  • the sub-pixel rows separated by one sub-pixel row can correspond to one first auxiliary portion 810, that is, the odd-numbered sub-pixel rows can correspond to one first auxiliary portion 810, or the even-numbered sub-pixel rows can be set to correspond to one first auxiliary portion 810.
  • the row corresponds to one first auxiliary part 810.
  • the sub-pixel rows separated by eleven sub-pixel rows may correspond to one first auxiliary part 810, that is, the first sub-pixel row may correspond to one first auxiliary part 810, and the Thirteen sub-pixel rows correspond to one first auxiliary portion 810, so that the twenty-fifth sub-pixel row corresponds to one first auxiliary portion 810, and the rest is deduced by analogy, which is not limited here.
  • the present disclosure includes but is not limited to this.
  • the first auxiliary portion 810 extends along the column direction F1. Further, for the first auxiliary part 810 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the first auxiliary part 810 is closer to the second gate line G2.
  • the part of the first auxiliary wiring 211 that overlaps with the orthographic projection of the first auxiliary portion 810 extends along the sub-pixel row direction.
  • the width is the first width W1
  • the width of the portion of the first auxiliary wiring 211 that overlaps with the orthographic projection of the first gate line G1 along the sub-pixel row direction is the second width W2.
  • the first width W1 is greater than the second width W2.
  • the part of the first auxiliary wiring 211 with the second width W2 can be made close to the second connection hole 0120. In this way, the part of the first auxiliary wiring 211 close to the second connection hole 0120 can be avoided.
  • each first auxiliary portion 810 can pass through at least four second via holes 720 and the corresponding first auxiliary portion.
  • the line 211 is electrically connected.
  • each first auxiliary part 810 may be electrically connected to the corresponding first auxiliary wiring 211 through four, five, six or more second via holes 720.
  • the electrical connection with the first auxiliary wiring 211 further reduces the risk of disconnection between the first auxiliary portion 810 and the first auxiliary wiring 211.
  • the present disclosure includes but is not limited to this.
  • one auxiliary trace 210 may correspond to multiple first vias 310, and one first via 310 corresponds to one sub-pixel row. ;
  • the orthographic projection of the first sub-via 311 on the base substrate 100 is in line with the second gate line G2
  • the orthographic projection of the base substrate 100 has an overlapping area; and the orthographic projection of the second sub-via 312 on the base substrate 100 is located between the orthographic projections of the first grid line G1 and the second grid line G2 on the base substrate 100.
  • the orthographic projection of the second sub-via 312 on the base substrate 100 is located between the orthographic projection of the second gate line G2 on the base substrate 100 and the orthographic projection of all the second vias 720 on the base substrate 100.
  • a plurality of second via holes 720 corresponding to the same first auxiliary wiring 211 can be arranged in the same row along the column direction F1. In a straight line.
  • the signal line with a double-layer wiring structure may include a detection line SL.
  • the detection line SL as a double-layer wiring structure electrically connected to each other, the resistance of the detection line SL can be reduced, thereby reducing the influence of IR Drop on the light emission uniformity of the display panel, and improving the display effect of the display panel.
  • the detection line SL may include: a first detection trace 221 located on the first conductive layer 200, and a first detection trace 221 located on the second conductive layer 800 of the second detection trace 222.
  • the first insulating layer 711 has a third via 730, and the first detection trace 221 is electrically connected to the second detection trace 222 through the third via 730 penetrating the first insulation layer 711.
  • the first detection trace 221 extends along the column direction F1 of the sub-pixel, and the first detection trace 221 extends along the sub-pixel's column direction F1. Arranged in the row direction F2.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first conductive layer 200 may further include: a plurality of second connection portions (ie, capacitor electrode portions Cst-010, Cst- 020, Cst-030), and the planarization layer 320 further includes a fifth connection hole 0150, and the fifth connection hole 0150 exposes the second connection portion (ie, the capacitor electrode portions Cst-010, Cst-020, Cst-030) Part; the anode 510 is electrically connected to the second connection portion (ie, the capacitor electrode portions Cst-010, Cst-020, Cst-030) through the fifth connection hole 0150.
  • second connection portion ie, capacitor electrode portions Cst-010, Cst- 020, Cst-030
  • the planarization layer 320 further includes a fifth connection hole 0150
  • the fifth connection hole 0150 exposes the second connection portion (ie, the capacitor electrode portions Cst-010, Cst-020, Cst-030) Part
  • the planarization layer 320 has a fifth connection hole 0150, and each sub-pixel corresponds to a fifth connection hole 0150.
  • the anode 510 in the first color sub-pixel 010 is electrically connected to the capacitor electrode portion Cst-010 through the fifth connection hole 0150
  • the anode 510 in the second color sub-pixel 020 is electrically connected to the capacitor electrode portion Cst-010 through the fifth connection hole 0150.
  • 020 is electrically connected
  • the anode 510 in the third color sub-pixel 030 is electrically connected to the capacitor electrode portion Cst-030 through the fifth connection hole 0150.
  • the second detection trace 222 may further include: a plurality of second auxiliary portions 820 arranged at intervals; wherein, In the same detection line SL, the first detection trace 221 is electrically connected to the corresponding second auxiliary portion 820 through the third via 730, respectively.
  • one first detection wire 221 corresponds to at least one second auxiliary portion 820, and the first detection wire 221 is electrically connected to the corresponding second auxiliary portion 820 through the third via 730.
  • the orthographic projection of the first detection trace 221 on the base substrate 100 and the corresponding second auxiliary The portion 820 has an overlapping area on the orthographic projection of the base substrate 100. Furthermore, in the same detection line SL, the orthographic projection of the first detection trace 221 on the base substrate 100 covers the orthographic projection of the corresponding second auxiliary part 820 on the base substrate 100. In this way, the influence of the second auxiliary part 820 on the display can be avoided.
  • the orthographic projection of the first connecting portion 520 on the base substrate 100 and the third via 730 on the front of the base substrate 100 do not overlap.
  • one first detection trace 221 can be made to correspond to multiple second auxiliary parts 820, and one second auxiliary part 820
  • the orthographic projection on the base substrate 100 is located between the orthographic projections of the base substrate 100 and the first gate line G1 and the second gate line G2 that are electrically connected to the same row of sub-pixels.
  • one sub-pixel row may correspond to one second auxiliary part 820. That is, each row of sub-pixels can correspond to one second auxiliary part 820 one by one.
  • a second auxiliary part 820 may be provided between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.
  • sub-pixel rows separated by at least one sub-pixel row may correspond to one second auxiliary part 820.
  • the sub-pixel rows separated by one sub-pixel row can correspond to one second auxiliary portion 820, that is, the odd-numbered sub-pixel rows can correspond to one second auxiliary portion 820, or the even-numbered sub-pixel rows can be set to correspond to one second auxiliary portion 820.
  • the row corresponds to one second auxiliary part 820.
  • the sub-pixel rows separated by eleven sub-pixel rows can correspond to one second auxiliary portion 820, that is, the first sub-pixel row can correspond to one second auxiliary portion 820, and the first sub-pixel row can correspond to one second auxiliary portion 820.
  • Thirteen sub-pixel rows correspond to one second auxiliary portion 820, so that the twenty-fifth sub-pixel row corresponds to one second auxiliary portion 820, and the rest is deduced by analogy, which is not limited here.
  • the present disclosure includes but is not limited to this.
  • the second auxiliary portion 820 extends along the column direction F1. Further, for the second auxiliary part 820 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the second auxiliary part 820 is closer to the second gate line G2.
  • each second auxiliary portion 820 can pass through at least three third vias 730 and the corresponding first detection path.
  • the line 221 is electrically connected.
  • each second auxiliary part 820 may be electrically connected to the corresponding first detection trace 221 through three, four, five or more third via holes 730.
  • the second auxiliary part 820 can still be connected to the first detection trace 221 through other contact points.
  • the connection between the first detection wiring 221 further reduces the risk of disconnection between the second auxiliary part 820 and the first detection wiring 221.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the second auxiliary part 820 on the base substrate 100 covers the corresponding third via 730 on the substrate Orthographic projection of the substrate 100.
  • the third via 730 can also be arranged between the sub-pixel columns, so as to avoid affecting the light-emitting display.
  • the third connection holes 0130 in a row of sub-pixels are arranged on a straight line along the row direction F2.
  • the four connecting holes 0140 are also arranged in a straight line along the row direction F2, and for the fourth via 720, the first gate line G1, and the second gate line G2 corresponding to the same row of sub-pixels, the third via 730 is on the base substrate
  • the orthographic projection of 100 is located between the line where the third connecting hole 0130 is located along the row direction F1 and the line where the fourth connecting hole 0140 is located along the row direction F1.
  • a plurality of third via holes 730 corresponding to the same first detection trace 221 can be arranged in the same row along the column direction F1. In a straight line.
  • two adjacent pixel unit columns are regarded as a second column group, and the sub-pixels in each second column group
  • a first detection wire 221 is electrically connected.
  • the first pixel unit column and the second pixel unit column are the first second column group
  • the third pixel unit column and The fourth pixel unit column is the second second column group.
  • the first detection trace 221 corresponding to the first second column group is located in the gap between the first pixel unit column and the second pixel unit column, and each sub-pixel in the first second column group
  • the sensing transistors are all electrically connected to the corresponding first detection wiring 221.
  • the first detection trace 221 corresponding to the second second column group is located in the gap between the third pixel unit column and the fourth pixel unit column, and each sub-pixel in the second second column group
  • the sensing transistors are all electrically connected to the corresponding first detection wiring 221. The rest of the settings can be deduced by analogy, so I won’t repeat them here.
  • each first detection trace 221 is correspondingly electrically connected to a plurality of first connection traces 0311, and for the same electrical connection
  • One first connection trace 0311 of the first detection trace 221 and each row of sub-pixels in the second column group corresponds to one first connection trace 0311 one-to-one.
  • each row of sub-pixels in the second column group is electrically connected to the first detection wiring 221 through the corresponding first connection wiring 0311.
  • the first detection wiring 221 is electrically connected to the corresponding first connection wiring 0311 through a via 911 penetrating the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713.
  • the first conductive layer 200 may further include: a plurality of third connection portions, each of which has a third connection portion in each sub-pixel.
  • the first color sub-pixel 010 has a third connection portion T3-010
  • the second color sub-pixel 020 has a third connection portion T3-020
  • the third color sub-pixel 030 has a third connection portion T3-030.
  • one end of the third connecting portion T3-030 is electrically connected to the drain region of the active semiconductor layer 0320 as a sensing transistor through the via 912 penetrating the first insulating layer 711 and the second insulating layer 712, and the other end penetrates the first insulating layer 712.
  • the vias 913 of an insulating layer 711, the second insulating layer 712, and the third insulating layer 713 are electrically connected to the corresponding first connection trace 0311.
  • One end of the third connecting portion T3-010 is electrically connected to the drain region of the sensing transistor in the active semiconductor layer through a via hole penetrating the first insulating layer and the second insulating layer, and the other end penetrates the first insulating layer and the second insulating layer.
  • the insulating layer and the via holes of the third insulating layer are electrically connected to the corresponding first connection traces.
  • One end of the third connecting portion T3-020 is electrically connected to the drain region of the active semiconductor layer serving as the sensing transistor through a via hole penetrating the first insulating layer and the second insulating layer, and the other end penetrates the first insulating layer and the second insulating layer.
  • the insulating layer and the via holes of the third insulating layer are electrically connected to the corresponding first connection traces.
  • FIG. 4b only takes the third connecting portion T3-030 as an example for description, and the implementation manners of the third connecting portion T3-010 and the third connecting portion T3-020 can be deduced in the same way, and will not be repeated here.
  • one first detection wiring 221 and one first auxiliary wiring 211 can be both arranged in the gap between the same pixel unit column .
  • the first detection wiring 221 for transmitting the detection signal and the first auxiliary wiring 211 for transmitting the fixed voltage are arranged in the same gap, so that the influence of the signal on the detection signal transmitted by the first detection wiring 221 can be reduced, and the first detection wiring 221 can be improved.
  • the accuracy of the signal transmitted by the trace 221 is detected.
  • the orthographic projection of the first sub-via 311 corresponding to the first auxiliary wiring 211 on the base substrate 100 and the orthographic projection of the first detection wiring 221 on the base substrate 100 also have an overlapping area.
  • the orthographic projection of the first connecting portion 520 on the base substrate 100 also overlaps with the orthographic projection of the first detection trace 221 on the base substrate 100, and the first connecting portion 520 is on the front of the base substrate 100.
  • the projection also has an overlapping area with the orthographic projection of the first auxiliary wiring 211 on the base substrate 100.
  • one second auxiliary part 820 and one first auxiliary part 810 may correspond to the same sub-pixel row. This can simplify the design of the second auxiliary part 820 and the first auxiliary part 810 and reduce the design difficulty.
  • the first auxiliary part 810 and the second auxiliary part 820 corresponding to the same row of sub-pixels can be used.
  • the via 720 and the third via 730 of the second auxiliary part 820 are arranged in a staggered arrangement.
  • the geometric center of the second via 720 corresponds to the gap between the two third vias 730.
  • the portion of the first detection trace 221 that overlaps the orthographic projection of the second auxiliary portion 820 is along the sub-pixel row direction F2.
  • the width of is the third width W3, and the width of the portion of the first detection trace 221 that overlaps with the orthographic projection of the first gate line G1 along the sub-pixel row direction F2 is the fourth width W4.
  • the third width W3 is greater than the fourth width W4. In this way, the area of the sub-pixel closest to the first detection wiring 221 can be increased by making the first detection wiring 221 avoid.
  • the portion of the first detection trace 221 with the fourth width W4 may be close to the second connection hole 0120. In this way, the part of the first detection trace 221 close to the second connection hole 0120 can be avoided.
  • the signal line with a double-layer wiring structure may include a power line VDD.
  • the resistance of the power supply line VDD can be reduced, thereby reducing the influence of IR Drop on the light-emitting uniformity of the display panel and improving the display effect of the display panel.
  • the power line includes: a first power trace 231 located on the first conductive layer 200, and a first power trace 231 located on the second conductive layer 800 The second power trace 232.
  • the first insulating layer 711 has a fourth via 740, and the first power trace 231 is electrically connected to the second power trace 232 through the fourth via 740 penetrating the first insulation layer 711.
  • the first power trace 231 extends along the column direction F1 of the sub-pixel, and the first power trace 231 extends along the sub-pixel's column direction F1. Arranged in the row direction F2.
  • the embodiments of the present disclosure include but are not limited to this.
  • each first power trace 231 is correspondingly electrically connected to a plurality of second connection traces 0312.
  • the first pixel unit column is electrically connected to a first power trace 231
  • the last pixel unit column is electrically connected to a first power trace 231.
  • two adjacent pixel unit columns are regarded as a third column group, and each sub-pixel in the third column group corresponds to A first power trace 231 is electrically connected.
  • the second pixel unit column and the third pixel unit column are the first third column group
  • the fourth pixel unit column and The fifth pixel unit column is the second and third column group.
  • the first power supply wiring 231 corresponding to the first third column group is located in the gap between the second pixel unit column and the third pixel unit column, and each sub-pixel in the first third column group
  • the driving transistors are all electrically connected to the corresponding first power traces 231.
  • the first power trace 231 corresponding to the second third column group is located in the gap between the fourth pixel unit column and the fifth pixel unit column, and each sub-pixel in the second third column group
  • the driving transistors are all electrically connected to the corresponding first power traces 231. The rest of the settings can be deduced by analogy, so I won’t repeat them here.
  • FIGS. 2b, 3, 4a, 4c, and 5d there is at least one column of pixel units between the first power trace 231 and the first auxiliary trace 211 .
  • a column of pixel units may be spaced between the first power wiring 231 and the first auxiliary wiring 211. It is also possible that the first power wiring 231 and the first auxiliary wiring 211 are separated by two, three, four or more columns of pixel units, which is not limited herein.
  • each first power trace 231 is correspondingly electrically connected to a plurality of second connection traces 0312, and the electrical connection is the same One second connection trace 0312 of the first power trace 231, and each row of sub-pixels in the third column group corresponds to one second connection trace 0312 one-to-one.
  • each row of sub-pixels in the third column group is electrically connected to the first power wiring 231 through the corresponding second connecting wiring 0312.
  • the first power trace 231 is electrically connected to the corresponding second connection trace 0312 through a via 916 penetrating the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713.
  • the second power trace 232 may include: a plurality of third auxiliary portions 830 arranged at intervals; wherein, the same In the power supply line VDD, the first power supply line 231 is electrically connected to the corresponding third auxiliary part 830 through the fourth via 740 respectively.
  • one first power trace 231 corresponds to at least one third auxiliary portion 830, and the first power trace 231 is electrically connected to the corresponding third auxiliary portion 830 through the fourth via 740.
  • the orthographic projection of the first power trace 231 on the base substrate 100 and the corresponding third auxiliary portion 830 on the front of the base substrate 100 The projection has overlapping areas. Furthermore, the orthographic projection of the first power trace 231 on the base substrate 100 covers the orthographic projection of the corresponding third auxiliary portion 830 on the base substrate 100. This can prevent the third auxiliary part 830 from affecting the display.
  • one first power trace 231 may correspond to multiple third auxiliary parts 830, and one third auxiliary part 830
  • the orthographic projection on the base substrate 100 is located between the orthographic projections of the base substrate 100 and the first gate line G1 and the second gate line G2 that are electrically connected to the same row of sub-pixels.
  • one sub-pixel row may correspond to one third auxiliary part 830. That is, each row of sub-pixels can correspond to one third auxiliary part 830 one by one.
  • a third auxiliary part 830 may be provided between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.
  • the sub-pixel rows separated by at least one sub-pixel row may correspond to one third auxiliary part 830.
  • sub-pixel rows separated by one sub-pixel row can correspond to one third auxiliary portion 830, that is, odd-numbered sub-pixel rows can correspond to one third auxiliary portion 830, or even-numbered sub-pixel rows can be set to correspond to one third auxiliary portion 830.
  • the row corresponds to a third auxiliary part 830.
  • the sub-pixel rows separated by eleven sub-pixel rows may correspond to one third auxiliary part 830, that is, the first sub-pixel row may correspond to one third auxiliary part 830, and the first sub-pixel row may correspond to one third auxiliary part 830.
  • Thirteen sub-pixel rows correspond to one third auxiliary part 830, so that the twenty-fifth sub-pixel row corresponds to one third auxiliary part 830, and the rest are deduced by analogy, which is not limited here.
  • the present disclosure includes but is not limited to this.
  • the third auxiliary portion 830 extends along the column direction F1. Further, for the third auxiliary part 830 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the third auxiliary part 830 is closer to the second gate line G2.
  • each third auxiliary part 830 can pass through at least four fourth via holes 740 to communicate with the corresponding first power source.
  • the line 231 is electrically connected.
  • each third auxiliary part 830 may be electrically connected to the corresponding first power trace 231 through three, four, five or more fourth via holes 740.
  • the third auxiliary part 830 can still be connected to the first power trace 231 through other contact points.
  • the connection between the first power line 231 further reduces the risk of disconnection between the third auxiliary part 830 and the first power line 231.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the third auxiliary part 830 on the base substrate 100 covers the corresponding fourth via 740 in the substrate Orthographic projection of the substrate 100.
  • the fourth via 740 can also be arranged between the sub-pixel columns, so as to avoid affecting the light-emitting display.
  • the first The orthographic projection of the four vias 740 on the base substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 on the base substrate 100.
  • a plurality of fourth vias 740 corresponding to the same first power trace 231 can be arranged in the same row along the column direction F1. In a straight line.
  • the first connection hole 0110 and the third auxiliary portion 830 corresponding to the same row of sub-pixels can be used.
  • a corresponding fourth via 740 and first connection hole 0110 are arranged in a straight line along the sub-pixel row direction.
  • one third auxiliary part 830 and one first auxiliary part 810 may correspond to the same sub-pixel row. This can simplify the design of the third auxiliary part 830 and the first auxiliary part 810 and reduce the design difficulty.
  • one third auxiliary part 830, one second auxiliary part 820, and one first auxiliary part 810 can correspond to the same sub-pixel row. This can further simplify the design of the third auxiliary part 830, the second auxiliary part 820, and the first auxiliary part 810, and reduce the design difficulty.
  • the portion of the first power trace 231 that overlaps the orthographic projection of the third auxiliary portion 830 is along the sub-pixel row direction.
  • the width of F2 is the fifth width W5
  • the width of the portion of the first power trace 231 that overlaps the orthographic projection of the first gate line G1 along the sub-pixel row direction F2 is the sixth width W6.
  • the fifth width W5 is greater than the sixth width W6.
  • the portion of the first power trace 231 with the sixth width W6 can be made close to the second connection hole 0120. In this way, the part of the first power trace 231 close to the second connection hole 0120 can be avoided.
  • first width, second width, third width, fourth width, fifth width, and sixth width can be designed and determined according to the actual application environment, which is not limited herein.
  • the above-mentioned features are not completely the same, and there may be some deviations. Therefore, the same relationship between the above-mentioned features as long as the above-mentioned conditions are roughly met. That is, all belong to the protection scope of the present disclosure.
  • the above-mentioned sameness may be the same as allowed within the allowable error range.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
  • the display device may be a full-screen mobile phone as shown in FIG. 6.
  • the display device can also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the display panel and the display device provided by the embodiments of the present disclosure can reduce the resistance of the signal line provided with the double-layer wiring structure by providing a double-layer wiring structure electrically connected to each other, thereby reducing the luminescence of the display panel by IR Drop.
  • the influence of uniformity improves the display effect of the display panel.

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Abstract

本公开实施例提供的显示面板及显示装置，包括：衬底基板；复数个像素单元，多个栅线组。至少一个像素单元包括多个子像素，至少一个子像素包括感测晶体管和驱动晶体管。各栅线组包括位于像素单元两侧的第一栅线和第二栅线；针对同一行子像素对应的第一栅线和第二栅线，感测晶体管位于子像素更靠近第二栅线的一侧，驱动晶体管位于子像素更靠近第一栅线的一侧；针对同一行中相互靠近且不位于同一像素单元中的两个子像素，两个子像素的第一连接孔和第二连接孔围成的区域至少有一条信号线具有双层走线结构，且同一信号线的双层走线结构相互电连接。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示面板应用研究领域的热点之一，受到了广泛关注。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板；
复数个像素单元，阵列排布于所述衬底基板上，且至少一个所述像素单元包括：多个子像素，至少一个所述子像素包括：感测晶体管和驱动晶体管；
多个栅线组，各所述栅线组包括位于所述像素单元两侧的第一栅线和第二栅线；
针对同一行所述子像素对应的所述第一栅线和所述第二栅线，所述感测晶体管位于所述子像素更靠近所述第二栅线的一侧，所述驱动晶体管位于所述子像素更靠近所述第一栅线的一侧；
同一所述子像素中，所述感测晶体管的第一极通过第一连接孔与驱动晶体管的第二极电连接，所述驱动晶体管的第一极通过第二连接孔与电源线电连接；
针对同一行中相互靠近且不位于同一像素单元中的两个子像素，所述两个子像素的所述第一连接孔和所述第二连接孔围成的区域至少有一条信号线具有双层走线结构，且同一所述信号线的所述双层走线结构相互电连接。
可选地，在本公开实施例中，所述子像素还包括：层叠设置的阳极、发光功能层以及阴极层；其中，同一子像素中，所述驱动晶体管的第二极与所述阳极电连接；
所述显示面板还包括：
多条辅助走线；其中，所述辅助走线位于相邻两个子像素列之间的间隙中，且所述阴极层通过第一过孔与所述辅助走线电连接；
多条检测线；其中，所述检测线位于相邻两个子像素列之间的间隙中，且所述检测线与所述辅助走线绝缘设置，所述检测线与所述感测晶体管的第二极电连接；
所述信号线包括：所述辅助走线、所述检测线以及所述电源线中的至少一条。
可选地，在本公开实施例中，所述显示面板还包括：
像素界定层，位于所述阳极所在层与所述发光功能层之间；
平坦化层，位于所述像素界定层面向所述衬底基板一侧；
第一导电层；位于所述平坦化层面向所述衬底基板一侧；
第一绝缘层，位于所述第一导电层面向所述衬底基板一侧；
第二导电层，位于所述第一绝缘层面向所述衬底基板一侧；
所述辅助走线包括：
第一辅助走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
第二辅助走线，位于所述第二导电层；
所述第一辅助走线通过贯穿所述第一绝缘层的第二过孔与所述第二辅助走线电连接。
可选地，在本公开实施例中，所述第二辅助走线包括多个间隔设置的第一辅助部；其中，同一所述辅助走线中，所述第一辅助走线分别通过所述第二过孔与对应的所述第一辅助部电连接。
可选地，在本公开实施例中，同一所述辅助走线中，所述第一辅助走线在所述衬底基板的正投影与对应的所述第一辅助部在所述衬底基板的正投影 具有交叠区域。
可选地，在本公开实施例中，所述第一辅助部在所述衬底基板的正投影覆盖对应的所述第二过孔在所述衬底基板的正投影。
可选地，在本公开实施例中，针对同一所述第一辅助走线电连接的多个第一辅助部，一个子像素行对应一个所述第一辅助部。
可选地，在本公开实施例中，针对同一所述第一辅助走线电连接的多个第一辅助部，间隔至少一个子像素行的子像素行对应一个所述第一辅助部。
可选地，在本公开实施例中，每个所述第一辅助部通过至少四个第二过孔与对应的第一辅助走线电连接。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一辅助部和所述第一栅线和所述第二栅线，所述第一辅助部更靠近所述第二栅线。
可选地，在本公开实施例中，所述第一过孔在所述衬底基板的正投影与所述阳极在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述显示面板还包括：
多个第一连接部，与所述阳极同层且绝缘；
所述第一过孔包括：贯穿所述像素界定层的第一子过孔和贯穿所述平坦化层的第二子过孔；
所述阴极层通过所述第一子过孔与所述第一连接部电连接，所述第一连接部通过所述第二子过孔与所述辅助走线电连接。
可选地，在本公开实施例中，所述第一子过孔在所述衬底基板的正投影与所述第二子过孔在所述衬底基板的正投影至少部分不交叠。
可选地，在本公开实施例中，一条所述辅助走线对应多个第一过孔，一个第一过孔对应一个子像素行；
针对同一行子像素对应的所述第一过孔和所述第一栅线和所述第二栅线，所述第一子过孔在所述衬底基板的正投影与所述第二栅线在所述衬底基板的正投影具有交叠区域；且所述第二子过孔在所述衬底基板的正投影位于所述第一栅线和所述第二栅线在所述衬底基板的正投影之间。
可选地，在本公开实施例中，针对同一行子像素对应的所述第二子过孔、所述第二过孔以及所述第二栅线，所述第二子过孔在所述衬底基板的正投影位于所述第二栅线在所述衬底基板的正投影与所有所述第二过孔在所述衬底基板的正投影之间。
可选地，在本公开实施例中，与所述第一辅助部的正投影具有交叠的第一辅助走线的部分沿所述子像素行方向的宽度为第一宽度，与所述第一栅线的正投影具有交叠的第一辅助走线的部分沿所述子像素行方向的宽度为第二宽度；
所述第一宽度大于所述第二宽度。
可选地，在本公开实施例中，具有所述第二宽度的第一辅助走线的部分靠近所述第二连接孔。
可选地，在本公开实施例中，所述第一辅助走线位于相邻的两个像素单元列之间的间隙中。
可选地，在本公开实施例中，以相邻的至少两个像素单元列为一个第一列组，一个所述第一列组对应一条第一辅助走线，所述第一辅助走线位于对应的所述第一列组中相邻的两个像素单元列之间的间隙中。
可选地，在本公开实施例中，所述显示面板还包括：
第二绝缘层，位于所述第二导电层面向所述衬底基板一侧；
有源半导体层，位于所述第二绝缘层面向所述衬底基板一侧；
第三绝缘层，位于所述有源半导体层面向所述衬底基板一侧；
遮光金属层，位于所述第三绝缘层面向所述衬底基板一侧；
所述遮光金属层包括：至少一个遮光电极；其中，一个所述遮光电极位于一个所述子像素中；
同一所述子像素中，所述遮光电极在所述衬底基板的正投影至少覆盖所述驱动晶体管的沟道区在所述衬底基板的正投影。
可选地，在本公开实施例中，至少一个所述子像素还包括：存储电容；其中，所述存储电容的第一极与所述驱动晶体管的栅极电连接，所述存储电 容的第二极与所述驱动晶体管的第二极电连接；
所述存储电容的第二极还通过第三连接孔与所述遮光电极电连接。
可选地，在本公开实施例中，所述检测线包括：
第一检测走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
第二检测走线，位于所述第二导电层；
所述第一检测走线通过贯穿所述第一绝缘层的第三过孔与所述第二检测走线电连接。
可选地，在本公开实施例中，所述第二检测走线包括多个间隔设置的第二辅助部；其中，同一所述检测线中，所述第一检测走线分别通过所述第三过孔与对应的所述第二辅助部电连接。
可选地，在本公开实施例中，同一所述检测线中，所述第一检测走线在所述衬底基板的正投影与对应的所述第二辅助部在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述第二辅助部在所述衬底基板的正投影覆盖对应的所述第三过孔在所述衬底基板的正投影。
可选地，在本公开实施例中，针对同一所述第一检测走线电连接的多个第二辅助部，一个子像素行对应一个所述第二辅助部。
可选地，在本公开实施例中，针对同一所述第一检测走线电连接的多个第二辅助部，间隔至少一个子像素行的子像素行对应一个所述第二辅助部。
可选地，在本公开实施例中，一个所述第二辅助部和一个所述第一辅助部对应同一个子像素行。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一辅助部和所述第二辅助部，所述第一辅助部的第二过孔与所述第二辅助部的第三过孔错位排列。
可选地，在本公开实施例中，每个所述第二辅助部通过至少三个第三过孔与对应的第一检测走线电连接。
可选地，在本公开实施例中，针对同一行子像素对应的所述第二辅助部 和所述第一栅线和所述第二栅线，所述第二辅助部更靠近所述第二栅线。
可选地，在本公开实施例中，与所述第二辅助部的正投影具有交叠的第一检测走线的部分沿所述子像素行方向的宽度为第三宽度，与所述第一栅线的正投影具有交叠的第一检测走线的部分沿所述子像素行方向的宽度为第四宽度；
所述第三宽度大于所述第四宽度。
可选地，在本公开实施例中，具有所述第四宽度的第一检测走线的部分靠近所述第二连接孔。
可选地，在本公开实施例中，针对设置于同一像素单元列之间的间隙中的所述第一检测走线与所述第一辅助走线，所述第一辅助走线对应的所述第一子过孔在所述衬底基板的正投影还与所述第一检测走线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，一条所述第一检测走线与一条所述第一辅助走线均设置于同一像素单元列之间的间隙中。
可选地，在本公开实施例中，所述电源线包括：
第一电源走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
第二电源走线，位于所述第二导电层；
所述第一电源走线通过贯穿所述第一绝缘层的第四过孔与所述第二电源走线电连接。
可选地，在本公开实施例中，所述第一电源走线与所述第一辅助走线之间间隔至少一列像素单元。
可选地，在本公开实施例中，所述第二电源走线包括多个间隔设置的第三辅助部；其中，同一所述电源线中，所述第一电源走线分别通过所述第四过孔与对应的所述第三辅助部电连接。
可选地，在本公开实施例中，同一所述电源线中，所述第一电源走线在所述衬底基板的正投影与对应的所述第三辅助部在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述第三辅助部在所述衬底基板的正投影覆盖对应的所述第四过孔在所述衬底基板的正投影。
可选地，在本公开实施例中，每个所述第三辅助部通过至少四个第四过孔与对应的第一电源走线电连接。
可选地，在本公开实施例中，针对同一所述第一电源走线电连接的多个第三辅助部，一个子像素行对应一个所述第三辅助部。
可选地，在本公开实施例中，针对同一所述第一电源走线电连接的多个第三辅助部，间隔至少一个子像素行的子像素行对应一个所述第三辅助部。
可选地，在本公开实施例中，一个所述第三辅助部和一个所述第一辅助部对应同一个子像素行。
可选地，在本公开实施例中，针对同一行子像素对应的所述第三辅助部和所述第一栅线和所述第二栅线，所述第三辅助部更靠近所述第二栅线。
可选地，在本公开实施例中，与所述第三辅助部的正投影具有交叠的第一电源走线的部分沿所述子像素行方向的宽度为第五宽度，与所述第一栅线的正投影具有交叠的第一电源走线的部分沿所述子像素行方向的宽度为第六宽度；
所述第五宽度大于所述第六宽度。
可选地，在本公开实施例中，具有所述第六宽度的第一电源走线的部分靠近所述第二连接孔。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一连接孔和所述第三辅助部，所述第三辅助部对应的一个第四过孔与所述第一连接孔沿子像素行方向排列于一条直线上。
本公开实施例还提供的显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的像素驱动电路的结构示意图；
图2a为本公开实施例提供的显示面板的俯视结构示意图；
图2b为本公开实施例提供的一些显示面板的俯视结构示意图；
图3为本公开实施例提供的又一些显示面板的布局结构示意图；
图4a为图3所示的显示面板沿AA’方向的剖视结构示意图；
图4b为图3所示的显示面板沿BB’方向的剖视结构示意图；
图4c为图3所示的显示面板沿CC’方向的剖视结构示意图；
图5a为图3所示的显示面板中遮光金属层的结构示意图；
图5b为图3所示的显示面板中有源半导体层的结构示意图；
图5c为图3所示的显示面板中第二导电层的结构示意图；
图5d为图3所示的显示面板中第一导电层的结构示意图；
图6为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
电致发光二极管一般属于电流驱动型，需要稳定的电流来驱动其发光。并且显示面板中采用像素驱动电路来驱动电致发光二极管发光。其中，电致发光二极管包括依次层叠设置于衬底基板上的阳极、发光功能层以及阴极层。像素驱动电路与阳极电连接，以向阳极加载信号。并且，向阴极层加载低电压信号VSS，以使电致发光二极管发光。然而，在实际应用中，顶发射型的电致发光二极管的发光面在阴极层这侧，为了增加阴极的透过率，一般使阴极采用透明导电材料或把阴极做的非常薄，这就导致阴极的方块电阻比较大。这样在显示面板工作时，流过阴极的电流则会较大，阴极上的电压降(IR-Drop)就较大，从而导致显示面板不同位置处的发光亮度不均匀的问题。
本公开实施例提供的显示面板，可以包括：衬底基板；阵列排布于衬底基板上的复数个像素单元，多个栅线组。其中，至少一个像素单元包括：多个子像素，至少一个子像素包括：感测晶体管和驱动晶体管。各栅线组包括位于像素单元两侧的第一栅线和第二栅线；针对同一行子像素对应的第一栅线和第二栅线，感测晶体管位于子像素更靠近第二栅线的一侧，驱动晶体管位于子像素更靠近第一栅线的一侧；同一子像素中，感测晶体管的第一极通过第一连接孔与驱动晶体管的第二极电连接，驱动晶体管的第一极通过第二连接孔与电源线电连接；针对同一行中相互靠近且不位于同一像素单元中的两个子像素，两个子像素的第一连接孔和第二连接孔围成的区域至少有一条信号线具有双层走线结构，且同一信号线的双层走线结构相互电连接。这样通过设置相互电连接的双层走线结构，可以使设置有双层走线结构的信号线的电阻降低，从而可以降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
在具体实施时，在本公开实施例中，至少一个子像素可以包括像素驱动电路和电致发光二极管L。下面结合像素驱动电路的结构对本公开实施例提供的显示面板进行描述。
如图1所示，像素驱动电路一般包括：驱动晶体管T1、开关晶体管T2、 感测晶体管T3以及存储电容Cst。其中，开关晶体管T2的栅极与第一栅线G1电连接，开关晶体管T2的第一极(例如源极)与数据线DA电连接，开关晶体管T2的第二极(例如漏极)与驱动晶体管T1的栅极电连接。驱动晶体管T1的第一极(例如源极)与电源线VDD电连接，驱动晶体管T1的第二极(例如漏极)与电致发光二极管L的阳极电连接，电致发光二极管L的阴极与低电压信号线VSS电连接。感测晶体管T3的栅极与第二栅线G2电连接，感测晶体管T3的第一极(例如源极)与驱动晶体管T1的第二极(例如漏极)电连接，感测晶体管T3的第二极(例如漏极)与检测线SL电连接。存储电容Cst的第一极与驱动晶体管T1的栅极电连接，存储电容Cst的第二极与驱动晶体管T1的第二极(例如漏极)电连接。
其中通过第一栅线G1上传输的信号控制开关晶体管T2打开，以将数据线DA上传输的数据电压写入驱动晶体管T1的栅极，控制驱动晶体管T1产生工作电流以驱动电致发光二极管L发光。以及通过第二栅线G2上传输的信号控制感测晶体管T3打开，以将驱动晶体管T1产生的工作电流输出给检测线SL，对检测线SL充电。之后，再通过检测每个检测线SL上的电压，并根据检测到的电压进行补偿计算，以得到该行各子像素对应的用于显示的数据电压。
示例性地，电源线VDD可以传输恒定的第一电压，第一电压为正电压；而低电压信号线VSS可以传输恒定的第二电压，第二电压为负电压。或者，在一些示例中，低电压信号线VSS也可以接地。
需要说明的是，在本公开实施例中，像素驱动电路除了可以为图1所示的结构之外，还可以为包括其他数量的晶体管和电容的结构，本公开实施例对此不作限定。
如图2a与图2b所示，显示面板可以包括位于显示区AA中的多个像素单元PX，例如复数个像素单元PX。至少一个像素单元PX可以包括多个子像素。例如，每个像素单元可以包括多个子像素。一般在显示领域，一个像素单元通常包括多个可分别显示单色(例如红色、绿色或蓝色)的子像素，并且， 每个子像素中设置一个电致发光二极管和一个像素驱动电路，以通过控制不同颜色的子像素的发光比例以实现显示不同的颜色，因此上述子像素可以为单色子像素。
例如，如图2a与图2b所示，像素单元PX可以包括：第一颜色子像素010、第二颜色子像素020以及第三颜色子像素030。其中，第一颜色子像素被配置为发第一颜色的光，第二颜色子像素被配置为发第二颜色的光，第三颜色子像素被配置为发第三颜色的光。在一些示例中，第一颜色、第二颜色以及第三颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色为蓝色。由此，该像素单元PX为红绿蓝子像素的排列结构。当然，本公开实施例包括但不限于此，上述的第一颜色、第二颜色和第三颜色还可为其他颜色。
示例性地，第一颜色子像素、第二颜色子像素以及第三颜色子像素沿行方向F2依次排列，同一列子像素的颜色相同。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图2a与图2b所示，显示面板还包括：多条辅助走线210、多条检测线SL、多条数据线DA(DA-010、DA-020、DA-030)以及电源线VDD。其中，检测线与辅助走线绝缘设置，辅助走线210位于相邻两个子像素列之间的间隙中。检测线SL位于相邻两个子像素列之间的间隙中，且检测线与感测晶体管的第二极电连接。驱动晶体管的第一极与电源线VDD电连接。
下面以同一像素单元中的第一颜色子像素010、第二颜色子像素020以及第三颜色子像素030为例，对本公开一些实施例提供的像素驱动电路的各层进行说明。如图3至图5d所示，其中，图5a至图5d为本公开一些实施例提供的像素驱动电路的各层的示意图。下面结合图5a至图5d描述像素驱动电路在衬底基板上的位置关系。
其中，如图3至图5d所示，显示面板可以包括：位于阳极所在层500与发光功能层600之间的像素界定层330，位于像素界定层330面向衬底基板 100一侧的平坦化层320，位于平坦化层面向衬底基板一侧的第一导电层200，位于第一导电层200面向衬底基板100一侧的第一绝缘层711；位于第一绝缘层711面向衬底基板100一侧的第二导电层800，位于第二导电层800面向衬底基板100一侧的第二绝缘层712，位于第二绝缘层712面向衬底基板100一侧的有源半导体层0320，位于有源半导体层0320面向衬底基板100一侧的第三绝缘层713，以及位于第三绝缘层713面向衬底基板100一侧的遮光金属层0310。
其中，图3至图5d还示出了连接到像素驱动电路的第一栅线G1、第二栅线G2、检测线SL、数据线DA-010、DA-020以及DA-030、电源线VDD，辅助走线210。其中，数据线DA-010与第一颜色子像素010中的像素驱动电路的开关晶体管T2电连接，数据线DA-020与第二颜色子像素020中的像素驱动电路的开关晶体管T2电连接，数据线DA-030与第三颜色子像素030中的像素驱动电路的开关晶体管T2电连接。
示例性地，结合图3与图5a，示出了该像素驱动电路的遮光金属层0310，位于衬底基板100上。遮光金属层0310包括：第一连接走线0311、第二连接走线0312以及遮光电极0313-010、0313-020、0313-030。其中，第一连接走线0311和第二连接走线0312沿行方向F2延伸。第一颜色子像素010包括遮光电极0313-010，第二颜色子像素020包括遮光电极0313-020，第三颜色子像素030包括遮光电极0313-030。其中，遮光电极0313-010、0313-020、0313-030在衬底基板100的正投影至少覆盖驱动晶体管的沟道区在衬底基板100的正投影。
示例性地，结合图3与图5b，示出了上述像素驱动电路的有源半导体层0320，并且，在有源半导体层0320与遮光金属层0310之间具有第三绝缘层713。有源半导体层0320可采用半导体材料图案化形成。有源半导体层0320可用于制作上述第一颜色子像素010、第二颜色子像素020以及第三颜色子像素030中的驱动晶体管T1、开关晶体管T2、感测晶体管T3的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。并 且，有源半导体层0320还包括导电区0323-010、0323-020、0323-030；其中，导电区0323-010形成第一颜色子像素010中存储电容Cst的第一极，导电区0323-020形成第二颜色子像素020中存储电容Cst的第一极，导电区0323-030形成第三颜色子像素030中存储电容Cst的第一极。当然，本公开实施例包括但不限于此。
进一步地，各晶体管的有源层间隔设置。示例性地，有源半导体层0320可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。上述的导电区可以为有源半导体层0320进行离子掺杂后形成的具有导电性能的区域。当然，本公开实施例包括但不限于此。
示例性地，像素驱动电路还包括位于有源半导体层0320背离衬底基板100一侧的第二导电层800。在上述的有源半导体层0320与第二导电层800之间形成有第二绝缘层720，用于保护上述的有源半导体层0320。结合图3与图5c所示，示出了第二导电层800。第二导电层800设置在第二绝缘层712上，从而与有源半导体层0320绝缘。其中，第二导电层800可以包括多条第一栅线G1、多条第二栅线G2以及多个栅极部(例如栅极部G-010、G-020、G-030)。示例性地，结合图3与图5c所示，开关晶体管T2的栅极可以为第一栅线G1与有源半导体层0320交叠的部分，感测晶体管T3的栅极可为第二栅线G2与有源半导体层0320交叠的部分。其中，栅极部G-010为第一颜色子像素010中驱动晶体管T1的栅极，栅极部G-020为第二颜色子像素020中驱动晶体管T1的栅极，栅极部G-030为第三颜色子像素030中驱动晶体管T1的栅极。
进一步地，在具体实施时，在本公开实施例中，各栅线组包括第一栅线G1和第二栅线G2；其中，一行子像素对应一个栅线组，同一栅线组中的第一栅线G1和第二栅线G2位于该行像素单元两侧。例如图2b与图3所示，一行子像素对应电连接一条第一栅线G1和一条第二栅线G2。并且，第一栅线G1和第二栅线G2沿列方向F1排布，沿行方向F2延伸。例如，在列方向F1上，存储电容Cst的第一极位于第一栅线G1和第二栅线G2之间。
需要说明的是，图5c中的各虚线矩形框(未标注的)示出了第二导电层800与有源半导体层0320交叠的各个部分。
在具体实施时，在上述的第二导电层800背离衬底基板100一侧具有第一绝缘层711，用于保护上述的第二导电层800。结合图3与图5d所示，示出了该像素驱动电路的第一导电层200，第一导电层200位于第一绝缘层711背离衬底基板100一侧。其中，第一导电层200包括：多条数据线(例如：数据线DA-010、DA-020以及DA-030)、以及电容电极部Cst-010、Cst-020、Cst-030。其中，电容电极部Cst-010作为第一颜色子像素010中存储电容Cst的第二极，电容电极部Cst-020作为第二颜色子像素020中存储电容Cst的第二极，电容电极部Cst-030作为第三颜色子像素030中存储电容Cst的第二极。
示例性地，在具体实施时，在本公开实施中，可以使数据线DA-010、DA-020以及DA-030沿列方向F1延伸且沿行方向F2排列。并且，数据线DA-010、DA-020以及DA-030分别通过在行方向F2上凸出的部分与开关晶体管的源极电连接。
在具体实施时，在本公开实施例中，如图3与图4a所示，像素界定层330可以包括多个发光开口区KB。并且，显示面板还可以包括：位于平坦化层320与像素界定层330之间的阳极所在层500，以及位于阳极所在层500与阴极层400之间的发光功能层600。并且阳极所在层500包括多个相互独立的阳极510；其中，一个阳极510对应一个发光开口区KB，且阳极510在衬底基板100的正投影与对应的发光开口区KB在衬底基板100的正投影具有交叠区域。示例性地，第一过孔310在衬底基板100的正投影与阳极510在衬底基板100的正投影不交叠。这样可以避免第一过孔310对阳极510的平坦性的影响。
其中，在上述的第一导电层200背离衬底基板100一侧具有平坦化层320，用于保护上述的第一导电层200以及实现平坦效果。在上述的阳极所在层500背离衬底基板100一侧具有像素界定层330，像素界定层330具有多个发光开口区KB，一个阳极510对应一个发光开口区KB，以通过发光开口区KB将对应的阳极510暴露出来。也就是说，第一导电层200位于阳极所在层500 面向衬底基板100一侧。这样使得第一导电层200不会对发光透过率造成影响，从而使得第一导电层200不会受限于宽度和厚度的影响，即使阴极层400采用透明导电材料或制备的厚度极薄，也能够通过设置第一导电层200使阴极层400的电阻降低，进而降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
示例性地，在具体实施时，顶发射型的电致发光二极管中，阳极510可以为反射阳极，以将光反射出去。并且，发光功能层600通过发光开口区KB与阳极510直接接触，以及发光功能层600和阴极层400直接接触，以通过阳极510上加载的信号和阴极层400上加载的信号，驱动发光功能层600发光。当然，本公开包括但不限于此。例如，发光功能层600和阳极510之间还可以设置有空穴传输层、空穴注入层，发光功能层600和阴极层400之间还可以设置有电子传输层、电子注入层等膜层。
示例性地，在具体实施时，阴极层400一般为一整层结构，覆盖在衬底基板100上。也就是说，阳极510、发光功能层600以及阴极层400层叠设置，形成了电致发光二极管。进一步地，可以使阳极510在衬底基板100的正投影覆盖对应的发光开口区KB在衬底基板100的正投影。并且，阳极510在衬底基板100的正投影的面积大于对应的发光开口区KB在衬底基板100的正投影的面积。也就是说，可以使阳极510在衬底基板100的正投影的边缘与对应的发光开口区KB在衬底基板100的正投影的边缘具有一定距离，该距离可以根据实际应用环境来设计确定，在此不作限定。
图3为上述的遮光金属层0310、有源半导体层0320、第二导电层800以及第一导电层200的层叠位置关系的示意图。结合图3至图5d所示，数据线DA-010沿行方向F2凸出的部分通过贯穿第一绝缘层711和第二绝缘层712中的至少一个过孔(例如，过孔341-010)与有源半导体层0320中的第一颜色子像素010的开关晶体管T2的源极区域电连接。数据线DA-020沿行方向F2凸出的部分通过贯穿第一绝缘层711和第二绝缘层712中的至少一个过孔(例如，过孔341-020)与有源半导体层0320中的第二颜色子像素020的开 关晶体管T2的源极区域电连接。数据线DA-030沿行方向F2凸出的部分通过贯穿第一绝缘层711和第二绝缘层712中的至少一个过孔(例如，过孔341-030)与有源半导体层0320中的第三颜色子像素030的开关晶体管T2的源极区域电连接。当然，本公开包括但不限于此。
结合图3至图5d中的部分图，每一个子像素中，感测晶体管T3的第一极通过第一连接孔0110与驱动晶体管T1的第二极电连接。具体地，例如如图3与图4b所示，有源半导体层0320中的感测晶体管T3的源极区通过贯穿第一绝缘层711和第二绝缘层712的第一连接孔0110与存储电容Cst的第一极电连接。有源半导体层0320中的驱动晶体管T1的漏极区通过贯穿第一绝缘层711和第二绝缘层712的第四连接孔0140与存储电容Cst的第一极电连接。这样可以实现感测晶体管T3的第一极与驱动晶体管T1的第二极电连接。
并且，结合图3至图5d中的部分图，每一个子像素中，驱动晶体管T1的第一极通过第二连接孔0120与电源线VDD电连接。具体地，例如如图3与图4b所示，第一导电层200还可以包括：多个第四连接部，部分子像素中分别具有一个第四连接部。例如，第二颜色子像素020中具有第四连接部T1-020，第三颜色子像素030中具有第四连接部T1-030。第四连接部T1-030的一端通过贯穿第一绝缘层711和第二绝缘层712以及第三绝缘层713的过孔917与对应的第二连接走线0312电连接，另一端通过贯穿第一绝缘层711和第二绝缘层712的第二连接孔0120与驱动晶体管的有源层的源极区电连接。第四连接部T1-020同理设置，在此不作赘述。
并且，存储电容的第二极还通过第三连接孔与遮光电极电连接。具体地，结合图3至图5d中的部分图，电容电极部Cst-030通过贯穿第一绝缘层711、第二绝缘层712以及第三绝缘层713的第三连接孔0130与遮光电极0313-030电连接，以扩大存储电容的电容值。电容电极部Cst-010和Cst-020同理，在此不作赘述。进一步地，同一子像素中，遮光电极在衬底基板100的正投影可以覆盖第一连接过孔和第二连接过孔围成的区域。
在具体实施时，如图3与图4a所示，阴极层400通过第一过孔310与辅 助走线210电连接。示例性地，具有双层走线结构的信号线可以包括辅助走线210。这样通过设置辅助走线210，并将阴极层400与辅助走线210电连接，以降低阴极层的电阻。从而可以降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
在具体实施时，在本公开实施例中，如图2a、图3、图4a与图5d所示，辅助走线210可以包括：位于第一导电层200的第一辅助走线211，位于第二导电层800的第二辅助走线212。其中，第一辅助走线211沿子像素的列方向F1延伸，且第一辅助走线211沿子像素的行方向F2排列。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施中，如图2b、图3与图5d所示，可以使第一辅助走线211位于相邻两个子像素列之间的间隙中，且阴极层400通过第一过孔310与第一辅助走线211电连接。示例性地，一条辅助走线210位于第三颜色子像素列与第一颜色子像素列之间的间隙中。进一步地，可以使第一辅助走线211位于相邻的两个像素单元列之间的间隙中。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施中，如图2a至图3所示，以相邻的至少两个像素单元列为一个第一列组，一个第一列组对应一条第一辅助走线211，第一辅助走线211位于对应的第一列组中相邻的两个像素单元列之间的间隙中。示例性地，以相邻的两个像素单元列为一个第一列组，例如，在F2箭头所指的方向上(即从左向右的方向上)，可以使第一个像素单元列和第二个像素单元列为第一个第一列组，第三个像素单元列和第四个像素单元列为第二个第一列组。第一个第一列组对应的第一辅助走线211位于第一个像素单元列和第二个像素单元列之间的间隙中，第二个第一列组对应的第一辅助走线211位于第三个像素单元列和第四个像素单元列之间的间隙中。其余设置依此类推，在此不作赘述。
可选地，在具体实施时，在本公开实施中，也可以使每相邻两个像素单元列之间的间隙设置一条辅助走线210。例如在F2箭头所指的方向上(即从 左向右的方向上)，第一个像素单元列和第二个像素单元列之间的间隙中设置有一条辅助走线210，第二个像素单元列和第三个像素单元列之间的间隙中设置有一条辅助走线210，第三个像素单元列和第四个像素单元列之间的间隙中设置有一条辅助走线210。其余设置依此类推，在此不作赘述。
在具体实施时，在本公开实施中，如图2a、图3与图5d所示，一条检测线SL与一条辅助走线210对应设置于同一像素单元列之间的同一间隙中。例如在F2箭头所指的方向上(即从左向右的方向上)，可以使第一个像素单元列和第二个像素单元列为第一个第一列组，第三个像素单元列和第四个像素单元列为第二个第一列组。第一个第一列组对应的辅助走线210和检测线SL位于第一个像素单元列和第二个像素单元列之间的间隙中，第二个第一列组对应的辅助走线210和检测线SL位于第三个像素单元列和第四个像素单元列之间的间隙中。其余设置依此类推，在此不作赘述。
在具体实施时，在本公开实施中，如图2b、图3与图4a所示，显示面板还可以包括：与阳极510同层且绝缘设置的多个第一连接部520。并且，第一过孔310可以包括：贯穿像素界定层330的第一子过孔311和贯穿平坦化层320的第二子过孔312；其中，阴极层400通过第一子过孔311与第一连接部520电连接，第一连接部520通过第二子过孔312与辅助走线210电连接，例如，第一连接部520通过第二子过孔312与第一辅助走线211电连接。由于平坦化层320为了实现较佳的平坦效果，从而使得平坦化层320相比其余绝缘层的厚度较厚，这样导致阴极层400与辅助走线210之间的膜层较厚，若是仅仅设置一个过孔，由于该过孔较深可能会导致阴极层400与辅助走线210不能真实电连接而断路的情况。因此本公开实施例通过设置第一子过孔311和第二子过孔312，可以优先将辅助走线210通过第二子过孔312与第一连接部520进行电连接，之后再将第一连接部520通过第一子过孔311与阴极层400电连接，从而可以避免仅仅设置一个过孔导致不能真实电连接而断路的情况。
在具体实施时，在本公开实施中，如图3与图4a所示，可以使第一子过 孔311在衬底基板100的正投影与第二子过孔312在衬底基板100的正投影至少部分不交叠。示例性地，如图3与图4a所示，第一子过孔311在衬底基板100的正投影与第二子过孔312在衬底基板100的正投影不交叠。这样可以进一步避免由于过孔过深导致阴极层400与辅助走线210不能电连接的问题。
进一步地，为了进一步降低阴极层400的电阻，在具体实施时，在本公开实施中，如图3与图4a所示，第一绝缘层711可以具有第二过孔720，并且第一辅助走线211通过贯穿第一绝缘层711的第二过孔720与第二辅助走线212电连接。这样，通过设置相互电连接的第一辅助走线211和第二辅助走线212，并将阴极层400、第一辅助走线211和第二辅助走线212电连接，可以进一步降低阴极层400的电阻。从而可以进一步降低IR Drop对显示面板的发光均一性的影响，进一步提高显示面板的显示效果。
在具体实施时，在本公开实施中，如图2b、图3、图4a以及图5c所示，第二辅助走线212包括多个间隔设置的第一辅助部810；同一辅助走线210中，第一辅助走线211通过第二过孔720与对应的第一辅助部810电连接。进一步地，同一辅助走线210中，第一辅助走线211在衬底基板100的正投影与对应的第一辅助部810在衬底基板100的正投影具有交叠区域。示例性地，同一辅助走线210中，第一辅助走线211在衬底基板100的正投影覆盖对应的第一辅助部810在衬底基板100的正投影。这样可以使第一辅助部810也设置在子像素列之间，从而可以避免第一辅助部810影响发光显示。
在具体实施时，在本公开实施中，如图2b、图3、图4a以及图5c所示，第一辅助部810在衬底基板100的正投影覆盖对应的第二过孔720在衬底基板100的正投影。这样可以使第二过孔720也设置在子像素列之间，从而可以避免影响发光显示。
在具体实施时，在本公开实施中，如图3、图4a以及图5c所示，可以使一条第一辅助走线211对应多个第一辅助部810。并且，一个第一辅助部810在衬底基板100的正投影位于同一行子像素电连接的第一栅线G1和第二栅线 G2在衬底基板100的正投影之间。
示例性地，如图2b所示，针对同一第一辅助走线211电连接的多个第一辅助部810，可以使一个子像素行对应一个第一辅助部810。即可以使每一行子像素分别一一对应一个第一辅助部810。例如，在沿F1的箭头方向上，可以使每行子像素电连接的第一栅线G1和第二栅线G2之间设置一个第一辅助部810。
示例性地，如图3所示，针对同一第一辅助走线211电连接的多个第一辅助部810，也可以使间隔至少一个子像素行的子像素行对应一个第一辅助部810。例如，在沿F1的箭头方向上，可以使间隔一个子像素行的子像素行对应一个第一辅助部810，即可以使奇数子像素行对应一个第一辅助部810，或可以使偶数子像素行对应一个第一辅助部810。或者，在沿F1的箭头方向上，可以使间隔十一个子像素行的子像素行对应一个第一辅助部810，即可以使第一个子像素行对应一个第一辅助部810，使第十三个子像素行对应一个第一辅助部810，使第二十五个子像素行对应一个第一辅助部810，其余依此类推，在此不作限定。当然，本公开包括但不限于此。
在具体实施时，在本公开实施中，如图2b、图3、图4a以及图5c所示，第一辅助部810沿列方向F1延伸。进一步地，针对同一行子像素对应的第一辅助部810和第一栅线G1和第二栅线G2，第一辅助部810更靠近第二栅线G2。
在具体实施时，在本公开实施中，如图2b、图3以及图5d所示，与第一辅助部810的正投影具有交叠的第一辅助走线211的部分沿子像素行方向的宽度为第一宽度W1，与第一栅线G1的正投影具有交叠的第一辅助走线211的部分沿子像素行方向的宽度为第二宽度W2。其中，第一宽度W1大于第二宽度W2。这样可以通过使第一辅助走线211进行避让，以使与第一辅助走线211最靠近的子像素的面积增加。
在具体实施时，在本公开实施中，如图2b、图3以及图5d所示，可以使具有第二宽度W2的第一辅助走线211的部分靠近第二连接孔0120。这样可 以使第一辅助走线211中靠近第二连接孔0120的部分进行避让。
在具体实施时，在本公开实施中，如图2b、图3、图4a以及图5c所示，每个第一辅助部810可以通过至少四个第二过孔720与对应的第一辅助走线211电连接。具体地，可以使每个第一辅助部810通过四个、五个、六个或更多个第二过孔720与对应的第一辅助走线211电连接。这样使得每个第一辅助部810与第一辅助走线211之间可以具有多个电连接接触点，即使在任一接触点处发生破裂或断裂，通过其他接触点仍能实现第一辅助部810与第一辅助走线211之间的电连通，从而更进一步地降低了第一辅助部810与第一辅助走线211发生断开的风险。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图2b、图3与图4a所示，一条辅助走线210可以对应多个第一过孔310，一个第一过孔310对应一个子像素行；其中，针对同一行子像素对应的第一过孔310和第一栅线G1和第二栅线G2，第一子过孔311在衬底基板100的正投影与第二栅线G2在衬底基板100的正投影具有交叠区域；且第二子过孔312在衬底基板100的正投影位于第一栅线G1和第二栅线G2在衬底基板100的正投影之间。
在具体实施时，在本公开实施例中，如图2b、与3与图4a所示，针对同一行子像素对应的第二子过孔312、第二过孔720以及第二栅线G2，第二子过孔312在衬底基板100的正投影位于第二栅线G2在衬底基板100的正投影与所有第二过孔720在衬底基板100的正投影之间。
在具体实施时，在本公开实施例中，如图2b、图3与图4a所示，可以使同一条第一辅助走线211对应的多个第二过孔720沿列方向F1排列于同一直线上。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，具有双层走线结构的信号线可以包括：检测线SL。这样通过使检测线SL设置为相互电连接的双层走线结构，可以降低检测线SL的电阻，从而可以降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，检测线 SL可以包括：位于第一导电层200的第一检测走线221，以及位于第二导电层800的第二检测走线222。其中，第一绝缘层711具有第三过孔730，第一检测走线221通过贯穿第一绝缘层711的第三过孔730与第二检测走线222电连接。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，第一检测走线221沿子像素的列方向F1延伸，且第一检测走线221沿子像素的行方向F2排列。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，第一导电层200还可以包括：多个第二连接部(即电容电极部Cst-010、Cst-020、Cst-030)，并且，平坦化层320还包括第五连接孔0150，且第五连接孔0150暴露第二连接部(即电容电极部Cst-010、Cst-020、Cst-030)的一部分；阳极510通过第五连接孔0150与第二连接部(即电容电极部Cst-010、Cst-020、Cst-030)电连接。具体地，平坦化层320具有第五连接孔0150，每个子像素对应一个第五连接孔0150。其中，第一颜色子像素010中的阳极510通过第五连接孔0150与电容电极部Cst-010电连接，第二颜色子像素020中的阳极510通过第五连接孔0150与电容电极部Cst-020电连接，第三颜色子像素030中的阳极510通过第五连接孔0150与电容电极部Cst-030电连接。
在具体实施时，在本公开实施例中，如图2b、图3、图4b以及图5c所示，第二检测走线222还可以包括：多个间隔设置的第二辅助部820；其中，同一检测线SL中，第一检测走线221分别通过第三过孔730与对应的第二辅助部820电连接。并且，一条第一检测走线221对应至少一个第二辅助部820，且第一检测走线221通过第三过孔730与对应的第二辅助部820电连接。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，同一检测线SL中，第一检测走线221在衬底基板100的正投影与对应的第二辅助部820在衬底基板100的正投影具有交叠区域。进一步地，同一检测线SL中，第一检测走线221在衬底基板100的正投影覆盖对应的第二辅助部820在衬底基板100的正投影。这样可以避免第二辅助部820对显示造成影响。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，第一连接部520在衬底基板100的正投影与第三过孔730在衬底基板100的正投影不交叠。
在具体实施时，在本公开实施中，如图2b、图3、图4b以及图5c所示，可以使一条第一检测走线221对应多个第二辅助部820，一个第二辅助部820在衬底基板100的正投影位于同一行子像素电连接的第一栅线G1和第二栅线G2在衬底基板100的正投影之间。
示例性地，如图2b所示，针对同一第一检测走线221电连接的多个第二辅助部820，可以使一个子像素行对应一个第二辅助部820。即可以使每一行子像素分别一一对应一个第二辅助部820。例如，在沿F1的箭头方向上，可以使每行子像素电连接的第一栅线G1和第二栅线G2之间设置一个第二辅助部820。
示例性地，如图3所示，针对同一第一检测走线221电连接的多个第二辅助部820，可以使间隔至少一个子像素行的子像素行对应一个第二辅助部820。例如，在沿F1的箭头方向上，可以使间隔一个子像素行的子像素行对应一个第二辅助部820，即可以使奇数子像素行对应一个第二辅助部820，或可以使偶数子像素行对应一个第二辅助部820。或者，在沿F1的箭头方向上，可以使间隔十一个子像素行的子像素行对应一个第二辅助部820，即可以使第一个子像素行对应一个第二辅助部820，使第十三个子像素行对应一个第二辅助部820，使第二十五个子像素行对应一个第二辅助部820，其余依此类推，在此不作限定。当然，本公开包括但不限于此。
在具体实施时，在本公开实施中，如图2b、图3、图4b以及图5c所示，第二辅助部820沿列方向F1延伸。进一步地，针对同一行子像素对应的第二辅助部820和第一栅线G1和第二栅线G2，第二辅助部820更靠近第二栅线G2。
在具体实施时，在本公开实施中，如图2b、图3、图4b以及图5c所示，每个第二辅助部820可以通过至少三个第三过孔730与对应的第一检测走线 221电连接。具体地，可以使每个第二辅助部820通过三个、四个、五个或更多第三过孔730与对应的第一检测走线221电连接。这样使得每个第二辅助部820与第一检测走线221之间具有多个电连接接触点，即使在任一接触点处发生破裂或断裂，通过其他接触点仍能实现第二辅助部820与第一检测走线221之间的连通，从而更进一步地降低了第二辅助部820与第一检测走线221发生断开的风险。当然，本公开包括但不限于此。
在具体实施时，在本公开实施中，如图2b、图3、图4b以及图5c所示，第二辅助部820在衬底基板100的正投影覆盖对应的第三过孔730在衬底基板100的正投影。这样可以使第三过孔730也设置在子像素列之间，从而可以避免影响发光显示。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，一行子像素中的第三连接孔0130沿行方向F2排列于一条直线上，一行子像素中的第四连接孔0140，沿行方向F2也排列于一条直线上，针对同一行子像素对应的第四过孔720、第一栅线G1以及第二栅线G2，第三过孔730在衬底基板100的正投影位于第三连接孔0130沿行方向F1所在的直线和第四连接孔0140沿行方向F1所在的直线之间。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，可以使同一条第一检测走线221对应的多个第三过孔730沿列方向F1排列于同一直线上。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，以相邻的两个像素单元列为一个第二列组，每一个第二列组中的子像素对应电连接一条第一检测走线221。例如，在F2箭头所指的方向上(即从左向右的方向上)，第一个像素单元列和第二个像素单元列为第一个第二列组，第三个像素单元列和第四个像素单元列为第二个第二列组。第一个第二列组对应的第一检测走线221位于第一个像素单元列和第二个像素单元列之间的间隙中，且第一个第二列组中的每个子像素中的感测晶体管均与对应的第一检测走线221电连接。第二个第二列组对应的第一检测走线221位于第三个像素单元列 和第四个像素单元列之间的间隙中，且第二个第二列组中的每个子像素中的感测晶体管均与对应的第一检测走线221电连接。其余设置依此类推，在此不作赘述。
在具体实施时，在本公开实施例中，如图2b、图3与图4b所示，每一条第一检测走线221对应电连接多条第一连接走线0311，且，针对电连接同一条第一检测走线221的第一连接走线0311，第二列组中的每一行子像素一一对应一条第一连接走线0311。并且，第二列组中每一行子像素通过对应的第一连接走线0311与第一检测走线221电连接。示例性地，第一检测走线221通过贯穿第一绝缘层711、第二绝缘层712以及第三绝缘层713的过孔911与对应的第一连接走线0311电连接。并且，第一导电层200还可以包括：多个第三连接部，每个子像素中分别具有一个第三连接部。例如，第一颜色子像素010中具有第三连接部T3-010，第二颜色子像素020中具有第三连接部T3-020，第三颜色子像素030中具有第三连接部T3-030。并且，第三连接部T3-030的一端通过贯穿第一绝缘层711和第二绝缘层712的过孔912与有源半导体层0320中作为感测晶体管的漏极区电连接，另一端贯穿第一绝缘层711、第二绝缘层712以及第三绝缘层713的过孔913与对应的第一连接走线0311电连接。第三连接部T3-010的一端通过贯穿第一绝缘层和第二绝缘层的过孔与有源半导体层中作为感测晶体管的漏极区电连接，另一端贯穿第一绝缘层、第二绝缘层以及第三绝缘层的过孔与对应的第一连接走线电连接。第三连接部T3-020的一端通过贯穿第一绝缘层和第二绝缘层的过孔与有源半导体层中作为感测晶体管的漏极区电连接，另一端贯穿第一绝缘层、第二绝缘层以及第三绝缘层的过孔与对应的第一连接走线电连接。需要说明的是，图4b仅是以第三连接部T3-030为例进行说明，第三连接部T3-010与第三连接部T3-020的实施方式可以依此类推，在此不作赘述。
在具体实施时，在本公开实施例中，如图2a至图3所示，可以使一条第一检测走线221与一条第一辅助走线211均设置于同一像素单元列之间的间隙中。这样通过是传输检测信号的第一检测走线221与传输固定电压的第一 辅助走线211设置于同一间隙中，可以减低信号对第一检测走线221传输的检测信号的影响，提高第一检测走线221传输的信号的精确度。
在具体实施时，在本公开实施例中，如图2b、图3与图4a所示，针对设置于同一像素单元列之间的间隙中的第一检测走线221与第一辅助走线211，第一辅助走线211对应的第一子过孔311在衬底基板100的正投影还与第一检测走线221在衬底基板100的正投影具有交叠区域。
在具体实施时，在本公开实施例中，如图2b、图3与图4a所示，针对设置于同一像素单元列之间的间隙中的第一检测走线221与第一辅助走线211，第一连接部520在衬底基板100的正投影还与该第一检测走线221在衬底基板100的正投影具有交叠区域，并且，第一连接部520在衬底基板100的正投影还与该第一辅助走线211在衬底基板100的正投影具有交叠区域。
在具体实施时，在本公开实施例中，如图2b与图3所示，可以使一个第二辅助部820和一个第一辅助部810对应同一个子像素行。这样可以简化第二辅助部820和第一辅助部810的设计方式，降低设计难度。
在具体实施时，在本公开实施例中，如图2b与图3所示，可以使针对同一行子像素对应的第一辅助部810和第二辅助部820，第一辅助部810的第二过孔720与第二辅助部820的第三过孔730错位排列。例如，第二过孔720的几何中心对应两个第三过孔730之间的间隙处。
在具体实施时，在本公开实施中，如图2b、图3以及图5d所示，与第二辅助部820的正投影具有交叠的第一检测走线221的部分沿子像素行方向F2的宽度为第三宽度W3，与第一栅线G1的正投影具有交叠的第一检测走线221的部分沿子像素行方向F2的宽度为第四宽度W4。其中，第三宽度W3大于第四宽度W4。这样可以通过使第一检测走线221进行避让，以使与第一检测走线221最靠近的子像素的面积增加。
在具体实施时，在本公开实施中，如图2b、图3以及图5d所示，可以使具有第四宽度W4的第一检测走线221的部分靠近第二连接孔0120。这样可以使第一检测走线221中靠近第二连接孔0120的部分进行避让。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，具有双层走线结构的信号线可以包括：电源线VDD。这样通过使电源线VDD设置为相互电连接的双层走线结构，可以降低电源线VDD的电阻，从而可以降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，电源线包括：位于第一导电层200的第一电源走线231，以及位于第二导电层800的第二电源走线232。其中，第一绝缘层711具有第四过孔740，第一电源走线231通过贯穿第一绝缘层711的第四过孔740与第二电源走线232电连接。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，第一电源走线231沿子像素的列方向F1延伸，且第一电源走线231沿子像素的行方向F2排列。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，每一条第一电源走线231对应电连接多条第二连接走线0312。在F2箭头所指的方向上(即从左向右的方向上)，第一个像素单元列对应电连接一条第一电源走线231，最后一个像素单元列对应电连接一条第一电源走线231，针对除第一个像素单元列和最后一个像素单元列之外的像素单元列，以相邻的两个像素单元列为一个第三列组，每一个第三列组中的子像素对应电连接一条第一电源走线231。例如，在F2箭头所指的方向上(即从左向右的方向上)，第二个像素单元列和第三个像素单元列为第一个第三列组，第四个像素单元列和第五个像素单元列为第二个第三列组。第一个第三列组对应的第一电源走线231位于第二个像素单元列和第三个像素单元列之间的间隙中，且第一个第三列组中的每个子像素中的驱动晶体管均与对应的第一电源走线231电连接。第二个第三列组对应的第一电源走线231位于第四个像素单元列和第五个像素单元列之间的间隙中，且第二个第三列组中的每个子像素中的驱动晶体管均与对应的第一电源走线231电连接。其余设置依此类推，在此不作赘述。
在具体实施时，在本公开实施例中，如图2b、图3、图4a、图4c以及图5d所示，第一电源走线231与第一辅助走线211之间间隔至少一列像素单元。 示例性地，可以使第一电源走线231与第一辅助走线211之间间隔一列像素单元。也可以使第一电源走线231与第一辅助走线211之间间隔两列、三列、四列或更多列像素单元，在此不作限定。
在具体实施时，在本公开实施例中，如图2b、图3以及图4c所示，每一条第一电源走线231对应电连接多条第二连接走线0312，且，针对电连接同一条第一电源走线231的第二连接走线0312，第三列组中的每一行子像素一一对应一条第二连接走线0312。并且，第三列组中每一行子像素通过对应的第二连接走线0312与第一电源走线231电连接。示例性地，第一电源走线231通过贯穿第一绝缘层711、第二绝缘层712以及第三绝缘层713的过孔916与对应的第二连接走线0312电连接。
在具体实施时，在本公开实施例中，如图2b、图3、图4c以及图5c所示，第二电源走线232可以包括：多个间隔设置的第三辅助部830；其中，同一电源线VDD中，第一电源走线231分别通过第四过孔740与对应的第三辅助部830电连接。并且，一条第一电源走线231对应至少一个第三辅助部830，且第一电源走线231通过第四过孔740与对应的第三辅助部830电连接。
在具体实施时，在本公开实施例中，如图3与图4c所示，第一电源走线231在衬底基板100的正投影与对应的第三辅助部830在衬底基板100的正投影具有交叠区域。进一步地，第一电源走线231在衬底基板100的正投影覆盖对应的第三辅助部830在衬底基板100的正投影。这样可以避免第三辅助部830对显示造成影响。
在具体实施时，在本公开实施中，如图2b、图3、图4c以及图5c所示，可以使一条第一电源走线231对应多个第三辅助部830，一个第三辅助部830在衬底基板100的正投影位于同一行子像素电连接的第一栅线G1和第二栅线G2在衬底基板100的正投影之间。
示例性地，如图2b所示，针对同一第一电源走线231电连接的多个第三辅助部830，可以使一个子像素行对应一个第三辅助部830。即可以使每一行子像素分别一一对应一个第三辅助部830。例如，在沿F1的箭头方向上，可 以使每行子像素电连接的第一栅线G1和第二栅线G2之间设置一个第三辅助部830。
示例性地，如图3所示，针对同一第一电源走线231电连接的多个第三辅助部830，可以使间隔至少一个子像素行的子像素行对应一个第三辅助部830。例如，在沿F1的箭头方向上，可以使间隔一个子像素行的子像素行对应一个第三辅助部830，即可以使奇数子像素行对应一个第三辅助部830，或可以使偶数子像素行对应一个第三辅助部830。或者，在沿F1的箭头方向上，可以使间隔十一个子像素行的子像素行对应一个第三辅助部830，即可以使第一个子像素行对应一个第三辅助部830，使第十三个子像素行对应一个第三辅助部830，使第二十五个子像素行对应一个第三辅助部830，其余依此类推，在此不作限定。当然，本公开包括但不限于此。
在具体实施时，在本公开实施中，如图3、图4c以及图5c所示，第三辅助部830沿列方向F1延伸。进一步地，针对同一行子像素对应的第三辅助部830和第一栅线G1和第二栅线G2，第三辅助部830更靠近第二栅线G2。
在具体实施时，在本公开实施中，如图2b、图3、图4c以及图5c所示，每个第三辅助部830可以通过至少四个第四过孔740与对应的第一电源走线231电连接。具体地，可以使每个第三辅助部830通过三个、四个、五个或更多第四过孔740与对应的第一电源走线231电连接。这样使得每个第三辅助部830与第一电源走线231之间具有多个电连接接触点，即使在任一接触点处发生破裂或断裂，通过其他接触点仍能实现第三辅助部830与第一电源走线231之间的连通，从而更进一步地降低了第三辅助部830与第一电源走线231发生断开的风险。当然，本公开包括但不限于此。
在具体实施时，在本公开实施中，如图2b、图3、图4c以及图5c所示，第三辅助部830在衬底基板100的正投影覆盖对应的第四过孔740在衬底基板100的正投影。这样可以使第四过孔740也设置在子像素列之间，从而可以避免影响发光显示。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，针对同 一行子像素对应的第四过孔740、第一栅线G1以及第二栅线G2，第四过孔740在衬底基板100的正投影位于第一栅线G1和第二栅线G2在衬底基板100的正投影之间。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，可以使同一条第一电源走线231对应的多个第四过孔740沿列方向F1排列于同一直线上。
在具体实施时，在本公开实施例中，如图2b、图3与图4c所示，可以使针对同一行子像素对应的第一连接孔0110和第三辅助部830，第三辅助部830对应的一个第四过孔740与第一连接孔0110沿子像素行方向排列于一条直线上。
在具体实施时，在本公开实施例中，如图2b与图3所示，可以使一个第三辅助部830和一个第一辅助部810对应同一个子像素行。这样可以简化第三辅助部830和第一辅助部810的设计方式，降低设计难度。
进一步地，在本公开实施例中，如图2b与图3所示，可以使一个第三辅助部830、一个第二辅助部820以及一个第一辅助部810对应同一个子像素行。这样可以进一步简化第三辅助部830、第二辅助部820和第一辅助部810的设计方式，降低设计难度。
在具体实施时，在本公开实施例中，如图2b、图3以及图5d所示，与第三辅助部830的正投影具有交叠的第一电源走线231的部分沿子像素行方向F2的宽度为第五宽度W5，与第一栅线G1的正投影具有交叠的第一电源走线231的部分沿子像素行方向F2的宽度为第六宽度W6。其中，第五宽度W5大于第六宽度W6。这样可以通过使第一电源走线231进行避让，以使与第一电源走线231最靠近的子像素的面积增加。
在具体实施时，在本公开实施中，如图2b、图3以及图5d所示，可以使具有第六宽度W6的第一电源走线231的部分靠近第二连接孔0120。这样可以使第一电源走线231中靠近第二连接孔0120的部分进行避让。
需要说明的是，上述第一宽度、第二宽度、第三宽度、第四宽度、第五 宽度以及第六宽度可以根据实际应用环境来设计确定，在此不作限定。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述各特征中的相同并不能完全相同，可能会有一些偏差，因此上述各特征之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为如图6所示的全面屏手机。
当然，在具体实施时，显示装置还可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板及显示装置，通过设置相互电连接的双层走线结构，可以使设置有双层走线结构的信号线的电阻降低，从而可以降低IR Drop对显示面板的发光均一性的影响，提高显示面板的显示效果。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (49)

  1. 一种显示面板，包括：
    衬底基板；
    复数个像素单元，阵列排布于所述衬底基板上，且至少一个所述像素单元包括：多个子像素，至少一个所述子像素包括：感测晶体管和驱动晶体管；
    多个栅线组，各所述栅线组包括位于所述像素单元两侧的第一栅线和第二栅线；
    针对同一行所述子像素对应的所述第一栅线和所述第二栅线，所述感测晶体管位于所述子像素更靠近所述第二栅线的一侧，所述驱动晶体管位于所述子像素更靠近所述第一栅线的一侧；
    同一所述子像素中，所述感测晶体管的第一极通过第一连接孔与驱动晶体管的第二极电连接，所述驱动晶体管的第一极通过第二连接孔与电源线电连接；
    针对同一行中相互靠近且不位于同一像素单元中的两个子像素，所述两个子像素的所述第一连接孔和所述第二连接孔围成的区域至少有一条信号线具有双层走线结构，且同一所述信号线的所述双层走线结构相互电连接。
  2. 如权利要求1所述的显示面板，其中，所述子像素还包括：层叠设置的阳极、发光功能层以及阴极层；其中，同一子像素中，所述驱动晶体管的第二极与所述阳极电连接；
    所述显示面板还包括：
    多条辅助走线；其中，所述辅助走线位于相邻两个子像素列之间的间隙中，且所述阴极层通过第一过孔与所述辅助走线电连接；
    多条检测线；其中，所述检测线位于相邻两个子像素列之间的间隙中，且所述检测线与所述辅助走线绝缘设置，所述检测线与所述感测晶体管的第二极电连接；
    所述信号线包括：所述辅助走线、所述检测线以及所述电源线中的至少 一条。
  3. 如权利要求2所述的显示面板，其中，所述显示面板还包括：
    像素界定层，位于所述阳极所在层与所述发光功能层之间；
    平坦化层，位于所述像素界定层面向所述衬底基板一侧；
    第一导电层；位于所述平坦化层面向所述衬底基板一侧；
    第一绝缘层，位于所述第一导电层面向所述衬底基板一侧；
    第二导电层，位于所述第一绝缘层面向所述衬底基板一侧；
    所述辅助走线包括：
    第一辅助走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
    第二辅助走线，位于所述第二导电层；
    所述第一辅助走线通过贯穿所述第一绝缘层的第二过孔与所述第二辅助走线电连接。
  4. 如权利要求3所述的显示面板，其中，所述第二辅助走线包括多个间隔设置的第一辅助部；其中，同一所述辅助走线中，所述第一辅助走线分别通过所述第二过孔与对应的所述第一辅助部电连接。
  5. 如权利要求4所述的显示面板，其中，同一所述辅助走线中，所述第一辅助走线在所述衬底基板的正投影与对应的所述第一辅助部在所述衬底基板的正投影具有交叠区域。
  6. 如权利要求4或5所述的显示面板，其中，所述第一辅助部在所述衬底基板的正投影覆盖对应的所述第二过孔在所述衬底基板的正投影。
  7. 如权利要求4-6任一项所述的显示面板，其中，针对同一所述第一辅助走线电连接的多个第一辅助部，一个子像素行对应一个所述第一辅助部。
  8. 如权利要求4-6任一项所述的显示面板，其中，针对同一所述第一辅助走线电连接的多个第一辅助部，间隔至少一个子像素行的子像素行对应一个所述第一辅助部。
  9. 如权利要求4-8任一项所述的显示面板，其中，每个所述第一辅助部通过至少四个第二过孔与对应的第一辅助走线电连接。
  10. 如权利要求4-9任一项所述的显示面板，其中，针对同一行子像素对应的所述第一辅助部和所述第一栅线和所述第二栅线，所述第一辅助部更靠近所述第二栅线。
  11. 如权利要求4-10任一项所述的显示面板，其中，所述第一过孔在所述衬底基板的正投影与所述阳极在所述衬底基板的正投影不交叠。
  12. 如权利要求4-11任一项所述的显示面板，其中，所述显示面板还包括：
    多个第一连接部，与所述阳极同层且绝缘；
    所述第一过孔包括：贯穿所述像素界定层的第一子过孔和贯穿所述平坦化层的第二子过孔；
    所述阴极层通过所述第一子过孔与所述第一连接部电连接，所述第一连接部通过所述第二子过孔与所述辅助走线电连接。
  13. 如权利要求12所述的显示面板，其中，所述第一子过孔在所述衬底基板的正投影与所述第二子过孔在所述衬底基板的正投影至少部分不交叠。
  14. 如权利要求13所述的显示面板，其中，一条所述辅助走线对应多个第一过孔，一个第一过孔对应一个子像素行；
    针对同一行子像素对应的所述第一过孔和所述第一栅线和所述第二栅线，所述第一子过孔在所述衬底基板的正投影与所述第二栅线在所述衬底基板的正投影具有交叠区域；且所述第二子过孔在所述衬底基板的正投影位于所述第一栅线和所述第二栅线在所述衬底基板的正投影之间。
  15. 如权利要求14所述的显示面板，其中，针对同一行子像素对应的所述第二子过孔、所述第二过孔以及所述第二栅线，所述第二子过孔在所述衬底基板的正投影位于所述第二栅线在所述衬底基板的正投影与所有所述第二过孔在所述衬底基板的正投影之间。
  16. 如权利要求4-15任一项所述的显示面板，其中，与所述第一辅助部的正投影具有交叠的第一辅助走线的部分沿所述子像素行方向的宽度为第一宽度，与所述第一栅线的正投影具有交叠的第一辅助走线的部分沿所述子像 素行方向的宽度为第二宽度；
    所述第一宽度大于所述第二宽度。
  17. 如权利要求16所述的显示面板，其中，具有所述第二宽度的第一辅助走线的部分靠近所述第二连接孔。
  18. 如权利要求3-17任一项所述的显示面板，其中，所述第一辅助走线位于相邻的两个像素单元列之间的间隙中。
  19. 如权利要求2-18任一项所述的显示面板，其中，以相邻的至少两个像素单元列为一个第一列组，一个所述第一列组对应一条第一辅助走线，所述第一辅助走线位于对应的所述第一列组中相邻的两个像素单元列之间的间隙中。
  20. 如权利要求3-19任一项所述的显示面板，其中，所述显示面板还包括：
    第二绝缘层，位于所述第二导电层面向所述衬底基板一侧；
    有源半导体层，位于所述第二绝缘层面向所述衬底基板一侧；
    第三绝缘层，位于所述有源半导体层面向所述衬底基板一侧；
    遮光金属层，位于所述第三绝缘层面向所述衬底基板一侧；
    所述遮光金属层包括：至少一个遮光电极；其中，一个所述遮光电极位于一个所述子像素中；
    同一所述子像素中，所述遮光电极在所述衬底基板的正投影至少覆盖所述驱动晶体管的沟道区在所述衬底基板的正投影。
  21. 如权利要求20所述的显示面板，其中，至少一个所述子像素还包括：存储电容；其中，所述存储电容的第一极与所述驱动晶体管的栅极电连接，所述存储电容的第二极与所述驱动晶体管的第二极电连接；
    所述存储电容的第二极还通过第三连接孔与所述遮光电极电连接。
  22. 如权利要求3-21任一项所述的显示面板，其中，所述检测线包括：
    第一检测走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
    第二检测走线，位于所述第二导电层；
    所述第一检测走线通过贯穿所述第一绝缘层的第三过孔与所述第二检测走线电连接。
  23. 如权利要求22所述的显示面板，其中，所述第二检测走线包括多个间隔设置的第二辅助部；其中，同一所述检测线中，所述第一检测走线分别通过所述第三过孔与对应的所述第二辅助部电连接。
  24. 如权利要求23所述的显示面板，其中，同一所述检测线中，所述第一检测走线在所述衬底基板的正投影与对应的所述第二辅助部在所述衬底基板的正投影具有交叠区域。
  25. 如权利要求23或24所述的显示面板，其中，所述第二辅助部在所述衬底基板的正投影覆盖对应的所述第三过孔在所述衬底基板的正投影。
  26. 如权利要求23-25任一项所述的显示面板，其中，针对同一所述第一检测走线电连接的多个第二辅助部，一个子像素行对应一个所述第二辅助部。
  27. 如权利要求23-25任一项所述的显示面板，其中，针对同一所述第一检测走线电连接的多个第二辅助部，间隔至少一个子像素行的子像素行对应一个所述第二辅助部。
  28. 如权利要求23-27任一项所述的显示面板，其中，一个所述第二辅助部和一个所述第一辅助部对应同一个子像素行。
  29. 如权利要求28所述的显示面板，其中，针对同一行子像素对应的所述第一辅助部和所述第二辅助部，所述第一辅助部的第二过孔与所述第二辅助部的第三过孔错位排列。
  30. 如权利要求23-29任一项所述的显示面板，其中，每个所述第二辅助部通过至少三个第三过孔与对应的第一检测走线电连接。
  31. 如权利要求23-30任一项所述的显示面板，其中，针对同一行子像素对应的所述第二辅助部和所述第一栅线和所述第二栅线，所述第二辅助部更靠近所述第二栅线。
  32. 如权利要求23-31任一项所述的显示面板，其中，与所述第二辅助部的正投影具有交叠的第一检测走线的部分沿所述子像素行方向的宽度为第三 宽度，与所述第一栅线的正投影具有交叠的第一检测走线的部分沿所述子像素行方向的宽度为第四宽度；
    所述第三宽度大于所述第四宽度。
  33. 如权利要求32所述的显示面板，其中，具有所述第四宽度的第一检测走线的部分靠近所述第二连接孔。
  34. 如权利要求23-33任一项所述的显示面板，其中，针对设置于同一像素单元列之间的间隙中的所述第一检测走线与所述第一辅助走线，所述第一辅助走线对应的所述第一子过孔在所述衬底基板的正投影还与所述第一检测走线在所述衬底基板的正投影具有交叠区域。
  35. 如权利要求22-34任一项所述的显示面板，其中，一条所述第一检测走线与一条所述第一辅助走线均设置于同一像素单元列之间的间隙中。
  36. 如权利要求3-35任一项所述的显示面板，其中，所述电源线包括：
    第一电源走线，位于所述第一导电层，且沿所述子像素的列方向延伸；
    第二电源走线，位于所述第二导电层；
    所述第一电源走线通过贯穿所述第一绝缘层的第四过孔与所述第二电源走线电连接。
  37. 如权利要求36所述的显示面板，其中，所述第一电源走线与所述第一辅助走线之间间隔至少一列像素单元。
  38. 如权利要求37所述的显示面板，其中，所述第二电源走线包括多个间隔设置的第三辅助部；其中，同一所述电源线中，所述第一电源走线分别通过所述第四过孔与对应的所述第三辅助部电连接。
  39. 如权利要求38所述的显示面板，其中，同一所述电源线中，所述第一电源走线在所述衬底基板的正投影与对应的所述第三辅助部在所述衬底基板的正投影具有交叠区域。
  40. 如权利要求39所述的显示面板，其中，所述第三辅助部在所述衬底基板的正投影覆盖对应的所述第四过孔在所述衬底基板的正投影。
  41. 如权利要求40所述的显示面板，其中，每个所述第三辅助部通过至 少四个第四过孔与对应的第一电源走线电连接。
  42. 如权利要求38-41任一项所述的显示面板，其中，针对同一所述第一电源走线电连接的多个第三辅助部，一个子像素行对应一个所述第三辅助部。
  43. 如权利要求38-41任一项所述的显示面板，其中，针对同一所述第一电源走线电连接的多个第三辅助部，间隔至少一个子像素行的子像素行对应一个所述第三辅助部。
  44. 如权利要求42或43所述的显示面板，其中，一个所述第三辅助部和一个所述第一辅助部对应同一个子像素行。
  45. 如权利要求44所述的显示面板，其中，针对同一行子像素对应的所述第三辅助部和所述第一栅线和所述第二栅线，所述第三辅助部更靠近所述第二栅线。
  46. 如权利要求38-45任一项所述的显示面板，其中，与所述第三辅助部的正投影具有交叠的第一电源走线的部分沿所述子像素行方向的宽度为第五宽度，与所述第一栅线的正投影具有交叠的第一电源走线的部分沿所述子像素行方向的宽度为第六宽度；
    所述第五宽度大于所述第六宽度。
  47. 如权利要求46所述的显示面板，其中，具有所述第六宽度的第一电源走线的部分靠近所述第二连接孔。
  48. 如权利要求38-47任一项所述的显示面板，其中，针对同一行子像素对应的所述第一连接孔和所述第三辅助部，所述第三辅助部对应的一个第四过孔与所述第一连接孔沿子像素行方向排列于一条直线上。
  49. 一种显示装置，其中，包括如权利要求1-48任一项所述的显示面板。
PCT/CN2019/122189 2019-11-29 2019-11-29 显示面板及显示装置 WO2021103003A1 (zh)

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CN201980002714.7A CN113196492A (zh) 2019-11-29 2019-11-29 显示面板及显示装置
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