WO2020244292A1 - 发光二极管驱动背板及其制备方法、显示装置 - Google Patents

发光二极管驱动背板及其制备方法、显示装置 Download PDF

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Publication number
WO2020244292A1
WO2020244292A1 PCT/CN2020/081839 CN2020081839W WO2020244292A1 WO 2020244292 A1 WO2020244292 A1 WO 2020244292A1 CN 2020081839 W CN2020081839 W CN 2020081839W WO 2020244292 A1 WO2020244292 A1 WO 2020244292A1
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metal strip
gate
insulating layer
doped region
substrate
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PCT/CN2020/081839
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English (en)
French (fr)
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李海旭
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京东方科技集团股份有限公司
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Priority to US16/973,091 priority Critical patent/US11398438B2/en
Publication of WO2020244292A1 publication Critical patent/WO2020244292A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other

Definitions

  • the embodiments of the present disclosure relate to a light-emitting diode driving backplane and a manufacturing method thereof, and a display device.
  • LED Semiconductor light-emitting diode
  • Mini Light Emitting Diode (Mini LED) display and Micro Light Emitting Diode (Micro LED) display have gradually become a hot spot for light emitting diode drive backplanes.
  • Micro LED as a new generation display technology has higher brightness, better luminous efficiency, and lower power consumption.
  • the preparation method of the Micro LED driver backplane is to prepare the Micro LED and the driver backplane separately, and then bond the Micro LED on the driver backplane through the transfer process to realize the Micro LED combining the Micro LED and the driver backplane. Drive the backplane.
  • a light-emitting diode driving backplane including a substrate and a driving structure.
  • the driving structure is disposed on the substrate and includes a thin film transistor and a stress relief structure;
  • the thin film transistor includes a The active layer on the substrate, the first insulating layer covering the active layer, and the first gate provided on the first insulating layer, wherein the active layer includes a channel region and a first A doped region and a second doped region;
  • the stress relief structure includes a first metal strip on the first side of the first gate and a second metal strip on the second side of the first gate, The first side and the second side are opposite, and the first metal strip and the second metal strip are arranged in the same layer as the first gate electrode and are made of the same material.
  • the thin film transistor further includes: a second insulating layer covering the first gate, the first metal strip and the second metal strip; and a third insulating layer disposed on On the second insulating layer, the third insulating layer is provided with a first via hole and a second via hole, the first via hole exposing the first doped region of the active layer, and the second Two via holes expose the second doped region of the active layer; a source electrode and a drain electrode, the source electrode and the drain electrode are both arranged on the third insulating layer, and the source electrode passes through the The first via is connected to the first doped region of the active layer, and the drain electrode is connected to the second doped region of the active layer through the second via, wherein The first metal strip is located between the first gate and the first via hole, and the second metal strip is located between the first gate and the second via hole.
  • the cross-sectional shapes of the first metal strip and the second metal strip are both rectangular or arched.
  • the widths of the first metal strip and the second metal strip are both 2.0 ⁇ m ⁇ 3.0 ⁇ m.
  • the separation distance between the first metal strip and the first gate is 1.5 ⁇ m-2 ⁇ m, and the separation between the second metal strip and the first gate is The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • the separation distance between the first metal strip and the first via is 1.5 ⁇ m to 2 ⁇ m, and the separation between the second metal strip and the second via The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • Various embodiments of the present disclosure also provide a method for preparing a light-emitting diode driving backplane, including:
  • the active layer including a channel region, a first doped region and a second doped region;
  • a first gate and a stress relief structure are formed on the first insulating layer through a single patterning process.
  • the stress relief structure includes a first metal strip and a second metal strip.
  • the first metal strip is located on the first gate.
  • the second metal strip is located on the second side of the first gate, and the first side and the second side are opposite.
  • the method further includes:
  • a third insulating layer is formed on the second insulating layer, and a first via hole and a second via hole are provided on the third insulating layer, wherein the first via hole exposes the first doped region, The second via hole exposes the second doped region;
  • a source electrode and a drain electrode are formed on the third insulating layer, the source electrode is connected to the first doped region through the first via hole, and the drain electrode is connected to the first doped region through the second via hole.
  • the first metal strip is located between the first via hole and the first gate, and the second metal strip is located between the second via hole and the first gate. Between the gates.
  • the cross-sectional shapes of the first metal strip and the second metal strip are rectangular or arched.
  • the width of the first metal strip in a plane parallel to the substrate and in a direction perpendicular to the first gate, is 2.0 ⁇ m to 3.0 ⁇ m, and the The width of the two metal bars is 2.0 ⁇ m to 3.0 ⁇ m.
  • the separation distance between the first metal strip and the first gate is 1.5 ⁇ m to 2 ⁇ m, and the separation between the second metal strip and the second gate The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • Various embodiments of the present disclosure also provide a display device including the aforementioned light-emitting diode driving backplane.
  • Figure 1 is a schematic diagram of applying pressure on the Micro LED
  • FIG. 2 is a schematic diagram of pressure transmission to the film layer where the second gate is located
  • Figure 3 is a schematic diagram of pressure applied to the first grid
  • FIG. 4 is an enlarged view of the corner area of the first gate edge in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a light-emitting diode driving backplane according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a structure after forming an active layer pattern on a substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a structure after forming a first gate and a first metal strip pattern on a substrate according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a structure after forming a second gate pattern on a substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a structure after forming a third insulating layer pattern on a substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a structure after source and drain electrode patterns are formed on a substrate according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a structure after forming a fourth insulating layer pattern on a substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a stress relief structure according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the position of the first metal strip according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a light emitting diode driving backplane according to another embodiment of the present disclosure.
  • Fig. 15 is a schematic diagram of stress relief of a stress relief structure according to another embodiment of the present disclosure.
  • first insulating layer 13—first insulating layer; 14—first gate; 15—second insulating layer;
  • 16 second gate
  • 17 third insulating layer
  • 18 source electrode
  • the transfer process is used to bind the Micro LED on the drive backplane to realize the Micro LED drive backplane that combines the Micro LED and the drive backplane.
  • TFT Thin Film Transistor
  • TFT Thin Film Transistor
  • FIG. 1 is a schematic diagram of applying pressure on the Micro LED
  • Figure 2 is a schematic diagram of pressure being transferred to the film layer where the second gate 16 is located
  • Figure 3 is a schematic diagram of pressure applied
  • the schematic diagram to the first gate 14 FIG. 4 is an enlarged view of the edge corner area of the first gate 14 in FIG.
  • the pressure applied to the Micro LED 200 is transmitted to the driving backplane 100, and is transmitted downward along the various film layers of the driving backplane 100, and finally acts on the area close to the active layer 12.
  • Several layers of film When pressure acts on the first grid 14 through the film layer where the second grid 16 is located, the magnitude and direction of the pressure at the edge corners of the first grid 14 are affected by factors such as the edge material and shape mutation of the first grid 14 With a large change, the pressure direction is toward the corner of the edge of the first grid 14, and the pressure increases at the same time, so that stress concentration occurs at the corner of the edge of the first grid 14.
  • the channel region of the active layer 12 will change the interface state and the trap state in the body. , The carrier transmission state and the transmission path are changed, thereby causing the off-state current I off to rise, and the subthreshold swing SS becomes larger.
  • the measurement parameters include: On-state current I on , off-state current I off , threshold voltage V th , mobility M ob and sub-threshold swing SS, the applied pressure is 0.1 MPa for 15 seconds.
  • the measurement results are shown in Table 1.
  • the light-emitting diode driving backplane includes a substrate and a driving structure layer.
  • the driving structure layer is disposed on the substrate and includes a thin film transistor and a stress relief structure.
  • the thin film transistor includes an active layer and a first insulating layer.
  • the active layer is disposed on the substrate and includes a channel region and a doped region
  • the first insulating layer covers the active layer
  • the first gate is disposed on the second
  • the stress relief structure includes a first metal strip and a second metal strip, and the first metal strip and the second metal strip are arranged on the same layer as the first gate electrode and are made of the same material
  • the first metal strip and the second metal strip are respectively located on the first side and the second side of the first gate.
  • the stress relief structure is configured to reduce or eliminate the stress acting on the channel region of the active layer of the thin film transistor, suppress the increase of the off-state current I off, increase the sub-threshold swing SS, and stabilize the TFT characteristics.
  • the stress relief structure is configured to reduce or eliminate the stress acting on the channel region of the active layer of the thin film transistor, thereby reducing the
  • the degree of change in the interface state of the source layer channel region and the trap state in the body reduces the change in the carrier transport state and the transport path, thereby suppressing the increase in the off-state current I off and the increase in the subthreshold swing SS. Stabilized TFT characteristics.
  • FIG. 5 is a schematic structural diagram of a light-emitting diode driving backplane according to some embodiments of the present disclosure.
  • the light-emitting diode driving backplane includes a substrate 10 and a driving structure layer.
  • the driving structure layer is disposed on the substrate 10 and includes a thin film transistor, a stress relief structure, a second gate, and a common electrode.
  • the thin film transistor includes an active layer, a first gate, a source electrode, and a drain electrode.
  • the stress relief structure includes a first metal strip on the first side of the first gate and a second metal strip on the second side of the first gate. One side is opposite to the second side of the first gate.
  • the light-emitting diode driving backplane includes:
  • the barrier layer 11 is disposed on the substrate 10;
  • the active layer 12 is disposed on the barrier layer 11 and includes a channel region, a first doped region, and a second doped region.
  • the first doped region and the second doped region are respectively located in the trench Both sides of the road area;
  • the first insulating layer 13 covers the active layer 12;
  • the first gate 14 is disposed on the first insulating layer 13;
  • a first metal strip 30 and a second metal strip the first metal strip is arranged on the first side of the first gate 14 and the second metal strip is arranged on the second side of the first gate 14 , The first side is opposite to the second side;
  • the second insulating layer 15 covers the first gate 14 and the first metal strip 30 and the second metal strip;
  • the second gate 16 is disposed on the second insulating layer 15;
  • the third insulating layer 17, covering the second gate 16, is provided with a first via hole and a second via hole, the first via hole and the second via hole respectively exposing the first doped region And the second doped region;
  • the source electrode 18, the drain electrode 19 and the common electrode 20 are arranged on the third insulating layer 17.
  • the source electrode 18 and the drain electrode 19 respectively pass through the first via hole and the second via hole and the first doped The region is connected to the second doped region;
  • the fourth insulating layer 21 covers the source electrode 18, the drain electrode 19 and the common electrode 20, and is provided with a third via hole and a fourth via hole, the third via hole and the fourth via hole Expose the drain electrode 19 and the common electrode 20 respectively;
  • the first connection electrode 22 and the second connection electrode 23 are disposed on the fourth insulating layer 21, the first connection electrode 22 is connected to the drain electrode 19 through the third via hole, and the second connection The electrode 23 is connected to the common electrode 20 through the fourth via hole.
  • the first metal strip 30 and the second metal strip are arranged on both sides of the first gate 14 and are configured to reduce stress concentration at the edge corners of the first gate 14 when the Micro LED is bound, thereby reducing the effect Stress in the channel region of the active layer 12.
  • the positions of the first metal strip 30 and the second metal strip correspond to the positions of the first doped region and the second doped region, respectively, that is, the first metal strip is on the substrate 10
  • the orthographic projection on the active layer 12 is located within the orthographic projection range of the first doped region of the active layer 12 on the substrate 10, and the orthographic projection of the second metal strip on the substrate 10 is located on the substrate 10.
  • the second doped region of the source layer is within the orthographic projection range on the substrate 10.
  • patterning process in the embodiments of the present disclosure includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature preparation process in related technologies.
  • the deposition may use known processes such as sputtering, vapor deposition, chemical vapor deposition, etc.
  • the coating may use a known coating process
  • the etching may use a known method, which is not limited here.
  • a pattern of connecting electrodes is formed.
  • Forming the pattern of the active layer includes: sequentially depositing a barrier film and an active layer film on the substrate 10, and patterning the active layer film through a patterning process to form an active layer 12 disposed on the barrier layer 11 , wherein the active layer 12 includes a channel region, a first doped region and a second doped region, the first doped region and the second doped region are located on both sides of the channel region ,As shown in Figure 6.
  • the barrier film can be silicon nitride SiNx or silicon oxide SiOx. It can be a single layer or a silicon nitride/silicon oxide multilayer structure.
  • the barrier layer 11 is used to improve the water and oxygen resistance of the substrate 10 and prevent the substrate
  • the metal ions in the active layer diffuse to the active layer to prevent the threshold voltage and leakage current from affecting the characteristics.
  • the active layer film can be made of materials such as amorphous silicon (a-Si), low temperature polysilicon (LTPS) or semiconductor oxide (Oxide). According to the material of the active layer film used, it is necessary to perform corresponding steps before and after the patterning process. deal with.
  • the preparation process includes: sequentially depositing a barrier material film and an amorphous silicon film on the substrate 10, and processing the amorphous silicon film by laser irradiation , The amorphous silicon film is crystallized into a polysilicon film; a layer of photoresist is coated on the polysilicon film, and the photoresist is stepwise exposed and developed using a halftone mask or a gray tone mask.
  • LTPS Low Temperature Poly-Silicon
  • a first photoresist region is formed, wherein the first photoresist region is unexposed and has a first thickness, and a second photoresist region is formed in the first doped region and the second doped region, wherein the The second photoresist area is partially exposed and has a second thickness, where the first thickness is greater than the second thickness, and a photoresist complete removal area is formed at the remaining positions; the photoresist is completely removed from the polysilicon in the area by an etching process The thin film is removed to form the active layer pattern; the thickness of the first photoresist area is reduced by the photoresist ashing process, the photoresist in the second photoresist area is removed, and the exposed area is exposed by ion implantation.
  • the source layer is subjected to ion implantation to form a first doped region and a second doped region; finally, the remaining photoresist is stripped off to form a channel region and a first doped region located on both sides of the channel region and The LTPS active layer pattern of the second doped region.
  • an LTPS active layer pattern including a heavily doped (Heavily Drain Doping, HDD) region, a lightly doped (Lightly Drain Doping, LDD) region, and an undoped (Undoped) region can also be formed.
  • a pattern of the first gate and the first metal strip and the second metal strip are formed.
  • Forming the pattern of the first gate, the first metal strip and the second metal strip includes: forming a first insulating layer 13 covering the active layer 12 on the substrate forming the aforementioned pattern, and forming a first insulating layer 13 on the first insulating layer 13.
  • the metal thin film, the first metal thin film is patterned by a patterning process to form a first gate 14 and a first metal strip 30 and a second metal strip disposed on the first insulating layer 13, the first metal strip 30 And the second metal strips are located on both sides of the first gate 14, as shown in FIG. 7.
  • the first insulating layer 13 may be formed by deposition.
  • the first metal thin film may be formed by a deposition method.
  • the first metal thin film may also be formed by other methods, such as magnetron sputtering.
  • the orthographic projection of the first gate 14 on the substrate and the channel region of the active layer 12 are in the The orthographic projections on the substrate overlap, the cross-sectional shapes of the first metal strip 30 and the second metal strip perpendicular to the substrate are rectangular, and the width in the direction parallel to the substrate is 2.0.
  • the separation distance L1 between the first metal strip 30 and the first gate 14 is 1.5 ⁇ m-2 ⁇ m, the distance between the second metal strip and the first gate 14 The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • the first insulating layer 13 is also called a first gate insulating layer (Gate Insulating layer, GI).
  • GI Gate Insulating layer
  • the cross-sectional shape of the first metal strip 30 may also be a trapezoid.
  • Forming the second gate pattern includes: forming a second insulating layer 15 covering the first gate 14 and the first metal strip 30 on the substrate on which the aforementioned pattern is formed, and forming on the second insulating layer 15
  • the second metal film is patterned by a patterning process to form a second gate 16 provided on the second insulating layer 15, as shown in FIG. 8.
  • the second insulating layer 15 can be formed by a deposition method, and the second insulating layer 15 is also called a second gate insulating layer (Gate Insulating layer, GI); the second metal thin film can be formed by a deposition method, or other methods Formation, such as magnetron sputtering.
  • Forming the pattern of the third insulating layer includes: depositing a third insulating layer 17 on the substrate where the aforementioned pattern is formed, forming a first via hole and a second via hole, a first via hole and a second via hole through a patterning process
  • the via holes penetrate the third insulating layer 17, the second insulating layer 15 and the first insulating layer 13, respectively exposing the first doped region and the second doped region of the active layer 12, as shown in FIG. 9.
  • the separation distance L2 between the first metal strip 30 and the first via hole is 1.5 ⁇ m to 2 ⁇ m
  • the separation distance between the second metal strip and the second via hole is 1.5 ⁇ m to 2 ⁇ m .
  • the third insulating layer is also called Interlayer Dielectrics.
  • the patterning of the source electrode, the drain electrode and the common electrode includes: forming a third metal film on the third insulating layer 17, and patterning the third metal film through a patterning process to form the source electrode 18,
  • the drain electrode 19 and the common electrode 20 are patterned, the source electrode 18 is connected to the first doped region through the first via hole, and the drain electrode 19 is connected to the second doped region through the second via hole.
  • Zone connection as shown in Figure 10.
  • Forming the pattern of the fourth insulating layer includes: forming a fourth insulating layer on the base forming the aforementioned pattern, and patterning the fourth insulating layer through a patterning process to form a third via hole penetrating the fourth insulating layer 21 and The fourth via hole respectively exposes the drain electrode 19 and the common electrode 20, as shown in FIG. 11.
  • the fourth insulating layer is also called a planarization layer (PLN).
  • Forming the connection electrode pattern includes: forming a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film through a patterning process to form a pattern of the first connection electrode 22 and the second connection electrode 23, the first connection electrode 22 and The second connection electrode 23 is connected to the drain electrode 19 and the common electrode 20 through the third via hole and the fourth via hole, respectively, as shown in FIG. 5.
  • the transparent conductive film may be formed of indium tin oxide ITO or indium zinc oxide IZO, and the first connection electrode 22 and the second connection electrode 23 are configured to be bound to the two electrodes of the Micro LED. So far, the preparation of the light-emitting diode driving backplane according to the embodiment of the present disclosure is completed.
  • FIG. 12 is a schematic diagram of stress relief of the stress relief structure according to an embodiment of the present disclosure, and is an enlarged view of the corner area of the first gate edge.
  • the first metal strip 30 and the second metal strip 40 are provided in this embodiment. , So that the stress concentration that appears at the corner of the edge of the first gate 14 is redistributed to appear at the corner of the edge of the first gate 14 and the first metal strip 30 and the second metal strip 40 are opposite to the first gate 14 at the same time.
  • the adjacent edge corners effectively reduce the stress acting on the channel region of the active layer 12, reduce the change degree of the interface state and trap state in the channel region of the active layer 12, and reduce the carrier transport state and transport path In turn, the degree of change in the off-state current I off is suppressed and the sub-threshold swing SS becomes larger.
  • ⁇ ⁇ i- ⁇ i0 is the amount of change in mobility
  • ⁇ i the amount of change in resistivity component ⁇ i . It can be seen from the above formula that under the action of stress, the carrier mobility will change, and the relative change rate is the product of the piezoresistive coefficient ⁇ ij and the stress ⁇ j .
  • the inventors have known that the stress concentration in the structure only occurs at the corner of the edge of the first gate, and the stress acts on this area, and the stress value is large.
  • the stress concentration in the structure according to the embodiment of the present disclosure appears at the edge corners of the first gate and the edge corners of the first metal strip and the second metal strip, respectively, and the stress acts on the four regions (left and right of the first gate On both sides), part of the stress is loaded on the corners of the first metal strip edge, so that the stress value at the corners of the first gate edge is reduced, the stress concentration tendency is reduced, the stress acting on the channel region of the active layer is reduced, and the The carrier mobility of the source layer stabilizes the TFT characteristics.
  • Fig. 13 is a plan view parallel to the plane of the substrate, schematically showing the position of the first metal strip according to an embodiment of the present disclosure.
  • the first metal strip 30 is located in the area between the first gate 14 and the first via 31, on the connection line between the first gate 14 and the first via, and the second metal strip 40 It is located in the area between the first gate 14 and the second via 41, and is located on the connection line between the first gate 14 and the second via 41.
  • the first metal strip 30 and the second metal strip 40 extend parallel to the first gate 14 to form a strip shape, and the length of the first metal strip 30 and the second metal strip 40 in the extending direction is greater than or equal to that of the active layer 12 The length in the direction.
  • the first metal strip and the second metal strip are respectively arranged on both sides of the first gate, and the first metal strip and the second metal strip make the first gate
  • the stress value at the corners of the pole edge is reduced, which reduces the stress acting on the channel region of the active layer, reduces the degree of change of the interface state and internal state of the active layer channel region, and reduces the carrier transport state and the transmission path
  • the degree of change in turn suppresses the increase in the off-state current I off and the increase in the sub-threshold swing SS, stabilizes the TFT characteristics, and effectively overcomes the problem of the transfer process affecting the TFT characteristics in the related technology.
  • the method for manufacturing a light-emitting diode drive backplane can utilize existing mature manufacturing equipment, is well compatible with existing manufacturing processes, has the advantages of simple process, easy implementation, and low production cost, and has the advantages of Good application prospects.
  • FIG. 14 is a schematic structural diagram of a light emitting diode driving backplane according to another embodiment of the present disclosure.
  • the light-emitting diode driving backplane includes a substrate 10 and a driving structure.
  • the driving structure is disposed on the substrate 10 and includes a thin film transistor, a stress relief structure, a second gate, and a common electrode.
  • the transistor includes an active layer 12, a first gate 14, a source electrode 19 and a drain electrode 18.
  • the stress relief structure includes a first metal strip 30 and a second metal strip 40.
  • the first metal strip 30 and the second metal strip 40 are disposed on the first insulating layer 13 and respectively located on the first gate 14
  • the first side and the second side are configured to eliminate the stress concentration at the edge corners of the first gate 14 when the Micro LED is bonded, thereby eliminating the stress acting on the channel region of the active layer 12.
  • the first side and The second side is opposite.
  • the cross-sectional shapes of the first metal strip 30 and the second metal strip 40 are arches.
  • the position and size of the first metal strip 30 and the second metal strip 40 are the same as those of the first metal strip 30 and the second metal strip 40 shown with reference to FIG. 13.
  • FIG. 15 is a schematic diagram of stress relief of a stress relief structure according to another embodiment of the present disclosure, and is an enlarged view of an edge corner area of the first gate.
  • the pressure applied by the binding Micro LED is transmitted to the area between the first grid 14 and the first metal strip 30, since the cross-sectional shape of the first metal strip is arched, the arched rounded arc profile is a support in classical mechanics
  • the structure has the best force, the most uniform stress, and the least prone to stress concentration shape, so that the pressure acting on the area between the first grid and the first metal strip can be well relieved, and the pressure is mainly concentrated in the second
  • the curved surface of the metal strip minimizes the probability of stress concentration at the corners of the edge of the first grid, that is, the corners of the edge of the first grid are not prone to stress concentration.
  • the stress concentration at the corner of the first gate edge is basically eliminated, the stress transferred from the corner of the first gate edge to the channel region of the active layer 12 is basically eliminated, and the channel region of the active layer is avoided.
  • the degree of change of the interface state and the trap state in the body avoids the change of the carrier transmission state and the transmission path, thereby eliminating the situation that the off-state current I off increases and the subthreshold swing SS becomes larger.
  • the cross section of the first metal strip 40 and the second metal strip perpendicular to the substrate is set to be rectangular
  • the cross section of the first metal strip 40 and the second metal strip perpendicular to the substrate is set to The arch-shaped embodiment can not only achieve the same technical effect, that is, by arranging the first metal strip 40 and the second metal strip 41 on both sides of the first grid, the first metal strip 40 and the second metal strip 41 make the first
  • the stress value at the corners of the gate edge is reduced, the stress acting on the channel region of the active layer is reduced, the off-state current I off rises, and the subthreshold swing SS becomes larger, and the TFT characteristics are stabilized
  • the cross-sectional shape of the first metal strip 40 and the second metal strip 41 is set to an arch shape, and the smooth arc profile makes the area between the first grid and the first metal strip 40 and the second metal strip 41
  • the pressure can be well relieved, the corners of the first grid edge are not easy to produce stress concentration, and the stress concentration at the corners of the first grid edge
  • the manufacturing process for preparing the light-emitting diode driving backplane shown in FIG. 14 is basically the same as the manufacturing process shown in FIG. 6 to FIG. 11 above.
  • the difference is that the first metal strip and the second
  • the cross-section of the metal strip perpendicular to the substrate is set in an arch shape, which can be achieved by adjusting the etching gas and the etching time, etc., which is well known to those skilled in the art and will not be repeated here.
  • the stress relief structure can also be expanded in various ways.
  • the first metal strip and the second metal strip respectively on both sides of the first gate as an example
  • the first metal strip and the second metal strip can be set as Multiple stress concentration points are generated simultaneously to further reduce the stress value at the corners of the first gate edge.
  • the first metal strip in a direction parallel to the first gate, can be a strip-shaped integrated structure, or a split structure formed by multiple blocks, which can also reduce or eliminate The effect of the stress value at the corner of the first gate edge.
  • various embodiments of the present disclosure also provide a method for manufacturing a light-emitting diode driving backplane.
  • the preparation method includes:
  • an active layer including a channel region, a first doped region and a second doped region on the substrate;
  • a first gate and a stress relief structure are formed on the first insulating layer through a single patterning process.
  • the stress relief structure includes a first metal strip and a second metal strip respectively located on both sides of the first gate.
  • the first gate and the stress relief structure after forming the first gate and the stress relief structure, it further includes:
  • a third insulating layer is formed on the second insulating layer, a first via hole and a second via hole are provided on the third insulating layer, and the first via hole and the second via hole respectively expose the A first doped region and the second doped region;
  • a source electrode and a drain electrode are formed on the third insulating layer, the source electrode is connected to the first doped region through the first via hole, and the drain electrode is connected to the first doped region through the second via hole.
  • the second doped region is connected, wherein the first metal strip and the second metal strip are located between the first gate and the first via hole, and the first gate and the second Between two vias.
  • the cross-sectional shapes of the first metal strip and the second metal strip are rectangular or arched.
  • the width of the first metal strip and the second metal strip in a direction parallel to the first insulating layer and perpendicular to the first gate is 2.0 ⁇ m to 3.0 ⁇ m.
  • the separation distance between the first metal strip and the first gate is 1.5 ⁇ m-2 ⁇ m, and the separation between the second metal strip and the first gate is The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • the separation distance between the first metal strip and the first via is 1.5 ⁇ m to 2 ⁇ m, and the separation between the second metal strip and the second via The distance is 1.5 ⁇ m ⁇ 2 ⁇ m.
  • the first metal strip and the second metal strip are respectively arranged on both sides of the first gate, the first metal strip and the second metal strip
  • the strip reduces the stress value at the corner of the first gate edge, reduces the stress acting on the channel region of the active layer, reduces the change degree of the interface state and trap state in the active layer channel region, and reduces the carrier
  • the degree of change in the transmission state and the transmission path further suppresses the increase in the off-state current I off and the increase in the sub-threshold swing SS, stabilizes the TFT characteristics, and effectively overcomes the problem that the transfer process in the related art affects the TFT characteristics.
  • the manufacturing method of the light-emitting diode driving backplane can be realized by using the existing manufacturing equipment, can be well compatible with the existing manufacturing process, has the advantages of simple process, easy implementation and low production cost, and has good advantages. Application prospects.
  • various embodiments of the present disclosure also provide a display device including the light-emitting diode driving backplane of the foregoing embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the fixed connection can also be a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be a connection between two components.
  • the fixed connection can also be a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be a connection between two components.

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Abstract

一种发光二极管驱动背板，其包括基底以及设置在所述基底上的驱动结构，所述驱动结构包括薄膜晶体管和应力疏解结构，所述薄膜晶体管包括设置在基底上的有源层、覆盖所述有源层的第一绝缘层、以及设置在所述第一绝缘层上的第一栅极，其中，所述应力疏解结构设置在所述第一绝缘层上并包括位于所述第一栅极的第一侧的第一金属条以及位于所述第一栅极的第二侧的第二金属条，所述第一侧和所述第二侧相对。还公开了一种发光二极管驱动背板制备方法以及显示装置。

Description

发光二极管驱动背板及其制备方法、显示装置
本申请要求于2019年6月5日提交的申请号为201910486911.2、发明名称为“发光二极管驱动背板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开的实施例涉及一种发光二极管驱动背板及其制备方法、以及一种显示装置。
背景技术
半导体发光二极管(Light Emitting Diode，LED)技术发展了近三十年，从最初的固态照明电源到显示领域的背光源再到LED显示屏，为其更广泛的应用提供了坚实的基础。随着芯片制作及封装技术的发展，次毫米发光二极管(Mini Light Emitting Diode，Mini LED)显示和微型发光二极管(Micro Light Emitting Diode，Micro LED)显示逐渐成为发光二极管驱动背板的一个热点。与有机发光二极管(Organic Light Emitting Diode，OLED)显示技术相比，作为新一代显示技术的Micro LED亮度更高、发光效率更好、以及功耗更低。
目前，Micro LED驱动背板的制备方式是分别制备Micro LED和驱动背板，然后通过转移工艺将Micro LED绑定(Bonding)在驱动背板上，实现Micro LED和驱动背板相结合的Micro LED驱动背板。
发明内容
本公开的多个实施例提供了一种发光二极管驱动背板，包括基底以及驱动结构，所述驱动结构设置在所述基底上，并包括薄膜晶体管和应力疏解结构；所述薄膜晶体管包括设置在所述基底上的有源层、覆盖所述有源层的第一绝缘层以及设置在所述第一绝缘层上的第一栅极，其中，所述有源层包括沟道区和第一掺杂区以及第二掺杂区；所述应力疏解结构包括位于所述第一栅极的第一 侧的第一金属条以及位于所述第一栅极的第二侧的第二金属条，所述第一侧和所述第二侧相对，所述第一金属条和所述第二金属条与所述第一栅极同层设置，且由相同的材料制成。
在本公开的一些实施例中，所述薄膜晶体管还包括：第二绝缘层，覆盖所述第一栅极和所述第一金属条以及所述第二金属条；第三绝缘层，设置在所述第二绝缘层上，所述第三绝缘层设置有第一过孔和第二过孔，所述第一过孔暴露所述有源层的所述第一掺杂区，所述第二过孔暴露所述有源层的所述第二掺杂区；源电极和漏电极，所述源电极和所述漏电极均设置在所述第三绝缘层上，所述源电极通过所述第一过孔连接至所述有源层的所述第一掺杂区，所述漏电极通过所述第二过孔连接至所述有源层的所述第二掺杂区，其中，所述第一金属条位于所述第一栅极和所述第一过孔之间，所述第二金属条位于所述第一栅极和所述第二过孔之间。
在本公开的一些实施例中，在垂直于基底的平面内，所述第一金属条和所述第二金属条的截面形状均为矩形或拱形。
在本公开的一些实施例中，在平行于所述基底的平面内，在垂直于所述第一栅极的方向上，所述第一金属条和所述第二金属条的宽度均为2.0μm～3.0μm。
在本公开的一些实施例中，所述第一金属条与所述第一栅极之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第一栅极之间的间隔距离为1.5μm～2μm。
在本公开的一些实施例中，所述第一金属条与所述第一过孔之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第二过孔之间的间隔距离为1.5μm～2μm。
本公开的多个实施例还提供了一种制备发光二极管驱动背板的方法，包括：
在基底上形成有源层，所述有源层包括沟道区、第一掺杂区和第二掺杂区；
形成覆盖所述有源层的第一绝缘层；
通过一次构图工艺在所述第一绝缘层上形成第一栅极和应力疏解结构，所述应力疏解结构包括第一金属条和第二金属条，所述第一金属条位于所述第一栅极的第一侧，所述第二金属条位于所述第一栅极的第二侧，所述第一侧和所述第二侧相对。
在本公开的一些实施例中，所述方法还包括：
形成第二绝缘层，所述第二绝缘层覆盖所述第一栅极、所述第一金属条以 及所述第二金属条；
在所述第二绝缘层上形成第三绝缘层，所述第三绝缘层上设置有第一过孔和第二过孔，其中，所述第一过孔暴露所述第一掺杂区，所述第二过孔暴露所述第二掺杂区；
在所述第三绝缘层上形成源电极和漏电极，所述源电极通过所述第一过孔连接至所述第一掺杂区，所述漏电极通过所述第二过孔连接至所述第二掺杂区，其中，所述第一金属条位于所述第一过孔和所述第一栅极之间，所述第二金属条位于所述第二过孔和所述第一栅极之间。
在本公开的一些实施例中，在垂直于基底的平面内，所述第一金属条和所述第二金属条的截面形状为矩形或拱形。
在本公开的一些实施例中，在平行于所述基底的平面内，在垂直于所述第一栅极的方向上，所述第一金属条的宽度为2.0μm～3.0μm，所述第二金属条的宽度为2.0μm～3.0μm。
在本公开的一些实施例中，所述第一金属条和所述第一栅极之间的间隔距离为1.5μm～2μm，所述第二金属条和所述第二栅极之间的间隔距离为1.5μm～2μm。
本公开的多个实施例还提供了一种显示装置，包括前述的发光二极管驱动背板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为在Micro LED上施加压力的示意图；
图2为压力传递到第二栅极所在膜层的示意图；
图3为压力施加到第一栅极上的示意图；
图4为图3中第一栅极边缘拐角区域的放大图；
图5为根据本公开的一个实施例的发光二极管驱动背板的结构示意图；
图6为根据本公开的一个实施例的在基底上形成有源层图案后的结构的示意图；
图7为根据本公开的一个实施例的在基底上形成第一栅极和第一金属条图案后的结构的示意图；
图8为根据本公开的一个实施例的在基底上形成第二栅极图案后的结构的示意图；
图9为根据本公开的一个实施例的在基底上形成第三绝缘层图案后的结构的示意图；
图10为根据本公开的一个实施例的在基底上形成源电极和漏电极图案后的结构的示意图；
图11为根据本公开的一个实施例的在基底上形成第四绝缘层图案后的结构的示意图；
图12为根据本公开的一个实施例的应力疏解结构的受力示意图；
图13为根据本公开的一个实施例的第一金属条的位置示意图；
图14为根据本公开的另一个实施例的发光二极管驱动背板的结构示意图；
图15为根据本公开的另一个实施例的应力疏解结构的受力示意图。
附图标记说明:
10—基底；11—阻挡层；12—有源层；
13—第一绝缘层；14—第一栅极；15—第二绝缘层；
16—第二栅极；17—第三绝缘层；18—源电极；
19—漏电极；20—公共电极；21—第四绝缘层；
22—第一连接电极；23—第二连接电极；30—第一金属条；
40—第二金属条；100—驱动背板；200—Micro LED。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开作进一步详细描述。以下实施例用于说明本公开，但并不用来限制本公开的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在发明人已知的技术中，采用转移工艺将Micro LED绑定(Bonding)在驱动背板上，实现Micro LED和驱动背板相结合的Micro LED驱动背板。
经发明人研究发现，转移工艺后，驱动背板的薄膜晶体管(Thin Film Transistor，TFT)特性受到较大影响，进而影响了Micro LED驱动背板的性能。
发明人发现，转移工艺对薄膜晶体管(Thin Film Transistor,TFT)特性的影响主要体现为关态电流I off升高，亚阈值摆幅SS(Subthreshold Swing)变大。由于关态电流I off影响TFT的开关比和功耗特性，亚阈值摆幅SS影响TFT开启状态与关断状态之间相互转换的速率特性，而这些速率特性是TFT特性的重要参数，因此这些TFT特性变化影响了Micro LED驱动背板的性能。
本公开发明人研究发现，转移工艺对关态电流I off和亚阈值摆幅SS的影响，主要是由于TFT的有源层受到应力作用造成的，而有源层受到的应力来源于将Micro LED绑定在驱动背板上时在Micro LED上施加的压力。图1至图4为转移工艺中压力传递的示意图，其中，图1为在Micro LED上施加压力的示意图，图2为压力传递到第二栅极16所在膜层的示意图，图3为压力施加到第一栅极14上的示意图，图4为图3中第一栅极14边缘拐角区域的放大图。如图1至图4所示，施加在Micro LED 200上的压力被传递到驱动背板100上，沿着驱动背板100的各个膜层向下传输，最终作用在与有源层12相近的几个膜层上。当压力经过第二栅极16所在膜层作用在第一栅极14上时，受第一栅极14边缘材料和形状突变等因素影响，第一栅极14边缘拐角处的压力大小和方向发生较大变化，压力方向朝向第一栅极14边缘的拐角处，同时压力增加，使得第一栅极14边缘的拐角处出现应力集中。由于朝向第一栅极14边缘拐角处的的应力会作用在有源层12的沟道区(未掺杂区)，使得有源层12的沟道区产生界面态及体内陷阱态状态的改变，改变了载流子传输状态以及传输路径，进而造成关态电流I off升高，亚阈值摆幅SS变大。
为了验证上述分析，发明人进行了试验研究。共选用4组TFT，在施加压力之前和施加压力之后进行参数测量，4组TFT的宽长比W/L分别为4/4、4/8、10.5/4和18/30，测量参数包括：开态电流I on、关态电流I off、阈值电压V th、迁移率M ob和亚阈值摆幅SS，施加的压力为0.1MPa，持续15秒。测量结果如表1所示。
研究表明，各组TFT的参数在施加压力前后均有变化，且关态电流和亚阈值摆幅变化较大，变化趋势是：关态电流I off增加，亚阈值摆幅SS增加。由此，上述测量结果进一步证明了关态电流I off升高、亚阈值摆幅SS变大是由于TFT的有源层受到应力作用造成的。
Figure PCTCN2020081839-appb-000001
表1
为了克服发明人已知的技术中存在的转移工艺影响TFT特性的问题，本公开的多个实施例提供了一种发光二极管驱动背板。根据本公开实施例的发光二极管驱动背板包括基底以及驱动结构层，所述驱动结构层设置在所述基底上， 包括薄膜晶体管以及应力疏解结构，所述薄膜晶体管包括有源层、第一绝缘层以及第一栅极，所述有源层设置在基底上并包括沟道区和掺杂区，所述第一绝缘层覆盖所述有源层，所述第一栅极设置在所述第一绝缘层上，所述应力疏解结构包括第一金属条和第二金属条，所述第一金属条和所述第二金属条与所述第一栅极同层设置，并由相同的材料制成，所述第一金属条和所述第二金属条分别位于所述第一栅极的第一侧和第二侧。所述应力疏解结构配置为减小或消除作用在薄膜晶体管的有源层沟道区的应力，抑制关态电流I off升高、亚阈值摆幅SS变大，稳定TFT特性。
在根据本公开实施例的发光二极管驱动背板中，通过在薄膜晶体管中设置应力疏解结构，应力疏解结构配置为减小或消除作用在薄膜晶体管的有源层沟道区的应力，降低了有源层沟道区界面态及体内陷阱态的改变程度，降低了载流子传输状态以及传输路径的改变程度，进而抑制了关态电流I off升高、亚阈值摆幅SS变大的程度，稳定了TFT特性。
下面通过具体实施例详细说明根据本公开实施例的发光二极管驱动背板。
图5为根据本公开的一些实施例的发光二极管驱动背板的结构示意图。如图5所示，所述发光二极管驱动背板包括基底10以及驱动结构层，所述驱动结构层设置在基底10上，并包括薄膜晶体管、应力疏解结构、第二栅极以及公共电极，其中薄膜晶体管包括有源层、第一栅极、源电极和漏电极。在图5所示的结构中，所述应力疏解结构包括位于第一栅极第一侧的第一金属条和位于所述第一栅极第二侧的第二金属条，第一栅极第一侧与第一栅极第二侧相对。在本公开的一些实施例中，所述发光二极管驱动背板包括：
基底10；
阻挡层11，设置在所述基底10上；
有源层12，设置在所述阻挡层11上，并包括沟道区、第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区分别位于沟道区两侧；
第一绝缘层13，覆盖所述有源层12；
第一栅极14，设置在所述第一绝缘层13上；
第一金属条30和第二金属条，所述第一金属条设置在所述第一栅极14的第一侧，所述第二金属条设置在所述第一栅极14的第二侧，第一侧和第二侧相对；
第二绝缘层15，覆盖所述第一栅极14和所述第一金属条30和所述第二金 属条；
第二栅极16，设置在所述第二绝缘层15上；
第三绝缘层17，覆盖所述第二栅极16，其上设置第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露所述第一掺杂区和所述第二掺杂区；
源电极18、漏电极19和公共电极20，设置在第三绝缘层17上，源电极18和漏电极19分别通过所述第一过孔和所述第二过孔与所述第一掺杂区和所述第二掺杂区连接；
第四绝缘层21，覆盖所述源电极18、所述漏电极19和所述公共电极20，并设置第三过孔和第四过孔，所述第三过孔和所述第四过孔分别暴露所述漏电极19和所述公共电极20；
第一连接电极22和第二连接电极23，设置在所述第四绝缘层21上，所述第一连接电极22通过所述第三过孔与所述漏电极19连接，所述第二连接电极23通过所述第四过孔与所述公共电极20连接。
所述第一金属条30和所述第二金属条设置在第一栅极14的两侧，配置为在绑定Micro LED时减小第一栅极14边缘拐角处的应力集中，进而降低作用在有源层12沟道区的应力。所述第一金属条30和所述第二金属条的位置分别与所述第一掺杂区和所述第二掺杂区的位置相对应，即所述第一金属条在所述基底10上的正投影位于所述有源层12的所述第一掺杂区在所述基底10上的正投影范围内，所述第二金属条在所述基底10上的正投影位于所述有源层的所述第二掺杂区在所述基底10上的正投影范围内。
下面通过发光二极管驱动背板的制备方法进一步说明根据本公开实施例的技术方案。本公开的实施例中所说的术语“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做任何限定。
根据本公开实施例的发光二极管驱动背板的制备方法包括以下：
形成有源层的图案；
形成第一栅极和第一金属条以及第二金属条的图案；
形成第二栅极的图案；
形成第三绝缘层的图案；
形成源电极、漏电极和公共电极的图案；
形成第四绝缘层的图案；以及
形成连接电极的图案。
形成所述有源层的图案包括：在基底10上依次沉积阻挡薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成设置在阻挡(Barrier)层11上的有源层12的图案，其中，所述有源层12包括沟道区、第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区分别位于沟道区两侧，如图6所示。阻挡薄膜可以采用氮化硅SiNx或氧化硅SiOx等，可以是单层，也可以是氮化硅/氧化硅的多层结构，阻挡层11用于提高基底10的抗水氧能力，并防止基底中的金属离子扩散至有源层，防止对阈值电压和漏电流等特性产生影响。所述有源层薄膜可以采用非晶硅(a-Si)、低温多晶硅(LTPS)或半导体氧化物(Oxide)等材料，根据采用的有源层薄膜的材料，在构图工艺前后需要进行相应的处理。
以制备低温多晶硅(Low Temperature Poly-Silicon,LTPS)有源层为例，制备过程包括：在基底10上依次沉积阻挡材料薄膜和非晶硅薄膜，采用激光照射的方法对非晶硅薄膜进行处理，使非晶硅薄膜结晶成多晶硅薄膜；在多晶硅薄膜上涂覆一层光刻胶，采用半色调掩膜版或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在沟道区位置形成第一光刻胶区域，其中，所述第一光刻胶区域未曝光，具有第一厚度，在第一掺杂区和第二掺杂区形成第二光刻胶区域，其中，所述第二光刻胶区域部分曝光，具有第二厚度，其中，第一厚度大于第二厚度，在其余位置形成光刻胶完全去除区域；通过刻蚀工艺将所述光刻胶完全去除区域的多晶硅薄膜去除，形成有源层图案；通过光刻胶灰化处理，使第一光刻胶区域的厚度减小厚度，去除第二光刻胶区域的光刻胶，采用离子注入方法对暴露的有源层进行离子注入处理，形成第一掺杂区和第二掺杂区；最后剥离掉剩余的光刻胶，形成包括沟道区和位于所述沟道区两侧的第一掺杂区和第二掺杂区的LTPS有源层图案。实际实施时，还可以形成包括重掺杂(Heavily Drain Doping，HDD)区、轻掺杂(Lightly Drain Doping，LDD)区和未掺杂(Undoped)区的LTPS有源层图案。
形成所述第一栅极和第一金属条以及第二金属条的图案。形成第一栅极和第一金属条以及第二金属条的图案包括：在形成前述图案的基底上形成覆盖有源层12的第一绝缘层13，并在第一绝缘层13上形成第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成设置在所述第一绝缘层13上的第一栅极14和第一金属条30以及第二金属条，所述第一金属条30和所述第二金属条位于 所述第一栅极14的两侧，如图7所示。在本公开的一些实施例中，可以采用沉积方式形成所述第一绝缘层13。在本公开的一些实施例中，可以采用沉积方式形成所述第一金属薄膜，当然，也可以采用其他方式形成所述第一金属薄膜，例如，磁控溅射等。在本公开的一些实施例中，在垂直于所述基底的平面内，所述第一栅极14在所述基底上的正投影与所述有源层12的所述沟道区在所述基底上的正投影相重叠，所述第一金属条30和所述第二金属条垂直于所述基底方向上的截面形状均为矩形，在平行于所述基底的方向上的宽度均为2.0μm～3.0μm，所述第一金属条30和所述第一栅极14之间的间隔距离L1为1.5μm～2μm，所述第二金属条和所述第一栅极14之间的间隔距离为1.5μm～2μm。其中，所述第一绝缘层13也称之为第一栅绝缘层(Gate Insulating layer,GI)。实际实施时，所述第一金属条30的截面形状还可以是梯形。
形成所述第二栅极图案包括：在形成前述图案的所述基底上形成覆盖第一栅极14和第一金属条30的第二绝缘层15，并在所述第二绝缘层15上形成第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成设置在第二绝缘层15上的第二栅极16，如图8所示。其中，第二绝缘层15可以用沉积方式形成，第二绝缘层15也称之为第二栅绝缘层(Gate Insulating layer,GI)；第二金属薄膜可以用沉积方式形成，还可以用其他方式形成，例如磁控溅射等。
形成所述第三绝缘层的所述图案包括：在形成前述图案的所述基底上沉积第三绝缘层17，通过构图工艺形成第一过孔和第二过孔，第一过孔和第二过孔均贯穿第三绝缘层17、第二绝缘层15和第一绝缘层13，分别暴露出有源层12的第一掺杂区和第二掺杂区，如图9所示。在本公开的一些实施例中，第一金属条30和第一过孔之间的间隔距离L2为1.5μm～2μm，第二金属条和第二过孔之间的间隔距离为1.5μm～2μm。第三绝缘层还被称之为层间绝缘层(Interlayer Dielectrics)。
形成所述源电极、所述漏电极和所述公共电极的图案包括：在所述第三绝缘层17上形成第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成源电极18、漏电极19和公共电极20图案，所述源电极18通过所述第一过孔与所述第一掺杂区连接，所述漏电极19通过所述第二过孔与所述第二掺杂区连接，如图10所示。
形成所述第四绝缘层的图案包括：在形成前述图案的基底上形成第四绝缘层，通过构图工艺对第四绝缘层进行构图，形成贯穿所述第四绝缘层21的第三 过孔和第四过孔，分别暴露出漏电极19和公共电极20，如图11所示。第四绝缘层还称之为平坦化层(PLN)。
形成所述连接电极图案包括：在形成前述图案的基底上形成透明导电薄膜，通过构图工艺对透明导电薄膜，形成第一连接电极22和第二连接电极23图案，所述第一连接电极22和所述第二连接电极23分别通过所述第三过孔和所述第四过孔与所述漏电极19和所述公共电极20连接，如图5所示。例如，所述透明导电薄膜可以由氧化铟锡ITO或氧化铟锌IZO形成，第一连接电极22和第二连接电极23配置为与Micro LED的两个电极绑定。至此，完成了对根据本公开实施例的发光二极管驱动背板的制备。
图12为根据本公开实施例的应力疏解结构的受力示意图，为第一栅极边缘拐角区域的放大图。当绑定Micro LED时施加的压力传递到第一栅极14和第一金属条30所在膜层中时，受第一栅极14边缘材料和形状突变和第一金属条30边缘材料和形状突变等因素影响，第一栅极14边缘拐角处(A区域所示)和第一金属条30边缘拐角处(B区域所示)的压力大小和方向均发生变化，压力分别方向朝向第一栅极14边缘的拐角处和第一金属条30边缘拐角处，使得第一栅极14边缘的拐角处和第一金属条30边缘拐角处同时出现应力集中。由于传递到第一栅极14和第一金属条30所在位置的压力是一定的，因而A区域和B区域同时出现应力集中使得每个区域的应力值大幅度下降，从第一栅极14边缘拐角处(A区域)传递到有源层12沟道区的应力值显著减小。虽然从第一金属条30边缘拐角处(B区域)会传递一部分应力到有源层12的掺杂区，但由于有源层12的掺杂区无载流子变化，因此这部分应力不会影响TFT的性能。因此，相对于仅在第一栅极14边缘拐角处一个位置出现应力集中，在根据本公开实施例的发光二极管驱动背板中，本实施例通过设置第一金属条30和第二金属条40，使得出现在第一栅极14边缘的拐角处的应力集中重新分配为同时出现在第一栅极14边缘的拐角处以及第一金属条30和第二金属条40与第一栅极14相邻的边缘拐角处，有效降低了作用在有源层12沟道区的应力，降低了有源层12沟道区界面态及体内陷阱态的改变程度，降低了载流子传输状态以及传输路径的改变程度，进而抑制了关态电流I off升高、亚阈值摆幅SS变大的程度。
由于压阻效应与应力的关系，载流子迁移率与应力的关系可以表示为：
Figure PCTCN2020081839-appb-000002
其中，Δμ＝μ i-μ i0是迁移率的变化量，Δρ i是电阻率分量ρ i的变化量。由上述公式可以看出，在应力作用下，载流子迁移率会发生变化，其相对变化率是压阻系数π ij与应力σ j的乘积。
发明人已知结构中的应力集中仅出现在第一栅极边缘拐角处，应力均作用于该区域，应力值较大。根据本公开实施例的结构中的应力集中分别出现在第一栅极边缘拐角处和第一金属条以及第二金属条的边缘拐角处，应力分别作用于四个区域(第一栅极的左右两侧)，一部分应力加载在第一金属条边缘拐角处，使得第一栅极边缘拐角处的应力值降低，应力集中趋势降低，降低了作用在有源层沟道区的应力，可以降低有源层的载流子迁移率，稳定TFT特性。
图13是平行于基底平面的平面图，示意地示出了根据本公开实施例的第一金属条的位置。如图13所示，第一金属条30位于第一栅极14与第一过孔31之间的区域内，位于第一栅极14与第一过孔的连线上，第二金属条40位于第一栅极14与第二过孔41之间的区域内，位于第一栅极14与第二过孔41之间的连线上。在本公开的一些实施例中，第一金属条30和第二金属条40的宽度L为2.0μm～3.0μm，第一金属条30与第一栅极14之间的间隔距离L1为1.5μm～2μm，第一金属条30与第一过孔31之间的间隔距离L2为1.5μm～2μm。类似地，第二金属条40与第一栅极14之间的间隔距离为1.5μm～2μm，第二金属条40与第二过孔41之间的间隔距离为1.5μm～2μm。在本公开的一些实施例中，L1＝L2。第一金属条30和第二金属条40平行于第一栅极14延伸形成条状，第一金属条30和第二金属条40在该延伸方向上的长度大于或等于有源层12在该方向上的长度。
在本公开的一些实施例中，可以按照第一栅极14与第一过孔31之间的距离设置第一金属条30的宽度。如果第一栅极14与第一过孔31之间的间隔距离为L0，可以设置L＝1/4～1/2*L0，L1＝1/4～1/2*L0。
通过上文描述可以看出，在本公开的实施例中，通过在第一栅极的两侧分别设置第一金属条和第二金属条，第一金属条和第二金属条使得第一栅极边缘拐角处的应力值降低，降低了作用在有源层沟道区的应力，降低了有源层沟道区界面态及体内态的改变程度，降低了载流子传输状态以及传输路径的改变程度，进而抑制了关态电流I off升高、亚阈值摆幅SS变大的程度，稳定了TFT特性，有效克服了相关技术中的转移工艺影响TFT特性的问题。此外，根据本公开实施例的制备发光二极管驱动背板的方法可以利用现有成熟的制备设备，能 够很好地与现有制备工艺兼容，具有工艺简单、易于实现和生产成本低等优点，具有良好的应用前景。
图14为根据本公开的另一个实施例的发光二极管驱动背板的结构示意图。如图14所示，所述发光二极管驱动背板包括基底10和驱动结构，所述驱动结构设置在所述基底10上并包括薄膜晶体管、应力疏解结构、第二栅极和公共电极，其中薄膜晶体管包括有源层12、第一栅极14、源电极19和漏电极18。所述应力疏解结构包括第一金属条30和第二金属条40，所述第一金属条30和所述第二金属条40设置在第一绝缘层13上，并分别位于第一栅极14的第一侧和第二侧，配置为在绑定Micro LED时消除第一栅极14边缘拐角处的应力集中，进而消除作用在有源层12沟道区的应力，其中，第一侧和第二侧相对。在垂直于基底的平面内，第一金属条30和第二金属条40的截面形状为拱形。第一金属条30和第二金属条40的位置、尺寸等参数与参照图13所示的第一金属条30和第二金属条40的位置、尺寸等参数相同。
图15为根据本公开的另一实施例的应力疏解结构受力示意图，为第一栅极的一个边缘拐角区域的放大图。当绑定Micro LED施加的压力传递到第一栅极14和第一金属条30之间区域时，由于第一金属条的截面形状为拱形，拱形圆滑的弧形轮廓是经典力学中支撑结构受力最好、应力最均匀、最不易产生应力集中的形状，因而使得作用在第一栅极与第一金属条之间区域的压力能够得到很好的疏解，且压力主要集中在第二金属条的弧形表面，最大限度地降低了第一栅极边缘的拐角处出现应力集中的概率，即第一栅极边缘的拐角处不易产生应力集中。这样，基本上消除了第一栅极边缘的拐角处的应力集中，基本上消除了从第一栅极边缘拐角处传递到有源层12沟道区的应力，避免了有源层沟道区界面态及体内陷阱态的改变程度，避免了载流子传输状态以及传输路径的改变程度，进而消除了关态电流I off升高、亚阈值摆幅SS变大的情况。
相对于将第一金属条30和第二金属条的垂直于所述基底的横截面设置为矩形的实施例，将第一金属条40和第二金属条垂直于所述基底的横截面设置为拱形的实施例不仅可以获得同样的技术效果，即通过在第一栅极的两侧设置第一金属条40和第二金属条41，第一金属条40和第二金属条41使得第一栅极边缘拐角处的应力值降低，降低了作用在有源层沟道区的应力，抑制了关态电流I off升高、亚阈值摆幅SS变大的程度，稳定了TFT特性；而且由于将第一金属条40和第二金属条41的截面形状设置为拱形，通过圆滑的弧形轮廓，使得作用在 第一栅极与第一金属条40和第二金属条41之间区域的压力能够得到很好的疏解，第一栅极边缘的拐角处不易产生应力集中，基本上消除了第一栅极边缘的拐角处的应力集中，基本上消除了从第一栅极边缘拐角处传递到有源层沟道区的应力，消除了关态电流I off升高、亚阈值摆幅SS变大的情况。
根据本公开实施例的用于制备如图14所示的发光二极管驱动背板制备过程与上述参照图6至图11所示的制备过程基本相同，差异在于，需要将第一金属条和第二金属条的垂直于所述基底的横截面设置为拱形，这可以通过调整刻蚀气体和刻蚀时间等方式来实现，为本领域技术人员所熟知，这里不再赘述。
在前述实施例基础上，基于本公开的技术构思，所述应力疏解结构还可以做多种扩展。例如，虽然前述实施例以第一栅极两侧分别设置第一金属条和第二金属条为例进行了说明，但在工艺条件允许情况下，第一金属条和第二金属条可以设置为多个，通过同时产生多个应力集中点以进一步减小第一栅极边缘拐角处的应力值。又如，在平行于所述第一栅极的方向上，第一金属条可以是条形的一体结构，也可以是由多个块形形成的分体结构，同样可以起到减小或消除第一栅极边缘拐角处应力值的作用。
基于前述实施例的技术构思，本公开的多个实施例还提供了一种发光二极管驱动背板的制备方法。所述制备方法包括：
在基底上形成包括沟道区和第一掺杂区以及第二掺杂区的有源层；
形成覆盖所述有源层的第一绝缘层；
通过一次构图工艺在所述第一绝缘层上形成第一栅极和应力疏解结构，所述应力疏解结构包括分别位于所述第一栅极两侧的第一金属条和第二金属条。
其中，形成第一栅极和应力疏解结构之后，还包括：
形成覆盖所述第一栅极和第一金属条和第二金属条的第二绝缘层；
在所述第二绝缘层上形成第三绝缘层，所述第三绝缘层上设置第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出所述第一掺杂区和所述第二掺杂区；
在所述第三绝缘层上形成源电极和漏电极，所述源电极通过所述第一过孔与所述第一掺杂区连接，所述漏电极通过所述第二过孔与所述第二掺杂区连接，其中，所述第一金属条和所述第二金属条分别位于所述第一栅极与所述第一过孔之间以及所述第一栅极与所述第二过孔之间。
在本公开的一些实施例中，在垂直于基底的平面内，所述第一金属条和所 述第二金属条的截面形状为矩形或拱形。
在本公开的一些实施例中，所述第一金属条和所述第二金属条在平行于所述第一绝缘层并垂直于所述第一栅极的方向上的宽度为2.0μm～3.0μm。
在本公开的一些实施例中，所述第一金属条与所述第一栅极之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第一栅极之间的间隔距离为1.5μm～2μm。
在本公开的一些实施例中，所述第一金属条与所述第一过孔之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第二过孔之间的间隔距离为1.5μm～2μm。
制备根据该实施例的发光二极管驱动背板的方法以及所制备的发光二极管驱动背板的结构等，已在前述实施例中详细说明，这里不再赘述。
在根据该实施例的发光二极管驱动背板的制备方法中，通过在第一栅极的两侧设置分别设置第一金属条和第二金属条，所述第一金属条和所述第二金属条使得第一栅极边缘拐角处的应力值降低，降低了作用在有源层沟道区的应力，降低了有源层沟道区界面态及体内陷阱态的改变程度，降低了载流子传输状态以及传输路径的改变程度，进而抑制了关态电流I off升高、亚阈值摆幅SS变大的程度，稳定了TFT特性，有效克服了相关技术中的转移工艺影响TFT特性的问题。此外，根据该实施例发光二极管驱动背板的制备方法利用现有制备设备即可实现，能够很好地与现有制备工艺兼容，具有工艺简单、易于实现和生产成本低等优点，具有良好的应用前景。
基于同一技术构思，本公开的多种实施例还提供了一种显示装置，包括前述实施例的发光二极管驱动背板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在对本公开的实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在对本公开的实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“绑定”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可 以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种发光二极管驱动背板，其包括基底以及设置在所述基底上的驱动结构，所述驱动结构包括薄膜晶体管和应力疏解结构，所述薄膜晶体管包括设置在基底上的有源层、覆盖所述有源层的第一绝缘层、以及设置在所述第一绝缘层上的第一栅极，所述有源层包括沟道区、第一掺杂区和第二掺杂区，其中，所述应力疏解结构设置在所述第一绝缘层上并包括位于所述第一栅极的第一侧的第一金属条以及位于所述第一栅极的第二侧的第二金属条，所述第一侧和所述第二侧相对。
  2. 根据权利要求1所述的发光二极管驱动背板，其中，在垂直于所述基底的平面内，所述第一金属条和所述第二金属条的截面形状为矩形或拱形。
  3. 根据权利要求1或2所述的发光二极管驱动背板，其中，所述第一金属条和所述第二金属条的宽度为2.0μm～3.0μm。
  4. 根据权利要求1至3中任何一项所述的发光二极管驱动背板，其中，所述第一金属条与所述第一栅极之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第一栅极之间的间隔距离为1.5μm～2μm。
  5. 根据权利要求1至4中任何一项所述的发光二极管驱动背板，其中，所述薄膜晶体管还包括第二绝缘层和第三绝缘层，所述第二绝缘层覆盖所述第一栅极、第一金属条以及第二金属条，所述第三绝缘层设置在所述第二绝缘层上，所述第三绝缘层上设置有第一过孔和第二过孔，所述第一过孔暴露所述第一掺杂区，所述第二过孔暴露所述第二掺杂区；设置在所述第三绝缘层上的源电极和漏电极，所述源电极通过所述第一过孔和所述第一掺杂区连接，和所述漏电极所述第二过孔与所述第二掺杂区连接，使所述第一金属条位于所述第一栅极与第一过孔之间，第二金属条位于所述第一栅极和所述第二过孔之间。
  6. 根据权利要求5所述的发光二极管驱动背板，其中，所述第一金属条与 所述第一过孔之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第二过孔之间的间隔距离为1.5μm～2μm。
  7. 根据权利要求1至6中任何一项所述的发光二极管驱动背板，其中，所述第一金属条在所述基底上的正投影位于所述有源层的所述第一掺杂区在所述基底上的正投影范围内，所述第二金属条在所述基底上的正投影位于所述有源层的所述第二掺杂区在所述基底上的正投影范围内。
  8. 根据权利要求1至6中任何一项所述的发光二极管驱动背板，其中，所述第一金属条和所述第二金属条平行于所述第一栅极延伸，所述第一金属条和所述第二金属条在延伸方向上的长度大于或等于有源层在该方向上的长度。
  9. 一种发光二极管驱动背板的制备方法，其中，包括：
    在基底上形成有源层，所述有源层包括沟道区、第一掺杂区和第二掺杂区；
    形成覆盖所述有源层的第一绝缘层；
    通过同一次构图工艺在所述第一绝缘层上形成第一栅极和应力疏解结构，所述应力疏解结构位于所述第一栅极第一侧的第一金属条以及位于所述第一栅极第二侧的第二金属条。
  10. 根据权利要求9所述的制备方法，其中，在垂直于所述基底的平面内，所述第一金属条和所述第二金属条的截面形状为矩形或拱形。
  11. 根据权利要求9或10所述的制备方法，其中，所述第一金属条和所述第二金属条的宽度为2.0μm～3.0μm。
  12. 根据权利要求9至11中任何一项所述的制备方法，其中，所述第一金属条与所述第一栅极之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第一栅极之间的间隔距离为1.5μm～2μm。
  13. 根据权利要求7所述的制备方法，其还包括：
    形成覆盖所述第一栅极、所述第一金属条以及所述第二金属条的第二绝缘层；
    在所述第二绝缘层上形成第三绝缘层，在所述第三绝缘层上开设第一过孔和第二过孔，所述第一过孔暴露所述第一掺杂区，所述第二过孔暴露所述第二掺杂区；
    在所述第三绝缘层上形成源电极和漏电极，所述源电极通过所述第一过孔与所述第一掺杂区连接，所述漏电极通过所述第二过孔与所述第二掺杂区连接，使所述第一金属条位于所述第一栅极与第一过孔之间，所述第二金属条位于所述第一栅极与所述第二过孔之间。
  14. 根据权利要求13所述的方法，其中，所述第一金属条与所述第一过孔之间的间隔距离为1.5μm～2μm，所述第二金属条与所述第二过孔之间的间隔距离为1.5μm～2μm。
  15. 根据权利要求9至14中任何一项所述的方法，其中，所述第一金属条在所述基底上的正投影位于所述有源层的所述第一掺杂区在所述基底上的正投影范围内，所述第二金属条在所述基底上的正投影位于所述有源层的所述第二掺杂区在所述基底上的正投影范围内。
  16. 根据权利要求9至14中任何一项所述的方法，其中，所述第一金属条和所述第二金属条平行于所述第一栅极延伸，所述第一金属条和所述第二金属条在延伸方向上的长度大于或等于有源层在该方向上的长度。
  17. 一种显示装置，包括如权利要求1～8任一所述的发光二极管驱动背板。
PCT/CN2020/081839 2019-06-05 2020-03-27 发光二极管驱动背板及其制备方法、显示装置 WO2020244292A1 (zh)

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