WO2020237767A1 - 图形化衬底、外延片、制作方法、存储介质及led芯片 - Google Patents

图形化衬底、外延片、制作方法、存储介质及led芯片 Download PDF

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WO2020237767A1
WO2020237767A1 PCT/CN2019/093260 CN2019093260W WO2020237767A1 WO 2020237767 A1 WO2020237767 A1 WO 2020237767A1 CN 2019093260 W CN2019093260 W CN 2019093260W WO 2020237767 A1 WO2020237767 A1 WO 2020237767A1
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patterned substrate
epitaxial
substrate
groove
patterned
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PCT/CN2019/093260
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English (en)
French (fr)
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林伟瀚
杨梅慧
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康佳集团股份有限公司
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Priority to US17/613,762 priority Critical patent/US20220231187A1/en
Publication of WO2020237767A1 publication Critical patent/WO2020237767A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Definitions

  • the present invention relates to the field of LED technology, in particular to a patterned substrate, an epitaxial wafer, a manufacturing method, a storage medium and an LED chip.
  • Micro LED Micro Light Emitting Diode
  • Micro LED miniaturization matrix technology refers to the integration of high-density and small-size LED arrays on a chip; each pixel of the LED display can be addressed and individually driven to light up, Micro LED display
  • the screen can be regarded as a miniature version of an outdoor LED display, reducing the pixel point distance from millimeters to micrometers.
  • Micro LED has many advantages. It has the advantages of inorganic LEDs such as high efficiency, high brightness, high reliability and fast response time. It also has the characteristics of self-luminescence without a backlight, and it has the advantages of energy saving, small size, and simple mechanism.
  • the manufacturing method of Micro LED display is as follows: firstly grow LED micro devices by molecular beam epitaxy on a sapphire substrate (and others such as SiC, Si, etc.), and then transfer the LED light emitting micro devices to a glass substrate. Since the size of the sapphire substrate for making LED micro-devices is basically the size of the silicon wafer, while the size of the glass substrate for making the display is much larger, it must be transported multiple times. Therefore, the core technology of Micro LED is the transportation of nano-level LEDs, not the technology of making LEDs. However, the manufacturing technology will also affect subsequent transportation. For example, to facilitate the transfer of large quantities and improve the yield, it is applied to Micro-LEDs.
  • the wavelength uniformity of the epitaxial wafer is required to be within 1nm, and the current process can only achieve about 3nm.
  • the LED epitaxial wafer is loaded with a substrate in a MOCVD (metal organic chemical vapor deposition) furnace, rotating at high speed in the chamber, using trimethylgallium sources such as TMGa and nitrogen as Ga and N sources, respectively, and ultrapure hydrogen as the carrier With gas, a ternary or quaternary GaN semiconductor layer is epitaxially grown on the substrate.
  • MOCVD metal organic chemical vapor deposition
  • each substrate will always rotate during the growth of the epitaxial layer. However, because of the constant rotation, the centrifugal force will cause uneven thickness on the monolithic epitaxial layer. The uneven thickness of the epitaxial layer will at least Causes uneven wavelength.
  • a patterned substrate applied to a Micro LED wherein the patterned substrate includes a substrate body, and at least one accommodating groove is provided on the substrate body, and the accommodating groove can accommodate at least a portion The epitaxial material dropped during the epitaxial process.
  • the accommodating groove includes: a first groove body in a fan ring shape, and when the patterned substrate is placed at a designated position of the MOCVD carrier, the axis of the first groove body Same as the axis of the carrier.
  • a plurality of supporting pillars are provided on the substrate body, and a containing groove is formed between every two adjacent supporting pillars.
  • a buffer layer is provided on the upper surface of the substrate body, and the containing groove is formed in the buffer layer.
  • An epitaxial board comprising the patterned substrate as described above, the epitaxial board further comprising: an epitaxial layer, and the containing groove is formed between the epitaxial layer and the patterned substrate.
  • a receiving groove is processed on the substrate body or the buffer layer on the upper surface of the substrate body to form a patterned substrate;
  • the patterned substrate is loaded on the carrier in the MOVCD furnace, and processed to generate an epitaxial layer.
  • An LED chip includes the patterned substrate as described above.
  • the patterned substrate provided by the present invention is provided with at least one accommodating groove capable of accommodating at least a part of the epitaxial material dropped during the epitaxial process, so that the patterned substrate is placed in the MOCVD furnace. At least a part of the excess epitaxial material generated during the process of forming the epitaxial layer by internal high-speed rotation can fall into the accommodating groove without remaining on the epitaxial layer, which improves the problem of uneven thickness of the epitaxial layer, thereby increasing the wavelength Uniformity, that is, the patterned substrate provided by the present invention at least improves the problem of uneven wavelength.
  • FIG. 1 is a schematic diagram of the structure of a patterned substrate in a preferred embodiment of the present invention.
  • Figure 2 is a schematic diagram of the structure of an epitaxial wafer in a preferred embodiment of the present invention.
  • FIG. 3 is a top view of the patterned substrate placed in the MOCVD cavity in the preferred embodiment of the present invention.
  • Fig. 4 is a flow chart of a method for manufacturing an epitaxial wafer in a preferred embodiment of the present invention.
  • the patterned substrate 100 provided by the present invention (in FIG. 3, 300 represents the carrier in the MOCVD, and the six circles placed on the carrier 300 represent the patterned substrate 100. It is understood that the carrier 300 can accommodate the number of patterned substrates 100 can be increased or decreased, not limited to six), applied to Micro LED, as shown in Figure 1, Figure 2 and Figure 3, which includes: the substrate body 101, the At least one accommodating groove 103 is provided above the substrate body 101.
  • the accommodating groove 103 has the function of receiving and accommodating the surplus epitaxial material 104 during the forming process of the epitaxial layer 200.
  • the excess epitaxial material 104 will be thrown out of the plane where the unformed epitaxial layer 200 is located along with the rotation of the MOCVD furnace; if the containing groove 103 is not provided, the excess epitaxial material 104 will be thrown out.
  • the epitaxial material 104 will adhere to the unformed epitaxial layer 200, which will eventually cause uneven thickness on the surface of the epitaxial layer 200; when the accommodating groove 103 is provided, part or all of the epitaxial material 104 thrown out It will fall into the accommodating groove 103, so that the problem of uneven thickness of the monolithic epitaxial layer 200 can be improved or solved, thereby improving or solving the problem of uneven wavelength.
  • the accommodating groove 103 can be selectively completed by a photolithography process, so that the accommodating groove 103 can be formed on the patterned substrate 100 according to a preset position to ensure the performance of the epitaxial wafer and the LED chip after molding.
  • the accommodating groove 103 is provided with a plurality of accommodating grooves 103 along the center line of the substrate body 101 (the center line here means that the substrate body 101 can be divided into symmetrical Any straight line of the two semicircles) are arranged in sequence, that is, the plurality of accommodating grooves 103 are arranged in sequence from one side of the substrate body 101 to the other side. Further, the arrangement density of the plurality of accommodating grooves 103 gradually decreases from one side to the other. Specifically, when the patterned substrate 100 is placed in the MOCVD, the accommodating grooves 103 are arranged on the side with a lower density near the other side.
  • the center of the carrier 300, the other side is away from the center of the carrier 300; because the farther from the axis of the carrier 300, the greater the centrifugal force, therefore, when the patterned substrate 100 is placed in the MOCVD internal and epitaxial formation
  • a plurality of supporting pillars 102 are provided on the upper surface of the patterned substrate 100, and a receiving groove 103 is formed between every two supporting pillars 102.
  • the supporting pillars 102 are fan-shaped. Ring. It should be noted that there is no limitation on whether each accommodating groove 103 is connected, that is, the adjacent accommodating grooves 103 may be connected or not connected.
  • the accommodating groove 103 includes: a first groove body in a fan ring shape.
  • the axis of the first groove body The line is the same as the axis line of the carrier 300.
  • the accommodating groove 103 itself has a fan ring shape, or at least a part of it has a fan ring shape, so as to adapt to the ejection law of the epitaxial material, and further improve the epitaxial material receiving capacity of the accommodating groove 103.
  • a buffer layer is provided on the upper surface of the patterned substrate 100, and the containing groove 103 is formed in the buffer layer.
  • the lattice constant of the material of the support pillar 102 matches the lattice constant of the substrate, and a doped nitride material similar to the material of the buffer layer or a silicon-based doped material can be used.
  • the present invention also provides an epitaxial wafer, which includes the patterned substrate 100 as described above, and an epitaxial layer 200 formed on the patterned substrate 100, as shown in FIG. 2 in detail. From the comparison of FIG. 1 and FIG. 2, it can be seen that before the patterned substrate 100 is loaded into the MOVCD furnace, there is no epitaxial material 104 in the accommodating groove 103; and after the epitaxial layer 200 is formed, there remains in the accommodating groove 103 There is an epitaxial material 104. Therefore, the epitaxial wafer is disassembled to check whether the accommodating groove 103 has an epitaxial material 104. It can be known whether the epitaxial wafer is made by the method provided by the present invention.
  • a plurality of patterned substrates 100 are respectively placed on the carrier 300 according to a certain rule, and then the carrier 300 is placed in the MOCVD cavity, and then the patterned substrate of FIG. 2 is grown in the MOCVD cavity.
  • the accommodating groove 103 is annularly distributed on the substrate body 101 in a plan view, and the center of the ring of the accommodating groove 103 coincides with the center of the carrier 300 in the MOCVD chamber. In this way, during the epitaxial growth process, each substrate 100 rotates at a high speed with the chamber carrier 300, and the centrifugal force generated by the rotation causes the epitaxial layer 200 material to expand to the side.
  • the excess epitaxial material 104 falls into the ring groove In 103, the thickness distribution and flatness of the epitaxial growth layer on the substrate are made uniform.
  • the epitaxial wafer is then subjected to a chip segment process to produce a special chip for Micro-LED.
  • the pattern structure layer groove distribution shape on the surface of the substrate is a concentric ring centered on the center of the MOCVD cavity, and the radii of the concentric rings are arranged at unequal intervals, but the accommodating grooves of each substrate are from the normal direction of the cavity center Beyond 103, the density gradually increases.
  • the material thickness and flatness of the epitaxial layer 200 are uniform, so that the manufactured Micro LED chip has a concentrated wavelength range and uniform brightness and color coordinates. It is conducive to the subsequent huge transfer of Micro-LEDs, and improves product efficiency and yield.
  • the epitaxial layer includes: an undoped GaN layer, an N-type doped layer, a current spreading layer, an MQW active region, a P-type AlGaN layer, and a P-type layer.
  • a current flows, the electrons in the N-type region and the holes in the P-type region enter the MQW active region and recombine, emitting visible light in the desired wavelength range.
  • the epitaxial layer includes: a buffer layer, an undoped GaN layer, an N-type doped layer, a current spreading layer, an MQW active region, a P-type AlGaN layer, and a P-type layer.
  • the specific structure of the epitaxial layer can form different differential structures according to the different patterned materials on the substrate.
  • the present invention also provides a method for manufacturing the epitaxial wafer as described above, which includes the steps:
  • a receiving groove is processed on the patterned substrate or the buffer layer on the upper surface of the patterned substrate, as described in the foregoing patterned substrate and epitaxial wafer embodiments.
  • the present invention also provides an LED chip, the LED chip includes the above-mentioned patterned substrate, and the manufacturing method is as follows:
  • a receiving groove is processed on the patterned substrate or the buffer layer on the upper surface of the patterned substrate, as described in the foregoing patterned substrate and epitaxial wafer embodiments.
  • the present invention also provides a storage medium on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the above-mentioned epitaxial wafer manufacturing method are realized.
  • Non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (SyNchliNk) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

Abstract

本发明涉及一种图形化衬底、外延片、制作方法、存储介质及LED芯片，所述图形化衬底应用于Micro LED，由于其本体上设置有至少一个可容置至少一部分外延过程中掉落的外延材料的容置槽。本发明所提供的图形化衬底，在MOCVD炉内高速旋转成型外延层的过程中所产生的多余外延材料，至少一部分可掉落至容置槽内，而不会残留在外延层上，改善了外延层厚度不均匀的问题，进而提高了波长均匀性，即本发明所提供的图形化衬底至少改善了波长不均匀的问题。

Description

图形化衬底、外延片、制作方法、存储介质及LED芯片 技术领域
本发明涉及LED技术领域，特别是涉及一种图形化衬底、外延片、制作方法、存储介质及LED芯片。
背景技术
Micro LED(微型发光二极管)技术，即LED微缩化矩阵化技术，指的是在一个芯片上集成高密度微小尺寸的LED阵列；LED显示屏每一个像素可定址、单独驱动点亮，Micro LED显示屏可看成是户外LED显示屏的微缩版，将像素点距离从毫米降低至微米级。
Micro LED的优点非常多，它具有无机LED的高效率、高亮度、高可靠度及反应时间快等优点，并且具有自发光无需背光源的特性，更具有节能、体积小、机构简易等优势。
通常，Micro LED显示器的制作方法为：先在蓝宝石类(还有其他如SiC、Si等)的基板上通过分子束外延生长出来LED微器件，然后把LED发光微器件转移到玻璃基板上。由于制作LED微器件的蓝宝石基板尺寸基本上就是硅晶元的尺寸，而制作显示器则是尺寸大得多的玻璃基板，因此必然需要进行多次转运。因此，Micro LED的核心技术是纳米级LED的转运，而不是制作LED这个技术本身，但制作技术同样会对后续转运产生影响，比如：为方便巨量转移，提高良率，应用于Micro-LED的外延片波长均匀性要求在1nm以内，目前的工艺只能做到3nm左右。
LED外延片是将衬底装载在MOCVD(金属有机化学气相沉积)炉中，在腔室内高速旋转，以TMGa等三甲基镓源和氮气分别作为Ga源和N源，以超纯氢气作为载气，在衬底上外延生长出三元或四元GaN类半导体层。
为了腔室内各衬底外延层均匀，各衬底在外延层生长过程中会一直旋转，但因为一直旋转，离心力的作用使单片外延层上厚度会产生不均，外延层厚度不均至少会导致波长的不均匀。
可见，现有技术还有待于改进和发展。
发明内容
基于此，有必要针对上述技术问题，提供一种图形化衬底、外延片、制作方法、存储介质及LED芯片，旨在解决现有技术中LED外延板在MOCVD炉内高速旋转导致外延层厚度不均匀，从而导致波长不均匀的问题。
本发明的技术方案如下：
一种图形化衬底，应用于Micro LED，其中，所述图形化衬底包括：衬底本体，所述衬底本体上设置有至少一个容置槽，所述容置槽可容置至少一部分外延过程中掉落的外延材料。
在进一步地优选方案中，所述容置槽包括：呈扇环形的第一槽体，当所述图形化衬底放置于MOCVD的载体的指定位置时，所述第一槽体的轴心线与所述载体的轴心线相同。
在进一步地优选方案中，所述容置槽设置有多个，多个容置槽沿所述衬底本体的中心线依次排布，且排布密度由一端向另一端依次递减。
在进一步地优选方案中，所述衬底本体上设置有多个支撑柱体，每两个相邻的支撑柱体之间形成有一个容置槽。
在进一步地优选方案中，所述衬底本体的上表面设置有缓冲层，所述容置槽形成于所述缓冲层。
一种包括如上所述图形化衬底的外延板，所述外延板还包括：外延层，所述容置槽形成于所述外延层与图形化衬底之间。
一种如上所述外延片的制作方法，其中，所述制作方法包括步骤：
根据预设的图形化制程，在衬底本体或衬底本体上表面的缓冲层上加工出容置槽，形成图形化衬底；
将所述图形化衬底装载至MOVCD炉内的载体上，并加工生成外延层。
一种存储介质，所述存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的制作方法的步骤。
一种LED芯片，所述LED芯片包括如上所述的图形化衬底。
与现有技术相比，本发明提供的图形化衬底，由于其本体上设置有至少一个可容置至少一部分外延过程中掉落的外延材料的容置槽，使得图形化衬底在MOCVD炉内高速旋转成型外延层的过程中所产生的多余外延材料，至少一部分可 掉落至容置槽内，而不会残留在外延层上，改善了外延层厚度不均匀的问题，进而提高了波长均匀性，即本发明所提供的图形化衬底至少改善了波长不均匀的问题。
附图说明
图1为本发明优选实施例中图形化衬底的结构示意图。
图2为本发明优选实施例中外延片的结构示意图。
图3为本发明优选实施例中图形化衬底在MOCVD腔内摆放方式俯视图。
图4为本发明优选实施例中外延片制作方法的流程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明所提供的图形化衬底100(在图3中，300表示MOCVD内的载体，放置在所述载体300上的六个圆即表示图形化衬底100，可以理解的是，所述载体300可容置图形化衬底100的数量可增可减，绝不仅限于六个)，应用于Micro LED，如图1、图2及图3所示，其包括：衬底本体101，所述衬底本体101的上方设置有至少一个容置槽103，所述容置槽103具有接收容纳外延层200成型过程中多余外延材料104的功能，即若通过MOCVD炉成型外延层200，则在图形化衬底100随MOCVD炉高速旋转时，会有多余的外延材料104随着MOCVD炉的旋转被甩出未成型外延层200所在平面；在未设置容置槽103的情况下，被甩出的外延材料104将附着于未成型的外延层200，最终导致外延层200的表面产生厚度不均匀的现象；在设置有容置槽103的情况下，被甩出的外延材料104中的一部分或者全部会掉落至容置槽103，从而可以改善或者解决单片外延层200厚度不均匀的问题，进而改善或解决波长不均匀的问题。
在具体实施时，所述容置槽103可以选择通过光刻制程完成，以便容置槽103可以根据预设位置形成于所述图形化衬底100，保证成型后外延片及LED芯片的性能。
作为本发明的优选实施例，所述容置槽103设置有多个，多个容置槽103沿衬底本体101的中心线(此处的中心线是指能够将衬底本体101分割为对称的两个半圆的任一直线)依次排布，也就是说，多个容置槽103由衬底本体101的一侧向另一侧依次排布。进一步地，多个容置槽103的排布密度由一侧向另一侧依次递减，具体地，当图形化衬底100放置于MOCVD内时，容置槽103设置密度小的一侧靠近所述载体300的中心，另一侧则背离所述载体300的中心；由于离所述载体300的轴心线越远，离心力越大，因此，当图形化衬底100被放置于MOCVD内外延形成外延层200的过程中，容置槽103的密度越大，所能收容的外延材料越多，形成的外延片的厚度均匀度越高，波长均匀度越好。
优选所述图形化衬底100上表面设置有多个支撑柱体102，而每两个支撑柱体102之间形成有一个容置槽103，较佳地是，所述支撑柱体102呈扇环形。需要注意的是，各个容置槽103之间并不限定是否相连通，即相邻容置槽103之间可以连通，也可以不连通。
较佳地是，所述容置槽103包括：呈扇环形的第一槽体，当所述图形化衬底100放置于所述载体300的指定位置时，所述第一槽体的轴心线与所述载体300的轴心线相同。也就是说，所述容置槽103本身呈扇环形，或者至少一部分呈扇环形，以适配于外延材料的甩出规律，进一步提高容置槽103的外延材料接收能力。
较佳地是，所述图形化衬底100上表面设置有缓冲层，所述容置槽103形成于所述缓冲层。优选所述支撑柱体102的材料的晶格常数与衬底的晶格常数匹配，可使用缓冲层材料类似的掺杂氮化物材料，或者硅基掺杂材料。
本发明还提供了一种外延片，所述外延片包括如上所述的图形化衬底100，以及形成于所述图形化衬底100上方的外延层200，具体如图2所示。由图1及图2的对比可知，在图形化衬底100上料至MOVCD炉之前，容置槽103内是没有外延材料104的；而在外延层200成型之后，容置槽103内余留有外延材料104，因此，拆解外延片查看容置槽103是是否有外延材料104，可知外延片是否通过本发明所提供的方法制作而成。
如图3所示，多个图形化衬底100按照一定的规律分别摆放在所述载体300上，然后将所述载体300放置在MOCVD的腔体内，而后在MOCVD腔室内生长出图 2的外延层200。容置槽103在俯视方向为环形分布在衬底本体101上，容置槽103环形的圆心与MOCVD腔室内载体300的圆心重合。这样外延生长过程中，各衬底100随着腔室载体300高速旋转，旋转产生的离心力使外延层200材料往边上扩，往外扩的过程中多余的外延材料104掉落在环形容置槽103内，使得衬底上的外延生长层厚度分布及平整度均匀。生长完成后的外延片再进行芯片段工艺，制出Micro-LED专用的芯片。
其中，衬底表面的图形结构层凹槽分布形状为以MOCVD腔体中心为圆心的同心环，同心环的半径不等间距排列，但是从腔体的圆心法线方向各衬底的容置槽103往外，密度逐渐加密。
由于本发明实施例所提供的外延片，外延层200材料厚度和平整度均匀，使得制出的Micro LED芯片波长段集中，亮度和色坐标均匀。利于Micro-LED后续的巨量转移，提高产品效率和良率。
作为本发明的优选实施例，所述外延层包括：非掺杂GaN层、N型掺杂层、电流扩展层、MQW有源区、P型AlGaN层及P型层。当有电流通过时，N型区的电子和P型区的空穴进入MQW有源区并且复合，发出我们需要波段的可见光。
作为本发明的另一优选实施例，所述外延层包括：缓冲层、未掺杂的GaN层、N型掺杂层、电流扩展层、MQW有源区、P型AlGaN层及P型层。
可以理解的是，外延层的具体结构可以根据衬底上图形化材料的不同而形成不同的差异结构。
如图4所示，本发明还提供了一种如上所述外延片的制作方法，该制作方法包括步骤：
S100、根据预设的图形化制程，在图形化衬底或图形化衬底上表面的缓冲层上加工出容置槽，具体如上述图形化衬底及外延片实施例所述。
S200、将加工出容置槽的图形化衬底装载至MOVCD炉内的腔室载体上，并加工生成外延层，具体如上述图形化衬底及外延片实施例所述。
本发明还提供了一种LED芯片，所述LED芯片包括如上所述的图形化衬底，其制作方法如下所述：
S100、根据预设的图形化制程，在图形化衬底或图形化衬底上表面的缓冲层上加工出容置槽，具体如上述图形化衬底及外延片实施例所述。
S200、将加工出容置槽的图形化衬底装载至MOVCD炉内的腔室载体上，并加工生成外延层，具体如上述图形化衬底及外延片实施例所述。
S300、利用生成外延层后的外延片，根据预设的芯片加工制程，制作LED芯片，此为现有技术，本发明在此不再赘述。
本发明还提供了一种存储介质，其上存储有计算机程序，其中，所述计算机程序被处理器执行时实现如上所述的外延片制作方法的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本发明所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(SyNchliNk)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种图形化衬底，应用于Micro LED，其特征在于，所述图形化衬底包括：衬底本体，所述衬底本体上设置有至少一个容置槽，所述容置槽可容置至少一部分外延过程中掉落的外延材料。
  2. 根据权利要求1所述的图形化衬底，其特征在于，所述容置槽包括：呈扇环形的第一槽体，当所述图形化衬底放置于MOCVD的载体的指定位置时，所述第一槽体的轴心线与所述载体的轴心线相同。
  3. 根据权利要求1所述的图形化衬底，其特征在于，所述容置槽设置有多个，多个容置槽沿所述衬底本体的中心线依次排布，且排布密度由一端向另一端依次递减。
  4. 根据权利要求1所述的图形化衬底，其特征在于，所述衬底本体上设置有多个支撑柱体，每两个相邻的支撑柱体之间形成有一个容置槽。
  5. 根据权利要求1至4中任意一项所述的图形化衬底，其特征在于，所述衬底本体的上表面设置有缓冲层，所述容置槽形成于所述缓冲层。
  6. 根据权利要求1至4中任意一项所述的图形化衬底，其特征在于，所述容置槽通过光刻制程完成。
  7. 一种包括如权利要求1至5中任意一项所述图形化衬底的外延板，其特征在于，所述外延板还包括：外延层，所述容置槽形成于所述外延层与图形化衬底之间。
  8. 一种如权利要求7所述外延片的制作方法，其特征在于，所述制作方法包括步骤：
    根据预设的图形化制程，在衬底本体或衬底本体上表面的缓冲层上加工出容置槽，形成图形化衬底；
    将所述图形化衬底装载至MOVCD炉内的载体上，并加工生成外延层。
  9. 一种存储介质，所述存储介质上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求8所述的制作方法的步骤。
  10. 一种LED芯片，其特征在于，所述LED芯片包括如权利要求1至6中任意一项所述的图形化衬底。
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