WO2020224110A1 - 用于显示屏的驱动电路 - Google Patents

用于显示屏的驱动电路 Download PDF

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Publication number
WO2020224110A1
WO2020224110A1 PCT/CN2019/102963 CN2019102963W WO2020224110A1 WO 2020224110 A1 WO2020224110 A1 WO 2020224110A1 CN 2019102963 W CN2019102963 W CN 2019102963W WO 2020224110 A1 WO2020224110 A1 WO 2020224110A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
pull
unit
reverse
Prior art date
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Ceased
Application number
PCT/CN2019/102963
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English (en)
French (fr)
Inventor
薛炎
韩佰祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020224110A1 publication Critical patent/WO2020224110A1/zh
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • This application relates to the field of electronic display, and in particular to a driving circuit for a display screen.
  • the response time of blue phase liquid crystal is sub-millimeter level. Compared with other types of displays, a display using blue phase liquid crystal has a simple manufacturing process, a wide viewing angle, and a fast response time.
  • the driving voltage of the blue phase liquid crystal is relatively high (greater than 30V), and the driving voltage output by the matched driving circuit is also relatively high.
  • the potential of the output signal of the drive circuit is determined by the potential of the clock signal and the trigger signal. An increase in the potential of the clock signal will greatly increase the power consumption of the drive circuit and the crosstalk between signals.
  • the present application provides a driving circuit for a display screen, which can greatly reduce the power consumption of the driving circuit and reduce the crosstalk between signals.
  • a driving circuit for a display screen which includes:
  • a pull-up unit the pull-up unit is used to convert a clock signal into a stage transmission signal, and convert a DC voltage signal into an output signal;
  • a pull-up control unit the pull-up control unit is used to control the opening time of the pull-up unit
  • Bootstrap capacitor the bootstrap capacitor is used to boost the stage transmission signal and output signal voltage
  • a pull-down unit which is used to pull the output voltage of the bootstrap capacitor to a low level
  • a pull-down sustaining unit configured to pull and maintain the output voltage of the bootstrap capacitor to a low potential
  • An inverter which is used to make the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down sustaining unit opposite;
  • the feedback unit is used to increase the output voltage of the pull-down unit.
  • the pull-up unit includes a first pull-up unit and a second pull-up unit
  • the first pull-up unit includes a first pull-up thin film transistor, a second pull-up thin film transistor, and a third pull-up thin film transistor; wherein,
  • the source of the first pull-up thin film transistor is connected to a first DC voltage, the drain is connected to the pull-down unit, and the gate is connected to the gate of the second pull-up thin film transistor and the drain of the third pull-up thin film transistor;
  • the source of the second pull-up thin film transistor is connected to the first DC voltage, and the drain is connected to a plate of the bootstrap capacitor;
  • the source electrode of the third pull-up thin film transistor is connected to the second direct current voltage, the gate electrode is connected to the stage signal of the previous stage, and the drain electrode is connected to the other plate of the bootstrap capacitor;
  • the second pull-up unit includes a fourth pull-up thin film transistor, the source of the fourth pull-up thin film transistor is connected to the second clock signal, the gate is connected to the bootstrap capacitor, and the drain is connected to the third DC voltage.
  • the first pull-up thin film transistor and the third pull-up thin film transistor are N-type thin film transistors
  • the second and fourth pull-up thin film transistors are P-type thin film transistors.
  • the pull-up control unit includes a first control thin film transistor and a second control thin film transistor; wherein,
  • the source of the first control thin film transistor is connected to the previous stage transmission signal, the gate is connected to the first clock signal, and the drain is connected to the source of the second control thin film transistor;
  • the gate of the second control thin film transistor is connected to the first clock signal, and the drain is connected to the pull-down sustain unit.
  • the first control thin film transistor and the second control thin film transistor are N-type thin film transistors.
  • the pull-down unit includes a first pull-down unit and a second pull-down unit; wherein,
  • the first pull-down unit includes a first pull-down thin film transistor, the source of the first pull-down thin film transistor is connected to the first pull-up unit, the gate is connected to the next stage signal, and the drain is connected to the The third DC voltage;
  • the second pull-down unit includes a second pull-down thin film transistor and a third pull-down thin film transistor;
  • the source of the second pull-down thin film transistor is connected to the bootstrap capacitor, the gate is connected to the next-stage stage signal, and the drain is connected to the source of the third pull-down thin film transistor;
  • the gate of the third pull-down thin film transistor is connected to the next stage signal, and the drain is connected to the third DC voltage.
  • the first pull-down thin film transistor and the third pull-down thin film transistor are N-type thin film transistors, and the second pull-down thin film transistor is a P-type thin film transistor.
  • the pull-down maintaining unit includes a first pull-down maintaining unit and a second pull-down maintaining unit; wherein,
  • the first pull-down sustain unit includes a first sustain thin film transistor, a second sustain thin film transistor, and a third sustain thin film transistor;
  • the source of the first sustaining thin film transistor is connected to the first pull-up unit, the gate is connected to the gate of the second sustaining thin film transistor, and the drain is connected to the third DC voltage;
  • the source of the second sustaining thin film transistor is connected to the second pull-up unit, and the drain is connected to the third DC voltage;
  • the source of the third sustaining thin film transistor is connected to the bootstrap capacitor, and the drain is connected to the third DC voltage;
  • the second pull-down sustain unit includes a fifth sustain thin film transistor and a sixth sustain thin film transistor;
  • the source of the fifth sustaining thin film transistor is connected to the pull-up control unit, the gate is connected to the inverter, and the drain is connected to the source of the sixth sustaining thin film transistor;
  • the gate of the sixth sustain thin film transistor is connected to the inverter, and the drain is connected to the third DC voltage.
  • the first sustain thin film transistor, the third sustain thin film transistor, the fifth sustain thin film transistor, and the sixth sustain thin film transistor are N-type thin film transistors, and the second sustain thin film transistor is a P-type thin film transistor. Transistor.
  • the inverter includes a first inverter and a second inverter; wherein,
  • the first inverter includes a first reverse thin film transistor, a second reverse thin film transistor, a third reverse thin film transistor, and a fourth reverse thin film transistor;
  • the source and gate of the first reverse thin film transistor are connected to the second pull-down unit, and the drain is connected to the source of the second reverse thin film transistor;
  • the gate of the second reverse thin film transistor is connected to the second pull-down unit, and the drain is connected to the third DC voltage;
  • the source of the third reverse thin film transistor is connected to the second pull-down unit, the gate is connected to the drain of the first reverse thin film transistor, and the drain is connected to the source of the fourth reverse thin film transistor;
  • the gate of the fourth reverse thin film transistor is connected to the gate of the second reverse thin film transistor, and the drain is connected to the third direct current voltage;
  • the second inverter includes a fifth reverse thin film transistor, a sixth reverse thin film transistor, a seventh reverse thin film transistor, and an eighth reverse thin film transistor;
  • the gate and source of the fifth reverse thin film transistor are connected to the feedback unit, and the drain is connected to the source of the sixth reverse thin film transistor;
  • the gate of the sixth reverse thin film transistor is connected to the second pull-up unit, and the drain is connected to the third DC voltage;
  • the source of the seventh reverse thin film transistor is connected to the feedback unit, the gate is connected to the drain of the fifth reverse thin film transistor, and the drain is connected to the source of the eighth reverse thin film transistor;
  • the gate of the eighth reverse thin film transistor is connected to the gate of the sixth reverse thin film transistor, and the drain is connected to the third DC voltage.
  • the first reverse thin film transistor, the third reverse thin film transistor, the fourth reverse thin film transistor, the fifth reverse thin film transistor, the seventh reverse thin film transistor, and the eighth reverse thin film transistor The transistor is an N-type thin film transistor; the second and sixth reverse thin film transistors are P-type thin film transistors.
  • the feedback unit includes a feedback thin film transistor, the source of the feedback thin film transistor is connected to the first pull-up unit, the drain is connected to the pull-up control unit, and the gate is connected to the current stage.
  • Level transmission signal the source of the feedback thin film transistor is connected to the first pull-up unit, the drain is connected to the pull-up control unit, and the gate is connected to the current stage.
  • the feedback thin film transistor is an N-type thin film transistor.
  • the bootstrap capacitor includes a first storage capacitor and a second storage capacitor; wherein,
  • One plate of the first storage capacitor is connected to the first pull-up unit, and the other plate is connected to the pull-down maintenance unit;
  • One plate of the second storage capacitor is connected to the second pull-up unit, and the other plate is connected to the second pull-down unit.
  • the drive circuit provided in the present application can raise the voltage of the clock signal, so that the drive circuit can output a high voltage for driving blue phase liquid crystal while maintaining a low voltage value of the voltage signal of the internal node, which can greatly reduce the power consumption of the drive circuit , And reduce crosstalk between signals.
  • FIG. 1 is a circuit diagram of a driving circuit in a specific embodiment of the application
  • FIG. 2 is a timing diagram of driving signals in the driving circuit in FIG. 1;
  • FIG. 3 is a schematic diagram of a simulation result of the driving circuit in a specific embodiment of the application.
  • the present application provides a driving circuit for a display screen, as shown in FIG. 1, which includes: a pull-up unit M2, the pull-up unit M2 is used to convert a clock signal into a stage transmission signal, and convert a DC voltage signal Is the output signal; pull-up control unit M1, the pull-up control unit M1 is used to control the open time of the pull-up unit M2; bootstrap capacitor, the bootstrap capacitor is used to raise the stage transmission signal and output signal Voltage; pull-down unit M3, the pull-down unit M3 is used to pull down the output voltage of the bootstrap capacitor to a low level; pull-down maintenance unit M4, the pull-down maintenance unit M4 is used to pull the output voltage of the bootstrap capacitor to maintain low An inverter M5, the inverter M5 is used to make the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down maintenance unit M4 opposite; and a feedback unit M6, the feedback unit M6 is used to increase the pull-down unit The output voltage of M3.
  • the pull-up unit M2 includes a first pull-up unit M21 and a second pull-up unit M22.
  • the first pull-up unit M21 includes a first pull-up thin film transistor T21, a second pull-up thin film transistor T22, and a third pull-up thin film transistor T23.
  • the source of the first pull-up thin film transistor T21 is connected to the first DC voltage VDD
  • the drain is connected to the pull-down unit M3
  • the gate is connected to the gate of the second pull-up thin film transistor T22 and the third pull-up thin film transistor Drain of T23.
  • the source of the second pull-up thin film transistor T22 is connected to the first DC voltage VDD, and the drain is connected to a plate of the bootstrap capacitor.
  • the source electrode of the third pull-up thin film transistor T23 is connected to the second direct current voltage VDDH, the gate electrode is connected to the previous stage transmission signal, and the drain electrode is connected to the other plate of the bootstrap capacitor.
  • the second pull-up unit M22 includes a fourth pull-up thin film transistor T24. The source of the fourth pull-up thin film transistor T24 is connected to the second clock signal, the gate is connected to the bootstrap capacitor, and the drain is connected to the third direct current. Voltage VGL.
  • the first pull-up thin film transistor T21 and the third pull-up thin film transistor T23 are N-type thin film transistors
  • the second pull-up thin film transistor T22 and the fourth pull-up thin film transistor T24 are P-type thin film transistors.
  • the pull-up control unit M1 includes a first control thin film transistor T11 and a second control thin film transistor T12. Wherein, the source of the first control thin film transistor T11 is connected to the previous stage transmission signal, the gate is connected to the first clock signal, and the drain is connected to the source of the second control thin film transistor T12; the second control The gate of the thin film transistor T12 is connected to the first clock signal, and the drain is connected to the pull-down sustain unit M4.
  • the first control thin film transistor T11 and the second control thin film transistor T12 are N-type thin film transistors.
  • the pull-down unit M3 includes a first pull-down unit M31 and a second pull-down unit M32.
  • the first pull-down unit M31 includes a first pull-down thin film transistor T31
  • the source of the first pull-down thin film transistor T31 is connected to the first pull-up unit M21
  • the gate is connected to the next stage pass Signal
  • the drain is connected to the third DC voltage VGL.
  • the second pull-down unit M32 includes a second pull-down thin film transistor T32 and a third pull-down thin film transistor T33.
  • the source of the second pull-down thin film transistor T32 is connected to the bootstrap capacitor, the gate is connected to the next stage signal, and the drain is connected to the source of the third pull-down thin film transistor T33.
  • the gate of the third pull-down thin film transistor T33 is connected to the next-stage stage signal, and the drain is connected to the third DC voltage VGL.
  • the first pull-down thin film transistor T31 and the third pull-down thin film transistor T33 are N-type thin film transistors, and the second pull-down thin film transistor T32 is a P-type thin film transistor.
  • the pull-down maintenance unit M4 includes a first pull-down maintenance unit M41 and a second pull-down maintenance unit M42.
  • the first pull-down sustain unit M41 includes a first sustain thin film transistor T41, a second sustain thin film transistor T42, and a third sustain thin film transistor T43.
  • the source of the first sustain thin film transistor T41 is connected to the first pull-up unit M21, the gate is connected to the gate of the second sustain thin film transistor T42, and the drain is connected to the third DC voltage VGL.
  • the source of the second sustain thin film transistor T42 is connected to the second pull-up unit M22, and the drain is connected to the third DC voltage VGL.
  • the source of the third sustaining thin film transistor T43 is connected to the bootstrap capacitor, and the drain is connected to the third DC voltage VGL.
  • the second pull-down sustain unit M42 includes a fifth sustain thin film transistor T45 and a sixth sustain thin film transistor T46.
  • the source of the fifth sustain thin film transistor T45 is connected to the pull-up control unit M1, the gate is connected to the inverter M5, and the drain is connected to the source of the sixth sustain thin film transistor T46.
  • the gate of the sixth sustain thin film transistor T46 is connected to the inverter M5, and the drain is connected to the third DC voltage VGL.
  • the first sustain thin film transistor T41 and the third sustain thin film transistor T43, the fifth sustain thin film transistor T45 and the sixth sustain thin film transistor T46 are N-type thin film transistors, and the second sustain thin film transistor T42 is a P-type thin film transistor. Transistor.
  • the inverter M5 includes a first inverter M51 and a second inverter M52.
  • the first inverter M51 includes a first reverse thin film transistor T51, a second reverse thin film transistor T52, a third reverse thin film transistor T53, and a fourth reverse thin film transistor T54.
  • the source and gate of the first reverse thin film transistor T51 are connected to the second pull-down unit M32, and the drain is connected to the source of the second reverse thin film transistor T52.
  • the gate of the second reverse thin film transistor T52 is connected to the second pull-down unit M32, and the drain is connected to the third DC voltage VGL.
  • the source of the third reverse thin film transistor T53 is connected to the second pull-down unit M32, the gate is connected to the drain of the first reverse thin film transistor T51, and the drain is connected to the fourth reverse thin film transistor T54. Source.
  • the gate of the fourth reverse thin film transistor T54 is connected to the gate of the second reverse thin film transistor T52, and the drain is connected to the third DC voltage VGL.
  • the second inverter M52 includes a fifth reverse thin film transistor T55, a sixth reverse thin film transistor T56, a seventh reverse thin film transistor T57, and an eighth reverse thin film transistor T58.
  • the gate and source of the fifth reverse thin film transistor T55 are connected to the feedback unit M6, and the drain is connected to the source of the sixth reverse thin film transistor T56.
  • the gate of the sixth reverse thin film transistor T56 is connected to the second pull-up unit M22, and the drain is connected to the third DC voltage VGL.
  • the source of the seventh reverse thin film transistor T57 is connected to the feedback unit M6, the gate is connected to the drain of the fifth reverse thin film transistor T55, and the drain is connected to the source of the eighth reverse thin film transistor T58. .
  • the gate of the eighth reverse thin film transistor T58 is connected to the gate of the sixth reverse thin film transistor T56, and the drain is connected to the third DC voltage VGL.
  • the transistor T58 is an N-type thin film transistor
  • the second reverse thin film transistor T52 and the sixth reverse thin film transistor T56 are P-type thin film transistors.
  • the feedback unit M6 includes a feedback thin film transistor T6.
  • the source of the feedback thin film transistor T6 is connected to the first pull-up unit M21, the drain is connected to the pull-up control unit M1, and the gate is connected to the stage transmission signal of the current stage.
  • the feedback thin film transistor T6 is an N-type thin film transistor.
  • the bootstrap capacitor includes a first storage capacitor Cbt1 and a second storage capacitor Cbt2. Wherein, one plate of the first storage capacitor Cbt1 is connected to the first pull-up unit M21, and the other plate is connected to the pull-down maintenance unit M4. One plate of the second storage capacitor Cbt2 is connected to the second pull-up unit M22, and the other plate is connected to the second pull-down unit M32.
  • FIG. 2 is a timing diagram of driving signals in the driving circuit in FIG. 1;
  • FIG. 3 is a schematic diagram of a simulation result of the driving circuit in a specific embodiment of the application.
  • CK1 is the first clock signal
  • CK2 is the second clock signal
  • the waveforms of the first clock signal CK1 and the second clock signal CK2 are opposite.
  • COUT(n) is the level transmission signal of this level
  • COUT(n-1) is the level transmission signal of the upper level
  • Cout(n+1) is the level transmission signal of the next level.
  • the working cycle of the driving circuit in this embodiment includes a first phase T1, a second phase T2, and a third phase T3.
  • the first stage when the first clock signal CK1 is at a high potential, the first control thin film transistor T11 and the second control thin film transistor T12 are turned on, COUT(n-1) is a high potential, and the potential of point Q is raised to a high potential.
  • the fourth pull-up thin film transistor T24, the second reverse thin film transistor T52, and the fourth reverse thin film transistor T54 are turned on, and QB is pulled down to a low potential.
  • the transistor T45 and the sixth maintaining thin film transistor T46 are turned off. Since the second clock signal CK2 is at a low level, the stage transfer signal COUT(n) of this stage is at a low level.
  • the sixth reverse thin film transistor T56 and the eighth reverse thin film transistor T58 Closed, point P is pulled up to a high potential, the first sustaining thin film transistor T41 and the second sustaining thin film transistor T42 are turned on, the previous stage transfer signal COUT (n-1) is at a high potential, and the third pull-up thin film transistor T23 is turned on , The potential at point M is pulled to a high potential, the first pull-up thin film transistor T21 and the second pull-up thin film transistor T22 are turned on. Since the second sustain thin film transistor T42 and the first sustain thin film transistor T41 are turned on, the point N and the output signal G(n ) Remains low.
  • the second stage when the first clock signal CK1 is at a low level, the first control thin film transistor T11 and the second control thin film transistor T12 are turned off, the fourth pull-up thin film transistor T24 is turned on, and CK2 becomes a high potential, and the level signal COUT (n) becomes a high potential. Therefore, the potential of point Q is pulled up to a higher potential, which is beneficial to turning on the fourth pull-up thin film transistor T24.
  • the feedback thin film transistor T6, the sixth reverse thin film transistor T56, and the eighth reverse thin film transistor T58 are turned on, and the point F rises to a high potential, which is beneficial to reduce the second control thin film transistor T12.
  • the fifth sustaining thin film transistors T45 and T32 leak current and maintain the potential at point Q.
  • Point P drops to a low potential.
  • the first sustain thin film transistor T41 and the second sustain thin film transistor T42 are turned off, and the point N is raised to a high potential. Due to the existence of the second storage capacitor Cbt2, the potential at point M is pulled up to a higher potential.
  • the first pull-up thin film transistor T21 and the second pull-up thin film transistor T22 are turned on, and the potential at point N and the output signal gradually rise to a high potential.
  • the first clock signal CK1 rises to a high potential
  • the first control thin film transistor T11 and the second control thin film transistor T12 are turned on, because the previous stage transfer signal COUT(n-1) is at a low potential, point Q The potential is pulled down to a low potential.
  • the fourth pull-up thin film transistor T24, the second reverse thin film transistor T52, and the fourth reverse thin film transistor T54 are turned off, and the QB point rises to a high potential.
  • the third sustain thin film transistor T43, the fourth sustain thin film transistor T44, the fifth sustain thin film transistor T45, and the sixth sustain thin film transistor T46 are turned on, and the stage transfer signal COUT(n) drops to a low level.
  • the sixth reverse thin film transistor T56, the eighth reverse thin film transistor T58 and the feedback thin film transistor T6 are turned off, and point P rises to a high potential.
  • the first sustaining thin film transistor T41 and the second sustaining thin film transistor T42 are turned on, and the level transfer signal COUT(n+1) of the next stage rises to a high level.
  • T31 is turned on, and the level transmission signal drops to a low level.
  • the drive circuit provided in the present application can raise the voltage of the clock signal, so that the drive circuit can output a high voltage for driving blue phase liquid crystal while maintaining a low voltage value of the voltage signal of the internal node, which can greatly reduce the power consumption of the drive circuit , And reduce crosstalk between signals.

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Abstract

一种用于显示屏的驱动电路，其包括：上拉单元（M2），所述上拉单元（M2）用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；上拉控制单元（M1），所述上拉控制单元（M1）用于控制所述上拉单元（M2）的打开时间；自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；下拉单元（M3），所述下拉单元（M3）用于将自举电容的输出电压拉低为低电位；下拉维持单元（M4），所述下拉维持单元（M4）用于将自举电容的输出电压拉保持为低电位；反相器（M5），所述反相器（M5）用于使所述自举电容的输出电压和下拉维持单元（M4）的输出电压电位相反；以及反馈单元（M6），所述反馈单元（M6）用于提高下拉单元（M3）的输出电压。

Description

用于显示屏的驱动电路 技术领域
本申请涉及电子显示领域，尤其涉及一种用于显示屏的驱动电路。
 背景技术
蓝相液晶的响应时间为亚毫米级。相比于其他类型的显示器，应用蓝相液晶的显示器制备工艺简单、视角广、响应时间快。
 技术问题
蓝相液晶的驱动电压相对较高（大于30V），与之匹配的驱动电路输出的驱动电压也相对较高。驱动电路的输出信号的电位由时钟信号及触发信号的电位决定，时钟信号的电位增加，会极大的增加驱动电路的功耗和信号之间的串扰。
 技术解决方案
本申请提供一种用于显示屏的驱动电路，能够大幅度降低驱动电路的功耗，并且减小信号之间的串扰。
为解决上述问题，本申请提供了一种用于显示屏的驱动电路，其包括：
上拉单元，所述上拉单元用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；
上拉控制单元，所述上拉控制单元用于控制所述上拉单元的打开时间；
自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；
下拉单元，所述下拉单元用于将自举电容的输出电压拉低为低电位；
下拉维持单元，所述下拉维持单元用于将自举电容的输出电压拉保持为低电位；
反相器，所述反相器用于使所述自举电容的输出电压和下拉维持单元的输出电压电位相反；以及
反馈单元，所述反馈单元用于提高下拉单元的输出电压。
根据本申请的其中一个方面，所述上拉单元包括第一上拉单元和第二上拉单元；
所述第一上拉单元包括第一上拉薄膜晶体管、第二上拉薄膜晶体管和第三上拉薄膜晶体管；其中，
所述第一上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述下拉单元，栅极连接第二上拉薄膜晶体管的栅极和第三上拉薄膜晶体管的漏极；
所述第二上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的一个极板；
所述第三上拉薄膜晶体管的源极连接第二直流电压，栅极连接上一级的级传信号，漏极连接所述自举电容的另一个极板；
所述第二上拉单元包括第四上拉薄膜晶体管，所述第四上拉薄膜晶体管的源极连接第二时钟信号，栅极连接所述自举电容，漏极连接第三直流电压。
根据本申请的其中一个方面，所述第一上拉薄膜晶体管和第三上拉薄膜晶体管为N型薄膜晶体管，所述第二上拉薄膜晶体管和第四上拉薄膜晶体管为P型薄膜晶体管。
根据本申请的其中一个方面，所述上拉控制单元包括第一控制薄膜晶体管和第二控制薄膜晶体管；其中，
所述第一控制薄膜晶体管的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管的源极；
所述第二控制薄膜晶体管的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元。
根据本申请的其中一个方面，所述第一控制薄膜晶体管和第二控制薄膜晶体管为N型薄膜晶体管。
根据本申请的其中一个方面，所述下拉单元包括第一下拉单元和第二下拉单元；其中，
所述第一下拉单元包括第一下拉薄膜晶体管，所述第一下拉薄膜晶体管的源极连接所述第一上拉单元，栅极连接下一级的级传信号，漏极连接所述第三直流电压；
所述第二下拉单元包括第二下拉薄膜晶体管和第三下拉薄膜晶体管；
所述第二下拉薄膜晶体管的源极连接所述自举电容，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管的源极；
所述第三下拉薄膜晶体管的栅极连接下一级的级传信号，漏极连接所述第三直流电压。
根据本申请的其中一个方面，所述第一下拉薄膜晶体管和第三下拉薄膜晶体管为N型薄膜晶体管，所述第二下拉薄膜晶体管为P型薄膜晶体管。
根据本申请的其中一个方面，所述下拉维持单元包括第一下拉维持单元和第二下拉维持单元；其中，
所述第一下拉维持单元包括第一维持薄膜晶体管、第二维持薄膜晶体管和第三维持薄膜晶体管；
所述第一维持薄膜晶体管的源极连接所述第一上拉单元，栅极连接所述第二维持薄膜晶体管的栅极，漏极连接所述第三直流电压；
所述第二维持薄膜晶体管的源极连接所述第二上拉单元，漏极连接所述第三直流电压；
所述第三维持薄膜晶体管的源极连接所述自举电容，漏极连接所述第三直流电压；
所述第二下拉维持单元包括第五维持薄膜晶体管和第六维持薄膜晶体管；
所述第五维持薄膜晶体管的源极连接所述上拉控制单元，栅极连接所述反相器，漏极连接所述第六维持薄膜晶体管的源极；
所述第六维持薄膜晶体管的栅极连接所述反相器，漏极连接所述第三直流电压。
根据本申请的其中一个方面，所述第一维持薄膜晶体管和第三维持薄膜晶体管、第五维持薄膜晶体管和第六维持薄膜晶体管为N型薄膜晶体管，所述第二维持薄膜晶体管为P型薄膜晶体管。
根据本申请的其中一个方面，所述反相器包括第一反相器和第二反相器；其中，
所述第一反相器包括第一反向薄膜晶体管、第二反向薄膜晶体管、第三反向薄膜晶体管和第四反向薄膜晶体管；
所述第一反向薄膜晶体管的源极和栅极连接所述第二下拉单元，漏极连接所述第二反向薄膜晶体管的源极；
所述第二反向薄膜晶体管的栅极连接所述第二下拉单元，漏极连接所述第三直流电压；
所述第三反向薄膜晶体管的源极连接所述第二下拉单元，栅极连接所述第一反向薄膜晶体管的漏极，漏极连接所述第四反向薄膜晶体管的源极；
所述第四反向薄膜晶体管的栅极连接所述第二反向薄膜晶体管的栅极，漏极连接所述第三直流电压；
所述第二反相器包括第五反向薄膜晶体管、第六反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管；
所述第五反向薄膜晶体管的栅极和源极连接所述反馈单元，漏极连接所述第六反向薄膜晶体管的源极；
所述第六反向薄膜晶体管的栅极连接所述第二上拉单元，漏极连接所述第三直流电压；
所述第七反向薄膜晶体管的源极连接所述反馈单元，栅极连接所述第五反向薄膜晶体管的漏极，漏极连接所述第八反向薄膜晶体管的源极；
所述第八反向薄膜晶体管的栅极连接所述第六反向薄膜晶体管的栅极，漏极连接所述第三直流电压。
根据本申请的其中一个方面，所述第一反向薄膜晶体管、第三反向薄膜晶体管、第四反向薄膜晶体管、第五反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管为N型薄膜晶体管；所述第二反向薄膜晶体管和第六反向薄膜晶体管为P型薄膜晶体管。
根据本申请的其中一个方面，所述反馈单元包括反馈薄膜晶体管，所述反馈薄膜晶体管的源极连接所述第一上拉单元，漏极连接所述上拉控制单元，栅极连接本级的级传信号。
根据本申请的其中一个方面，所述反馈薄膜晶体管为N型薄膜晶体管。
根据本申请的其中一个方面，所述自举电容包括第一存储电容和第二存储电容；其中，
所述第一存储电容的一个极板连接所述第一上拉单元，另一个极板连接所述下拉维持单元；
所述第二存储电容的一个极板连接所述第二上拉单元，另一个极板连接所述第二下拉单元。
 有益效果
本申请提供的驱动电路能够抬高时钟信号的电压，使得驱动电路在内部节点的电压信号保持较低电压值的同时输出用于驱动蓝相液晶的高电压，能够大幅度降低驱动电路的功耗，并且减小信号之间的串扰。
 附图说明
图1为本申请的一个具体实施例中的驱动电路的电路图；
图2为图1中的驱动电路中的驱动信号的时序图；
图3为本申请的一个具体实施例中的驱动电路的仿真结果示意图。
本申请的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供了一种用于显示屏的驱动电路，如图1所示，其包括：上拉单元M2，所述上拉单元M2用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；上拉控制单元M1，所述上拉控制单元M1用于控制所述上拉单元M2的打开时间；自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；下拉单元M3，所述下拉单元M3用于将自举电容的输出电压拉低为低电位；下拉维持单元M4，所述下拉维持单元M4用于将自举电容的输出电压拉保持为低电位；反相器M5，所述反相器M5用于使所述自举电容的输出电压和下拉维持单元M4的输出电压电位相反；以及反馈单元M6，所述反馈单元M6用于提高下拉单元M3的输出电压。
所述上拉单元M2包括第一上拉单元M21和第二上拉单元M22。所述第一上拉单元M21包括第一上拉薄膜晶体管T21、第二上拉薄膜晶体管T22和第三上拉薄膜晶体管T23。其中，所述第一上拉薄膜晶体管T21的源极连接第一直流电压VDD，漏极连接所述下拉单元M3，栅极连接第二上拉薄膜晶体管T22的栅极和第三上拉薄膜晶体管T23的漏极。所述第二上拉薄膜晶体管T22的源极连接第一直流电压VDD，漏极连接所述自举电容的一个极板。所述第三上拉薄膜晶体管T23的源极连接第二直流电压VDDH，栅极连接上一级的级传信号，漏极连接所述自举电容的另一个极板。所述第二上拉单元M22包括第四上拉薄膜晶体管T24，所述第四上拉薄膜晶体管T24的源极连接第二时钟信号，栅极连接所述自举电容，漏极连接第三直流电压VGL。
优选的，所述第一上拉薄膜晶体管T21和第三上拉薄膜晶体管T23为N型薄膜晶体管，所述第二上拉薄膜晶体管T22和第四上拉薄膜晶体管T24为P型薄膜晶体管。
所述上拉控制单元M1包括第一控制薄膜晶体管T11和第二控制薄膜晶体管T12。其中，所述第一控制薄膜晶体管T11的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管T12的源极；所述第二控制薄膜晶体管T12的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元M4。
所述第一控制薄膜晶体管T11和第二控制薄膜晶体管T12为N型薄膜晶体管。
所述下拉单元M3包括第一下拉单元M31和第二下拉单元M32。其中，所述第一下拉单元M31包括第一下拉薄膜晶体管T31，所述第一下拉薄膜晶体管T31的源极连接所述第一上拉单元M21，栅极连接下一级的级传信号，漏极连接所述第三直流电压VGL。所述第二下拉单元M32包括第二下拉薄膜晶体管T32和第三下拉薄膜晶体管T33。所述第二下拉薄膜晶体管T32的源极连接所述自举电容，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管T33的源极。所述第三下拉薄膜晶体管T33的栅极连接下一级的级传信号，漏极连接所述第三直流电压VGL。
优选的，所述第一下拉薄膜晶体管T31和第三下拉薄膜晶体管T33为N型薄膜晶体管，所述第二下拉薄膜晶体管T32为P型薄膜晶体管。
所述下拉维持单元M4包括第一下拉维持单元M41和第二下拉维持单元M42。其中，所述第一下拉维持单元M41包括第一维持薄膜晶体管T41、第二维持薄膜晶体管T42和第三维持薄膜晶体管T43。所述第一维持薄膜晶体管T41的源极连接所述第一上拉单元M21，栅极连接所述第二维持薄膜晶体管T42的栅极，漏极连接所述第三直流电压VGL。所述第二维持薄膜晶体管T42的源极连接所述第二上拉单元M22，漏极连接所述第三直流电压VGL。所述第三维持薄膜晶体管T43的源极连接所述自举电容，漏极连接所述第三直流电压VGL。所述第二下拉维持单元M42包括第五维持薄膜晶体管T45和第六维持薄膜晶体管T46。所述第五维持薄膜晶体管T45的源极连接所述上拉控制单元M1，栅极连接所述反相器M5，漏极连接所述第六维持薄膜晶体管T46的源极。所述第六维持薄膜晶体管T46的栅极连接所述反相器M5，漏极连接所述第三直流电压VGL。
优选的，所述第一维持薄膜晶体管T41和第三维持薄膜晶体管T43、第五维持薄膜晶体管T45和第六维持薄膜晶体管T46为N型薄膜晶体管，所述第二维持薄膜晶体管T42为P型薄膜晶体管。
所述反相器M5包括第一反相器M51和第二反相器M52。
其中，所述第一反相器M51包括第一反向薄膜晶体管T51、第二反向薄膜晶体管T52、第三反向薄膜晶体管T53和第四反向薄膜晶体管T54。所述第一反向薄膜晶体管T51的源极和栅极连接所述第二下拉单元M32，漏极连接所述第二反向薄膜晶体管T52的源极。所述第二反向薄膜晶体管T52的栅极连接所述第二下拉单元M32，漏极连接所述第三直流电压VGL。所述第三反向薄膜晶体管T53的源极连接所述第二下拉单元M32，栅极连接所述第一反向薄膜晶体管T51的漏极，漏极连接所述第四反向薄膜晶体管T54的源极。所述第四反向薄膜晶体管T54的栅极连接所述第二反向薄膜晶体管T52的栅极，漏极连接所述第三直流电压VGL。
所述第二反相器M52包括第五反向薄膜晶体管T55、第六反向薄膜晶体管T56、第七反向薄膜晶体管T57和第八反向薄膜晶体管T58。所述第五反向薄膜晶体管T55的栅极和源极连接所述反馈单元M6，漏极连接所述第六反向薄膜晶体管T56的源极。所述第六反向薄膜晶体管T56的栅极连接所述第二上拉单元M22，漏极连接所述第三直流电压VGL。所述第七反向薄膜晶体管T57的源极连接所述反馈单元M6，栅极连接所述第五反向薄膜晶体管T55的漏极，漏极连接所述第八反向薄膜晶体管T58的源极。所述第八反向薄膜晶体管T58的栅极连接所述第六反向薄膜晶体管T56的栅极，漏极连接所述第三直流电压VGL。
优选的，所述第一反向薄膜晶体管T51、第三反向薄膜晶体管T53、第四反向薄膜晶体管T54、第五反向薄膜晶体管T55、第七反向薄膜晶体管T57和第八反向薄膜晶体管T58为N型薄膜晶体管；所述第二反向薄膜晶体管T52和第六反向薄膜晶体管T56为P型薄膜晶体管。
所述反馈单元M6包括反馈薄膜晶体管T6，所述反馈薄膜晶体管T6的源极连接所述第一上拉单元M21，漏极连接所述上拉控制单元M1，栅极连接本级的级传信号。优选的，所述反馈薄膜晶体管T6为N型薄膜晶体管。
所述自举电容包括第一存储电容Cbt1和第二存储电容Cbt2。其中，所述第一存储电容Cbt1的一个极板连接所述第一上拉单元M21，另一个极板连接所述下拉维持单元M4。所述第二存储电容Cbt2的一个极板连接所述第二上拉单元M22，另一个极板连接所述第二下拉单元M32。
下面将结合具体的实施例对本申请中的驱动电路的工作原理进行详细说明。参见图2和图3，图2为图1中的驱动电路中的驱动信号的时序图；图3为本申请的一个具体实施例中的驱动电路的仿真结果示意图。
其中，CK1为第一时钟信号，CK2为第二时钟信号，第一时钟信号CK1和第二时钟信号CK2的波形相反。COUT(n)为本级的级传信号；COUT(n-1)为上一级的级传信号；Cout(n+1)为下一级的级传信号。
参见图3，本实施例中的驱动电路的工作周期包括第一阶段T1，第二阶段T2和第三阶段T3。
第一阶段时：当第一时钟信号CK1处于高电位时，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12打开，COUT(n-1)为高电位，Q点电位被抬升为高电位，第四上拉薄膜晶体管T24、第二反向薄膜晶体管T52及第四反向薄膜晶体管T54打开，QB被拉低至低电位第三维持薄膜晶体管T43、第四维持薄膜晶体管T44、第五维持薄膜晶体管T45和第六维持薄膜晶体管T46关闭，由于第二时钟信号CK2为低电位，本级的级传信号COUT(n)为低电位，第六反向薄膜晶体管T56与第八反向薄膜晶体管T58关闭，P点被拉升至高电位，第一维持薄膜晶体管T41与第二维持薄膜晶体管T42打开，上一级的级传信号COUT (n-1)为高电位，第三上拉薄膜晶体管T23打开，M点电位被拉至高电位，第一上拉薄膜晶体管T21与第二上拉薄膜晶体管T22打开，由于第二维持薄膜晶体管T42与第一维持薄膜晶体管T41打开，N点与输出讯号G(n)仍然维持低电位。
第二阶段时：当第一时钟信号CK1处于低电位时，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12关闭，第四上拉薄膜晶体管T24打开，CK2变为高电位，级传讯号COUT (n)变为高电位，因此，Q点电位被上拉至更高电位，有利于第四上拉薄膜晶体管T24打开。同时反馈薄膜晶体管T6、第六反向薄膜晶体管T56与第八反向薄膜晶体管T58管打开，点F升至高电位，有利于减少第二控制薄膜晶体管T12。第五维持薄膜晶体管T45及T32管漏电，维持Q 点电位。P点降为低电位。第一维持薄膜晶体管T41与第二维持薄膜晶体管T42关闭，N点被抬升至高电位。由于第二存储电容Cbt2的存在，M点电位被上拉至更高电位。第一上拉薄膜晶体管T21与第二上拉薄膜晶体管T22打开，N点电位与输出信号也逐渐升至高电位。
第三阶段时：第一时钟信号CK1升为高电位，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12打开，由于上一级的级传信号COUT(n-1)为低电位，Q点电位被拉低至低电位。第四上拉薄膜晶体管T24、第二反向薄膜晶体管T52和第四反向薄膜晶体管T54关闭，QB点升至高电位。第三维持薄膜晶体管T43、第四维持薄膜晶体管T44、第五维持薄膜晶体管T45和第六维持薄膜晶体管T46打开，级传信号COUT(n)降至低电位。第六反向薄膜晶体管T56与第八反向薄膜晶体管T58及反馈薄膜晶体管T6关闭，P点升为高电位。第一维持薄膜晶体管T41与第二维持薄膜晶体管T42打开，下一级的级传信号COUT(n+1)升为高电位。T31打开，级传信号降为低电位。
本申请提供的驱动电路能够抬高时钟信号的电压，使得驱动电路在内部节点的电压信号保持较低电压值的同时输出用于驱动蓝相液晶的高电压，能够大幅度降低驱动电路的功耗，并且减小信号之间的串扰。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种用于显示屏的驱动电路，其中，所述驱动电路包括：
    上拉单元，所述上拉单元用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；
    上拉控制单元，所述上拉控制单元用于控制所述上拉单元的打开时间；
    自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；
    下拉单元，所述下拉单元用于将自举电容的输出电压拉低为低电位；
    下拉维持单元，所述下拉维持单元用于将自举电容的输出电压拉保持为低电位；
    反相器，所述反相器用于使所述自举电容的输出电压和下拉维持单元的输出电压电位相反；以及
    反馈单元，所述反馈单元用于提高下拉单元的输出电压。
  2. 根据权利要求1所述的驱动电路，其中，所述上拉单元包括第一上拉单元和第二上拉单元；
    所述第一上拉单元包括第一上拉薄膜晶体管、第二上拉薄膜晶体管和第三上拉薄膜晶体管；其中，
    所述第一上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述下拉单元，栅极连接第二上拉薄膜晶体管的栅极和第三上拉薄膜晶体管的漏极；
    所述第二上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的一个极板；
    所述第三上拉薄膜晶体管的源极连接第二直流电压，栅极连接上一级的级传信号，漏极连接所述自举电容的另一个极板；
    所述第二上拉单元包括第四上拉薄膜晶体管，所述第四上拉薄膜晶体管的源极连接第二时钟信号，栅极连接所述自举电容，漏极连接第三直流电压。
  3. 根据权利要求2所述的驱动电路，其中，所述第一上拉薄膜晶体管和第三上拉薄膜晶体管为N型薄膜晶体管，所述第二上拉薄膜晶体管和第四上拉薄膜晶体管为P型薄膜晶体管。
  4. 根据权利要求2所述的驱动电路，其中，所述上拉控制单元包括第一控制薄膜晶体管和第二控制薄膜晶体管；其中，
    所述第一控制薄膜晶体管的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管的源极；
    所述第二控制薄膜晶体管的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元。
  5. 根据权利要求2所述的驱动电路，其中，所述第一控制薄膜晶体管和第二控制薄膜晶体管为N型薄膜晶体管。
  6. 根据权利要求4所述的驱动电路，其中，所述下拉单元包括第一下拉单元和第二下拉单元；其中，
    所述第一下拉单元包括第一下拉薄膜晶体管，所述第一下拉薄膜晶体管的源极连接所述第一上拉单元，栅极连接下一级的级传信号，漏极连接所述第三直流电压；
    所述第二下拉单元包括第二下拉薄膜晶体管和第三下拉薄膜晶体管；
    所述第二下拉薄膜晶体管的源极连接所述自举电容，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管的源极；
    所述第三下拉薄膜晶体管的栅极连接下一级的级传信号，漏极连接所述第三直流电压。
  7. 根据权利要求6所述的驱动电路，其中，所述第一下拉薄膜晶体管和第三下拉薄膜晶体管为N型薄膜晶体管，所述第二下拉薄膜晶体管为P型薄膜晶体管。
  8. 根据权利要求6所述的驱动电路，其中，所述下拉维持单元包括第一下拉维持单元和第二下拉维持单元；其中，
    所述第一下拉维持单元包括第一维持薄膜晶体管、第二维持薄膜晶体管和第三维持薄膜晶体管；
    所述第一维持薄膜晶体管的源极连接所述第一上拉单元，栅极连接所述第二维持薄膜晶体管的栅极，漏极连接所述第三直流电压；
    所述第二维持薄膜晶体管的源极连接所述第二上拉单元，漏极连接所述第三直流电压；
    所述第三维持薄膜晶体管的源极连接所述自举电容，漏极连接所述第三直流电压；
    所述第二下拉维持单元包括第五维持薄膜晶体管和第六维持薄膜晶体管；
    所述第五维持薄膜晶体管的源极连接所述上拉控制单元，栅极连接所述反相器，漏极连接所述第六维持薄膜晶体管的源极；
    所述第六维持薄膜晶体管的栅极连接所述反相器，漏极连接所述第三直流电压。
  9. 根据权利要求8所述的驱动电路，其中，所述第一维持薄膜晶体管和第三维持薄膜晶体管、第五维持薄膜晶体管和第六维持薄膜晶体管为N型薄膜晶体管，所述第二维持薄膜晶体管为P型薄膜晶体管。
  10. 根据权利要求8所述的驱动电路，其中，所述反相器包括第一反相器和第二反相器；其中，
    所述第一反相器包括第一反向薄膜晶体管、第二反向薄膜晶体管、第三反向薄膜晶体管和第四反向薄膜晶体管；
    所述第一反向薄膜晶体管的源极和栅极连接所述第二下拉单元，漏极连接所述第二反向薄膜晶体管的源极；
    所述第二反向薄膜晶体管的栅极连接所述第二下拉单元，漏极连接所述第三直流电压；
    所述第三反向薄膜晶体管的源极连接所述第二下拉单元，栅极连接所述第一反向薄膜晶体管的漏极，漏极连接所述第四反向薄膜晶体管的源极；
    所述第四反向薄膜晶体管的栅极连接所述第二反向薄膜晶体管的栅极，漏极连接所述第三直流电压；
    所述第二反相器包括第五反向薄膜晶体管、第六反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管；
    所述第五反向薄膜晶体管的栅极和源极连接所述反馈单元，漏极连接所述第六反向薄膜晶体管的源极；
    所述第六反向薄膜晶体管的栅极连接所述第二上拉单元，漏极连接所述第三直流电压；
    所述第七反向薄膜晶体管的源极连接所述反馈单元，栅极连接所述第五反向薄膜晶体管的漏极，漏极连接所述第八反向薄膜晶体管的源极；
    所述第八反向薄膜晶体管的栅极连接所述第六反向薄膜晶体管的栅极，漏极连接所述第三直流电压。
  11. 根据权利要求10所述的驱动电路，其中，所述第一反向薄膜晶体管、第三反向薄膜晶体管、第四反向薄膜晶体管、第五反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管为N型薄膜晶体管；所述第二反向薄膜晶体管和第六反向薄膜晶体管为P型薄膜晶体管。
  12. 根据权利要求10所述的驱动电路，其中，所述反馈单元包括反馈薄膜晶体管，所述反馈薄膜晶体管的源极连接所述第一上拉单元，漏极连接所述上拉控制单元，栅极连接本级的级传信号。
  13. 根据权利要求10所述的驱动电路，其中，所述反馈薄膜晶体管为N型薄膜晶体管。
  14. 根据权利要求12所述的驱动电路，其中，所述自举电容包括第一存储电容和第二存储电容；其中，
    所述第一存储电容的一个极板连接所述第一上拉单元，另一个极板连接所述下拉维持单元；
    所述第二存储电容的一个极板连接所述第二上拉单元，另一个极板连接所述第二下拉单元。
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