WO2020215426A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2020215426A1
WO2020215426A1 PCT/CN2019/088054 CN2019088054W WO2020215426A1 WO 2020215426 A1 WO2020215426 A1 WO 2020215426A1 CN 2019088054 W CN2019088054 W CN 2019088054W WO 2020215426 A1 WO2020215426 A1 WO 2020215426A1
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Prior art keywords
thin film
stage
film transistor
goa
scan signal
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PCT/CN2019/088054
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English (en)
French (fr)
Inventor
薛炎
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/608,307 priority Critical patent/US11355067B2/en
Publication of WO2020215426A1 publication Critical patent/WO2020215426A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display technology, and in particular to an array substrate.
  • OLED display devices can be divided into passive matrix OLED (Passive Matrix OLED, PMOLED) and active matrix OLED (Active MatrixOLED, AMOLED) two categories.
  • PMOLED Passive Matrix OLED
  • AMOLED Active MatrixOLED
  • pixels arranged in an array is an active display type, has high luminous efficiency, and is generally used as a high-definition large-size display device.
  • large-size AMOELD panel pixels generally adopt an external compensation scheme.
  • the external compensation scheme requires the GOA circuit in the array substrate to output an ultra-wide pulse signal (>3ms), so in the output stage, the first node (Q) of the GOA circuit needs to be maintained for a long time Wide pulse, and the Q point is in a floating state at this time. If the leakage current of the thin film transistor TFT is large, the Q point cannot maintain a high potential for a long time, and GOA cannot output an ultra-wide pulse.
  • the GOA circuit can theoretically output a pulse width of 3ms. But in fact, the Q point cannot maintain a high voltage for a long time. Therefore, the GOA circuit cannot output a wide pulse. At this time, the actual pulse width of the GOA circuit is 2ms; and because the pulse width of the GOA circuit is less than 3ms, the circuit level transmission will also Invalidate.
  • the present invention provides an array substrate, which can facilitate the realization of GOA ultra-wide pulse output in the compensation stage, so as to solve the problem that the existing array substrate has a large leakage current of TFT, the Q point cannot maintain a long-term high potential, and the GOA cannot output an ultra-wide pulse Technical issues.
  • the present invention provides an array substrate, which includes a GOA circuit and a plurality of And logic gate units integrated at the back end of the GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA units, each of the GOA units includes a scan signal terminal, and at least three consecutive GOA units are connected to one And logic gate unit through the scan signal terminal.
  • n be a natural number, and the GOA unit of the nth level outputs the nth level scan signal
  • the scan signal of the n-1th stage, the scan signal of the nth stage, and the scan signal of the n+1th stage are input signals of the And logic gate unit of the n-1th stage;
  • the scan signal of the nth stage, the scan signal of the n+1th stage, and the scan signal of the n+2th stage are input signals of the And logic gate unit of the nth stage.
  • m is a natural number
  • the GOA circuit includes m GOA units (m>n)
  • the GOA units of the m-1th and mth levels are virtual GOA unit.
  • the n-th level And logic gate unit circuit includes six thin film transistors, a first DC low voltage, a second DC low voltage, a DC high voltage, a WR control signal and an And logic gate. output signal;
  • the gate of the first thin film transistor is connected to the DC high voltage, and the source and drain are respectively connected to the output signal of the And logic gate of the nth stage and the gate of the second thin film transistor;
  • the source and drain of the second thin film transistor are respectively connected to the DC high voltage and the gate of the third thin film transistor;
  • the source and drain of the third thin film transistor are respectively connected to the second direct current low voltage and the n-th stage And logic gate output signal;
  • the gate of the fourth thin film transistor is connected to the scan signal of the nth stage, and the source and drain are respectively connected to the WR control signal and the first DC low voltage;
  • the gate of the fifth thin film transistor is connected to the scan signal of the n+1th stage, and the source and drain are respectively connected to the WR control signal and the first DC low voltage;
  • the gate of the sixth thin film transistor is connected to the scan signal of the n+2th stage, and the source and drain are respectively connected to the WR control signal and the first DC low voltage.
  • the scan signal of the nth stage is at a high potential
  • the sixth thin film transistor is turned on
  • the WR control signal is at a low potential
  • the third thin film transistor is turned off
  • the The first thin film transistor is turned on, and the output signal of the And logic gate of the nth stage outputs a high potential.
  • the scan signal at the nth stage is at a low potential
  • the scan signal at the n+1th stage is at a high potential
  • the fifth thin film transistor is turned on
  • the sixth thin film transistor Closed
  • the WR control signal is at a low level
  • the And logic gate output signal of the nth stage outputs a high level.
  • the scan signal at the n+1th stage is at a low potential
  • the scan signal at the n+2th stage is at a high potential
  • the sixth thin film transistor is turned on
  • the fifth The thin film transistor is turned off
  • the WR control signal is at a low level
  • the And logic gate output signal of the nth stage outputs a high level.
  • the scan signal of the n+2th stage is at a low level
  • the fourth thin film transistor is turned off
  • the WR control signal is at a high potential
  • the third thin film transistor is turned on
  • the output signal of the And logic gate of the nth stage outputs a low level.
  • the second DC low voltage is greater than the first DC low voltage.
  • the GOA circuit is a GOA circuit prepared based on IGZO material.
  • the array substrate of the present invention includes a GOA circuit and a plurality of And logic gate units integrated in the back end of the GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit includes a scanning signal terminal, At least three consecutive GOA units are connected to an And logic gate unit through the scan signal terminal; when the circuit is working, at least three consecutive GOA units can be raised to a high potential one after another, so that the output signal terminal of the And logic gate unit can maintain longer The high potential of time;
  • the array substrate of the present invention can reduce the output pulse width of the GOA circuit, and the reduction of the pulse width is beneficial to reduce the leakage current of the first node (Q), which is beneficial to obtain a stable GOA output signal, and the GOA circuit can be normal Grade pass.
  • Figure 1 is a signal waveform diagram of a conventional array substrate
  • FIG. 2 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of an array substrate provided by an embodiment of the present invention.
  • FIG. 5 is a signal waveform diagram when the array substrate provided by an embodiment of the present invention outputs a narrow pulse
  • FIG. 6 is a schematic circuit diagram of a 31st level GOA unit of an array substrate provided by an embodiment of the present invention.
  • FIG. 7 is a signal waveform diagram of the 31st level GOA unit of the array substrate provided by an embodiment of the present invention.
  • the present invention addresses the technical problem of the existing array substrate that due to the large leakage current of the TFT, the Q point cannot maintain a high potential for a long time, and the GOA cannot output an ultra-wide pulse. This embodiment can solve this defect.
  • the present invention provides an array substrate.
  • the array substrate includes a GOA circuit and a plurality of And logic gate units integrated at the back end of the GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA units, Each GOA unit includes a scanning signal terminal, and at least three consecutive GOA units are connected to one And logic gate unit through the scanning signal terminal.
  • a pulse width of 3ms can be obtained by connecting a multi-level GOA unit to an And logic gate unit, and finally the output pulse width of the GOA circuit can be reduced to 1ms.
  • the number of GOA units connected to the And logic gate unit can be more.
  • the pulse width of the GOA circuit can be reduced. The reduction of the pulse width of the GOA circuit is conducive to reducing the leakage current of the Q point, and reducing the leakage current of the Q point can obtain a stable GOA output signal, and at the same time can ensure the normal level transmission of the GOA circuit.
  • n be a natural number
  • the GOA unit of the nth stage outputs the nth stage scan signal
  • the n-1th stage scan signal, the nth stage scan signal, and the n+1th stage scan signal are the n-th stage
  • the input signal of the And logic gate unit of level 1; the scan signal of the nth level, the scan signal of the n+1 level, and the scan signal of the n+2 level are the inputs of the logic gate unit of the nth level signal.
  • the GOA circuit includes m GOA units (m>n), and the GOA units at the m-1th and mth levels are virtual GOA units.
  • the last two levels of GOA units are virtual GOA units. On the one hand, they provide feedback signals for the upper level of GOA units, and on the other hand, they provide signal sources for the last level of And logic gate units.
  • the GOA units are connected to one of the And logic gate units.
  • the m-2, m-1, and mth levels are virtual GOA units, and the virtual GOA units are The upper level GOA unit provides feedback signals and at the same time provides a signal source for the last level And logic gate unit. If the number of GOA units connected is 5 or more, the same rules apply.
  • FIG. 3 is a circuit diagram of the And logic gate of the present invention.
  • the n-th level And logic gate unit circuit includes six thin film transistors, a first DC low voltage VGL1, a second DC low voltage VGL2, a DC high voltage VGH, WR control signals and The nth stage And logic gate output signal Out(n); wherein, the gate of the first thin film transistor T1 is connected to the DC high voltage, and the source and drain are respectively connected to the nth stage And logic gate output signal and the second The gate of the thin film transistor T2; the source and drain of the second thin film transistor T2 are respectively connected to the DC high voltage and the gate of the third thin film transistor T3; the source and drain of the third thin film transistor T3 are respectively connected to the The second DC low voltage and the output signal of the And logic gate of the nth stage; the gate of the fourth thin film transistor T4 is connected to the scan signal of the nth stage, and the source and drain are respectively connected to the WR control signal and the first A direct current low voltage; the gate
  • T4, T5, and T6 are connected to the scan signals of the GOA units of the nth, n+1, and n+2 stages; the WR control signal is an internal control signal in the And logic circuit.
  • Fig. 4 is a signal waveform diagram of the n-th And logic gate of the present invention.
  • the wide pulse working process of the n-th And logic gate circuit can be divided into four stages:
  • the scanning signal of the nth stage rises to a high potential
  • the sixth thin film transistor is turned on
  • the WR control signal is a low potential
  • the third thin film transistor is turned off
  • the first thin film transistor is turned on
  • the nth thin film transistor is turned on.
  • the output signal of the And logic gate outputs a high level.
  • the scan signal of the nth stage drops to a low level, the scan signal of the n+1th stage is high, the fifth thin film transistor is turned on, the sixth thin film transistor is turned off, and the WR control signal is The output signal of the And logic gate of the nth stage outputs a high potential.
  • the scan signal of the n+1th stage drops to a low level
  • the scan signal of the n+2th stage is a high level
  • the sixth thin film transistor is turned on
  • the fifth thin film transistor is turned off
  • the WR control The signal is at a low level
  • the output signal of the And logic gate of the nth stage outputs a high level.
  • the pulse width of the GOA circuit can be increased from 1 ms to 3 ms.
  • GOA does not need to output wide pulses, and can also use the structure of the present invention to output narrow pulses, as shown in Figure 5, which is a schematic diagram of the narrow pulse output of the array substrate of the present invention.
  • Figure 5 is a schematic diagram of the narrow pulse output of the array substrate of the present invention.
  • the working process of the GOA circuit in the array substrate is the same as when outputting a wide pulse.
  • the pulse width of the GOA circuit can be increased from 5 ⁇ s to 15 ⁇ s.
  • the 31st level GOA unit is composed of 18 thin film transistors TFT and a capacitor Cbt.
  • CLK and CLKB are AC power supplies with opposite waveforms
  • VGH, VGL1 and VGL2 are DC DC power supplies
  • STV is a start pulse trigger signal , Required to start the first level GOA unit.
  • Nodes N, Q, QB, Cout(n-1), Cout(n), Cout(n+1), G(n), etc. are important nodes in the circuit.
  • CLKB is the first clock signal
  • CLK is the second clock signal
  • Cout(n-1) is the output terminal of the previous stage transmission signal
  • G(n) is the output terminal of the nth stage scan signal
  • Q is the first node
  • N is the third node
  • QB is the fourth node.
  • T11 and T12 belong to the pull-up control module; T21, T22 and T23 belong to the pull-up module; T31, T32 and T33 belong to the pull-down module; T41-T45 belong to the pull-down maintenance module ; T51-T54 belong to the inverter module; T6 is the feedback module; taking the 31st level GOA unit as an example, the following describes the specific working process of the GOA circuit:
  • the final output of the GOA unit is the scan signal G(n), and each GOA unit is connected to multiple And logic gate units through the scan signal terminal to provide input signals for the And logic gate unit.
  • the array substrate of the present invention includes a GOA circuit and a plurality of And logic gate units integrated in the back end of the GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit includes a scanning signal terminal, At least three consecutive GOA units are connected to an And logic gate unit through the scan signal terminal; when the circuit is working, at least three consecutive GOA units can be raised to a high potential one after another, so that the output signal terminal of the And logic gate unit can maintain longer High potential of time;
  • the array substrate of the present invention can reduce the output pulse width of the GOA circuit, and the reduction of the pulse width is beneficial to reduce the leakage current of the first node (Q), which is beneficial to obtain a stable GOA output signal, and the GOA circuit can be normal Grade pass.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种阵列基板，该阵列基板包括GOA电路以及集成于GOA电路后端的多个And逻辑门单元；GOA电路包括多个级联的GOA单元，每个GOA单元包含有扫描信号端，至少三个连续的GOA单元通过扫描信号端接入一个And逻辑门单元。

Description

阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板。
 背景技术
OLED显示装置按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active MatrixOLED，AMOLED)两大类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
目前大尺寸AMOELD面板像素普遍采用外部补偿方案，外部补偿方案需要阵列基板中的GOA电路输出超宽脉冲信号（>3ms），因而在输出阶段，GOA电路的第一节点（Q）需要长时间维持宽脉冲，而此时Q点处于浮动状态，如果薄膜晶体管TFT的漏电流较大，Q点无法维持长时间高电位，GOA则无法输出超宽脉冲。
如图1所示，当时钟周期（CK）的脉冲宽度为3ms时，理论上GOA电路能够输出3ms的脉宽。但实际上，Q点无法长时间维持高电压，因此，GOA电路也无法输出宽脉冲，此时，GOA电路的实际脉宽为2ms；而由于GOA电路的脉宽不满3ms，电路级传也会失效。
因此，需要提出一种新的阵列基板，以解决上述问题。
 技术问题
本发明提供一种阵列基板，能够利于实现补偿阶段的GOA超宽脉冲输出，以解决现有的阵列基板因TFT的漏电流较大，Q点无法维持长时间高电位，GOA无法输出超宽脉冲的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板，所述阵列基板包括GOA电路以及集成于所述GOA电路后端的多个And逻辑门单元；
所述GOA电路包括多个级联的GOA单元，每个所述GOA单元包含有扫描信号端，至少三个连续的所述GOA单元通过所述扫描信号端接入一个所述And逻辑门单元。
在本申请实施例所提供的阵列基板中，设n为自然数，第n级所述GOA单元输出第n级扫描信号；
第n-1级所述扫描信号、第n级所述扫描信号、第n+1级所述扫描信号为第n-1级所述And逻辑门单元的输入信号；
第n级所述扫描信号、第n+1级所述扫描信号、第n+2级所述扫描信号为第n级所述And逻辑门单元的输入信号。
在本申请实施例所提供的阵列基板中，设m为自然数，所述GOA电路包括m个所述GOA单元（m>n），第m-1级和第m级所述GOA单元为虚拟GOA单元。
在本申请实施例所提供的阵列基板中，第n级And逻辑门单元电路包括六个薄膜晶体管，第一直流低电压，第二直流低电压，直流高电压，WR控制信号和And逻辑门输出信号；
其中，第一薄膜晶体管的栅极连接所述直流高电压，源极和漏极分别连接第n级所述And逻辑门输出信号和第二薄膜晶体管的栅极；
第二薄膜晶体管的源极和漏极分别连接所述直流高电压和第三薄膜晶体管的栅极；
第三薄膜晶体管的源极和漏极分别连接所述第二直流低电压和第n级所述And逻辑门输出信号；
第四薄膜晶体管的栅极连接第n级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；
第五薄膜晶体管的栅极连接第n+1级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；
第六薄膜晶体管的栅极连接第n+2级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压。
在本申请实施例所提供的阵列基板中，第n级所述扫描信号为高电位，所述第六薄膜晶体管打开，所述WR控制信号为低电位，所述第三薄膜晶体管关闭，所述第一薄膜晶体管打开，第n级所述And逻辑门输出信号输出高电位。
在本申请实施例所提供的阵列基板中，第n级所述扫描信号为低电位，第n+1级所述扫描信号为高电位，所述第五薄膜晶体管打开，所述第六薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
在本申请实施例所提供的阵列基板中，第n+1级所述扫描信号为低电位，第n+2级所述扫描信号为高电位，所述第六薄膜晶体管打开，所述第五薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
在本申请实施例所提供的阵列基板中，第n+2级所述扫描信号为低电位，所述第四薄膜晶体管关闭，所述WR控制信号为高电位，所述第三薄膜晶体管打开，第n级所述And逻辑门输出信号输出低电位。
在本申请实施例所提供的阵列基板中，所述第二直流低电压大于所述第一直流低电压。
在本申请实施例所提供的阵列基板中，所述GOA电路为基于IGZO材料制备的GOA电路。
 有益效果
本发明的有益效果为：本发明的阵列基板包括GOA电路以及集成于GOA电路后端的多个And逻辑门单元； GOA电路包括多个级联的GOA单元，每个GOA单元包含有扫描信号端，至少三个连续的GOA单元通过扫描信号端接入一个And逻辑门单元；当电路工作时，至少三个连续的GOA单元可以接连升至高电位，使And逻辑门单元的输出信号端能够维持更长时间的高电位；本发明的阵列基板可以降低GOA电路的输出脉宽，而脉冲宽度的降低利于降低第一节点（Q）的漏电流，有利于获得稳定的GOA输出信号，同时GOA电路能够正常级传。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有阵列基板的信号波形图；
图2为本发明实施例提供的阵列基板的结构示意图；
图3为本发明实施例提供的阵列基板的电路示意图；
图4为本发明实施例提供的阵列基板的信号波形图；
图5为本发明实施例提供的阵列基板输出窄脉冲时的信号波形图；
图6为本发明实施例提供的阵列基板的第31级GOA单元的电路示意图；
图7为本发明实施例提供的阵列基板的第31级GOA单元的信号波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的阵列基板，因TFT的漏电流较大，Q点无法维持长时间高电位，GOA无法输出超宽脉冲的技术问题，本实施例能够解决该缺陷。
如图2所示，本发明提供一种阵列基板，所述阵列基板包括GOA电路以及集成于所述GOA电路后端的多个And逻辑门单元；所述GOA电路包括多个级联的GOA单元，每个所述GOA单元包含有扫描信号端，至少三个连续的所述GOA单元通过所述扫描信号端接入一个所述And逻辑门单元。
例如，如果需要得到3ms的脉冲宽度，可以由多级GOA单元接入And逻辑门单元获得，最后GOA电路的输出脉宽可以降为1ms。
在其它实施例中，连入And逻辑门单元的GOA单元的数目可以更多，当连入And逻辑门单元的GOA单元的数目越多，越能够降低GOA电路的脉冲宽度。而GOA电路的脉冲宽度的降低有利于降低Q点的漏电流，降低Q点的漏电流能够获得稳定的GOA输出信号，同时能够保证GOA电路正常级传。
设n为自然数，第n级所述GOA单元输出第n级扫描信号；第n-1级所述扫描信号、第n级所述扫描信号、第n+1级所述扫描信号为第n-1级所述And逻辑门单元的输入信号；第n级所述扫描信号、第n+1级所述扫描信号、第n+2级所述扫描信号为第n级所述逻辑门单元的输入信号。
设m为自然数，所述GOA电路包括m个所述GOA单元（m>n），第m-1级和第m级所述GOA单元为虚拟GOA单元。最后两级GOA单元为虚拟GOA单元，一方面为上一级GOA单元提供反馈信号，另一方面为最后一级的And逻辑门单元提供信号源。
在其它实施例中，例如，四个所述GOA单元接入一个所述And逻辑门单元，此时第m-2级、第m-1级、第m级为虚拟GOA单元，虚拟GOA单元为上一级GOA单元提供反馈信号，并同时为最后一级的And逻辑门单元提供信号源。若是接入的GOA单元为5个或更多，皆以此规律类推。
图3为本发明的And逻辑门电路图，第n级And逻辑门单元电路包括有六个薄膜晶体管，第一直流低电压VGL1，第二直流低电压VGL2，直流高电压VGH，WR控制信号和第n级And逻辑门输出信号Out（n）；其中，第一薄膜晶体管T1的栅极连接所述直流高电压，源极和漏极分别连接第n级所述And逻辑门输出信号和第二薄膜晶体管T2的栅极；第二薄膜晶体管T2的源极和漏极分别连接所述直流高电压和第三薄膜晶体管T3的栅极；第三薄膜晶体管T3的源极和漏极分别连接所述第二直流低电压和第n级所述And逻辑门输出信号；第四薄膜晶体管T4的栅极连接第n级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；第五薄膜晶体管T5的栅极连接第n+1级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；第六薄膜晶体管T6的栅极连接第n+2级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压。
其中，T4、T5、T6连入第n级、第n+1级和第n+2级的所述GOA单元的扫描信号；所述WR控制信号为所述And逻辑电路中的内部控制信号。
图4为本发明的第n级And逻辑门信号波形图，所述第n级And逻辑门电路宽脉冲的工作过程可以分为四个阶段：
S1阶段：第n级所述扫描信号升为高电位，所述第六薄膜晶体管打开，所述WR控制信号为低电位，所述第三薄膜晶体管关闭，所述第一薄膜晶体管打开，第n级所述And逻辑门输出信号输出高电位。
S2阶段：第n级所述扫描信号降为低电位，第n+1级所述扫描信号为高电位，所述第五薄膜晶体管打开，所述第六薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
S3阶段：第n+1级所述扫描信号降为低电位，第n+2级所述扫描信号为高电位，所述第六薄膜晶体管打开，所述第五薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
S4阶段：第n+2级所述扫描信号降为低电位，所述第四薄膜晶体管关闭，所述WR控制信号为高电位，所述第三薄膜晶体管打开，第n级所述And逻辑门输出信号输出低电位。
通过所述And逻辑门电路，可以让GOA电路的脉冲宽度由1ms升至3ms。
在GOA电路的编程阶段，GOA无需输出宽脉冲，同样能够利用本发明的结构输出窄脉冲，如图5所示，其为本发明的阵列基板输出窄脉冲的波形示意图，在输出窄脉冲时，阵列基板中的GOA电路的工作过程与输出宽脉冲时一致，通过And逻辑门电路，可以让GOA电路的脉冲宽度由5μs升至15μs。
如图6、图7所示，其为第31级GOA（G31）单元的电路图与信号波形图。
第31级GOA单元是由18个薄膜晶体管TFT和一个电容Cbt构成，其中，CLK、CLKB是波形相反的交流电源，VGH、VGL1和VGL2是DC直流电源，STV是启动脉冲(start pulse)触发信号，为启动第一级GOA单元所需。节点N、Q、QB、Cout(n-1)、Cout(n)、Cout(n+1)、G(n)等是电路中重要的节点。
其中，CLKB是第一时钟信号，CLK是第二时钟信号；Cout（n-1）为前一级级传信号输出端；G（n）是第n级扫描信号输出端；Q为第一节点；N为第三节点；QB为第四节点。
第31级GOA单元中的18个TFT按照功能性划分，T11和T12属于上拉控制模块；T21、T22及T23属于上拉模块；T31、T32及T33属于下拉模块；T41-T45属于下拉维持模块；T51-T54属于反相器模块；T6为反馈模块；以第31级GOA单元为例，下面介绍GOA电路的具体工作过程：
当Cout(30)为高电位时，CLK同时处于高电位，T11和T22打开，Cout(30)的高电位传入到Q点， Q点为高电位，同时T21、T22与T23打开，由于Q与QB点之间连接反相器结构，它们之间的电位相反，因此，QB处于低电位，T41、T42、T43、T44与T45均关闭、同时，Cout(32)处于低电位，T31、T32和T33关闭，CLKB处于低电位，输出Cout(n)与G(n)为低电位。
然后，Cout(30)和CLK为低电位，T11与T12关闭，此时，Q点受到电容耦合效应，被抬到更高的电位， T31、T32、T33、T41、T42、T43、T44与T45继续关闭，CLKB是高电位，此时Cout(31)与G(31)为高电位。此时，T6打开，N点处于高电位，该电位降低了T12、T44与T32管的漏电流。需要说明的是我们引入两条VGL线，其中VGL2>VGL1，使得Vgs<0，降低了T31、T41、T43与T6管Vth为负值时漏电的风险。另外，在168ms的电位维持阶段，Q点电位并未降低，说明该电路能够有效解决Q点电位维持问题。
随后，CLK升为高电位，Cout(30)为低电位，同时Cout(32)为高电位，T11、T12、T31、T32与T33打开，Q点电位迅速被拉低，此时，QB点电位被拉至高电位，T41、T42、T43、T44与T45均打开，Cout(31)与G(31)被分别拉低至低电位VGL1与VGL2。
GOA单元最后输出为扫描信号G（n），每个GOA单元通过扫描信号端接入多个And逻辑门单元，为And逻辑门单元提供输入信号。
本发明的有益效果为：本发明的阵列基板包括GOA电路以及集成于GOA电路后端的多个And逻辑门单元； GOA电路包括多个级联的GOA单元，每个GOA单元包含有扫描信号端，至少三个连续的GOA单元通过扫描信号端接入一个And逻辑门单元；当电路工作时，至少三个连续的GOA单元可以接连升至高电位，使And逻辑门单元的输出信号端能维持更长时间的高电位；本发明的阵列基板可以降低GOA电路的输出脉宽，而脉冲宽度的降低利于降低第一节点（Q）的漏电流，有利于获得稳定的GOA输出信号，同时GOA电路能够正常级传。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种阵列基板，其中，所述阵列基板包括GOA电路以及集成于所述GOA电路后端的多个And逻辑门单元；
    所述GOA电路包括多个级联的GOA单元，每个所述GOA单元包含有扫描信号端，至少三个连续的所述GOA单元通过所述扫描信号端接入一个所述And逻辑门单元。
  2. 根据权利要求1所述的阵列基板，其中，设n为自然数，第n级所述GOA单元输出第n级扫描信号；
    第n-1级所述扫描信号、第n级所述扫描信号、第n+1级所述扫描信号为第n-1级所述And逻辑门单元的输入信号；
    第n级所述扫描信号、第n+1级所述扫描信号、第n+2级所述扫描信号为第n级所述And逻辑门单元的输入信号。
  3. 根据权利要求1所述的阵列基板，其中，设m为自然数，所述GOA电路包括m个所述GOA单元（m>n），第m-1级和第m级所述GOA单元为虚拟GOA单元。
  4. 根据权利要求2所述的阵列基板，其中，第n级And逻辑门单元电路包括六个薄膜晶体管，第一直流低电压，第二直流低电压，直流高电压，WR控制信号和And逻辑门输出信号；
    其中，第一薄膜晶体管的栅极连接所述直流高电压，源极和漏极分别连接第n级所述And逻辑门输出信号和第二薄膜晶体管的栅极；
    第二薄膜晶体管的源极和漏极分别连接所述直流高电压和第三薄膜晶体管的栅极；
    第三薄膜晶体管的源极和漏极分别连接所述第二直流低电压和第n级所述And逻辑门输出信号；
    第四薄膜晶体管的栅极连接第n级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；
    第五薄膜晶体管的栅极连接第n+1级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压；
    第六薄膜晶体管的栅极连接第n+2级所述扫描信号，源极和漏极分别连接所述WR控制信号和所述第一直流低电压。
  5. 根据权利要求4所述的阵列基板，其中，第n级所述扫描信号为高电位，所述第六薄膜晶体管打开，所述WR控制信号为低电位，所述第三薄膜晶体管关闭，所述第一薄膜晶体管打开，第n级所述And逻辑门输出信号输出高电位。
  6. 根据权利要求4所述的阵列基板，其中，第n级所述扫描信号为低电位，第n+1级所述扫描信号为高电位，所述第五薄膜晶体管打开，所述第六薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
  7. 根据权利要求4所述的阵列基板，其中，第n+1级所述扫描信号为低电位，第n+2级所述扫描信号为高电位，所述第六薄膜晶体管打开，所述第五薄膜晶体管关闭，所述WR控制信号为低电位，第n级所述And逻辑门输出信号输出高电位。
  8. 根据权利要求4所述的阵列基板，其中，第n+2级所述扫描信号为低电位，所述第四薄膜晶体管关闭，所述WR控制信号为高电位，所述第三薄膜晶体管打开，第n级所述And逻辑门输出信号输出低电位。
  9. 根据权利要求4所述的阵列基板，其中，所述第二直流低电压大于所述第一直流低电压。
  10. 根据权利要求1所述的阵列基板，其中，所述GOA电路为基于IGZO材料制备的GOA电路。
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