WO2020206751A1 - 显示面板、显示模组及制作方法 - Google Patents

显示面板、显示模组及制作方法 Download PDF

Info

Publication number
WO2020206751A1
WO2020206751A1 PCT/CN2019/084223 CN2019084223W WO2020206751A1 WO 2020206751 A1 WO2020206751 A1 WO 2020206751A1 CN 2019084223 W CN2019084223 W CN 2019084223W WO 2020206751 A1 WO2020206751 A1 WO 2020206751A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
substrate
goa
display area
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/084223
Other languages
English (en)
French (fr)
Inventor
奚苏萍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020206751A1 publication Critical patent/WO2020206751A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • This application relates to the field of display, and in particular to a display panel, a display module and a manufacturing method.
  • Gate Driver On Array (Gate Driver On Array, GOA) is to use the existing thin-film transistor liquid crystal display array manufacturing process to fabricate the gate row scan driving signal circuit on the array substrate to realize the driving method of the gate progressive scan.
  • the gate traces located in the non-display area are M2 traces (source-drain layer), and the gate traces located in the display area are M1 traces (gate layer). Therefore, the gate traces in the non-display area in the existing GOA circuit need to pass through vias to be changed to the metal lines on the same layer as the gate traces in the display area.
  • the periphery of the via hole close to the display area is a low point of terrain, when the via hole is formed, the film material in the display area is likely to accumulate to the periphery of the via hole, which affects the quality of the product.
  • the present application provides a display panel, a display module, and a manufacturing method, so as to solve the technical problem of accumulation of film materials in the gate switching area of the existing display panel.
  • the present application provides a display panel, which includes a display area and a non-display area located at the periphery of the display area;
  • the non-display area includes GOA wiring area and GOA wiring area;
  • a substrate and a pad on the substrate are arranged in the GOA line change area.
  • the non-display area also includes a common wiring area
  • the common wiring area is located between the GOA wiring area and the display area;
  • the GOA line swap area is located in the common routing area.
  • the orthographic projection of the GOA wire changing area on the substrate and the orthographic projection of the common routing area on the substrate do not overlap.
  • the absolute value is less than the threshold.
  • the pad portion includes one of a color resist unit, a black photoresist or a photoresist;
  • the raised portion When the raised portion is a color resist unit, the raised portion includes one of a red color resist block, a green color resist block, or a blue color resist block.
  • a first-type signal line, a second-type signal line, and via holes are arranged in the wire change area;
  • the first type signal line is electrically connected to the second type signal line through the via;
  • the first type signal line and the gate layer in the display area are formed in the same photomask process
  • the second type signal lines and the source and drain layers in the display area are formed in the same photomask process.
  • GOA signal lines are arranged in the GOA wiring area, and common electrode lines are arranged in the common wiring area;
  • the GOA signal line and the source and drain layers in the display area are formed in the same photomask process
  • the common electrode line and the gate layer in the display area are formed in the same photomask process.
  • the present application also proposes a method for manufacturing a display panel, wherein the display panel includes a display area and a non-display area located at the periphery of the display area;
  • the non-display area includes a GOA wiring area, a GOA wiring area, and a public wiring area, and the GOA wiring area is located in the public wiring area;
  • the manufacturing method of the display panel includes:
  • a pixel electrode layer is formed on the color resist layer.
  • a substrate is provided, and the step of forming a thin film transistor layer on the substrate includes:
  • Forming a gate layer on the substrate includes:
  • the first metal layer is patterned to form a gate layer located in the display area, a common electrode line located in the common wiring area, and a second wire-changing area A signal line;
  • Forming a source and drain layer on a substrate includes:
  • the second metal layer is patterned to form a source and drain layer located in the display area, GOA signal lines located in the GOA wiring area, and The second signal line.
  • the orthographic projection of the GOA wire changing area on the substrate and the orthographic projection of the common routing area on the substrate do not overlap.
  • the distance between the surface of the raised portion on the side away from the substrate and the substrate and the surface of the color resist layer in the display area on the side away from the substrate to the The absolute value of the difference in the pitch of the substrate is smaller than the threshold value.
  • a first-type signal line, a second-type signal line, and via holes are arranged in the wire change area;
  • the first type signal line is electrically connected to the second type signal line through the via;
  • the first type signal line and the gate layer in the display area are formed in the same photomask process
  • the second type signal lines and the source and drain layers in the display area are formed in the same photomask process.
  • GOA signal lines are arranged in the GOA wiring area, and common electrode lines are arranged in the common wiring area;
  • the GOA signal line and the source and drain layers in the display area are formed in the same photomask process
  • the common electrode line and the gate layer in the display area are formed in the same photomask process.
  • the application also proposes a display module, including a display panel and a polarizer layer and a cover layer on the display panel, wherein the display panel includes a display area and a non-display area located at the periphery of the display area ;
  • the non-display area includes GOA wiring area and GOA wiring area;
  • a substrate and a pad on the substrate are arranged in the GOA line change area.
  • the non-display area also includes a common wiring area
  • the common wiring area is located between the GOA wiring area and the display area;
  • the GOA line swap area is located in the common routing area.
  • the orthographic projection of the GOA wire changing area on the substrate and the orthographic projection of the common routing area on the substrate do not overlap.
  • the absolute value is less than the threshold.
  • the pad portion includes one of a color resist unit, a black photoresist or a photoresist;
  • the raised portion When the raised portion is a color resist unit, the raised portion includes one of a red color resist block, a green color resist block, or a blue color resist block.
  • a first-type signal line, a second-type signal line, and via holes are arranged in the wire change area;
  • the first type signal line is electrically connected to the second type signal line through the via;
  • the first type signal line and the gate layer in the display area are formed in the same photomask process
  • the second type signal lines and the source and drain layers in the display area are formed in the same photomask process.
  • GOA signal lines are arranged in the GOA wiring area, and common electrode lines are arranged in the common wiring area;
  • the GOA signal line and the source and drain layers in the display area are formed in the same photomask process
  • the common electrode line and the gate layer in the display area are formed in the same photomask process.
  • the present application by setting up a raised part in the GOA line change area, the terrain difference between the GOA line change area and the display area is reduced, and the film material is prevented from forming a via hole in the GOA line change area. Accumulation on the periphery improves the quality of the display panel.
  • Figure 1 is a plan structure diagram of a display panel of this application.
  • Figure 2 is an enlarged view of area X in Figure 1;
  • Figure 3 is a cross-sectional view of section AA in Figure 2;
  • FIG. 4 is a step diagram of a manufacturing method of a display panel of the present application.
  • FIG. 1 is a plan structure diagram of the display panel 100 of the present application.
  • the display panel 100 includes a display area 10 and a non-display area 20 located at the periphery of the display area 10.
  • the display area 10 is used to display images.
  • the non-display area is provided with GOA wiring areas 21 located on both sides of the display panel 100 and a driving chip 22 located at the bottom of the display panel 100.
  • a GOA signal line 211 is provided in the GOA wiring area 21.
  • the GOA signal line 211 is used to transmit or receive the driving signal of the display panel 100.
  • the GOA signal line 211 and the source and drain layers 127 of the display panel 100 are formed in the same photomask process.
  • Figure 2 is an enlarged view of the area X in Figure 1.
  • the non-display area 20 also includes a GOA line change area 23 and a common wiring area 24.
  • the GOA routing area 23 and the common routing area 24 are located between the GOA routing area 21 and the display area 10.
  • a first type signal line 231, a second type signal line 232 and a via 233 are provided in the GOA line change area 23.
  • the first type signal line 231 is electrically connected to the second type signal line 232 through the via 233.
  • a common electrode line 241 is provided in the common wiring area 24.
  • the GOA switching area 23 is located in the common wiring area 24 and is surrounded by the common wiring area 24.
  • the common electrode line 241 and the gate layer 125 in the display area 10 are formed in the same photomask process. However, the common electrode line 241 is insulated from the gate line in the gate layer 125.
  • the common electrode line 241 is insulated from the first type signal line 231 and the second type signal line 232.
  • the orthographic projection of the GOA wire changing area 23 on the substrate 11 of the display panel 100 and the orthographic projection of the common wiring area 24 on the substrate 11 do not overlap.
  • FIG. 3 is a cross-sectional view of section AA in FIG.
  • the display area 10 is provided with a substrate 11, a thin film transistor layer on the substrate 11, and a color resist layer 13 on the thin film transistor layer.
  • the substrate 11 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • the substrate 11 may also be a flexible substrate, and the material of the flexible substrate may be PI (polyimide).
  • the thin film transistor layer may include a plurality of thin film transistor units 12.
  • the thin film transistor unit 12 includes an etch barrier type, a back channel etch type, or a top gate thin film transistor type structure, which is not specifically limited. This application takes the top-gate thin film transistor type as an example for description.
  • the thin film transistor unit may include a light shielding layer 121 on the substrate 11, a buffer layer 122 on the light shielding layer 121, an active layer 123 on the buffer layer 122, and an active layer 123 on the buffer layer 122.
  • the gate insulating layer 124 on the 123, the gate layer 125 on the gate insulating layer 124, the inter insulating layer 126 on the gate layer 125, the source and drain layer 127 on the inter insulating layer 126 A passivation layer 128 on the source and drain layer 127.
  • a substrate 11, a buffer layer 122 located on the substrate 11, a gate insulating layer 124 located on the buffer layer 122, and a The inter-insulating layer 126 on the gate insulating layer 124 and the padding portion 30 on the inter-insulating layer 126 are described.
  • the raised portion 30 may be one of other organic or inorganic substances such as a color resist unit, a black photoresist, or a photoresist.
  • the raised portion 30 of the present application is selected as a color resist unit.
  • the raised portion 30 may be one of a red color block, a green color block, or a blue color block, and there is no specific limitation.
  • the raised portion 30 may also cover the entire common wiring area 24.
  • the GOA wire changing area 23 there are also a first type signal line 231 located on the gate insulating layer 124, and a second type signal line 232 located on the inter insulating layer 126.
  • the first type signal line 231 and the gate layer 125 in the display area 10 are formed in the same photomask process; the second type signal line 232 is formed with the gate layer 125 in the display area 10
  • the source and drain layers 127 are formed in the same photomask process.
  • the first type signal line 231 and the common electrode line 241 are arranged in the same layer, in order to ensure the short connection between the first type signal line 231 and the common electrode line 241, the first type signal line 231 is The common electrode line 241 should be insulated.
  • the GOA wire change area 23 is also provided with a via 233, which is a wire change hole.
  • the first type signal line 231 is electrically connected to the second type signal line 232 through the via 233.
  • the first type signal line 231 is electrically connected to the scan line (gate line) in the display area 10, and the second type signal line 232 is connected to the GOA signal of the GOA wiring area 21
  • the line 211 is electrically connected.
  • the first type signal line 231, the second type signal line 232, and the via 233 electrically connect the GOA signal line 211 and the scan line to receive and transmit data signals.
  • the distance between the surface of the raised portion 30 on the side away from the substrate 11 and the substrate 11 is the same as the distance between the color resist layer 13 in the display area 10 on the side away from the substrate 11
  • the absolute value of the difference in the distance between the surface and the substrate 11 is smaller than the threshold.
  • the raised portion 30 and the color resist layer 13 of the display area 10 can be formed in a photomask process, or a photomask process can be applied separately. It is only necessary to ensure that the thickness from the raised portion 30 of the common wiring area 24 to the corresponding substrate 11 is not much different from the thickness from the color resist layer 13 in the display area 10 to the corresponding substrate 11.
  • the common wiring area 24 and the display area 10 are both provided with color resistance units.
  • the thickness of the color resistance unit is larger than that of each layer structure in the display panel 100 array, so the actual thickness difference between the common wiring area 24 and the display area 10 is relatively small.
  • FIG. 4 is a step diagram of a method for manufacturing the display panel 100 of the present application.
  • the display panel 100 of the present application includes a display area 10 and a non-display area 20 located at the periphery of the display area 10.
  • the display area 10 is used to display images.
  • the non-display area is provided with GOA wiring areas 21 located on both sides of the display panel 100 and a driving chip 22 located at the bottom of the display panel 100.
  • a GOA signal line 211 is provided in the GOA wiring area 21.
  • the GOA signal line 211 is used to transmit or receive the driving signal of the display panel 100.
  • the non-display area 20 also includes a GOA line change area 23 and a common wiring area 24.
  • the GOA routing area 23 and the common routing area 24 are located between the GOA routing area 21 and the display area 10.
  • the manufacturing method includes the steps:
  • the substrate 11 may be one of a glass substrate, a quartz substrate, a resin substrate, and the like.
  • the substrate 11 may also be a flexible substrate, and the material of the flexible substrate may be PI (polyimide).
  • the thin film transistor layer may include a plurality of thin film transistor units 12.
  • the thin film transistor unit 12 includes an etch barrier type, a back channel etch type, or a top gate thin film transistor type structure, which is not specifically limited. This application takes the top-gate thin film transistor type as an example for description.
  • the step of forming the thin film transistor unit 12 may include:
  • a light shielding layer 121 is formed on the substrate 11; a buffer layer 122 formed on the light shielding layer 121; an active layer 123 is formed on the buffer layer 122; a gate insulating layer is formed on the active layer 123 124; forming a gate layer 125 on the gate insulating layer 124; forming an inter-insulating layer 126 on the gate layer 125; forming a source-drain layer 127 on the inter-insulating layer 126; on the source and drain A passivation layer 128 is formed on the pole layer 127.
  • the step of forming the gate layer 125 specifically includes:
  • the first metal layer is patterned to form the gate layer 125 located in the display area 10, the common electrode line 241 located in the common wiring area 24, and the common electrode line 241 located in the change line The first signal line of the area.
  • the step of forming the source and drain layer 127 specifically includes:
  • the second metal layer is patterned to form the source and drain layer 127 in the display area 10, the GOA signal line 211 in the GOA wiring area 21, and the GOA signal line 211 in the switch The second signal line of the line area.
  • the color resist layer 13 corresponding to the display area 10 includes a plurality of color resist units, and the color resist units may include a red color resist block, a green color resist block, or a blue color resist.
  • the color resist units may include a red color resist block, a green color resist block, or a blue color resist.
  • One of the blocks is a red color resist block, a green color resist block, or a blue color resist.
  • the raised portion 30 may be one of other organic or inorganic substances such as a color resist unit, a black photoresist, or a photoresist.
  • the raised portion 30 of the present application is selected as a color resist unit.
  • the raised portion 30 may be one of a red color block, a green color block, or a blue color block, and there is no specific limitation.
  • the raised portion 30 may also cover the entire common wiring area 24.
  • the pixel electrode layer (not shown) is located on the color resist layer 13 corresponding to the display area 10.
  • the pixel electrode layer is electrically connected to the source and drain layer 127 through via holes.
  • the GOA wire change area 23 is also provided with a first type signal line 231 located on the gate insulating layer 124 and a second type signal line 232 located on the inter-insulating layer 126.
  • a common electrode line 241 is provided in the common wiring area 24.
  • the GOA switching area 23 is located in the common wiring area 24 and is surrounded by the common wiring area 24.
  • the common electrode line 241 and the gate layer 125 in the display area 10 are formed in the same photomask process, the common electrode line 241 and the gate layer 125 in the gate layer 125
  • the grid lines are insulated and do not cross each other.
  • the common electrode line 241 is insulated from the first type signal line 231 and the second type signal line 232.
  • the orthographic projection of the GOA wire changing area 23 on the substrate 11 of the display panel 100 and the orthographic projection of the common wiring area 24 on the substrate 11 do not overlap.
  • the first type signal line 231 and the common electrode line 241 are arranged in the same layer, in order to ensure the short connection between the first type signal line 231 and the common electrode line 241, the first type signal line 231 is The common electrode line 241 should be insulated.
  • the GOA wire change area 23 is also provided with a via 233, which is a wire change hole.
  • the first type signal line 231 is electrically connected to the second type signal line 232 through the via 233.
  • the first type signal line 231 is electrically connected to the scan line (gate line) in the display area 10, and the second type signal line 232 is connected to the GOA signal of the GOA wiring area 21
  • the line 211 is electrically connected.
  • the first type signal line 231, the second type signal line 232, and the via 233 electrically connect the GOA signal line 211 and the scan line to receive and transmit data signals.
  • the distance between the surface of the raised portion 30 on the side away from the substrate 11 and the substrate 11 is the same as the distance between the color resist layer 13 in the display area 10 on the side away from the substrate 11
  • the absolute value of the difference in the distance between the surface and the substrate 11 is smaller than the threshold.
  • the raised portion 30 and the color resist layer 13 of the display area 10 can be formed in a photomask process, or a photomask process can be applied separately. It is only necessary to ensure that the thickness from the raised portion 30 of the common wiring area 24 to the corresponding substrate 11 is not much different from the thickness from the color resist layer 13 in the display area 10 to the corresponding substrate 11.
  • the common wiring area 24 and the display area 10 are both provided with color resistance units.
  • the thickness of the color resistance unit is larger than that of each layer structure in the display panel 100 array, so the actual thickness difference between the common wiring area 24 and the display area 10 is relatively small.
  • the application also proposes a display module, which includes the above-mentioned display panel.
  • the display module also includes a polarizer layer and a cover layer on the display panel.
  • the working principle of the display module is the same or similar to that of the display panel, and will not be repeated in this application.
  • the display panel includes a display area and a non-display area located at the periphery of the display area; the non-display area includes a GOA wiring area and a GOA wire change area; the GOA A substrate and a pad on the substrate are arranged in the line change area.
  • the present application by setting up a raised part in the GOA line change area, the terrain difference between the GOA line change area and the display area is reduced, and the film material is prevented from forming a via hole in the GOA line change area. Accumulation on the periphery improves the quality of the display panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板(100)、显示模组及制作方法，显示面板(100)包括显示区域(10)和位于显示区域(100)外围的非显示区域(20)；非显示区域(20)包括GOA走线区(21)和GOA换线区(23)；GOA换线区(23)内设置有衬底(11)和位于衬底(11)上的垫高部(30)。

Description

显示面板、显示模组及制作方法 技术领域
本申请涉及显示领域，尤其涉及一种显示面板、显示模组及制作方法。
 背景技术
阵列栅极驱动（Gate Driver On Array，GOA）就是利用现有薄膜晶体管液晶显示器中的阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式。
在GOA电路中，位于非显示区域的Gate走线为M2走线（源漏极层），位于显示区域的Gate走线为M1走线（栅极层）。因此，现有GOA电路中非显示区域的Gate走线需要经过过孔换线至与显示区域的Gate走线同层的金属线。而由于靠近显示区域的过孔周边为地势低点，因此在形成过孔时容易导致显示区域中的膜层材料向该过孔周边堆积，影响产品的品质。
因此，目前亟需一种显示面板以解决上述问题。
 技术问题
本申请提供一种显示面板、显示模组及制作方法，以解决现有显示面板的栅极换线区膜层材料堆积的技术问题。
 技术解决方案
本申请提供一种显示面板，其包括显示区域和位于所述显示区域外围的非显示区域；
所述非显示区域包括GOA走线区和GOA换线区；
所述GOA换线区内设置有衬底和位于所述衬底上的垫高部。
在本申请的显示面板中，
所述非显示区域还包括公共走线区；
所述公共走线区位于所述GOA走线区与所述显示区域之间；
所述GOA换线区位于所述公共走线区内。
在本申请的显示面板中，
所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
在本申请的显示面板中，
所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
在本申请的显示面板中，
所述垫高部包括色阻单元、黑色光阻或光刻胶中的一种；
当所述垫高部为色阻单元时，所述垫高部包括红色色阻块、绿色色阻块或蓝色色阻块中的一种。
在本申请的显示面板中，
所述换线区内设置有第一类信号线、第二类信号线以及过孔；
所述第一类信号线通过所述过孔与所述第二类信号线电连接；
所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
在本申请的显示面板中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
本申请还提出了一种显示面板的制作方法，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
所述非显示区域包括GOA走线区、GOA换线区以及公共走线区，所述GOA换线区位于所述公共走线区内；
所述显示面板的制作方法包括：
提供一衬底，在所述衬底上形成薄膜晶体管层；
在所述显示区域对应的所述薄膜晶体管层上形成色阻层、以及在所述公共走线区对应的所述薄膜晶体管层上形成垫高部；
在所述色阻层上形成像素电极层。
在本申请的制作方法中，
提供一衬底，在所述衬底上形成薄膜晶体管层的步骤包括：
在所述衬底上形成栅极层，包括：
在所述衬底上形成第一金属层；
使用第一光罩工艺，使所述第一金属层经图案化处理形成位于所述显示区域的栅极层、位于所述公共走线区的公共电极线、及位于所述换线区的第一信号线；
以及
在衬底上形成源漏极层，包括：
在所述衬底上形成第二金属层；
使用第二光罩工艺，使所述第二金属层经图案化处理形成位于所述显示区域的源漏极层、位于所述GOA走线区的GOA信号线、及位于所述换线区的第二信号线。
在本申请的制作方法中，
所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
在本申请的制作方法中，所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
在本申请的制作方法中，
所述换线区内设置有第一类信号线、第二类信号线以及过孔；
所述第一类信号线通过所述过孔与所述第二类信号线电连接；
所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
在本申请的制作方法中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
本申请还提出了一种显示模组，包括显示面板及位于所述显示面板上的偏光片层及盖板层，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
所述非显示区域包括GOA走线区和GOA换线区；
所述GOA换线区内设置有衬底和位于所述衬底上的垫高部。
在本申请的显示模组中，
所述非显示区域还包括公共走线区；
所述公共走线区位于所述GOA走线区与所述显示区域之间；
所述GOA换线区位于所述公共走线区内。
在本申请的显示模组中，
所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
在本申请的显示模组中，
所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
在本申请的显示模组中，
所述垫高部包括色阻单元、黑色光阻或光刻胶中的一种；
当所述垫高部为色阻单元时，所述垫高部包括红色色阻块、绿色色阻块或蓝色色阻块中的一种。
在本申请的显示模组中，
所述换线区内设置有第一类信号线、第二类信号线以及过孔；
所述第一类信号线通过所述过孔与所述第二类信号线电连接；
所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
在本申请的显示模组中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
 有益效果
本申请通过在该GOA换线区内设置垫高部，减小GOA换线区与显示区域之间的地势差，避免了在该GOA换线区形成过孔时，膜层材料向该过孔周边堆积，提高了显示面板的品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请显示面板的平面结构图；
图2为图1中区域X的放大图；
图3为图2中截面AA的剖面图；
图4为本申请显示面板制作方法的步骤图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
请参阅图1，图1为本申请显示面板100的平面结构图。
所述显示面板100包括显示区域10和位于所述显示区域10外围的非显示区域20。所述显示区域10用于显示图像。
所述非显示区内设置有位于所述显示面板100两侧的GOA走线区21以及位于所述显示面板100底端的驱动芯片22。
所述GOA走线区21内设置有GOA信号线211。所述GOA信号线211用于传递或者接受所述显示面板100的驱动信号。
在本实施例中，所述GOA信号线211与所述显示面板100的源漏极层127在同一道光罩工艺中形成。
请参阅图2，图2为图1中区域X的放大图。
所述非显示区域20还包括GOA换线区23和公共走线区24。
所述GOA换线区23和所述公共走线区24位于所述GOA走线区21域所述显示区域10之间。
所述GOA换线区23内设置有第一类信号线231、第二类信号线232以及过孔233。所述第一类信号线231通过所述过孔233与所述第二类信号线232电连接。所述公共走线区24内设置有公共电极线241。所述GOA换线区23位于所述公共走线区24内，被所述公共走线区24所包围。
在本实施例中，所述公共电极线241与所述显示区域10中的栅极层125在同一道光罩工艺中形成。但所述公共电极线241与所述栅极层125中的栅线绝缘设置。
在本实施例中，所述公共电极线241与所述第一类信号线231及所述第二类信号线232绝缘设置。
在本实施例中，所述GOA换线区23在所述显示面板100的衬底11上的正投影与所述公共走线区24在所述衬底11上的正投影不重叠。
请参阅图3，图3为图2中截面AA的剖面图。
所述显示区域10内设置有衬底11、位于所述衬底11上的薄膜晶体管层、及位于所述薄膜晶体管层上的色阻层13。
在本实施例中，所述衬底11的可以为玻璃基板、石英基板、树脂基板等中的一种。所述衬底11还可以为柔性基板，所述柔性基板的材料可以为PI（聚酰亚胺）。
所述薄膜晶体管层可以包括多个薄膜晶体管单元12。
所述薄膜晶体管单元12包括蚀刻阻挡层型、背沟道蚀刻型或顶栅薄膜晶体管型等结构，具体没有限制。本申请以顶栅薄膜晶体管型为例进行说明。
所述薄膜晶体管单元可以包括位于所述衬底11上的遮光层121、位于所述遮光层121上的缓冲层122、位于所述缓冲层122上的有源层123、位于所述有源层123上的栅绝缘层124、位于所述栅绝缘层124上的栅极层125、位于所述栅极层125上的间绝缘层126、位于所述间绝缘层126上的源漏极层127、位于所述源漏极层127上的钝化层128。
在所述非显示区域20中，所述GOA换线区23内设置有衬底11、位于所述衬底11上的缓冲层122、位于所述缓冲层122上的栅绝缘层124、位于所述栅绝缘层124上的间绝缘层126、及位于所述间绝缘层126上的垫高部30。
在本实施例中，所述垫高部30可以为色阻单元、黑色光阻或光刻胶等其他有机或无机物中的一种。
在本实施例中，考虑到工艺成本问题，本申请的所述垫高部30选择为色阻单元。所述垫高部30可以为红色色阻块、绿色色阻块或蓝色色阻块中的一种，具体没有限制。
在本实施例中，所述垫高部30还可以覆盖整个所述公共走线区24。
请参阅图3，在所述GOA换线区23内还设置有位于栅绝缘层124上的第一类信号线231，位于所述间绝缘层126上的第二类信号线232。
在本实施例中，所述第一类信号线231与所述显示区域10中的栅极层125在同一道光罩工艺中形成；所述第二类信号线232与所述显示区域10中的源漏极层127在同一道光罩工艺中形成。
由于所述第一类信号线231与所述公共电极线241同层设置，为了保证所述第一类信号线231与所述公共电极线241的短接，所述第一类信号线231与所述公共电极线241应该绝缘设置。
所述GOA换线区23还设置有过孔233，所述过孔233为换线孔。所述第一类信号线231通过所述过孔233与所述第二类信号线232电连接。
在本实施例中，所述第一类信号线231与所述显示区域10中的扫描线（栅线）电连接，所述第二类信号线232与所述GOA走线区21的GOA信号线211电连接。所述第一类信号线231、所述第二类信号线232及所述过孔233使所述GOA信号线211与所述扫描线电连接，进行数据信号的接收与传递。
在本实施例中，所述垫高部30远离所述衬底11一侧的表面与所述衬底11的间距与所述显示区域10中色阻层13远离所述衬底11一侧的表面至所述衬底11的间距的差值的绝对值小于阈值。
所述垫高部30可以与显示区域10的色阻层13在一道光罩工艺中形成，也可以单独施加一道光罩工艺。只要保证所述公共走线区24的所述垫高部30到对应衬底11的厚度与所述显示区域10中的色阻层13到对应衬底11的厚度相差不大即可。
在本申请的显示面板100中，由于公共走线区24紧邻所述显示区域10设置，所述公共走线区24和所述显示区域10内都设置有色阻单元。而色阻单元的厚度较所述显示面板100阵列中的各膜层结构较大，因此所述公共走线区24和所述显示区域10实际厚度差较小。
请参阅图4，图4为本申请显示面板100制作方法的步骤图。
请参阅图1，本申请的所述显示面板100包括显示区域10和位于所述显示区域10外围的非显示区域20。所述显示区域10用于显示图像。
所述非显示区内设置有位于所述显示面板100两侧的GOA走线区21以及位于所述显示面板100底端的驱动芯片22。
所述GOA走线区21内设置有GOA信号线211。所述GOA信号线211用于传递或者接受所述显示面板100的驱动信号。
请参阅图2，所述非显示区域20还包括GOA换线区23和公共走线区24。所述GOA换线区23和所述公共走线区24位于所述GOA走线区21域所述显示区域10之间。
所述制作方法包括步骤：
S10、提供一衬底11，在所述衬底11上形成薄膜晶体管层；
请参与图3，在本实施例中，所述衬底11的可以为玻璃基板、石英基板、树脂基板等中的一种。所述衬底11还可以为柔性基板，所述柔性基板的材料可以为PI（聚酰亚胺）。
所述薄膜晶体管层可以包括多个薄膜晶体管单元12。
所述薄膜晶体管单元12包括蚀刻阻挡层型、背沟道蚀刻型或顶栅薄膜晶体管型等结构，具体没有限制。本申请以顶栅薄膜晶体管型为例进行说明。
形成所述薄膜晶体管单元12的步骤可以包括：
在所述衬底11上形成遮光层121；在所述遮光层121上形成的缓冲层122；在所述缓冲层122上形成有源层123；在所述有源层123上形成栅绝缘层124；在所述栅绝缘层124上形成栅极层125；在所述栅极层125上形成间绝缘层126；在所述间绝缘层126上形成源漏极层127；在所述源漏极层127上形成钝化层128。
在形成所述栅极层125的步骤具体包括：
在所述衬底11上形成第一金属层；
使用第一光罩工艺，所述第一金属层经图案化处理形成位于所述显示区域10的栅极层125、位于所述公共走线区24的公共电极线241、及位于所述换线区的第一信号线。
在形成所述源漏极层127的步骤具体包括：
在所述衬底11上形成第二金属层；
使用第二光罩工艺，所述第二金属层经图案化处理形成位于所述显示区域10的源漏极层127、位于所述GOA走线区21的GOA信号线211、及位于所述换线区的第二信号线。
S20、在所述显示区域10对应的所述薄膜晶体管层上形成色阻层13、以及在所述公共走线区24对应的所述薄膜晶体管层上形成垫高部30；
请参与图3，在本步骤中，所述显示区域10对应的所述色阻层13包括多个色阻单元，所述色阻单元可以包括红色色阻块、绿色色阻块或蓝色色阻块中的一种。
在本实施例中，所述垫高部30可以为色阻单元、黑色光阻或光刻胶等其他有机或无机物中的一种。
在本实施例中，考虑到工艺成本问题，本申请的所述垫高部30选择为色阻单元。所述垫高部30可以为红色色阻块、绿色色阻块或蓝色色阻块中的一种，具体没有限制。
在本实施例中，所述垫高部30还可以覆盖整个所述公共走线区24。
S30、在所述色阻层13上形成像素电极层。
请参与图3，所述像素电极层（未画出）位于所述显示区域10对应的色阻层13上。所述像素电极层通过过孔与所述源漏极层127电连接。
所述GOA换线区23内还设置有位于栅绝缘层124上的第一类信号线231，位于所述间绝缘层126上的第二类信号线232。所述公共走线区24内设置有公共电极线241。所述GOA换线区23位于所述公共走线区24内，被所述公共走线区24所包围。
在本实施例中，虽然所述公共电极线241与所述显示区域10中的栅极层125在同一道光罩工艺中形成，但但是所述公共电极线241与所述栅极层125中的栅线绝缘设置，彼此不相交。
在本实施例中，所述公共电极线241与所述第一类信号线231及所述第二类信号线232绝缘设置。
在本实施例中，所述GOA换线区23在所述显示面板100的衬底11上的正投影与所述公共走线区24在所述衬底11上的正投影不重叠。
由于所述第一类信号线231与所述公共电极线241同层设置，为了保证所述第一类信号线231与所述公共电极线241的短接，所述第一类信号线231与所述公共电极线241应该绝缘设置。
所述GOA换线区23还设置有过孔233，所述过孔233为换线孔。所述第一类信号线231通过所述过孔233与所述第二类信号线232电连接。
在本实施例中，所述第一类信号线231与所述显示区域10中的扫描线（栅线）电连接，所述第二类信号线232与所述GOA走线区21的GOA信号线211电连接。所述第一类信号线231、所述第二类信号线232及所述过孔233使所述GOA信号线211与所述扫描线电连接，进行数据信号的接收与传递。
在本实施例中，所述垫高部30远离所述衬底11一侧的表面与所述衬底11的间距与所述显示区域10中色阻层13远离所述衬底11一侧的表面至所述衬底11的间距的差值的绝对值小于阈值。
所述垫高部30可以与显示区域10的色阻层13在一道光罩工艺中形成，也可以单独施加一道光罩工艺。只要保证所述公共走线区24的所述垫高部30到对应衬底11的厚度与所述显示区域10中的色阻层13到对应衬底11的厚度相差不大即可。
在本申请的显示面板100中，由于公共走线区24紧邻所述显示区域10设置，所述公共走线区24和所述显示区域10内都设置有色阻单元。而色阻单元的厚度较所述显示面板100阵列中的各膜层结构较大，因此所述公共走线区24和所述显示区域10实际厚度差较小。
本申请还提出了一种显示模组，所述显示模组包括上述显示面板。所述显示模组还包括位于所述显示面板上的偏光片层及盖板层。所述显示模组的工作原理与所述显示面板的相同或者相似，本申请不再赘述。
本申请提出了一种显示面板、显示模组及制作方法，该显示面板包括显示区域和位于该显示区域外围的非显示区域；该非显示区域包括GOA走线区和GOA换线区；该GOA换线区内设置有衬底和位于该衬底上的垫高部。本申请通过在该GOA换线区内设置垫高部，减小GOA换线区与显示区域之间的地势差，避免了在该GOA换线区形成过孔时，膜层材料向该过孔周边堆积，提高了显示面板的品质。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括显示区域和位于所述显示区域外围的非显示区域；
    所述非显示区域包括GOA走线区和GOA换线区；
    所述GOA换线区内设置有衬底和位于所述衬底上的垫高部。
  2. 根据权利要求1所述的显示面板，其中，
    所述非显示区域还包括公共走线区；
    所述公共走线区位于所述GOA走线区与所述显示区域之间；
    所述GOA换线区位于所述公共走线区内。
  3. 根据权利要求2所述的显示面板，其中，
    所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
  4. 根据权利要求1所述的显示面板，其中，
    所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
  5. 根据权利要求1所述的显示面板，其中，
    所述垫高部包括色阻单元、黑色光阻或光刻胶中的一种；
    当所述垫高部为色阻单元时，所述垫高部包括红色色阻块、绿色色阻块或蓝色色阻块中的一种。
  6. 根据权利要求1所述的显示面板，其中，
    所述换线区内设置有第一类信号线、第二类信号线以及过孔；
    所述第一类信号线通过所述过孔与所述第二类信号线电连接；
    所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
    所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
  7. 根据权利要求6所述的显示面板，其中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
    所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
    所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
  8. 一种显示面板的制作方法，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
    所述非显示区域包括GOA走线区、GOA换线区以及公共走线区，所述GOA换线区位于所述公共走线区内；
    所述显示面板的制作方法包括：
    提供一衬底，在所述衬底上形成薄膜晶体管层；
    在所述显示区域对应的所述薄膜晶体管层上形成色阻层、以及在所述公共走线区对应的所述薄膜晶体管层上形成垫高部；
    在所述色阻层上形成像素电极层。
  9. 根据权利要求8所述的制作方法，其中，
    提供一衬底，在所述衬底上形成薄膜晶体管层的步骤包括：
    在所述衬底上形成栅极层，包括：
    在所述衬底上形成第一金属层；
    使用第一光罩工艺，使所述第一金属层经图案化处理形成位于所述显示区域的栅极层、位于所述公共走线区的公共电极线、及位于所述换线区的第一信号线；
    以及
    在衬底上形成源漏极层，包括：
    在所述衬底上形成第二金属层；
    使用第二光罩工艺，使所述第二金属层经图案化处理形成位于所述显示区域的源漏极层、位于所述GOA走线区的GOA信号线、及位于所述换线区的第二信号线。
  10. 根据权利要求8所述的制作方法，其中，
    所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
  11. 根据权利要求8所述的制作方法，其中，
    所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
  12. 根据权利要求8所述的制作方法，其中，
    所述换线区内设置有第一类信号线、第二类信号线以及过孔；
    所述第一类信号线通过所述过孔与所述第二类信号线电连接；
    所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
    所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
  13. 根据权利要求12所述的制作方法，其中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
    所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
    所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
  14. 一种显示模组，包括显示面板及位于所述显示面板上的偏光片层及盖板层，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
    所述非显示区域包括GOA走线区和GOA换线区；
    所述GOA换线区内设置有衬底和位于所述衬底上的垫高部。
  15. 根据权利要求14所述的显示模组，其中，
    所述非显示区域还包括公共走线区；
    所述公共走线区位于所述GOA走线区与所述显示区域之间；
    所述GOA换线区位于所述公共走线区内。
  16. 根据权利要求15所述的显示模组，其中，
    所述GOA换线区在所述衬底上的正投影与所述公共走线区在所述衬底上的正投影不重叠。
  17. 根据权利要求14所述的显示模组，其中，
    所述垫高部远离所述衬底一侧的表面与所述衬底的间距与所述显示区域中色阻层远离所述衬底一侧的表面至所述衬底的间距的差值的绝对值小于阈值。
  18. 根据权利要求14所述的显示模组，其中，
    所述垫高部包括色阻单元、黑色光阻或光刻胶中的一种；
    当所述垫高部为色阻单元时，所述垫高部包括红色色阻块、绿色色阻块或蓝色色阻块中的一种。
  19. 根据权利要求14所述的显示模组，其中，
    所述换线区内设置有第一类信号线、第二类信号线以及过孔；
    所述第一类信号线通过所述过孔与所述第二类信号线电连接；
    所述第一类信号线与所述显示区域中的栅极层在同一道光罩工艺中形成；
    所述第二类信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成。
  20. 根据权利要求19所述的显示面板，其中，所述GOA走线区内设置有GOA信号线，公共走线区内设置有公共电极线；
    所述GOA信号线与所述显示区域中的源漏极层在同一道光罩工艺中形成；
    所述公共电极线与所述显示区域中的栅极层在同一道光罩工艺中形成。
PCT/CN2019/084223 2019-04-08 2019-04-25 显示面板、显示模组及制作方法 Ceased WO2020206751A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910277776.0 2019-04-08
CN201910277776.0A CN109976049A (zh) 2019-04-08 2019-04-08 显示面板及其制作方法

Publications (1)

Publication Number Publication Date
WO2020206751A1 true WO2020206751A1 (zh) 2020-10-15

Family

ID=67083500

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/084223 Ceased WO2020206751A1 (zh) 2019-04-08 2019-04-25 显示面板、显示模组及制作方法

Country Status (2)

Country Link
CN (1) CN109976049A (zh)
WO (1) WO2020206751A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110415662B (zh) 2019-07-18 2021-01-01 深圳市华星光电技术有限公司 Goa器件及栅极驱动电路
CN111103715B (zh) * 2019-12-23 2023-03-31 Tcl华星光电技术有限公司 显示面板及其制作方法
CN113138487B (zh) 2021-04-13 2022-08-05 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090261339A1 (en) * 2008-04-18 2009-10-22 Tung-Chang Tsai Gate driver on array of a display and method of making device of a display
CN103456746A (zh) * 2013-09-10 2013-12-18 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107121852A (zh) * 2017-06-20 2017-09-01 武汉华星光电技术有限公司 一种阵列基板及液晶面板
CN108761941A (zh) * 2018-05-31 2018-11-06 深圳市华星光电技术有限公司 Coa型液晶显示面板结构及coa型液晶显示面板的制作方法
CN109346463A (zh) * 2018-10-10 2019-02-15 深圳市华星光电半导体显示技术有限公司 具有静电防护的显示面板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106547127B (zh) * 2017-01-16 2019-10-25 上海天马微电子有限公司 阵列基板、液晶显示面板和显示装置
CN109557708A (zh) * 2018-11-26 2019-04-02 惠科股份有限公司 一种显示面板和显示装置
CN109343280B (zh) * 2018-11-26 2020-12-29 惠科股份有限公司 一种显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090261339A1 (en) * 2008-04-18 2009-10-22 Tung-Chang Tsai Gate driver on array of a display and method of making device of a display
CN103456746A (zh) * 2013-09-10 2013-12-18 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107121852A (zh) * 2017-06-20 2017-09-01 武汉华星光电技术有限公司 一种阵列基板及液晶面板
CN108761941A (zh) * 2018-05-31 2018-11-06 深圳市华星光电技术有限公司 Coa型液晶显示面板结构及coa型液晶显示面板的制作方法
CN109346463A (zh) * 2018-10-10 2019-02-15 深圳市华星光电半导体显示技术有限公司 具有静电防护的显示面板及其制造方法

Also Published As

Publication number Publication date
CN109976049A (zh) 2019-07-05

Similar Documents

Publication Publication Date Title
CN207380420U (zh) 一种阵列基板及显示装置
US8045074B2 (en) Array substrate and display device
CN103383512B (zh) 液晶显示装置及其制造方法
US9244317B2 (en) Active matrix substrate and display device
CN107957645A (zh) 显示面板与其制作方法
WO2014190727A1 (zh) 阵列基板及其制造方法、显示装置
US9971212B2 (en) Array substrate, liquid crystal display panel, and liquid crystal display
US10854681B2 (en) Display device
CN112748616A (zh) 阵列基板、阵列基板的制作方法、显示面板以及显示装置
CN102998865A (zh) 一种阵列基板及其制作方法、显示装置
WO2022052243A1 (zh) 阵列基板及其制备方法、显示面板
WO2017219702A1 (zh) 一种显示基板、其制作方法及显示装置
WO2022011815A1 (zh) 一种无边框显示面板、显示装置及拼接型显示装置
WO2020206751A1 (zh) 显示面板、显示模组及制作方法
WO2020206785A1 (zh) 显示面板及显示模组
US11876102B2 (en) Display substrate, display panel and display apparatus
KR20180014363A (ko) 표시 장치 및 이의 제조 방법
US20150372013A1 (en) Array substrate, manufacturing method thereof, and display device
WO2018205524A1 (zh) 一种阵列基板及其制作方法、显示装置
WO2020206772A1 (zh) 显示面板和电子设备
JP2019148775A (ja) 液晶表示装置
CN111240113A (zh) 阵列基板及显示面板
WO2021114355A1 (zh) 液晶显示装置
WO2021031245A1 (zh) 阵列基板及oled显示装置
WO2022262120A1 (zh) 一种显示面板及显示终端

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19923841

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19923841

Country of ref document: EP

Kind code of ref document: A1