WO2021031245A1 - 阵列基板及oled显示装置 - Google Patents

阵列基板及oled显示装置 Download PDF

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Publication number
WO2021031245A1
WO2021031245A1 PCT/CN2019/104608 CN2019104608W WO2021031245A1 WO 2021031245 A1 WO2021031245 A1 WO 2021031245A1 CN 2019104608 W CN2019104608 W CN 2019104608W WO 2021031245 A1 WO2021031245 A1 WO 2021031245A1
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WIPO (PCT)
Prior art keywords
signal line
electrically connected
thin film
film transistor
line
Prior art date
Application number
PCT/CN2019/104608
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English (en)
French (fr)
Inventor
杜鹏
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/616,462 priority Critical patent/US11152448B2/en
Publication of WO2021031245A1 publication Critical patent/WO2021031245A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and an OLED display device.
  • OLED panels have gradually been used in the field of large-size panels, especially the bottom emission (Bottom Emission) structure, so that the manufacturing process is relatively simple and the cost can be effectively controlled.
  • OLED pixels are more complex, and there are more non-luminous devices in the pixels, especially the vertical lines between sub-pixels are densely distributed, occupying a large area, which will cause the pixel
  • the low aperture ratio results in low brightness and high power consumption of the display device, which is not conducive to product competitiveness.
  • OLED pixels are more complex, and there are more non-luminous devices in the pixels, especially the vertical lines between sub-pixels are densely distributed, occupying a large area, which will cause the pixel
  • the low aperture ratio results in low brightness and high power consumption of the display device, which is not conducive to product competitiveness.
  • the present disclosure provides an array substrate, which can increase the aperture ratio by reducing the area occupied by the lines in the vertical direction of the pixels, thereby solving the problem of the uneven aperture ratio caused by the dense vertical lines in the existing display device. It is a technical problem that affects the brightness and power consumption of the display device.
  • the embodiment of the present disclosure provides an array substrate including: sub-pixels distributed in an array, and data lines and power signal lines are arranged between the sub-pixels in two adjacent columns; and
  • the compensation signal line is arranged in parallel with the power signal line;
  • the data line and the power signal line are prepared on different film surface, and the data line and the power signal line at least partially overlap;
  • the data line is disposed on the array substrate
  • the power signal line is prepared on the back side of the array substrate and is arranged in alignment with the data line, and the signal input end of the power signal line extends to the binding
  • the area is electrically connected to the control chip through the through hole opened in the array substrate.
  • the extension direction of the data line and the power signal line are the same.
  • each sub-pixel of the array substrate includes a first thin film transistor, a second thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, and a storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the scan line, and the source is electrically connected to the data line;
  • the gate of the second thin film transistor is electrically connected to the drain of the first thin film transistor, the source is electrically connected to the power signal line, and the drain is electrically connected to the anode of the OLED;
  • the cathode of the OLED is electrically connected to the cathode signal line;
  • the storage capacitor is electrically connected to the gate and drain of the second thin film transistor.
  • each column of the sub-pixels corresponds to one data line and one power signal line.
  • the compensation signal line and the data line at least partially overlap, and the compensation signal line and the data line extend in the same direction.
  • the compensation signal line is prepared on the back side of the array substrate, and is arranged alternately with the power signal line.
  • one sub-pixel of the array substrate includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, and the The compensation signal line and a storage capacitor; its adjacent sub-pixels include a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, the Compensation signal line and a storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the scan line, and the source is electrically connected to the N-level data line;
  • the gate of the second thin film transistor is electrically connected to the drain of the first thin film transistor, the source is electrically connected to the N-level power signal line, and the drain is electrically connected to the anode of the OLED;
  • the cathode of the OLED is electrically connected to the cathode signal line;
  • the gate of the third thin film transistor is electrically connected to the scan line, the source is electrically connected to the compensation signal line, and the drain is electrically connected to the drain of the second thin film transistor;
  • the gate of the fourth thin film transistor is electrically connected to the scan line, and the source is electrically connected to the N+1 level data line;
  • the gate of the fifth thin film transistor is electrically connected to the drain of the fourth thin film transistor, the source is electrically connected to the N+1 level power signal line, and the drain is electrically connected to the anode of the OLED;
  • the gate of the sixth thin film transistor is electrically connected to the scan line, the source is electrically connected to the compensation signal line, and the drain is electrically connected to the drain of the fifth thin film transistor;
  • the storage capacitor is electrically connected to the gate and drain of the second thin film transistor or is electrically connected to the gate and drain of the fifth thin film transistor;
  • the two adjacent sub-pixels share one compensation signal line.
  • each column of the sub-pixels corresponds to one of the data line, and every two columns of the sub-pixels corresponds to one of the power signal line or the compensation signal line.
  • an array substrate including sub-pixels distributed in an array, and data lines and power signal lines are arranged between two adjacent columns of sub-pixels;
  • the data line and the power signal line are prepared on different film surfaces, and the data line and the power signal line at least partially overlap.
  • the data line is disposed on the array substrate
  • the power signal line is prepared on the back side of the array substrate, and is arranged in alignment with the data line
  • the power signal line The signal input end extends to the binding area, and is electrically connected to the control chip through the through hole opened in the array substrate.
  • the extension direction of the data line and the power signal line are the same.
  • each sub-pixel of the array substrate includes a first thin film transistor, a second thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, and a storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the scan line, and the source is electrically connected to the data line;
  • the gate of the second thin film transistor is electrically connected to the drain of the first thin film transistor, the source is electrically connected to the power signal line, and the drain is electrically connected to the anode of the OLED;
  • the cathode of the OLED is electrically connected to the cathode signal line;
  • the storage capacitor is electrically connected to the gate and drain of the second thin film transistor.
  • each column of the sub-pixels corresponds to one data line and one power signal line.
  • the array substrate further includes a compensation signal line arranged in parallel with the power signal line, the compensation signal line and the data line at least partially overlap, the compensation signal line and the data line
  • the extension direction is the same.
  • the compensation signal line is prepared on the back side of the array substrate, and is arranged alternately with the power signal line.
  • one sub-pixel of the array substrate includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, and the The compensation signal line and a storage capacitor; its adjacent sub-pixels include a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a scan line, a cathode signal line, the data line, the power signal line, the Compensation signal line and a storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the scan line, and the source is electrically connected to the N-level data line;
  • the gate of the second thin film transistor is electrically connected to the drain of the first thin film transistor, the source is electrically connected to the N-level power signal line, and the drain is electrically connected to the anode of the OLED;
  • the cathode of the OLED is electrically connected to the cathode signal line;
  • the gate of the third thin film transistor is electrically connected to the scan line, the source is electrically connected to the compensation signal line, and the drain is electrically connected to the drain of the second thin film transistor;
  • the gate of the fourth thin film transistor is electrically connected to the scan line, and the source is electrically connected to the N+1 level data line;
  • the gate of the fifth thin film transistor is electrically connected to the drain of the fourth thin film transistor, the source is electrically connected to the N+1 level power signal line, and the drain is electrically connected to the anode of the OLED;
  • the gate of the sixth thin film transistor is electrically connected to the scan line, the source is electrically connected to the compensation signal line, and the drain is electrically connected to the drain of the fifth thin film transistor;
  • the storage capacitor is electrically connected to the gate and drain of the second thin film transistor or is electrically connected to the gate and drain of the fifth thin film transistor;
  • the two adjacent sub-pixels share one compensation signal line.
  • each column of the sub-pixels corresponds to one of the data line, and every two columns of the sub-pixels corresponds to one of the power signal line or the compensation signal line.
  • an OLED display device including an array substrate, the array substrate including: sub-pixels distributed in an array, and data lines and power signal lines are arranged between two adjacent columns of sub-pixels;
  • the data line and the power signal line are prepared on different film surfaces, and the data line and the power signal line at least partially overlap.
  • the data line is disposed on the array substrate
  • the power signal line is prepared on the back side of the array substrate, and is arranged in alignment with the data line
  • the power signal line The signal input end extends to the binding area, and is electrically connected to the control chip through the through hole opened in the array substrate.
  • the extension direction of the data line and the power signal line are the same.
  • the beneficial effects of the present disclosure are: compared with the existing array substrate and OLED display device, the array substrate and the OLED display device of the present disclosure prepare vertical data lines and power signal lines on the surfaces of different film layers, and The data line and the power signal line at least partially overlap, so that each column of sub-pixels corresponds to one data line and one power signal line, so that the area occupied by the line in the vertical direction of the pixel becomes smaller, so that the aperture ratio of the pixel can be increased.
  • the dense vertical lines in the existing array substrate result in a technical problem that the aperture ratio is low, which affects the brightness and power consumption of the display device.
  • FIG. 1 is a schematic diagram of a pixel structure in a conventional array substrate
  • 2A is a schematic diagram of a partial structure of the first embodiment of the disclosed array substrate
  • 2B is a schematic diagram of the pixel structure of the first embodiment of the disclosed array substrate
  • FIG. 2C is a schematic cross-sectional structure diagram of the A-A ⁇ area in FIG. 2B;
  • 2D is a pixel equivalent circuit diagram of the first embodiment of the disclosed array substrate
  • 3A is a schematic diagram of the pixel structure of the second embodiment of the disclosed array substrate
  • 3B is a schematic cross-sectional structure diagram of the B-B ⁇ area in FIG. 3A;
  • 3C is a pixel equivalent circuit diagram of the second embodiment of the disclosed array substrate.
  • Figure 1 is a schematic diagram of the pixel structure of the existing array substrate. It can be seen that there are multiple sub-pixels 101 distributed in the pixels, and multiple data lines 102 and power signal lines are arranged between the sub-pixels 101. 103. There are a large number of data lines 102 and power signal lines 103, which are distributed in the pixels and occupy a large area, resulting in the low aperture ratio of the existing OLED pixels, which in turn makes the OLED display device low in brightness and high in power consumption
  • the present disclosure is directed to the existing array substrate and OLED display device. Because the vertical lines intensively occupy a large area, the pixel aperture ratio is low and the display device has low brightness and high power consumption. This embodiment can solve the technical problem The defect.
  • the array substrate provided by the first embodiment of the present disclosure includes: sub-pixels 201 distributed in an array, and data lines are arranged between two adjacent columns of sub-pixels 201 202 and the power signal line 203, wherein the data line 202 and the power signal line 203 are prepared on different film surfaces, and the data line 202 and the power signal line 203 at least partially overlap.
  • the data line 202 is disposed on the array substrate, and the power signal line 203 is prepared on the back side of the array substrate.
  • This embodiment is prepared on the back side of the glass substrate 204, and The data line 202 is aligned, and the signal input end of the power signal line 203 extends to the bonding area, and is electrically connected to the control chip 206 through the through hole 205 opened in the array substrate.
  • the binding area includes: a bonding pad 207, which is provided on the surface of one side of the glass substrate 204 and covers one side opening of the through hole 205; a conductive film layer 208, the conductive The film layer 208 is laid on the surface of the pad 207; the power signal line 203 is connected to the through hole 205, the pad 207, and the conductive film layer 208.
  • a conductive object 209 is provided in the through hole 205, and the conductive object 209 may be an iron rod, a copper block, or any other conductive material.
  • the conductive film layer 208 is composed of two stacked layers of conductive glue.
  • the conductive film layer 208 can bond and conduct the pad 207 and the control chip 206 at the other end of the conductive film layer 208, so that The control chip 206 can drive the array substrate.
  • the power signal line 203 is prepared on the surface of one side of the glass substrate 204, and another power signal line 203 is connected to the other end of the pad 207 (not shown in FIG. 2A),
  • the power signal lines 203 are connected and conducted through the through hole 205 and the conductive object 209, the pad 207, and the conductive film layer 208, and the two sides of the glass substrate 204 Conduction.
  • the pixel structure of the first embodiment of the array substrate of the present disclosure is that each column of the sub-pixels 201 corresponds to one data line 202 and one power signal line 203, and the data line 202 At least partially overlapped with the power signal line 203, so that the area occupied by the vertical wiring in the pixel structure can be reduced.
  • the power signal of the pixel structure of this embodiment is The area between the line 203 and the data line 202 is reduced, which increases the aperture ratio of the pixel.
  • the sub-pixels in this embodiment are R, G, and B. However, in other embodiments, there may be more than three sub-pixels 201, and the arrangement of the sub-pixels 201 is not limited, and may be Any kind of layout.
  • FIG. 2C is a cross-sectional view at AA′ of FIG. 2B, from top to bottom in the figure are the data line 202, the gate insulating layer 210, the scan line 211, the glass substrate 204, and the power signal line 203, wherein
  • the data line 202 is prepared on the surface of the gate insulating layer 210.
  • the data line 202 can also be prepared on another film layer, the film layer and the glass substrate 204 are parallel to each other, and the data
  • the wires 202 are prepared along the extending direction of the surface of the film layer, and the power signal wires 203 are prepared along the extending direction of the array substrate, that is, the power signal wires 203 and the data wires 202 extend in the same direction.
  • the thickness of the glass substrate 204 is relatively large, about 0.5 mm, and the thickness of the insulating layers such as the gate insulating layer 210 and the planarization layer (not shown in the figure) is much smaller than the thickness of the glass substrate 204, generally It is several microns in size, so the parasitic capacitance between the power signal line 203 and the data line 202 is very small, and the mutual coupling between the two can be ignored.
  • each sub-pixel 201 of the array substrate includes a first thin film transistor T1 and a second thin film transistor T1.
  • Thin film transistor T2 scan line Gate, cathode signal line VSS, said data line Data, said power signal line VDD, and a storage capacitor Clc; wherein, the gate of said first thin film transistor T1 is electrically connected to said scan line Gate, the source is electrically connected to the data line Data; the gate of the second thin film transistor T2 is electrically connected to the drain of the first thin film transistor T1, the source is electrically connected to the power signal line VDD, and the drain The electrode is electrically connected to the anode of the OLED; the cathode of the OLED is electrically connected to the cathode signal line VSS; the storage capacitor Clc is electrically connected to the gate and the drain of the second thin film transistor T2.
  • the pixel in this embodiment is composed of two thin film transistors, a storage capacitor, and an OLED device.
  • the power signal line VDD is used to provide power to the OLED device, and the data line Data is responsible for transmitting image data signals.
  • the data line 202 and the power signal line 203 are respectively prepared on both sides of the glass substrate 204, and the power signal line 203 is prepared on the surface of one side of the glass substrate 204
  • the data line 202 is prepared on the surface of the gate insulating layer 210, but in other embodiments, the data line 202 and the power signal line 203 can be prepared on the surface of any two different film layers, as long as The power signal line 203 and the data line 202 extend in the same direction, and the data line 202 and the power signal line 203 can at least partially overlap in the pixel structure.
  • the first embodiment of the present disclosure increases the aperture ratio of the pixel by reducing the area between the data line 202 and the power signal line 203 so that the two at least partially overlap.
  • FIGS. 3A-3C are schematic diagrams of the second embodiment of the array substrate of the present disclosure.
  • the array substrate provided by the second embodiment of the present disclosure includes: sub-pixels 301 distributed in an array, and data are arranged between two adjacent columns of sub-pixels 301 Line 302, power signal line 303 and compensation signal line 312, wherein the data line 302, the power signal line 303 and the compensation signal line 312 are prepared on different film surfaces, and the data line 302 is The power signal line 303 at least partially overlaps, the compensation signal line 312 and the data line 302 at least partially overlap, the data line 302 and the power signal line 303 extend in the same direction, and the compensation signal line 312 and the The data lines 302 extend in the same direction.
  • the signal input end of the compensation signal line 312 extends to the bonding area, and is electrically connected to the control chip through the through hole opened in the array substrate.
  • the compensation signal line 312 and the power signal line 303 are prepared on the surface of the same film layer.
  • the compensation signal line 312 and the power signal line 303 are prepared on the back side of the glass substrate 304.
  • the compensation signal lines 312 and the power signal lines 303 are alternately distributed on the surface of the film layer, and respectively correspond to the data lines 302 on the surface of another film layer.
  • each column of the sub-pixel 301 corresponds to one of the data line 302, and every two columns of the sub-pixel 301 corresponds to one of the power signal line 303 or one of the compensation signal line 312, that is, in the pixel structure In the vertical direction of, the power signal line 303 and the compensation signal line 312 are alternately distributed with each column of the sub-pixels 301 as separation lines.
  • this embodiment has more compensation signal lines 312, except that the power signal line 303 and the data line 302 at least partially overlap to increase the aperture ratio of the pixel, because the compensation signal The line 312 and the data line 302 also at least partially overlap, so that the area between the compensation signal line 312 and the data line 302 is reduced, and the aperture ratio of the pixel can also be increased.
  • the sub-pixels 301 are R, G, and B. However, in other embodiments, there may be more than three types of the sub-pixels 301, and the arrangement of the sub-pixels 301 is not limited. It is any kind of layout.
  • 3B is a cross-sectional view at BB' in FIG. 3A. It can be seen from the figure that the compensation signal line 312 and the power signal line 303 are located on the same side surface of the glass substrate 304, and the data line 302 is located On the other side of the glass substrate 304, the gate insulating layer 310 and the scan line 311 are laid between the data line 302 and the glass substrate 304, the compensation signal line 312 and the power signal line 303 are arranged at intervals on the surface of the glass substrate 304, respectively corresponding to the data lines 302.
  • the power signal lines 303 and the compensation signal lines 312 can be made of the same layer of metal, wherein the data lines 302 It is prepared on the surface of the gate insulating layer 210.
  • the data line 302 can also be prepared on another film layer.
  • the film layer and the glass substrate 304 are parallel to each other, and the data line 302 runs along the film
  • the surface extension direction of the layer is prepared, and the power signal line 303 and the compensation signal line 312 are prepared along the extension direction of the array substrate, that is, the power signal line 303, the compensation signal line 312 and the The extension direction of the data line 302 is the same.
  • the conduction method between the power signal lines 303, the compensation signal lines 312, and both sides of the glass substrate 304 in this embodiment is the same as that of the first embodiment, which consists of through holes and binding areas. To achieve this, similarly, the through hole and the bonding area can also be connected to the conductive array substrate and the control chip.
  • 3C is a pixel equivalent circuit diagram of the second embodiment of the array substrate of the present disclosure.
  • One sub-pixel of the array substrate includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a scan line Gate,
  • its adjacent sub-pixels include a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth Thin film transistor T6, scan line Gate, cathode signal line VSS, said data line Data, said power signal line VDD, said compensation signal line Vc, and a storage capacitor Clc;
  • the gate of said first thin film transistor T1 Is electrically connected to the scan line Gate, and the source is electrically connected to the N-level data line Data(n);
  • the gate of the second thin film transistor T2 is electrically connected to the drain of the first thin film transistor T1, and the source The electrode is electrically connected
  • This embodiment uses a 3T1C pixel architecture. Compared with the first embodiment, the second embodiment adds a compensation signal Vc.
  • the pixel of this embodiment includes three thin film transistors, a storage capacitor, and an OLED device. Vc The signal line is connected to the anode of the OLED through a thin film transistor.
  • the data line 302, the power signal line 303, and the compensation signal line 312 are respectively arranged on both sides of the glass substrate 304, wherein the power signal line 303 and the compensation signal line 312
  • the compensation signal line 312 is located on the same side surface of the glass substrate 304, and the data line 302 is prepared on the surface of the gate insulating layer 310.
  • the data line 302 and the power signal line 303 and the compensation signal line 312 can be prepared on any two different film surfaces, as long as the data line 302 and the power signal line 303 extend in the same direction, and the data line 302 and the compensation signal line 312
  • the extension direction is the same, and in the pixel structure, the data line 302 and the power signal line 303 at least partially overlap, the data line 302 and the compensation signal line 312 at least partially overlap, and the power signal line 303 and the power signal line 303 overlap at least partially.
  • the compensation signal lines 312 may be arranged alternately on the surface of the same film layer.
  • the second embodiment of the present disclosure reduces the area between the compensation signal line 312 and the data line 302, so that the data line 302 and the power signal line 303 are ,
  • the data line 302 and the compensation signal line 312 at least partially overlap, so as to increase the aperture ratio of the pixel.
  • the working principle of the OLED display device of this embodiment is consistent with the working principle of the array substrate of the above-mentioned embodiment.
  • the beneficial effects of the present disclosure are: compared with the existing array substrate and OLED display device, the array substrate and the OLED display device of the present disclosure prepare vertical data lines and power signal lines on the surfaces of different film layers, and The data line and the power signal line at least partially overlap, so that each column of sub-pixels corresponds to one data line and one power signal line, so that the area occupied by the line in the vertical direction of the pixel becomes smaller, so that the aperture ratio of the pixel can be increased.
  • the dense vertical lines in the existing array substrate result in a technical problem that the aperture ratio is low, which affects the brightness and power consumption of the display device.

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Abstract

一种阵列基板，包括阵列分布的子像素（201），相邻两列子像素（201）之间设置有数据线（202）和电源信号线（203）；其中，数据线（202）与电源信号线（203）制备于不同的膜层表面，且数据线（202）与电源信号线（203）至少部分重叠，其还提供一种包括所述阵列基板的OLED显示装置，该阵列基板具有较高的开口率。

Description

阵列基板及OLED显示装置 技术领域
本揭示涉及显示技术领域，尤其涉及一种阵列基板及OLED显示装置。
 背景技术
OLED面板已经逐渐应用在大尺寸面板领域中，尤其是底发光（Bottom Emission）的结构，这样制程相对简单，成本也能得到有效的控制。
与TFT-LCD的像素相比，OLED的像素更加复杂，像素中的不发光器件较多，尤其是子像素之间的竖直线路的分布密集，占用了很大的面积，这样会造成像素的开口率偏低，进而导致显示装置的亮度低、功耗大，不利于产品的竞争力。
因此，提高OLED像素的开口率是业内亟待解决的问题。
 技术问题
与TFT-LCD的像素相比，OLED的像素更加复杂，像素中的不发光器件较多，尤其是子像素之间的竖直线路的分布密集，占用了很大的面积，这样会造成像素的开口率偏低，进而导致显示装置的亮度低、功耗大，不利于产品的竞争力。
 技术解决方案
为解决上述问题，本揭示提供一种阵列基板，通过减小像素在竖直方向被线路占用的面积，从而能够提高开口率，以此解决现有显示装置中的竖直线路密集造成开口率偏低而影响显示装置的亮度和功耗的技术问题。
为解决上述问题，本揭示提供的技术方案如下：
根据本揭示一实施例，本揭示实施例提供一种阵列基板，包括：阵列分布的子像素，相邻两列所述子像素之间设置有数据线和电源信号线；以及
补偿信号线，所述补偿信号线与所述电源信号线平行设置；
其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠；
所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
根据本揭示一实施例，所述数据线与所述电源信号线的延伸方向相同。
根据本揭示一实施例，所述阵列基板的每个子像素包括第一薄膜晶体管、第二薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线以及一存储电容；
其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述数据线；
所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述电源信号线，漏极电连接于所述OLED的阳极；
所述OLED的阴极电连接于所述阴极信号线；
所述存储电容电连接于所述第二薄膜晶体管的栅极与漏极。
根据本揭示一实施例，每一列所述子像素对应一条所述数据线与一条所述电源信号线。
根据本揭示一实施例，所述补偿信号线与所述数据线至少部分重叠，所述补偿信号线与所述数据线的延伸方向相同。
根据本揭示一实施例，所述补偿信号线制备于所述阵列基板的背侧，且与所述电源信号线交替设置。
根据本揭示一实施例，所述阵列基板的一个子像素包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；其相邻子像素包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；
其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N级数据线；
所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述N级电源信号线，漏极电连接于所述OLED的阳极；
所述OLED的阴极电连接于所述阴极信号线；
所述第三薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第二薄膜晶体管的漏极；
所述第四薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N+1级数据线；
所述第五薄膜晶体管的栅极电连接于所述第四薄膜晶体管的漏极，源极电连接于所述N+1级电源信号线，漏极电连接于所述OLED的阳极；
所述第六薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第五薄膜晶体管的漏极；
所述存储电容电连接于所述第二薄膜晶体管的栅极和漏极或电连接于所述第五薄膜晶体管的栅极和漏极；
所述两个相邻的子像素共用一条所述补偿信号线。
根据本揭示一实施例，每一列所述子像素对应一条所述数据线，每两列所述子像素对应一条所述电源信号线或所述补偿信号线。
本揭示实施例的第二方面，提供一种阵列基板，包括阵列分布的子像素，相邻两列子像素之间设置有数据线和电源信号线；
其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠。
根据本揭示一实施例，所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
根据本揭示一实施例，所述数据线与所述电源信号线的延伸方向相同。
根据本揭示一实施例，所述阵列基板的每个子像素包括第一薄膜晶体管、第二薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线以及一存储电容；
其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述数据线；
所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述电源信号线，漏极电连接于所述OLED的阳极；
所述OLED的阴极电连接于所述阴极信号线；
所述存储电容电连接于所述第二薄膜晶体管的栅极与漏极。
根据本揭示一实施例，每一列所述子像素对应一条所述数据线与一条所述电源信号线。
根据本揭示一实施例，所述阵列基板还包括与所述电源信号线平行设置的补偿信号线，所述补偿信号线与所述数据线至少部分重叠，所述补偿信号线与所述数据线的延伸方向相同。
根据本揭示一实施例，所述补偿信号线制备于所述阵列基板的背侧，且与所述电源信号线交替设置。
根据本揭示一实施例，所述阵列基板的一个子像素包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；其相邻子像素包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；
其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N级数据线；
所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述N级电源信号线，漏极电连接于所述OLED的阳极；
所述OLED的阴极电连接于所述阴极信号线；
所述第三薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第二薄膜晶体管的漏极；
所述第四薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N+1级数据线；
所述第五薄膜晶体管的栅极电连接于所述第四薄膜晶体管的漏极，源极电连接于所述N+1级电源信号线，漏极电连接于所述OLED的阳极；
所述第六薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第五薄膜晶体管的漏极；
所述存储电容电连接于所述第二薄膜晶体管的栅极和漏极或电连接于所述第五薄膜晶体管的栅极和漏极；
所述两个相邻的子像素共用一条所述补偿信号线。
根据本揭示一实施例，每一列所述子像素对应一条所述数据线，每两列所述子像素对应一条所述电源信号线或所述补偿信号线。
根据本揭示实施例的第三方面，还提供一种OLED显示装置，包括阵列基板，所述阵列基板包括：阵列分布的子像素，相邻两列子像素之间设置有数据线和电源信号线；
其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠。
根据本揭示一实施例，所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
根据本揭示一实施例，所述数据线与所述电源信号线的延伸方向相同。
 有益效果
本揭示的有益效果为：相较于现有的阵列基板和OLED显示装置，本揭示的阵列基板和OLED显示装置将竖直方向的数据线与电源信号线分别制备于不同膜层的表面，且数据线与电源信号线至少部分重叠，使得每一列子像素对应一条数据线和一条电源信号线，这样像素在竖直方向被线路占用的面积变小，从而能够提高像素的开口率，以此解决现有阵列基板中的竖直线路密集造成开口率偏低而影响显示装置亮度和功耗的技术问题。
 附图说明
图1为一种现有的阵列基板中的像素结构示意图；
图2A为本揭示的阵列基板的第一种实施例的部分结构示意图；
图2B为本揭示的阵列基板的第一种实施例的像素结构示意图；
图2C为图2B中A-A`区域的截面结构示意图；
图2D为本揭示的阵列基板的第一种实施例的像素等效电路图；
图3A为本揭示的阵列基板的第二种实施例的像素结构示意图；
图3B为图3A中B-B`区域的截面结构示意图；
图3C为本揭示的阵列基板的第二种实施例的像素等效电路图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
OLED的像素结构较为复杂，图1为现有阵列基板的像素结构示意图，图中可看出，像素中分布有多个子像素101，子像素101之间设置有多条数据线102和电源信号线103，数据线102和电源信号线103数量较多，分布在像素中占据了很大的面积，导致现有的OLED像素开口率不高，进而使得OLED显示装置的亮度低、功耗大
本揭示针对现有的阵列基板和OLED显示装置，由于竖直方向的线路密集占用大量的面积，导致像素开口率偏低而使显示装置的亮度低功耗大的技术问题，本实施例能够解决该缺陷。
图2A-2D为本揭示阵列基板的第一种实施例的示意图，本揭示第一种实施例提供的阵列基板包括：阵列分布的子像素201，相邻两列子像素201之间设置有数据线202和电源信号线203，其中，所述数据线202与所述电源信号线203制备于不同的膜层表面，且所述数据线202与所述电源信号线203至少部分重叠。
如图2A所示，所述数据线202设置于所述阵列基板上，所述电源信号线203制备于所述阵列基板的背侧，本实施例为制备于玻璃基板204的背侧，且与所述数据线202对位设置，所述电源信号线203的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔205与控制芯片206电性连接。
其中，所述绑定区域包括：焊盘207，所述焊盘207设置于所述玻璃基板204一侧的表面且覆盖于所述通孔205的一侧开口；导电膜层208，所述导电膜层208铺设于所述焊盘207表面；所述电源信号线203与所述通孔205、所述焊盘207、所述导电膜层208连接导通。
所述通孔205中设置有导电物209，所述导电物209可以是铁棒、铜块或其它任何可以导电的物质。
所述导电膜层208是由两层叠层设置的导电胶组成，所述导电膜层208可黏结导通所述焊盘207与位于所述导电膜层208另一端的所述控制芯片206，使得所述控制芯片206可驱动所述阵列基板。
在本实施例中，所述电源信号线203制备于所述玻璃基板204一侧的表面，在所述焊盘207的另一端连接有另外的电源信号线203（图2A中未示出），通过所述通孔205及其内部的所述导电物209、所述焊盘207、所述导电膜层208将所述电源信号线203之间连接导通，以及将所述玻璃基板204两侧导通。
如图2B所示，本揭示的阵列基板的第一种实施例的像素结构为每一列所述子像素201对应一条所述数据线202与一条所述电源信号线203，且所述数据线202和所述电源信号线203至少有部分重叠在一起，这样可以使得像素结构中竖直走线所占据的面积减少，图2B和图1相比较可知，本实施例的像素结构的所述电源信号线203和所述数据线202之间的面积缩减，这样使得像素的开口率升高。
本实施例中的所述子像素为R、G、B三种，但在其它实施例中，可以不止有三种所述子像素201，且所述子像素201的排布方式不限定，可以是任一种布局。
图2C为图2B的A-A`处的截面图，图中由上至下分别是所述数据线202、栅绝缘层210、扫描线211、所述玻璃基板204和所述电源信号线203，其中，所述数据线202制备于栅绝缘层210表面，在其它实施例中，所述数据线202也可以制备于其它膜层，所述膜层与所述玻璃基板204互相平行，且所述数据线202沿所述膜层的表面延伸方向进行制备，而所述电源信号线203沿所述阵列基板的延伸方向进行制备，即所述电源信号线203与所述数据线202的延伸方向相同。
由于所述玻璃基板204的厚度较大，约为0.5mm，而所述栅绝缘层210和平坦化层（图中未示出）等绝缘层的厚度远小于所述玻璃基板204的厚度，一般为数微米大小，因此所述电源信号线203和所述数据线202之间的寄生电容非常小，两者之间的相互耦合可以忽略。
图2D为本揭示的阵列基板的第一种实施例的像素等效电路图，本实施例采用的是2T1C的像素架构，即所述阵列基板的每个子像素201包括第一薄膜晶体管T1、第二薄膜晶体管T2、扫描线Gate、阴极信号线VSS、所述数据线Data、所述电源信号线VDD以及一存储电容Clc；其中，所述第一薄膜晶体管T1的栅极电连接于所述扫描线Gate，源极电连接于所述数据线Data；所述第二薄膜晶体管T2的栅极电连接于所述第一薄膜晶体管T1的漏极，源极电连接于所述电源信号线VDD，漏极电连接于所述OLED的阳极；所述OLED的阴极电连接于所述阴极信号线VSS；所述存储电容电Clc电连接于所述第二薄膜晶体管T2的栅极与漏极。
本实施例的像素由两个薄膜晶体管、一个存储电容和OLED器件组成，其中，所述电源信号线VDD的作用是给OLED器件提供电源，所述数据线Data则是负责传输图像的数据信号。
本揭示的第一种实施例是将所述数据线202和所述电源信号线203分别制备于所述玻璃基板204两侧，所述电源信号线203制备于所述玻璃基板204一侧的表面，所述数据线202制备于所述栅绝缘层210的表面，但在其它实施例中，所述数据线202和所述电源信号线203可以制备在任意不同两个膜层的表面，只要所述电源信号线203与所述数据线202延伸方向相同，且在像素结构中所述数据线202和所述电源信号线203至少能部分重叠即可。
本揭示的第一种实施例通过减少所述数据线202与所述电源信号线203之间的面积，使两者至少部分重叠来提高像素的开口率。
图3A-3C为本揭示的阵列基板的第二种实施例的示意图，本揭示第二种实施例提供的阵列基板包括：阵列分布的子像素301，相邻两列子像素301之间设置有数据线302和电源信号线303及补偿信号线312，其中，所述数据线302与所述电源信号线303及所述补偿信号线312制备于不同的膜层表面，且所述数据线302与所述电源信号线303至少部分重叠，所述补偿信号线312与所述数据线302至少部分重叠，所述数据线302与所述电源信号线303的延伸方向相同，所述补偿信号线312与所述数据线302延伸方向相同。
所述补偿信号线312的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
所述补偿信号线312与所述电源信号线303制备于同一层膜层的表面，本实施例为所述补偿信号线312与所述电源信号线303制备于所述玻璃基板304的背侧，且所述补偿信号线312与所述电源信号线303在膜层的表面交替分布，并与另一膜层表面的所述数据线302分别对应。
如图3A所示，每一列所述子像素301对应一条所述数据线302，每两列所述子像素301对应一条所述电源信号线303或一条所述补偿信号线312，即在像素结构的竖直方向上，所述电源信号线303与所述补偿信号线312以每列所述子像素301为分隔线交替分布。本实施例与第一种实施例相比，多了所述补偿信号线312，除了所述电源信号线303与所述数据线302至少部分重叠提高像素的开口率之外，由于所述补偿信号线312与所述数据线302也至少部分重叠，使得所述补偿信号线312与所述数据线302之间的面积缩减，也能够提高像素的开口率。
本实施例中的所述子像素301为R、G、B三种，但在其它实施例中，可以不止有三种所述子像素301，且所述子像素301的排布方式不限定，可以是任一种布局。
图3B是图3A中B-B`处的截面图，由图中可看到，所述补偿信号线312与所述电源信号线303位于所述玻璃基板304的同一侧表面，所述数据线302位于所述玻璃基板304的另一侧，所述数据线302和所述玻璃基板304之间铺设有所述栅绝缘层310和所述扫描线311，所述补偿信号线312和所述电源信号线303在所述玻璃基板304的表面间隔排列，分别与所述数据线302相对应，所述电源信号线303与所述补偿信号线312可以用同一层金属来制作，其中，所述数据线302制备于栅绝缘层210表面，在其它实施例中，所述数据线302也可以制备于其它膜层，所述膜层与所述玻璃基板304互相平行，且所述数据线302沿所述膜层的表面延伸方向进行制备，而所述电源信号线303和所述补偿信号线312沿所述阵列基板的延伸方向进行制备，即所述电源信号线303、所述补偿信号线312与所述数据线302的延伸方向相同。
本实施例中的所述电源信号线303之间和所述补偿信号线312之间以及所述玻璃基板304两侧的导通方法与第一种实施例一样，是由通孔及绑定区域来实现，同样，通孔及绑定区域也可以连接导通阵列基板和控制芯片。
图3C是本揭示阵列基板的第二种实施例的像素等效电路图，所述阵列基板的一个子像素包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、扫描线Gate、阴极信号线VSS、所述数据线Data、所述电源信号线VDD、所述补偿信号线Vc以及一存储电容Clc；其相邻子像素包括第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、扫描线Gate、阴极信号线VSS、所述数据线Data、所述电源信号线VDD、所述补偿信号线Vc以及一存储电容Clc；其中，所述第一薄膜晶体管T1的栅极电连接于所述扫描线Gate，源极电连接于所述N级数据线Data(n)；所述第二薄膜晶体管T2的栅极电连接于所述第一薄膜晶体管T1的漏极，源极电连接于所述N级电源信号线VDD(n)，漏极电连接于所述OLED的阳极；所述OLED的阴极电连接于所述阴极信号线VSS；所述第三薄膜晶体管T3的栅极电连接于所述扫描线Gate，源极电连接于所述补偿信号线Vc，漏极电连接于所述第二薄膜晶体管T2的漏极；所述第四薄膜晶体管T4的栅极电连接于所述扫描线Gate，源极电连接于所述N+1级数据线Data(n+1)；所述第五薄膜晶体管T5的栅极电连接于所述第四薄膜晶体管T4的漏极，源极电连接于所述N+1级电源信号线VDD(n+1)，漏极电连接于所述OLED的阳极；所述第六薄膜晶体管T6的栅极电连接于所述扫描线Gate，源极电连接于所述补偿信号线Vc，漏极电连接于所述第五薄膜晶体管T5的漏极；所述存储电容电Clc连接于所述第二薄膜晶体管T2的栅极和漏极或电连接于所述第五薄膜晶体管T5的栅极和漏极；所述两个相邻的子像素共用一条所述补偿信号线Vc。
本实施例采用的是3T1C像素架构，与第一种实施例相比，第二种实施例增加了一个补偿信号Vc，本实施例的像素包括三个薄膜晶体管、一个存储电容和OLED器件，Vc信号线通过一个薄膜晶体管和OLED的阳极连接。
本揭示的第二种实施例是将所述数据线302和所述电源信号线303与所述补偿信号线312分别设置在所述玻璃基板304的两侧，其中所述电源信号线303和所述补偿信号线312位于所述玻璃基板304的同一侧表面，所述数据线302制备于所述栅绝缘层310的表面，但在其它实施例中，所述数据线302和所述电源信号线303以及所述补偿信号线312可以制备在任意两个不同的膜层表面，只需所述数据线302与所述电源信号线303延伸方向相同、所述数据线302与所述补偿信号线312延伸方向相同，且在像素结构中，所述数据线302和所述电源信号线303至少部分重叠，所述数据线302和所述补偿信号线312至少部分重叠，所述电源信号线303与所述补偿信号线312在同一膜层表面交替排列即可。
本揭示的第二种实施例在第一种的实施例的基础上，减少所述补偿信号线312与所述数据线302之间的面积，使所述数据线302与所述电源信号线303、所述数据线302与所述补偿信号线312至少部分重叠，以此来提高像素的开口率。
本实施例的OLED显示装置的工作原理跟上述实施例的阵列基板的工作原理一致，具体可参考上述实施例的阵列基板的工作原理，此处不再做赘述。
本揭示的有益效果为：相较于现有的阵列基板和OLED显示装置，本揭示的阵列基板和OLED显示装置将竖直方向的数据线与电源信号线分别制备于不同膜层的表面，且数据线与电源信号线至少部分重叠，使得每一列子像素对应一条数据线和一条电源信号线，这样像素在竖直方向被线路占用的面积变小，从而能够提高像素的开口率，以此解决现有阵列基板中的竖直线路密集造成开口率偏低而影响显示装置亮度和功耗的技术问题。
综上所述，虽然本揭示实施例揭露如上，但上述实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括：阵列分布的子像素，相邻两列所述子像素之间设置有数据线和电源信号线；以及
    补偿信号线，所述补偿信号线与所述电源信号线平行设置；
    其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠；
    所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
  2. 根据权利要求1所述的阵列基板，其中所述数据线与所述电源信号线的延伸方向相同。
  3. 根据权利要求2所述的阵列基板，其中所述阵列基板的每个子像素包括第一薄膜晶体管、第二薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线以及一存储电容；
    其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述数据线；
    所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述电源信号线，漏极电连接于所述OLED的阳极；
    所述OLED的阴极电连接于所述阴极信号线；
    所述存储电容电连接于所述第二薄膜晶体管的栅极与漏极。
  4. 根据权利要求3所述的阵列基板，其中每一列所述子像素对应一条所述数据线与一条所述电源信号线。
  5. 根据权利要求1所述的阵列基板，其中所述补偿信号线与所述数据线至少部分重叠，所述补偿信号线与所述数据线的延伸方向相同。
  6. 根据权利要求5所述的阵列基板，其中所述补偿信号线制备于所述阵列基板的背侧，且与所述电源信号线交替设置。
  7. 根据权利要求6所述的阵列基板，其中所述阵列基板的一个子像素包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；其相邻子像素包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；
    其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N级数据线；
    所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述N级电源信号线，漏极电连接于所述OLED的阳极；
    所述OLED的阴极电连接于所述阴极信号线；
    所述第三薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第二薄膜晶体管的漏极；
    所述第四薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N+1级数据线；
    所述第五薄膜晶体管的栅极电连接于所述第四薄膜晶体管的漏极，源极电连接于所述N+1级电源信号线，漏极电连接于所述OLED的阳极；
    所述第六薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第五薄膜晶体管的漏极；
    所述存储电容电连接于所述第二薄膜晶体管的栅极和漏极或电连接于所述第五薄膜晶体管的栅极和漏极；
    所述两个相邻的子像素共用一条所述补偿信号线。
  8. 根据权利要求7所述的阵列基板，其中每一列所述子像素对应一条所述数据线，每两列所述子像素对应一条所述电源信号线或所述补偿信号线。
  9. 一种阵列基板，包括：阵列分布的子像素，相邻两列所述子像素之间设置有数据线和电源信号线；
    其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠。
  10. 根据权利要求9所述的阵列基板，其中所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
  11. 根据权利要求10所述的阵列基板，其中所述数据线与所述电源信号线的延伸方向相同。
  12. 根据权利要求11所述的阵列基板，其中所述阵列基板的每个子像素包括第一薄膜晶体管、第二薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线以及一存储电容；
    其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述数据线；
    所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述电源信号线，漏极电连接于所述OLED的阳极；
    所述OLED的阴极电连接于所述阴极信号线；
    所述存储电容电连接于所述第二薄膜晶体管的栅极与漏极。
  13. 根据权利要求12所述的阵列基板，其中每一列所述子像素对应一条所述数据线与一条所述电源信号线。
  14. 根据权利要求9所述的阵列基板，其中所述阵列基板还包括与所述电源信号线平行设置的补偿信号线，所述补偿信号线与所述数据线至少部分重叠，所述补偿信号线与所述数据线的延伸方向相同。
  15. 根据权利要求14所述的阵列基板，其中所述补偿信号线制备于所述阵列基板的背侧，且与所述电源信号线交替设置。
  16. 根据权利要求15所述的阵列基板，其中所述阵列基板的一个子像素包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；其相邻子像素包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、扫描线、阴极信号线、所述数据线、所述电源信号线、所述补偿信号线以及一存储电容；
    其中，所述第一薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N级数据线；
    所述第二薄膜晶体管的栅极电连接于所述第一薄膜晶体管的漏极，源极电连接于所述N级电源信号线，漏极电连接于所述OLED的阳极；
    所述OLED的阴极电连接于所述阴极信号线；
    所述第三薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第二薄膜晶体管的漏极；
    所述第四薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述N+1级数据线；
    所述第五薄膜晶体管的栅极电连接于所述第四薄膜晶体管的漏极，源极电连接于所述N+1级电源信号线，漏极电连接于所述OLED的阳极；
    所述第六薄膜晶体管的栅极电连接于所述扫描线，源极电连接于所述补偿信号线，漏极电连接于所述第五薄膜晶体管的漏极；
    所述存储电容电连接于所述第二薄膜晶体管的栅极和漏极或电连接于所述第五薄膜晶体管的栅极和漏极；
    所述两个相邻的子像素共用一条所述补偿信号线。
  17. 根据权利要求16所述的阵列基板，其中每一列所述子像素对应一条所述数据线，每两列所述子像素对应一条所述电源信号线或所述补偿信号线。
  18. 一种OLED显示装置，包括阵列基板，所述阵列基板包括：阵列分布的子像素，相邻两列子像素之间设置有数据线和电源信号线；
    其中，所述数据线与所述电源信号线制备于不同的膜层表面，且所述数据线与所述电源信号线至少部分重叠。
  19. 根据权利要求18所述的OLED显示装置，其中所述数据线设置于所述阵列基板上，所述电源信号线制备于所述阵列基板的背侧，且与所述数据线对位设置，所述电源信号线的信号输入端延伸至绑定区域，通过开设于所述阵列基板的通孔与控制芯片电性连接。
  20. 根据权利要求18所述的OLED显示装置，其中所述数据线与所述电源信号线的延伸方向相同。
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Publication number Priority date Publication date Assignee Title
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置
CN106353943A (zh) * 2016-10-26 2017-01-25 上海天马微电子有限公司 一种阵列基板、显示面板以及驱动方法
CN108766984A (zh) * 2018-05-29 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN109449180A (zh) * 2018-10-25 2019-03-08 京东方科技集团股份有限公司 一种oled显示基板和oled显示装置
CN109599031A (zh) * 2018-12-13 2019-04-09 合肥鑫晟光电科技有限公司 一种显示基板及其制作方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101420479B1 (ko) * 2011-10-31 2014-07-17 엘지디스플레이 주식회사 유기발광 표시장치
CN103278984A (zh) * 2012-12-27 2013-09-04 上海天马微电子有限公司 一种薄膜晶体管阵列基板、显示面板及液晶显示器
CN104167177A (zh) * 2014-08-15 2014-11-26 合肥鑫晟光电科技有限公司 像素电路、有机电致发光显示面板及显示装置
TWI582739B (zh) * 2016-04-29 2017-05-11 群創光電股份有限公司 顯示器面板
KR102538411B1 (ko) * 2018-07-25 2023-05-31 삼성디스플레이 주식회사 표시 장치
US10852607B2 (en) * 2018-08-21 2020-12-01 Apple Inc. Displays with data lines that accommodate openings
US11581385B2 (en) * 2019-03-28 2023-02-14 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate having additional pad layer
US11637166B2 (en) * 2019-04-12 2023-04-25 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof, and display apparatus
CN110176465A (zh) * 2019-06-27 2019-08-27 上海天马有机发光显示技术有限公司 一种显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置
US20140159609A1 (en) * 2012-12-10 2014-06-12 Boe Technology Group Co., Ltd. Pixle unit driving circuit, method for driving the pixel unit driving circuit and display device
CN106353943A (zh) * 2016-10-26 2017-01-25 上海天马微电子有限公司 一种阵列基板、显示面板以及驱动方法
CN108766984A (zh) * 2018-05-29 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN109449180A (zh) * 2018-10-25 2019-03-08 京东方科技集团股份有限公司 一种oled显示基板和oled显示装置
CN109599031A (zh) * 2018-12-13 2019-04-09 合肥鑫晟光电科技有限公司 一种显示基板及其制作方法、显示装置

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