WO2022052243A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2022052243A1
WO2022052243A1 PCT/CN2020/124723 CN2020124723W WO2022052243A1 WO 2022052243 A1 WO2022052243 A1 WO 2022052243A1 CN 2020124723 W CN2020124723 W CN 2020124723W WO 2022052243 A1 WO2022052243 A1 WO 2022052243A1
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WIPO (PCT)
Prior art keywords
substrate
driving circuit
thin film
array
array substrate
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Application number
PCT/CN2020/124723
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English (en)
French (fr)
Inventor
肖邦清
许森
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/252,232 priority Critical patent/US11971639B2/en
Publication of WO2022052243A1 publication Critical patent/WO2022052243A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.
  • GOA circuits Gate Drive On Array, the gate drive circuit is integrated on the display panel
  • PGIA Partial GOA In Active Area
  • the wiring method of the GOA circuit will occupy the area of the display area, resulting in a decrease in the pixel aperture ratio.
  • the application of PGIA is difficult to meet the pixel transmittance requirements.
  • Embodiments of the present application provide an array substrate, a method for manufacturing the same, and a display panel, so as to solve the problem that in the prior art, part of the GOA circuit is designed in the display area of the panel, and the wiring method of the GOA circuit will occupy the area of the display area, resulting in pixel
  • the opening rate decreases, which in turn affects the technical problem of the penetration rate.
  • An embodiment of the present application provides an array substrate, including a display area, the display area including a drive circuit area, the array substrate including a first substrate, a GOA circuit, and a pixel drive circuit, the first substrate including oppositely disposed the first side and the second side, the GOA circuit is arranged on the first side of the first substrate and is located in the driving circuit area, and the pixel driving circuit is arranged on all the first substrates The second side is located in the driving circuit area; wherein, the first substrate is provided with a plurality of via holes located in the driving circuit area, and the GOA circuit and the pixel driving circuit pass through the plurality of through holes. hole connection.
  • the GOA circuit includes a plurality of first thin film transistors distributed in an array.
  • the pixel driving circuit includes a plurality of second thin film transistors distributed in an array and a plurality of scan lines.
  • the source or drain of the first thin film transistor is connected to one of the scan lines through the via hole.
  • each of the first thin film transistors and one of the second thin film transistors are disposed in layers corresponding to each other.
  • a color filter layer is provided on a side of the pixel driving circuit away from the first substrate.
  • the array substrate further includes a pixel electrode, and the pixel electrode is disposed on a side of the color filter layer away from the first substrate.
  • Embodiments of the present application further provide a display panel, including an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, the array substrate includes a display area, and the display The area includes a drive circuit area, the array substrate includes a first substrate, a GOA circuit, and a pixel drive circuit, the first substrate includes a first side and a second side disposed oppositely, and the GOA circuit is disposed on the the first side of the first substrate is located in the driving circuit area, the pixel driving circuit is disposed on the second side of the first substrate and located in the driving circuit area; wherein, the first A substrate is provided with a plurality of via holes located in the driving circuit region, and the GOA circuit and the pixel driving circuit are connected through the plurality of via holes.
  • the GOA circuit includes a plurality of first thin film transistors distributed in an array
  • the pixel driving circuit includes a plurality of second thin film transistors distributed in an array and a plurality of scan lines.
  • the source or drain of the first thin film transistor is connected to one of the scan lines through the via hole.
  • each of the first thin film transistors and one of the second thin film transistors are disposed in layers corresponding to each other.
  • a color filter layer is provided on a side of the pixel driving circuit away from the first substrate, and the color filter substrate includes a black matrix and a common electrode.
  • Embodiments of the present application further provide a method for preparing an array substrate, comprising the following steps:
  • the S20 includes: forming a plurality of first thin film transistors distributed in an array on the first side.
  • the S30 includes: forming a plurality of array-distributed second thin film transistors and a plurality of scan lines on the second side.
  • the source or drain of the first thin film transistor is connected to one of the scan lines through the via hole.
  • each of the first thin film transistors and one of the second thin film transistors are disposed in layers corresponding to each other.
  • the preparation method further includes: preparing a color filter layer on the pixel driving circuit; and preparing a pixel electrode on the color filter layer.
  • the perforated glass is used as the carrier, and the GOA circuit and the pixel driving circuit are respectively arranged on opposite sides of the perforated glass, so that the wiring area of the GOA circuit and the wiring area of the pixel driving circuit are spatially overlapped, reducing the need for pixels.
  • the occupied area of the display area thereby increasing the aperture ratio of the pixel.
  • FIG. 1 is a schematic structural diagram of a display area of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a driving circuit region of an array substrate according to an embodiment of the present application.
  • FIG. 3 is another schematic structural diagram of a driving circuit region of an array substrate provided by an embodiment of the present application.
  • FIGS. 4A-4D are schematic structural diagrams of the GOA circuit in the process of preparing the GOA circuit provided by the embodiment of the present application.
  • 5A-5D are schematic structural diagrams of the pixel driving circuit provided in the embodiment of the present application in the manufacturing process.
  • FIG. 6 is a schematic flowchart of steps of a method for fabricating an array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the present application provides an array substrate, a preparation method thereof, and a display panel.
  • a display panel In order to make the purposes, technical solutions and effects of the present application clearer and clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • an embodiment of the present application provides an array substrate 100 , the array substrate 100 includes a display area 101 , and the display area 101 includes a driving circuit area 1011 and an opening area 1012 , and FIG. 1 only schematically shows One of the sub-pixel regions of the region 101, the driving circuit region 1011 is used for distributing metal devices and wirings of the driving circuit, and the opening region 1012 is the light-emitting region of the pixel.
  • the array substrate 100 includes a first substrate 10, a GOA (Gate Driver On Array) circuit 20, and a pixel driving circuit 30, wherein the GOA circuit 20 and the pixel driving circuit 30 are respectively disposed on two opposite sides of the first substrate 10, and the GOA circuit 20 and the pixel The driving circuits 30 are all located in the driving circuit area 1011 .
  • GOA Gate Driver On Array
  • the first substrate 10 is provided with a plurality of via holes 11 , the plurality of via holes 11 are located in the driving circuit region 1011 , and the GOA circuit 20 is electrically connected to the pixel driving circuit 30 through the via holes 11 . , so that the gate driving signal is transmitted to the pixel driving circuit 30 to light up the pixel.
  • the wiring area of the pixel driving circuit 30 and the wiring area of the GOA circuit 20 can overlap in space, thereby reducing the need for the The occupied area of the opening area 1012 increases the PGIA (Partial GOA In Active Area) product penetration rate.
  • PGIA Partial GOA In Active Area
  • the GOA circuit 20 includes a plurality of first thin film transistors 21 distributed in an array.
  • the pixel driving circuit 30 includes a plurality of second thin film transistors 31 and a plurality of scan lines 32 distributed in an array.
  • the GOA circuit 20 includes a plurality of GOA drive units, each GOA drive unit is connected to a scan line 32, each of the GOA drive units includes at least one of the first thin film transistors 21, and each scan line 32 is connected to a row of sub-pixels , the on or off state of the second thin film transistor 31 corresponding to the row of sub-pixels can be controlled, and the GOA driving unit transmits the drive signal to the corresponding scan line 32 according to the timing signal, thereby driving the row of sub-pixels.
  • the source or drain of the first thin film transistor 21 is connected to one of the scan lines 32 through one of the via holes 11 , wherein one scan line 32 is connected to the second thin film transistor 31 corresponding to a row of sub-pixels The gate, thereby controlling the switching of the second thin film transistor 31 .
  • each of the first thin film transistors 21 may be stacked corresponding to one of the second thin film transistors 31 , thereby reducing the area occupied by wiring and increasing the pixel aperture ratio.
  • the array substrate 100 may be a COA (Color Filter On Array, color filter integrated on the array substrate) type array substrate.
  • the array substrate 100 includes a color filter layer 70 , the color filter layer 70 is disposed on the side of the pixel driving circuit 30 away from the first substrate 10 , and the color filter layer 70 is integrated on the array substrate 100 . , the alignment accuracy can be increased in the subsequent alignment process of the upper and lower substrates.
  • the array substrate 100 may further include a pixel electrode 90 , and the pixel electrode 90 is disposed on a side of the color filter layer 70 away from the first substrate 10 .
  • a flat layer 80 is further disposed between the pixel electrode 90 and the color filter layer 70 , and the flat layer 80 may be an inorganic film layer or an organic film layer.
  • one of the first thin film transistors 21 includes a first gate electrode 214 , a first source electrode 211 , a first drain electrode 212 , and a first active layer 213 .
  • the first source electrode 211 and the first drain electrode 212 are disposed on the first side 12 of the first substrate 10 (the backside of the first substrate 10 ), and the first active layer 213 is disposed on the On the side of the first source electrode 211 and the first drain electrode 212 away from the first substrate 10 , the first active layer 213 , the first source electrode 211 and the first drain electrode 212
  • the surface is covered with an interlayer insulating layer 41, the side of the interlayer insulating layer 41 facing away from the first substrate 10 is provided with a first gate electrode 214, and the surface of the first gate electrode 214 is covered with a first gate insulating layer layer 42.
  • one of the second thin film transistors 31 includes a second gate electrode 311 , a second active layer 312 , a second source electrode 313 , and a second drain electrode 314 .
  • the second gate 311 is disposed on the second side 13 of the first substrate 10 (the front surface of the first substrate 10 ), and the scan line 32 can be disposed in the same layer as the second gate 311 .
  • the second gate electrode 311 is covered with a second gate insulating layer 50 , and the second active layer 312 is provided on the side of the second gate insulating layer 50 away from the first substrate 10 .
  • the second source electrode 313 and the second drain electrode 314 are provided on the side of the second active layer 312 facing away from the first substrate 10 .
  • the scan line 32 is connected to the lower first drain electrode 212 through the via hole 11 , or can also be connected to the first source electrode 211 .
  • the above-mentioned second thin film transistor 31 has a bottom gate structure.
  • the second thin film transistor 31 can have a top gate structure, that is, the second gate electrode 311 is disposed above the second active layer 312 .
  • an embodiment of the present application further provides a method for fabricating the above-mentioned array substrate 100 , which includes the following steps:
  • the first substrate 10 can be a glass substrate or other materials.
  • the S20 specifically includes: forming a plurality of first thin film transistors 21 distributed in an array on the first side 12 .
  • a first metal layer is first deposited on the first side 12, and subjected to patterning treatment to form a first source electrode 211 and a first drain electrode 212 at corresponding positions, so that the first source electrode 211 or the first drain electrode is formed.
  • One of the two electrodes 212 is deposited at the via hole 11 , so that the subsequent first source electrode 211 or the first drain electrode 212 is electrically connected to the upper scan line 32 .
  • a semiconductor material is deposited on the first source electrode 211 and the first drain electrode 212, and a first active layer 213 is formed after patterning, and the semiconductor material can be amorphous silicon, or metal oxide, etc., There are no restrictions here.
  • an insulating material is deposited on the first active layer to form an interlayer insulating layer 41
  • a second metal layer is deposited on the interlayer insulating layer 41 , and patterned to form a first gate electrode 214 and finally depositing an insulating material on the first gate electrode 214 to form a first gate insulating layer 42 .
  • the GOA circuit 20 further includes a capacitor and surrounding wirings, and the capacitors and surrounding wirings can be prepared by using the first metal layer or by using the second metal layer.
  • the step S30 includes: forming a plurality of arrayed second thin film transistors 31 and a plurality of scan lines 32 on the second side 13 .
  • a third metal layer is deposited on the second side 13, and a second gate electrode 311 is formed by patterning.
  • a plurality of the scan lines 32 can be arranged in the same layer as the second gate electrode 311, that is, the third metal layer can be etched to form the pattern of the scan lines 32 at the corresponding positions.
  • the scan line 32 may correspond to one of the via holes 11 , and the scan line 32 is disposed at the via hole 11 to realize connection with the GOA circuit below.
  • an insulating material is deposited on the second gate electrode 311 to form a second gate insulating layer 50; then a semiconductor material is deposited on the second gate insulating layer 50, and is patterned to form a second gate insulating layer 50.
  • source layer 312 after that, a fourth metal layer is deposited on the second active layer 312 , and patterned to form a second source electrode 313 and a second drain electrode 314 .
  • An interlayer insulating layer may also be deposited between the second source electrode 313 , the second drain electrode 314 and the second active layer 312 .
  • the pixel driving circuit 30 may further include a plurality of data lines, and the plurality of the data lines and the plurality of scan lines are interlaced with each other to define a plurality of sub-pixel regions.
  • the data lines can be disposed in the same layer as the second source electrode 313 and the second drain electrode 314, that is, the fourth metal layer can be etched to form data lines at corresponding positions.
  • the preparation method further includes preparing a color filter layer 70 on the pixel driving circuit 30 , and preparing a pixel electrode 90 on the color filter layer 70 .
  • a passivation layer 60 is prepared on the second source electrode 313 and the second drain electrode 314, and the passivation layer 60 is used to protect the thin film transistor device.
  • a color filter layer 70 can be formed on the passivation layer 60 , a flat layer 80 can be formed on the color filter layer 70 , and a pixel electrode 90 can be formed on the flat layer 80 .
  • a via hole is provided on the passivation layer 60 and the color filter layer 70 to expose part of the surface of the second drain electrode 314 below, and the pixel electrode 90 is connected to the second drain electrode 314 through the via hole .
  • via holes may also be provided above the second source electrode 313 , and the pixel electrode 90 is connected to the second source electrode 313 .
  • an embodiment of the present application further provides a display panel 1000 , which includes a color filter substrate 200 , the array substrate 100 described in any of the above embodiments, and a display panel 100 sandwiched between the array substrate 100 and the color filter substrate The liquid crystal layer 300 between 200.
  • the color filter substrate 200 includes a second substrate 210, a black matrix 220 disposed on the side of the second substrate 210 facing the array substrate 100, and disposed on the side of the black matrix 220 facing the array substrate 100 the common electrode 230.
  • the black matrix 220 is disposed corresponding to the driving circuit area 1011 and covers the driving circuit area 1011 for shielding light.
  • the common electrode 230 may be disposed on the entire surface and cover the second substrate 210 .
  • the color filter substrate 200 when the array substrate 100 is a COA array substrate, that is, the color filter layer 70 is integrated on the array substrate 100 , the color filter substrate 200 does not need to be provided with color resists, only The black matrix 220 and the common electrode 230 need to be set.
  • the color filter substrate 200 when the color filter layer 70 is not integrated on the array substrate 100 , the color filter substrate 200 further needs to include color resists, and each color resist is disposed between the adjacent black matrixes 220 . between.
  • the perforated glass is used as the carrier, and the GOA circuit and the pixel driving circuit are respectively arranged on opposite sides of the perforated glass, so that the wiring area of the GOA circuit and the wiring area of the pixel driving circuit are spatially overlapped, reducing the need for pixels.
  • the occupied area of the display area thereby increasing the aperture ratio of the pixel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种阵列基板，包括显示区，显示区包括驱动电路区，阵列基板包括第一衬底、分别设置于第一衬底的两相对侧且均位于驱动电路区的GOA电路和像素驱动电路，GOA电路与像素驱动电路通过多个过孔连接，从而使得GOA电路的布线区域能够与像素驱动电路的布线区域在空间上重合，减少对像素显示区域的占用面积，从而增大像素的开口率。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
为了促进液晶显示器的超窄边框的发展，需要将部分GOA电路（Gate Drive On Array，栅极驱动电路集成于显示面板上）设计在面板的显示区域内，即PGIA（Partial GOA In Active Area）。现有技术中，GOA电路的布线方式会占用显示区域的面积，造成像素开口率下降，尤其对于像素开口率极低的8K产品而言，PGIA的应用难以满足像素穿透率的要求。
因此，现有的GOA技术有待改进。
 技术问题
本申请实施例提供一种阵列基板及其制备方法、显示面板，以解决现有技术中，将部分GOA电路设计在面板的显示区域内，GOA电路的布线方式会占用显示区域的面积，导致像素开口率下降，进而影响穿透率的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本申请实施例提供一种阵列基板，包括显示区，所述显示区包括驱动电路区，所述阵列基板包括第一衬底、GOA电路、以及像素驱动电路，所述第一衬底包括相对设置的第一侧和第二侧，所述GOA电路设置于所述第一衬底的所述第一侧且位于所述驱动电路区，所述像素驱动电路设置于所述第一衬底的所述第二侧且位于所述驱动电路区；其中，所述第一衬底开设有位于所述驱动电路区的多个过孔，所述GOA电路与所述像素驱动电路通过多个所述过孔连接。
在本申请的一种实施例中，所述GOA电路包括多个阵列分布的第一薄膜晶体管。
在本申请的一种实施例中，所述像素驱动电路包括多个阵列分布的第二薄膜晶体管和多条扫描线。
在本申请的一种实施例中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
在本申请的一种实施例中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
在本申请的一种实施例中，所述像素驱动电路背离所述第一衬底的一侧设置有彩色滤光层。
在本申请的一种实施例中，所述阵列基板还包括像素电极，所述像素电极设置于所述彩色滤光层背离所述第一衬底的一侧。
本申请实施例还提供一种显示面板，包括阵列基板、彩膜基板、以及夹设于所述阵列基板和所述彩膜基板之间的液晶层，所述阵列基板包括显示区，所述显示区包括驱动电路区，所述阵列基板包括第一衬底、GOA电路、以及像素驱动电路，所述第一衬底包括相对设置的第一侧和第二侧，所述GOA电路设置于所述第一衬底的所述第一侧且位于所述驱动电路区，所述像素驱动电路设置于所述第一衬底的所述第二侧且位于所述驱动电路区；其中，所述第一衬底开设有位于所述驱动电路区的多个过孔，所述GOA电路与所述像素驱动电路通过多个所述过孔连接。
在本申请的一种实施例中，所述GOA电路包括多个阵列分布的第一薄膜晶体管，所述像素驱动电路包括多个阵列分布的第二薄膜晶体管和多条扫描线。
在本申请的一种实施例中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
在本申请的一种实施例中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
在本申请的一种实施例中，所述像素驱动电路背离所述第一衬底的一侧设置有彩色滤光层，所述彩膜基板包括黑矩阵和公共电极。
本申请实施例还提供一种阵列基板的制备方法，包括以下步骤：
S10，提供具有多个过孔的第一衬底，所述第一衬底包括显示区，所述显示区包括驱动电路区；
S20，在所述第一衬底第一侧的所述驱动电路区形成GOA电路；
S30，在所述第一衬底第二侧的所述驱动电路区形成像素驱动电路，其中，所述第一侧与所述第二侧相对，且所述GOA电路通过多个所述过孔与所述像素驱动电路连接。
在本申请的一种实施例中，所述S20包括：在所述第一侧形成多个阵列分布的第一薄膜晶体管。
在本申请的一种实施例中，所述S30包括：在所述第二侧形成多个阵列分布的第二薄膜晶体管和多条扫描线。
在本申请的一种实施例中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
在本申请的一种实施例中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
在本申请的一种实施例中，所述制备方法还包括：在所述像素驱动电路上制备彩色滤光层；在所述彩色滤光层上制备像素电极。
 有益效果
本申请实施例以有孔玻璃为载体，将GOA电路和像素驱动电路分别设置在有孔玻璃相对的两侧，使得GOA电路的布线区域与像素驱动电路的布线区域在空间上重合，减少对像素显示区域的占用面积，从而增大像素的开口率。
 附图说明
图1为本申请实施例提供的阵列基板的显示区的结构示意图。
图2为本申请实施例提供的阵列基板的驱动电路区的结构示意图。
图3为本申请实施例提供的阵列基板的驱动电路区的另一结构示意图。
图4A-图4D为本申请实施例提供的GOA电路制备过程中的结构示意图。
图5A-图5D为本申请实施例提供的像素驱动电路制备过程中的结构示意图。
图6为本申请实施例提供的阵列基板的制备方法的步骤流程示意图。
图7为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
本申请提供一种阵列基板及其制备方法、显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1和图2，本申请实施例提供一种阵列基板100，所述阵列基板100包括显示区101，所述显示区101包括驱动电路区1011和开口区1012，图1仅示意出显示区101的其中一个子像素区域，所述驱动电路区1011用以分布驱动电路的金属器件及走线，所述开口区1012为像素的发光区。
所述阵列基板100包括第一衬底10、GOA（Gate Driver On Array）电路20、以及像素驱动电路30，其中，所述GOA电路20和所述像素驱动电路30分别设置于所述第一衬底10的两相对侧，且所述GOA电路20和所述像素驱动电路30均位于所述驱动电路区1011。
所述第一衬底10开设有多个过孔11，多个所述过孔11位于所述驱动电路区1011，所述GOA电路20通过所述过孔11与所述像素驱动电路30电连接，从而将栅极驱动信号传输至像素驱动电路30，点亮像素。
通过将像素驱动电路30和GOA电路20分别设置于所述第一衬底10的正反面，使得像素驱动电路30的布线区域和GOA电路20的布线区域能够在空间上重叠，从而减少对所述开口区1012的占用面积，提高PGIA（Partial GOA In Active Area）产品的穿透率。
请参阅图3，一种实施例中，所述GOA电路20包括多个阵列分布的第一薄膜晶体管21。所述像素驱动电路30包括多个阵列分布的第二薄膜晶体管31和多条扫描线32。
所述GOA电路20包括多个GOA驱动单元，每一GOA驱动单元连接一条扫描线32，每一所述GOA驱动单元包括至少一个所述第一薄膜晶体管21，每一条扫描线32连接一行子像素，可控制该行子像素对应的第二薄膜晶体管31的打开或关闭状态，所述GOA驱动单元根据时序信号将驱动信号传递给对应的扫描线32，从而驱动该行子像素。
具体地，所述第一薄膜晶体管21的源极或漏极通过其中一个所述过孔11与其中一条扫描线32连接，其中，一条扫描线32连接一行子像素对应的第二薄膜晶体管31的栅极，进而控制第二薄膜晶体管31的开关。
一种实施例中，每一所述第一薄膜晶体管21可与其中一个所述第二薄膜晶体管31对应层叠设置，从而减少布线所占用的面积，增大像素开口率。
一种实施例中，所述阵列基板100可为COA（Color Filter On Array，彩色滤光片集成于阵列基板上）型阵列基板。所述阵列基板100包括彩色滤光层70，彩色滤光层70设置于所述像素驱动电路30背离所述第一衬底10的一侧，将彩色滤光层70集成于所述阵列基板100上，可在后续上下基板对位过程中增加对位的精准度。
一种实施例中，所述阵列基板100还可包括像素电极90，所述像素电极90设置于所述彩色滤光层70背离所述第一衬底10的一侧。
所述像素电极90和所述彩色滤光层70之间还设置有平坦层80，所述平坦层80可为无机膜层，也可为有机膜层。
请参阅图4A至图4D，一种实施例中，一个所述第一薄膜晶体管21包括第一栅极214、第一源极211、第一漏极212、以及第一有源层213。
其中，所述第一源极211和第一漏极212设置于所述第一衬底10的第一侧12（第一衬底10的背面），所述第一有源层213设置于所述第一源极211、第一漏极212背离所述第一衬底10的一侧，所述第一有源层213、所述第一源极211、以及所述第一漏极212的表面覆盖有层间绝缘层41，所述层间绝缘层41背离所述第一衬底10的一侧设置有第一栅极214，所述第一栅极214表面覆盖有第一栅极绝缘层42。
请参阅图5A和5D，一种实施例中，一个所述第二薄膜晶体管31包括第二栅极311、第二有源层312、第二源极313、以及第二漏极314。
其中，所述第二栅极311设置于所述第一衬底10的第二侧13（第一衬底10的正面），所述扫描线32可与所述第二栅极311同层设置。
所述第二栅极311上覆盖有第二栅极绝缘层50，所述第二栅极绝缘层50背离所述第一衬底10的一侧设置有所述第二有源层312，所述第二有源层312背离所述第一衬底10的一侧设置有所述第二源极313和所述第二漏极314。
所述扫描线32通过所述过孔11与下方的第一漏极212连接，或者也可与第一源极211连接。
上述第二薄膜晶体管31为底栅结构，在其他实施例中，所述第二薄膜晶体管31可为顶栅结构，即第二栅极311设置于第二有源层312的上方。
请参阅图6，本申请实施例还提供上述阵列基板100的制备方法，包括以下步骤：
S10，提供具有多个过孔11的第一衬底10，所述第一衬底10包括显示区101，所述显示区101包括驱动电路区1011；
S20，在所述第一衬底10第一侧12的所述驱动电路区1011形成GOA电路20；
S30，在所述第一衬底10第二侧13的所述驱动电路区1011形成像素驱动电路30，其中，所述第一侧12与所述第二侧13相对，且所述GOA电路20通过多个所述过孔11与所述像素驱动电路30连接。
所述第一衬底10可为玻璃基板，也可为其他材质。
请参阅图4A至图4D，所述S20具体包括：在所述第一侧12形成多个阵列分布的第一薄膜晶体管21。
具体地，首先在所述第一侧12沉积第一金属层，并经过图案化处理，在相应位置形成第一源极211和第一漏极212，使得第一源极211或第一漏极212二者之一沉积于所述过孔11处，以使得后续第一源极211或第一漏极212与上方的扫描线32实现电连接。
然后在所述第一源极211和所述第一漏极212上沉积半导体材料，并经图案化处理后形成第一有源层213，半导体材料可为非晶硅、或者金属氧化物等，这里不做限制。
之后，在所述第一有源层上沉积绝缘材料以形成层间绝缘层41，再在所述层间绝缘层41上沉积第二金属层，并经过图案化处理，形成第一栅极214，最后在所述第一栅极214上沉积绝缘材料以形成第一栅极绝缘层42。
所述GOA电路20还包括电容以及周围走线，所述电容和周围走线可利用第一金属层来制备，也可利用第二金属层来制备。
请参阅图5A和图5D，所述S30包括：在所述第二侧13形成多个阵列分布的第二薄膜晶体管31和多条扫描线32。
具体地，在所述第二侧13沉积第三金属层，并经过图案化处理形成第二栅极311。
一种实施例中，多条所述扫描线32可与所述第二栅极311同层设置，即可对第三金属层进行刻蚀，以在相应位置形成扫描线32的图案，每一条所述扫描线32可对应一个所述过孔11，将所述扫描线32设置于所述过孔11处，以实现与下方的GOA电路连接。
再在所述第二栅极311上沉积绝缘材料，以形成第二栅极绝缘层50；然后在所述第二栅极绝缘层50上沉积半导体材料，并经图案化处理以形成第二有源层312；之后在所述第二有源层312上沉积第四金属层，并经图案化处理以形成第二源极313和第二漏极314。所述第二源极313、所述第二漏极314与所述第二有源层312之间也可沉积层间绝缘层。
所述像素驱动电路30还可包括多条数据线，多条所述数据线与多条扫描线相互交错，限定出多个子像素区域。所述数据线可与所述第二源极313和所述第二漏极314同层设置，即可对第四金属层进行刻蚀在相应位置形成数据线。
所述制备方法还包括在像素驱动电路30上制备彩色滤光层70，以及在所述彩色滤光层70上制备像素电极90。
具体地，在所述第二源极313和所述第二漏极314上制备钝化层60，所述钝化层60用以保护薄膜晶体管器件。
之后可在所述钝化层60上制备彩色滤光层70，再在所述彩色滤光层70上制备平坦层80，然后在所述平坦层80上制备像素电极90。
所述钝化层60和所述彩色滤光层70上设置有过孔以露出下方的第二漏极314的部分表面，所述像素电极90通过该过孔与所述第二漏极314连接。其他实施例中，也可在所述第二源极313上方设置过孔，所述像素电极90与第二源极313连接。
请参阅图7，本申请实施例还提供一种显示面板1000，包括彩膜基板200、上述任一实施例所述的阵列基板100、以及夹设于所述阵列基板100和所述彩膜基板200之间的液晶层300。
所述阵列基板100的结构可参考上述实施例中对阵列基板100的描述，这里不再赘述。
所述彩膜基板200包括第二衬底210，设置于所述第二衬底210面向所述阵列基板100一侧的黑矩阵220，设置于所述黑矩阵220面向所述阵列基板100一侧的公共电极230。所述黑矩阵220与所述驱动电路区1011对应设置，且覆盖所述驱动电路区1011，用以遮光。所述公共电极230可整面设置，覆盖所述第二衬底210。
一种实施例中，当所述阵列基板100为COA阵列基板时，即将所述彩色滤光层70集成于所述阵列基板100上，所述彩膜基板200上可不必设置彩色色阻，仅需设置所述黑矩阵220和所述公共电极230。
其他实施例中，当所述阵列基板100上未集成所述彩色滤光层70时，所述彩膜基板200还需包括彩色色阻，每一色阻设置于相邻的所述黑矩阵220之间。
本申请实施例以有孔玻璃为载体，将GOA电路和像素驱动电路分别设置在有孔玻璃相对的两侧，使得GOA电路的布线区域与像素驱动电路的布线区域在空间上重合，减少对像素显示区域的占用面积，从而增大像素的开口率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种阵列基板，包括显示区，所述显示区包括驱动电路区，其中，所述阵列基板包括：
    第一衬底，包括相对设置的第一侧和第二侧；
    GOA电路，设置于所述第一衬底的所述第一侧且位于所述驱动电路区；以及
    像素驱动电路，设置于所述第一衬底的所述第二侧且位于所述驱动电路区；其中，
    所述第一衬底开设有位于所述驱动电路区的多个过孔，所述GOA电路与所述像素驱动电路通过多个所述过孔连接。
  2. 根据权利要求1所述的阵列基板，其中，所述GOA电路包括多个阵列分布的第一薄膜晶体管。
  3. 根据权利要求2所述的阵列基板，其中，所述像素驱动电路包括多个阵列分布的第二薄膜晶体管和多条扫描线。
  4. 根据权利要求3所述的阵列基板，其中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
  5. 根据权利要求3所述的阵列基板，其中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
  6. 根据权利要求1所述的阵列基板，其中，所述像素驱动电路背离所述第一衬底的一侧设置有彩色滤光层。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括像素电极，所述像素电极设置于所述彩色滤光层背离所述第一衬底的一侧。
  8. 一种显示面板，包括阵列基板、彩膜基板、以及夹设于所述阵列基板和所述彩膜基板之间的液晶层，所述阵列基板包括显示区，所述显示区包括驱动电路区，其中，所述阵列基板包括：
    第一衬底，包括相对设置的第一侧和第二侧；
    GOA电路，设置于所述第一衬底的所述第一侧且位于所述驱动电路区；以及
    像素驱动电路，设置于所述第一衬底的所述第二侧且位于所述驱动电路区；其中，
    所述第一衬底开设有位于所述驱动电路区的多个过孔，所述GOA电路与所述像素驱动电路通过多个所述过孔连接。
  9. 根据权利要求8所述的显示面板，其中，所述GOA电路包括多个阵列分布的第一薄膜晶体管，所述像素驱动电路包括多个阵列分布的第二薄膜晶体管和多条扫描线。
  10. 根据权利要求9所述的显示面板，其中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
  11. 根据权利要求9所述的显示面板，其中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
  12. 根据权利要求8所述的显示面板，其中，所述像素驱动电路背离所述第一衬底的一侧设置有彩色滤光层，所述彩膜基板包括黑矩阵和公共电极。
  13. 一种阵列基板的制备方法，包括以下步骤：
    S10，提供具有多个过孔的第一衬底，所述第一衬底包括显示区，所述显示区包括驱动电路区；
    S20，在所述第一衬底第一侧的所述驱动电路区形成GOA电路；
    S30，在所述第一衬底第二侧的所述驱动电路区形成像素驱动电路，其中，所述第一侧与所述第二侧相对，且所述GOA电路通过多个所述过孔与所述像素驱动电路连接。
  14. 根据权利要求13所述的制备方法，其中，所述S20包括：
    在所述第一侧形成多个阵列分布的第一薄膜晶体管。
  15. 根据权利要求14所述的制备方法，其中，所述S30包括：
    在所述第二侧形成多个阵列分布的第二薄膜晶体管和多条扫描线。
  16. 根据权利要求15所述的制备方法，其中，所述第一薄膜晶体管的源极或漏极通过所述过孔与其中一条所述扫描线连接。
  17. 根据权利要求13所述的制备方法，其中，每一所述第一薄膜晶体管与其中一个所述第二薄膜晶体管对应层叠设置。
  18. 根据权利要求13所述的制备方法，其中，所述制备方法还包括：
    在所述像素驱动电路上制备彩色滤光层；
    在所述彩色滤光层上制备像素电极。
PCT/CN2020/124723 2020-09-10 2020-10-29 阵列基板及其制备方法、显示面板 WO2022052243A1 (zh)

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