WO2020206707A1 - 顶栅自对准金属氧化物半导体tft及其制作方法、显示面板 - Google Patents

顶栅自对准金属氧化物半导体tft及其制作方法、显示面板 Download PDF

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Publication number
WO2020206707A1
WO2020206707A1 PCT/CN2019/082980 CN2019082980W WO2020206707A1 WO 2020206707 A1 WO2020206707 A1 WO 2020206707A1 CN 2019082980 W CN2019082980 W CN 2019082980W WO 2020206707 A1 WO2020206707 A1 WO 2020206707A1
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Prior art keywords
layer
gate
metal oxide
insulating layer
source
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French (fr)
Inventor
余明爵
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technology, in particular to a top gate self-aligned metal oxide semiconductor TFT, a manufacturing method thereof, and a display panel.
  • each light emitting unit is made of TFT (Thin Film Transistor (thin film transistor) control, through its corresponding TFT on and off, control the operation of each light-emitting unit.
  • TFT Thin Film Transistor
  • a TFT usually includes a gate 103, a source 104, and a drain 105.
  • the source 104 and the drain 105 are located on the same layer and are connected through the active layer 101.
  • the gate 103 is connected to the source 104 and drain 105.
  • the electrodes 105 are located in different layers, and there is a gate insulating layer 102 between the gate 103 and the active layer 101.
  • the source 104 of the thin film transistor and the driving electrode of the light-emitting unit (not shown)
  • the drain 105 is electrically connected to the data line (not shown in the figure) in the organic light emitting display device, and the gate 103 is electrically connected to the scan line (not shown in the figure) in the organic light emitting display device.
  • the signal controls the on and off of the thin film transistor.
  • the drain 105 of the thin film transistor receives the data signal in the data line connected to it, and transmits it to the source 104 of the thin film transistor, and then transmits it to the driving electrode of the light-emitting unit through the source 104, thereby controlling light emission Unit work.
  • the driving thin film transistor and the switching thin film transistor will use a top gate self-aligned structure, but in the process of preparing the active layer 101, the indium gallium zinc oxide (IGZO) After patterning, during the chemical vapor deposition of the gate insulating layer 102, the plasma will damage the indium gallium zinc oxide, and affect the characteristics and reliability of the TFT device. Therefore, the chemical vapor deposition of the gate insulating layer 102 is divided into two stages. The first stage uses low power consumption to reduce the damage to indium gallium zinc oxide, and the second stage uses higher power consumption.
  • IGZO indium gallium zinc oxide
  • the purpose of the present invention is to provide a top-gate self-aligned metal oxide semiconductor TFT, a manufacturing method thereof, and a display panel.
  • the top-gate self-aligned metal oxide semiconductor TFT adds an ultra-thin metal layer to prevent Plasma damages the indium gallium zinc oxide during the chemical vapor deposition of the gate, while improving the mobility and reliability of the device.
  • the present invention provides a top-gate self-aligned metal oxide semiconductor TFT, which includes: an active layer, a gate insulating layer and a gate sequentially arranged above the active layer, And a first barrier layer arranged between the active layer and the gate insulating layer.
  • the first barrier layer is a metal oxide layer; the material of the metal oxide layer is titanium dioxide or molybdenum trioxide.
  • the thickness of the first barrier layer ranges from 10 angstroms to 50 angstroms.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: a first substrate disposed under the active layer, and the first substrate includes: a base substrate, A light-shielding layer arranged on the base substrate, and a buffer layer arranged on the light-shielding layer and covering the light-shielding layer.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: an interlayer insulating layer disposed on the buffer layer and covering the gate and the active layer, A source electrode and a drain electrode are arranged on the interlayer insulating layer, and a passivation layer is arranged on the interlayer insulating layer and covers the source electrode and the drain electrode.
  • the active layer is disposed on the buffer layer and corresponding to the top of the light shielding layer, and the active layer includes: a channel region corresponding to the gate and a A source contact area and a drain contact area on both sides of the channel area; the source and the drain are respectively connected to the source contact area and the drain contact area of the active layer.
  • a first source contact hole and a first drain contact hole corresponding to the source contact area and the drain contact area are provided on the interlayer insulating layer, and the source And the drain are respectively connected to the source contact area and the drain contact area of the active layer through the first source contact hole and the first drain contact hole.
  • a second source contact hole and a second drain contact corresponding to the source contact area and the drain contact area are provided on the interlayer insulating layer and the metal oxide layer
  • the source electrode and the drain electrode are respectively connected to the source contact area and the drain contact area of the active layer through the second source contact hole and the second drain contact hole.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes a first signal-connecting via, and the first signal-connecting via is provided in the interlayer insulating layer and the On the buffer layer and corresponding to the upper side of the light shielding layer, the source electrode is connected to the light shielding layer through the first signal connection via hole.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes a second signal-connecting via, and the second signal-connecting via is provided in the interlayer insulating layer, the On the metal oxide layer and the buffer layer and corresponding to the upper side of the light shielding layer, the source electrode is connected to the light shielding layer through the second signal connection via hole.
  • the present invention provides a display panel including the above-mentioned top gate self-aligned metal oxide semiconductor TFT.
  • the present invention provides a method for manufacturing a top-gate self-aligned metal oxide semiconductor TFT, which includes the following steps: (1) Provide a base substrate, and form a top-gate self-aligned metal oxide semiconductor TFT.
  • a light-shielding layer, a buffer layer covering the light-shielding layer is formed on the base substrate, and an active layer corresponding to the upper side of the light-shielding layer is formed on the buffer layer; (2) on the buffer layer Deposit a metal layer covering the active layer, and oxidize the metal layer to form a metal oxide layer; (3) form a gate insulating layer on the metal oxide layer, and A gate metal layer is deposited on the insulating layer; (4) a photoresist layer is formed on the gate metal layer, and the photoresist layer is patterned to define a gate pattern; (5) The photoresist layer is a barrier layer, and the gate metal layer is etched to form a gate corresponding to the active layer; (6) the photoresist layer and the gate are used as a barrier layer , The gate insulating layer is etched to form a corresponding gate insulating layer; (7) using the photoresist layer, the gate and the gate insulating layer as a barrier layer, the metal The oxide layer
  • the present invention provides a method for manufacturing a top-gate self-aligned metal oxide semiconductor TFT, which includes the following steps: (1) Provide a base substrate on which a substrate is formed. A light-shielding layer, a buffer layer covering the light-shielding layer is formed on the base substrate, and an active layer corresponding to the upper side of the light-shielding layer is formed on the buffer layer; (2) on the buffer layer Deposit a metal layer covering the active layer, and oxidize the metal layer to form a metal oxide layer; (3) form a gate insulating layer on the metal oxide layer, and A gate metal layer is deposited on the insulating layer; (4) a photoresist layer is formed on the gate metal layer, and the photoresist layer is patterned to define a gate pattern; (5) The photoresist layer is a barrier layer, and the gate metal layer is etched to form a gate corresponding to the active layer; (6) using the photoresist layer and the gate as the barrier layer, The
  • the gate and the gate insulating layer define a channel region corresponding to the gate on the active layer and are respectively located in the trench A source contact area and a drain contact area on both sides of the track area; (7)
  • the photoresist layer, the gate and the gate insulating layer are used as barrier layers to protect the metal oxide layer and the active layer.
  • Conduct conductive treatment after the completion of the conductive process, strip the photoresist layer; (8) form an interlayer insulating layer covering the gate and the active layer on the buffer layer; between the interlayer insulating layer and the A second source contact hole and a second drain contact hole corresponding to the source contact area and the drain contact area are formed on the metal oxide layer; (9) formed on the interlayer insulating layer A source electrode and a drain electrode, the source electrode and the drain electrode are respectively connected to the source electrode contact area and the drain electrode contact area through the second source electrode contact hole and the second drain contact hole Connected; (10) forming a passivation layer covering the source and drain electrodes on the interlayer insulating layer.
  • the advantage of the present invention is that the top gate self-aligned metal oxide semiconductor TFT of the present invention adds an ultra-thin metal layer to prevent the plasma from damaging indium gallium zinc oxide during the chemical vapor deposition of the gate. At the same time, the mobility and reliability of the device are improved.
  • FIG. 1 is a schematic structural diagram of a TFT in the prior art.
  • FIG. 2 is a schematic diagram of the structure of a top gate self-aligned metal oxide semiconductor TFT in the first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a top gate self-aligned metal oxide semiconductor TFT in the second embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the method steps of the top-gate self-aligned metal oxide semiconductor TFT in the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the method steps of a top-gate self-aligned metal oxide semiconductor TFT in the second embodiment of the present invention.
  • the invention provides a top gate self-aligned metal oxide semiconductor TFT, a manufacturing method thereof, and a display panel. The detailed description will be given below.
  • a top-gate self-aligned metal oxide semiconductor TFT which includes: an active layer 204, and an active layer 204 sequentially disposed above the active layer 204 The gate insulating layer 206 and the gate 207, and a first barrier layer (namely 205 hereinafter) disposed between the active layer 204 and the gate insulating layer 206.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: a first substrate (not marked in the figure) disposed under the active layer 204, and the first substrate includes: a base substrate 201 A light-shielding layer 202 disposed on the base substrate 201, and a buffer layer 203 disposed on the light-shielding layer 202 and covering the light-shielding layer 202.
  • the base substrate 201 is a glass substrate, but is not limited to this, and may also be a PI substrate or other substrates.
  • the material of the light shielding layer 202 is metal.
  • the material of the light shielding layer 202 includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • the thickness of the buffer layer 203 may be 1000 angstroms to 5000 angstroms, and the buffer layer 203 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxide film and a silicon nitride film alternately stacked to form a composite film.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • the thickness of the active layer 204 may be 100 angstroms to 1000 angstroms, and its material is a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide One or more of.
  • the area of the active layer 204 is smaller than the light shielding layer, and the orthographic projection of the light shielding layer 202 on the base substrate 201 covers the orthographic projection of the active layer 204 on the base substrate 201, so that The light-shielding layer 202 can completely cover the active layer 204, prevent the active layer 204 from being irradiated by light and cause negative drift of the TFT threshold voltage, and improve the stability of the TFT.
  • the active layer 204 is disposed on the buffer layer 203 and corresponds to the light shielding layer 202, and the active layer 204 includes: a channel region 2041 corresponding to the gate 207 And a source contact region 2042 and a drain contact region 2043 respectively located on both sides of the channel region.
  • a gate insulating layer 206 and a gate 207 are provided on the active layer 204.
  • the gate insulating layer 206 is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the material of the gate 207 includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • the present invention uses a top-gate self-aligned structure, and uses the gate 207 and the gate insulating layer 206 to define a channel region 2041 corresponding to the gate 207 on the active layer 204 and the channels located on both sides of the channel region 2041.
  • the source contact area 2042 and the drain contact area 2043, during the conductive process of the active layer 204, the gate 207, the gate insulating layer 206 and the metal oxide layer 205 described below can effectively protect the The channel region 2041 of the source layer 204 is not conductive.
  • a first barrier layer is provided between the active layer 204 and the gate insulating layer 206.
  • the first barrier layer is a metal oxide layer 205.
  • the material of the metal oxide layer 205 is titanium dioxide or molybdenum trioxide.
  • the thickness of the metal layer ranges from 10 angstroms to 50 angstroms, so when After the metal layer is heated and oxidized, the active layer 204 can be prevented from being damaged by the plasma of the subsequent chemical vapor deposition (such as the PEVCD process) of the gate insulating layer 206, thereby improving the reliability of the top-gate self-aligned metal oxide semiconductor TFT device .
  • the metal layer is oxidized to form a metal oxide layer 205, which reacts with the active layer 204, so that the oxygen content of the active layer 204 is reduced, thereby further improving the electron migration of the top gate self-aligned metal oxide semiconductor TFT device. rate.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: an interlayer insulating layer 208 disposed on the buffer layer and covering the gate 207 and the active layer 204, A source electrode 212 and a drain electrode 213 disposed on the interlayer insulating layer 208, and a passivation layer 214 disposed on the interlayer insulating layer 208 and covering the source electrode 212 and the drain electrode 213 .
  • the source electrode 212 and the drain electrode 213 are respectively connected to the source contact area 2042 and the drain contact area 2043 of the active layer 204.
  • the interlayer insulating layer 208 is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking silicon oxide films and silicon nitride films.
  • the material of the source electrode 212 and the drain electrode 213 includes one or more alloys of molybdenum, aluminum, copper, and titanium.
  • the interlayer insulating layer 208 is provided with a first source contact hole 209 and a first drain contact hole corresponding to the source contact region 2042 and the drain contact region 2043. 210.
  • the source electrode 212 and the drain electrode 213 are connected to the source contact area 2042 and the drain electrode of the active layer 204 through the first source contact hole 209 and the first drain contact hole 210, respectively.
  • the contact area 2043 is connected.
  • a first signal via 211 is provided on the interlayer insulating layer 208 and the buffer layer 203 and above the light shielding layer 202.
  • a signal via 211 passes through the interlayer insulating layer 208 and the buffer layer 203 sequentially.
  • the source electrode 212 is connected to the light shielding layer 202 through the first signal connection via 211, so that a stable voltage is generated on the light shielding layer 202, which can avoid the floating gate effect and ensure the working stability of the TFT device .
  • the first source contact hole 209, the first drain contact hole 210 and the first signal via 211 are formed in the same photolithography process.
  • FIG. 3 is a schematic structural diagram of a top gate self-aligned metal oxide semiconductor TFT in a second embodiment of the present invention.
  • the structure of the top-gate self-aligned metal oxide semiconductor TFT is similar to that of the top-gate self-aligned metal oxide semiconductor TFT in the first embodiment described in FIG. The structure is the same.
  • the top-gate self-aligned metal oxide semiconductor TFT includes: an active layer 304, a gate insulating layer 305 and a gate electrode which are sequentially arranged above the active layer 304 306, and a first barrier layer (that is, reference numeral 305 hereinafter) disposed between the active layer 304 and the gate insulating layer 305.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: a first substrate (not marked in the figure) disposed under the active layer, and the first substrate includes: a base substrate 301, a substrate The light shielding layer 302 on the base substrate 301 and a buffer layer 303 disposed on the light shielding layer 302 and covering the light shielding layer 302.
  • the top-gate self-aligned metal oxide semiconductor TFT further includes: an interlayer insulating layer 308 arranged on the buffer layer 303 and covering the gate 307 and the active layer 304, and an interlayer insulating layer 308 arranged on the The source electrode 312 and the drain electrode 313 on the interlayer insulating layer 308, and a passivation layer 314 disposed on the interlayer insulating layer 308 and covering the source electrode 312 and the drain electrode 313.
  • the active layer 304 is disposed on the buffer layer 303 and above the light shielding layer 302.
  • the active layer 304 includes: a channel region 3041 corresponding to the gate 307 and a channel region 3041 respectively located in the channel A source contact area 3042 and a drain contact area 3043 on both sides of the area 3041; the source electrode 312 and the drain electrode 313 are respectively connected to the source contact area 3042 and the drain contact area 3043 of the active layer 304 connection.
  • the interlayer insulating layer 308 and the metal oxide layer 305 are provided with a second source contact corresponding to the source contact region 3042 and the drain contact region 3043.
  • Hole 309 and a second drain contact hole 310 wherein the second source contact hole 309 passes through the interlayer insulating layer 308 and the metal oxide layer 305 sequentially, and the second drain contact hole 3043 passes through all
  • the interlayer insulating layer 308 and the metal oxide layer 305, the source electrode 312 and the drain electrode 313 respectively pass through the second source contact hole 309 and the second drain contact hole 310 to connect to the The source contact region 3042 and the drain contact region 3043 of the source layer 304 are connected.
  • a second signal connection is provided on the interlayer insulating layer 308, the metal oxide layer 305, and the buffer layer 303 and corresponding to the light shielding layer 302.
  • the second signal via hole 311 passes through the interlayer insulating layer 308, the metal oxide layer 305 and the buffer layer 303 in sequence.
  • the source electrode 312 is connected to the light shielding layer 302 through the second signal receiving via 311, so that a stable voltage is generated on the light shielding layer 302, which can avoid the floating gate effect and ensure the working stability of the TFT device .
  • the second source contact hole 309, the second drain contact hole 310, and the second signal via 311 are formed in the same photolithography process.
  • the present invention also provides a display panel including a top gate self-aligned metal oxide semiconductor TFT.
  • the specific structure of the top gate self-aligned metal oxide semiconductor TFT is as described above, and will not be repeated here.
  • FIG. 4 is a schematic diagram of the method steps of the top gate self-aligned metal oxide semiconductor TFT in the first embodiment of the present invention.
  • the present invention provides a method for manufacturing a top gate self-aligned metal oxide semiconductor TFT, wherein the top gate self-aligned metal oxide semiconductor TFT
  • the structure is the same as the TFT structure described in the first embodiment above, and will not be repeated here.
  • the method includes the following steps:
  • Step S410 Provide a base substrate, form a light-shielding layer on the base substrate, form a buffer layer covering the light-shielding layer on the base substrate, and form a buffer layer corresponding to the light-shielding layer on the buffer layer.
  • the active layer above the light shielding layer.
  • the base substrate is a glass substrate, but is not limited to this, and may also be a PI substrate or other substrates.
  • the material of the light shielding layer is metal.
  • the material of the light shielding layer includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • the buffer layer is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxide film and a silicon nitride film alternately stacked to form a composite film.
  • the thickness of the active layer may be 100 angstroms to 1000 angstroms, and its material is a metal oxide semiconductor material, such as one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide. kind or more.
  • the active layer has a smaller area than the light shielding layer, and the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate, so that the light shielding layer can The active layer is completely covered to prevent the active layer from being irradiated by light to cause negative drift of the TFT's threshold voltage and improve the stability of the TFT.
  • Step S420 Deposit a metal layer covering the active layer on the buffer layer, and perform oxidation treatment on the metal layer to form a metal oxide layer.
  • the material of the metal layer is titanium or molybdenum, which is oxidized to form titanium dioxide or molybdenum trioxide.
  • the metal layer is oxidized to form a metal oxide layer, which reacts with the active layer, so that the oxygen content of the active layer is reduced (slightly), thereby further improving the electron mobility of the top gate self-aligned metal oxide semiconductor TFT device.
  • Step S430 forming a gate insulating layer on the metal oxide layer, and depositing a gate metal layer on the gate insulating layer.
  • the gate insulating layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the material of the gate metal layer includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • Step S440 forming a photoresist layer on the gate metal layer, and patterning the photoresist layer to define a gate pattern.
  • the photoresist layer is patterned by a yellow light process, and the remaining photoresist layer defines a gate pattern on the gate metal layer.
  • Step S450 using the photoresist layer as a barrier layer, etching the gate metal layer to form a gate corresponding to the active layer.
  • the gate metal layer wet etch the gate metal layer to form a gate corresponding to the top of the active layer.
  • Step S460 Using the photoresist layer and the gate as a barrier layer, the gate insulating layer is etched to form a corresponding gate insulating layer.
  • step S460 the remaining gate insulating layer is substantially aligned with the top and bottom of the gate. Since the gate is formed by wet etching, the gate is insulated The layer is formed by dry etching. Therefore, in the actual manufacturing process, the gate insulating layer is slightly wider than the gate.
  • Step S470 Using the photoresist layer, the gate and the gate insulating layer as barrier layers, the metal oxide layer is etched to form a corresponding metal oxide layer.
  • the gate insulating layer and the metal oxide layer define a channel region corresponding to the gate on the active layer, and a source contact region and a drain contact region respectively located on both sides of the channel region.
  • the photoresist layer, the gate and the gate insulating layer as barrier layers to etch the metal oxide layer, leaving only the part below the gate insulating layer, and the rest After being etched, the remaining metal oxide layer is located in the active layer.
  • the remaining metal oxide layer and the remaining gate insulating layer are substantially aligned up and down.
  • the gate, the gate insulating layer, and the metal oxide layer define a channel region corresponding to the gate on the active layer, and source contact regions and drain regions located on both sides of the channel region. ⁇ contact area.
  • the gate insulating layer has a certain thickness, and avoids the influence on the active layer during the etching process of the gate insulating layer. Therefore, the gate insulating layer has no effect on the drain contact area and the source contact area.
  • the metal oxide layer is etched, and the specific process is described in the second embodiment below.
  • the plasma of subsequent chemical vapor deposition of the gate insulating layer (such as the PEVCD process) can be prevented from being active. Layer damage, thereby improving the reliability of the top gate self-aligned metal oxide semiconductor TFT device.
  • Step S480 Use the photoresist layer, the gate, the gate insulating layer, and the metal oxide layer as barrier layers to conduct the conductive treatment on the active layer, and after the conductive process is completed, peel off The photoresist layer.
  • the thickness of the active layer may be 100 angstroms to 1000 angstroms, and its material is a metal oxide semiconductor material, such as one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide. kind or more. Conducting the conductive treatment on the active layer makes the metal oxide semiconductor material in the source contact region and the drain contact region become a conductor, and the metal oxide semiconductor material in the channel region maintains semiconductor characteristics.
  • IGZO indium gallium zinc oxide
  • IZTO indium zinc tin oxide
  • IZTO indium gallium zinc tin oxide
  • the conductive treatment method for the active layer is plasma treatment, which reduces the oxygen content in the metal oxide semiconductor material, so that the resistivity of the metal oxide semiconductor material decreases and becomes a conductor.
  • the plasma includes one or more of helium plasma, argon plasma, and ammonia plasma.
  • the photoresist layer is stripped.
  • Step S490 forming an interlayer insulating layer covering the gate and the active layer on the buffer layer; forming on the interlayer insulating layer corresponding to the source contact area and the drain A first source contact hole and a first drain contact hole in the electrode contact area.
  • the interlayer insulating layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • a first source contact hole and a first drain contact hole respectively corresponding to the source contact area and the drain contact area are formed on the interlayer insulating layer.
  • step S490 further includes: forming a first signal connection via on the interlayer insulating layer and the buffer layer; the source electrode is connected to the light shielding layer through the first signal connection via hole .
  • the source electrode is connected to the light shielding layer through the first signal connection via hole, so that a stable voltage is generated on the light shielding layer, which can avoid the floating gate effect and ensure the working stability of the TFT device.
  • the first source contact hole, the first drain contact hole and the first signal connection via are formed in the same photolithography process.
  • Step S4100 A source electrode and a drain electrode are formed on the interlayer insulating layer, and the source electrode and the drain electrode respectively pass through the first source electrode contact hole and the first drain electrode contact hole.
  • the source contact area is connected to the drain contact area.
  • the material of the source electrode and the drain electrode includes an alloy of one or more of molybdenum, aluminum, copper, and titanium.
  • the source electrode and the drain electrode are obtained by depositing a metal layer and performing patterning treatment.
  • Step S4110 forming a passivation layer covering the source and drain electrodes on the interlayer insulating layer.
  • a passivation layer covering the source electrode and the drain electrode is formed on the interlayer insulating layer to complete the production of the top gate self-aligned metal oxide semiconductor TFT.
  • step S4110 further includes forming a flat layer on the passivation layer, forming an anode on the flat layer, the anode is an indium tin oxide (ITO) electrode, and pixels are arranged on the anode A defining layer, the pixel defining layer has an opening, and an organic light emitting layer is arranged at the opening position.
  • ITO indium tin oxide
  • FIG. 5 is a schematic diagram of the method steps of the top gate self-aligned metal oxide semiconductor TFT in the second embodiment of the present invention.
  • the present invention provides a method for manufacturing a top gate self-aligned metal oxide semiconductor TFT, wherein the top gate self-aligned metal oxide semiconductor TFT
  • the structure is the same as the TFT structure described in the second embodiment above, and will not be repeated here.
  • the method includes the following steps:
  • Step S510 Provide a base substrate, form a light-shielding layer on the base substrate, form a buffer layer covering the light-shielding layer on the base substrate, and form a buffer layer corresponding to the light-shielding layer on the buffer layer.
  • the active layer above the light shielding layer.
  • the base substrate is a glass substrate, but is not limited to this, and may also be a PI substrate or other substrates.
  • the material of the light shielding layer is metal.
  • the material of the light shielding layer includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • the buffer layer is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxide film and a silicon nitride film alternately stacked to form a composite film.
  • the thickness of the active layer may be 100 angstroms to 1000 angstroms, and its material is a metal oxide semiconductor material, such as one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide. kind or more.
  • the active layer has a smaller area than the light shielding layer, and the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate, so that the light shielding layer can The active layer is completely covered to prevent the active layer from being irradiated by light to cause negative drift of the TFT's threshold voltage and improve the stability of the TFT.
  • Step S520 Deposit a metal layer covering the active layer on the buffer layer, and perform oxidation treatment on the metal layer to form a metal oxide layer.
  • the material of the metal layer is titanium or molybdenum, which is oxidized to form titanium dioxide or molybdenum trioxide.
  • the metal layer is oxidized to form a metal oxide layer, which reacts with the active layer, so that the oxygen content of the active layer is reduced (slightly), thereby further improving the electron mobility of the top gate self-aligned metal oxide semiconductor TFT device.
  • Step S530 forming a gate insulating layer on the metal oxide layer, and depositing a gate metal layer on the gate insulating layer.
  • the gate insulating layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the material of the gate metal layer includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti).
  • Step S540 forming a photoresist layer on the gate metal layer, and patterning the photoresist layer to define a gate pattern.
  • Step S550 Using the photoresist layer as a barrier layer, etching the gate metal layer to form a gate corresponding to the top of the active layer.
  • the gate metal layer wet etch the gate metal layer to form a gate corresponding to the top of the active layer.
  • Step S560 Using the photoresist layer and the gate as a barrier layer, the gate insulating layer is etched to form a corresponding gate insulating layer.
  • the gate and the gate insulating layer are
  • the source layer defines a channel region corresponding to the gate and a source contact region and a drain contact region respectively located on both sides of the channel region.
  • the gate insulating layer Using the photoresist layer and the gate as a barrier layer, dry etching the gate insulating layer. Only the part below the gate is retained, and the rest is removed by etching, and the remaining gate insulating layer is located above the active layer. Since the gate insulating layer has a certain thickness and avoids the influence on the active layer during the etching process of the gate insulating layer, the metal oxide layer corresponding to the drain contact area and the source contact area is not affected. Perform etching.
  • the plasma of subsequent chemical vapor deposition of the gate insulating layer (such as the PEVCD process) can be prevented from being active. Layer damage, thereby improving the reliability of the top gate self-aligned metal oxide semiconductor TFT device.
  • Step S570 Using the photoresist layer, the gate and the gate insulating layer as barrier layers, conduct a conductive treatment on the metal oxide layer and the active layer, and after the completion of the conductive process, peel off the photoresist layer.
  • the conductive treatment method is plasma treatment, which reduces the oxygen content in the metal oxide semiconductor material, so that the resistivity of the metal oxide semiconductor material decreases and becomes a conductor.
  • the plasma includes one or more of helium plasma, argon plasma, and ammonia plasma.
  • Step S580 forming an interlayer insulating layer covering the gate and the active layer on the buffer layer; forming the interlayer insulating layer and the metal oxide layer corresponding to the source contact area and the A second source contact hole and a second drain contact hole in the drain contact area.
  • the interlayer insulating layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • Step S580 further includes: forming a second signal-connecting via on the interlayer insulating layer, the metal oxide layer, and the buffer layer; the source electrode is connected to the second signal-connecting via via the second signal-connecting via The light shielding layer.
  • the source electrode is connected to the light shielding layer through the second signal connection via hole, so that a stable voltage is generated on the light shielding layer, which can avoid the floating gate effect and ensure the working stability of the TFT device.
  • the second source contact hole, the second drain contact hole and the second signal via hole are formed in the same photolithography process.
  • Step S590 A source electrode and a drain electrode are formed on the interlayer insulating layer, and the source electrode and the drain electrode pass through the second source electrode contact hole and the second drain electrode contact hole respectively.
  • the source contact area is connected to the drain contact area.
  • the material of the source electrode and the drain electrode includes an alloy of one or more of molybdenum, aluminum, copper, and titanium.
  • the source electrode and the drain electrode are obtained by depositing a metal layer and performing patterning treatment.
  • Step S5100 forming a passivation layer covering the source and drain electrodes on the interlayer insulating layer.
  • a passivation layer covering the source electrode and the drain electrode is formed on the interlayer insulating layer to complete the production of the top gate self-aligned metal oxide semiconductor TFT.
  • step S5100 further includes forming a flat layer on the passivation layer, forming an anode on the flat layer, the anode is an indium tin oxide (ITO) electrode, and pixels are arranged on the anode A defining layer, the pixel defining layer has an opening, and an organic light emitting layer is arranged at the opening position.
  • ITO indium tin oxide
  • the advantage of the present invention is that the top gate self-aligned metal oxide semiconductor TFT of the present invention adds an ultra-thin metal layer to prevent the plasma from damaging indium gallium zinc oxide during the chemical vapor deposition of the gate. At the same time, the mobility and reliability of the device are improved.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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  • Thin Film Transistor (AREA)

Abstract

一种顶栅自对准金属氧化物半导体TFT及其制作方法和显示面板，所述顶栅自对准金属氧化物半导体TFT通过新增一超薄金属层，以防止在栅极207的化学气相沉积时等离子体对氧化铟镓锌造成的伤害，同时提升器件的迁移率和可靠度。

Description

顶栅自对准金属氧化物半导体TFT及其制作方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种顶栅自对准金属氧化物半导体TFT及其制作方法以及显示面板。
 背景技术
现有技术中有机发光显示装置中，每个发光单元均由TFT（Thin Film Transistor，薄膜晶体管）控制，通过其对应的TFT的导通和截止，控制每个发光单元的工作与否。如图1所示，通常TFT包括栅极103、源极104和漏极105，源极104和漏极105位于同一层，通过有源层101相连，所述栅极103与源极104、漏极105位于不同层，且所述栅极103和有源层101之间具有栅极绝缘层102，在工作时，所述薄膜晶体管的源极104与发光单元的驱动电极（图中未示）连接，漏极105与有机发光显示装置中的数据线（图中未示）电连接，栅极103与有机发光显示装置中的扫描线（图中未示）电连接，通过扫描线中输出的信号控制薄膜晶体管的导通和截止。当薄膜晶体管导通时，薄膜晶体管的漏极105接收与其相连的数据线中的数据信号，并传输至薄膜晶体管的源极104，再通过源极104传输给发光单元的驱动电极，从而控制发光单元的工作。
 技术问题
现有的有机发光显示装置中的驱动电路为了降低寄生电容，驱动薄膜晶体管和开关薄膜晶体管会使用顶栅自对准结构，但是在对制备有源层101的过程中，即在氧化铟镓锌（IGZO）图案化后，进行栅极绝缘层102的化学气相沉积时，等离子体会对氧化铟镓锌造成伤害，影响TFT器件特性与可靠性。因此，在栅极绝缘层102的化学气相沉积时，分成两个阶段，第一阶段采用低功耗来减少对氧化铟镓锌的伤害，第二阶段再使用较高功耗。
有鉴于此，如何能够更好地避免对氧化铟镓锌受到等离子体的伤害成为了相关研究者的重要研究课题。
 技术解决方案
本发明的目的在于，提供一种顶栅自对准金属氧化物半导体TFT及其制作方法和显示面板，所述顶栅自对准金属氧化物半导体TFT通过新增一超薄金属层，以防止在栅极的化学气相沉积时等离子体对氧化铟镓锌造成的伤害，同时提升器件的迁移率和可靠度。
根据本发明的一方面，本发明提供一种顶栅自对准金属氧化物半导体TFT，其包括：一有源层、一依次设置于所述有源层上方的栅极绝缘层和栅极，以及一设置在所述有源层和所述栅极绝缘层之间的第一阻挡层。
在本发明的一实施例中，所述第一阻挡层为金属氧化层；所述金属氧化层的材料为二氧化钛或三氧化钼。
在本发明的一实施例中，所述第一阻挡层的厚度范围为10埃至50埃。
在本发明的一实施例中，所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述有源层下方的第一基板，所述第一基板包括：一衬底基板、一设置与所述衬底基板上的遮光层、一设置于所述遮光层上且覆盖所述遮光层的缓冲层。
在本发明的一实施例中，所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述缓冲层上且覆盖所述栅极和所述有源层的层间绝缘层、一设置在所述层间绝缘层上的源极和漏极、一设置在在所述层间绝缘层上且覆盖所述源极和所述漏极的钝化层。
在本发明的一实施例中，所述有源层设置在所述缓冲层上且对应于所述遮光层上方，所述有源层包括：一对应于栅极的沟道区以及分别位于所述沟道区两侧的一源极接触区和一漏极接触区；所述源极和所述漏极分别与所述有源层的源极接触区和漏极接触区连接。
在本发明的一实施例中，所述层间绝缘层上设有对应于源极接触区和漏极接触区的一第一源极接触孔和一第一漏极接触孔，所述源极和所述漏极分别通过所述第一源极接触孔和所述第一漏极接触孔与所述有源层的源极接触区和漏极接触区连接。
在本发明的一实施例中，所述层间绝缘层和所述金属氧化层上设有对应于源极接触区和漏极接触区的一第二源极接触孔和一第二漏极接触孔，所述源极和所述漏极分别通过所述第二源极接触孔和所述第二漏极接触孔与所述有源层的源极接触区和漏极接触区连接。
在本发明的一实施例中，所述顶栅自对准金属氧化物半导体TFT还包括一第一接信号过孔，所述第一接信号过孔设置在所述层间绝缘层和所述缓冲层上且对应于所述遮光层的上方，所述源极通过所述第一接信号过孔与所述遮光层相连。
在本发明的一实施例中，所述顶栅自对准金属氧化物半导体TFT还包括一第二接信号过孔，所述第二接信号过孔设置在所述层间绝缘层、所述金属氧化层和所述缓冲层上且对应于所述遮光层的上方，所述源极通过所述第二接信号过孔与所述遮光层相连。
根据本发明的另一方面，本发明提供一种显示面板，所述显示面板包括上述顶栅自对准金属氧化物半导体TFT。
根据本发明的另一方面，本发明提供一种顶栅自对准金属氧化物半导体TFT的制作方法，其包括以下步骤：（1）提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层；（2）在所述缓冲层上沉积一覆盖所述有源层的金属层，并且对所述金属层进行氧化处理，以形成金属氧化层；（3）在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层；（4）在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案；（5）以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于所述有源层上方的栅极；（6）以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层；（7）以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对所述金属氧化层进行刻蚀，以形成相应的金属氧化层，所述栅极、所述栅极绝缘层、所述金属氧化层在所述有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的源极接触区和漏极接触区；（8）以所述光阻层、所述栅极、所述栅极绝缘层、所述金属氧化层为阻挡层，对所述有源层进行导体化处理，在导体化制程结束之后，剥离所述光阻层；（9）在所述缓冲层上形成一覆盖所述栅极和所述有源层的层间绝缘层；在所述层间绝缘层上形成分别对应于所述源极接触区和所述漏极接触区的一第一源极接触孔和一第一漏极接触孔；（10）在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第一源极接触孔和所述第一漏极接触孔与所述源极接触区和所述漏极接触区相连；（11）在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
根据本发明的又一方面，本发明提供一种顶栅自对准金属氧化物半导体TFT的制作方法，其包括以下步骤：（1）提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层；（2）在所述缓冲层上沉积一覆盖所述有源层的金属层，并且对所述金属层进行氧化处理，以形成金属氧化层；（3）在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层；（4）在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案；（5）以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于有源层上方的栅极；（6）以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层，所述栅极和所述栅极绝缘层在有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的一源极接触区和一漏极接触区；（7）以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对金属氧化层和有源层进行导体化处理，在导体化制程结束之后，剥离光阻层；（8）在所述缓冲层上形成覆盖栅极和有源层的层间绝缘层；在所述层间绝缘层和所述金属氧化层上形成分别对应于所述源极接触区和所述漏极接触区的一第二源极接触孔和一第二漏极接触孔；（9）在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第二源极接触孔和所述第二漏极接触孔与所述源极接触区和所述漏极接触区相连；（10）在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
 有益效果
本发明的优点在于，本发明所述顶栅自对准金属氧化物半导体TFT通过新增一超薄金属层，以防止在栅极的化学气相沉积时等离子体对氧化铟镓锌造成的伤害，同时提升器件的迁移率和可靠度。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的一种TFT的结构示意图。
图2是本发明的第一实施例中的顶栅自对准金属氧化物半导体TFT的结构示意图。
图3是本发明的第二实施例中的顶栅自对准金属氧化物半导体TFT的结构示意图。
图4是本发明的第一实施例中的顶栅自对准金属氧化物半导体TFT的方法步骤示意图。
图5是本发明的第二实施例中的顶栅自对准金属氧化物半导体TFT的方法步骤示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本发明公开的原理的各实施例仅用于说明，而不应解释为限制本发明公开的范围。所属领域的技术人员将理解，本发明的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本发明说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本发明的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本发明说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本发明说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
本发明提供一种顶栅自对准金属氧化物半导体TFT及其制作方法和显示面板。以下将分别进行详细说明。
参阅图2所示，在本发明的第一实施例中，提供一种顶栅自对准金属氧化物半导体TFT，其包括：一有源层204、一依次设置于所述有源层204上方的栅极绝缘层206和栅极207，以及一设置在所述有源层204和所述栅极绝缘层206之间的第一阻挡层（即下文中的标号205）。
进一步，所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述有源层204下方的第一基板（图中未标），所述第一基板包括：一衬底基板201、一设置与所述衬底基板201上的遮光层202、一设置于所述遮光层202上且覆盖所述遮光层202的缓冲层203。具体地，所述衬底基板201为玻璃基板，但不限于此，也可以为PI基板或其他基板。所述遮光层202的材料为金属，优选的，所述遮光层202的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。所述缓冲层203的厚度可以为1000埃至5000埃，所述缓冲层203为氧化硅（SiOx）薄膜、氮化硅（SiNx）薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成复合薄膜。
进一步，所述有源层204的厚度可以为100埃至1000埃，其材料为金属氧化物半导体材料，例如包括氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）、氧化铟镓锌锡中的一种或多种。另外，所述有源层204的面积小于所述遮光层，且所述遮光层202在衬底基板201上的正投影覆盖所述有源层204在衬底基板201上的正投影，从而使得所述遮光层202能够对有源层204进行完全遮盖，防止有源层204收到光线照射造成TFT阈值电压负漂，提升TFT的稳定性。
在第一实施例中，所述有源层204设置在所述缓冲层203上且对应于所述遮光层202上方，所述有源层204包括：一对应于栅极207的沟道区2041以及分别位于所述沟道区两侧的一源极接触区2042和一漏极接触区2043。所述有源层204上方设有一栅极绝缘层206和栅极207。其中，栅极绝缘层206为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。所述栅极207的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。
本发明采用顶栅自对准结构，利用栅极207和栅极绝缘层206在有源层204上定义出对应于栅极207的沟道区2041以及分别位于所述沟道区2041两侧的源极接触区2042和漏极接触区2043，在有源层204的导体化过程中，所述栅极207和所述栅极绝缘层206以及下文所述的金属氧化层205能够有效地保护有源层204的沟道区2041不被导体化。
由于在现有对制备有源层204的过程中，即在进行如氧化铟镓锌（IGZO）图案化后，进行栅极绝缘层206的化学气相沉积时，等离子体会对氧化铟镓锌造成伤害，影响器件特性与可靠性，因此，本发明第一实施例中，在所述有源层204和所述栅极绝缘层206之间设置有第一阻挡层。所述第一阻挡层为金属氧化层205，具体的，所述金属氧化层205的材料为二氧化钛或三氧化钼。由于在所述有源层204上喷涂并沉积一层很薄的金属层(与金属氧化层205采用相同的标号)，所述金属层的厚度范围为10埃至50埃，因此，当对该金属层加热氧化后可阻挡后继对栅极绝缘层206的化学气相沉积（例如PEVCD制程）的等离子体对有源层204的伤害，从而改善顶栅自对准金属氧化物半导体TFT器件的可靠性。另外，所述金属层经氧化后形成金属氧化层205，与有源层204反应，使得有源层204的含氧量降低，从而进一步提升顶栅自对准金属氧化物半导体TFT器件的电子迁移率。
在本实施例中，所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述缓冲层上且覆盖所述栅极207和所述有源层204的层间绝缘层208、一设置在所述层间绝缘层208上的源极212和漏极213、一设置在在所述层间绝缘层208上且覆盖所述源极212和所述漏极213的钝化层214。所述源极212和所述漏极213分别与所述有源层204的源极接触区2042和漏极接触区2043连接。其中，所述层间绝缘层208为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。所述源极212和所述漏极213的材料包括钼、铝、铜、钛中的一种或多种的合金。
在本发明的第一实施例中，所述层间绝缘层208上设有对应于源极接触区2042和漏极接触区2043的一第一源极接触孔209和一第一漏极接触孔210，所述源极212和所述漏极213分别通过所述第一源极接触孔209和所述第一漏极接触孔210与所述有源层204的源极接触区2042和漏极接触区2043连接。
另外，在本发明的第一实施例中，在所述层间绝缘层208和所述缓冲层203上且对应于所述遮光层202的上方设置有一第一接信号过孔211，所述第一接信号过孔211依次穿过层间绝缘层208和缓冲层203。所述源极212通过所述第一接信号过孔211与所述遮光层202相连，从而使得所述遮光层202上产生稳定的电压，能够避免产生浮栅效应，保证TFT器件的工作稳定性。此外，所述第一源极接触孔209和所述第一漏极接触孔210以及第一接信号过孔211在同一道光刻制程中形成。
参阅图3，图3为本发明的第二实施例中的顶栅自对准金属氧化物半导体TFT的结构示意图。在本发明的第二实施例中，除了所述金属氧化层305的结构、所述源极312、所述漏极313与所述有源层304之间的连接方式以及所述源极312与所述遮光层302之间的连接方式不同之外，所述顶栅自对准金属氧化物半导体TFT的结构与图2所述第一实施例中的顶栅自对准金属氧化物半导体TFT的结构相同。
在本发明的第二实施例中，所述顶栅自对准金属氧化物半导体TFT包括：一有源层304、一依次设置于所述有源层304上方的栅极绝缘层305和栅极306，以及一设置在所述有源层304和所述栅极绝缘层305之间的第一阻挡层（即下文中的标号305）。
所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述有源层下方的第一基板（图中未标），所述第一基板包括：一衬底基板301、一设置与所述衬底基板301上的遮光层302、一设置于所述遮光层302上且覆盖所述遮光层302的缓冲层303。
所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述缓冲层303上且覆盖所述栅极307和所述有源层304的层间绝缘层308、一设置在所述层间绝缘层308上的源极312和漏极313、一设置在在所述层间绝缘层上308且覆盖所述源极312和所述漏极313的钝化层314。
所述有源层304设置在所述缓冲层303上且对应于所述遮光层302上方，所述有源层304包括：一对应于栅极307的沟道区3041以及分别位于所述沟道区3041两侧的一源极接触区3042和一漏极接触区3043；所述源极312和所述漏极313分别与所述有源层304的源极接触区3042和漏极接触区3043连接。
具体地，在本发明的第二实施例中，所述层间绝缘层308和所述金属氧化层305上设有对应于源极接触区3042和漏极接触区3043的一第二源极接触孔309和一第二漏极接触孔310，其中，第二源极接触孔309依次穿过所述层间绝缘层308和所述金属氧化层305，第二漏极接触孔3043依次穿过所述层间绝缘层308和所述金属氧化层305，所述源极312和所述漏极313分别通过所述第二源极接触孔309和所述第二漏极接触孔310与所述有源层304的源极接触区3042和漏极接触区3043连接。
另外，在本发明的第二实施例中，在所述层间绝缘层308、所述金属氧化层305和所述缓冲层303上且对应于所述遮光层302的上方设置有一第二接信号过孔311，所述第二接信号过孔311依次穿过层间绝缘层308、金属氧化层305和缓冲层303。所述源极312通过所述第二接信号过孔311与所述遮光层302相连，从而使得所述遮光层302上产生稳定的电压，能够避免产生浮栅效应，保证TFT器件的工作稳定性。此外，所述第二源极接触孔309和所述第二漏极接触孔310以及第二接信号过孔311在同一道光刻制程中形成。
本发明还提供一种显示面板，所述显示面板包括顶栅自对准金属氧化物半导体TFT。所述顶栅自对准金属氧化物半导体TFT的具体结构如上文所述，在此不再赘述。
参阅图4，图4为本发明的第一实施例中的顶栅自对准金属氧化物半导体TFT的方法步骤示意图。
结合图2所示，在本发明的第一实施例中，本发明提供一种顶栅自对准金属氧化物半导体TFT的制作方法，其中，所述顶栅自对准金属氧化物半导体TFT的结构如上文第一实施例中所述的TFT结构，在此不再赘述。
所述方法包括以下步骤：
步骤S410：提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层。
在此步骤中，所述衬底基板为玻璃基板，但不限于此，也可以为PI基板或其他基板。所述遮光层的材料为金属，优选的，所述遮光层的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。所述缓冲层为氧化硅（SiOx）薄膜、氮化硅（SiNx）薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成复合薄膜。
所述有源层的厚度可以为100埃至1000埃，其材料为金属氧化物半导体材料，例如包括氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）、氧化铟镓锌锡中的一种或多种。另外，所述有源层的面积小于所述遮光层，且所述遮光层在衬底基板上的正投影覆盖所述有源层在衬底基板上的正投影，从而使得所述遮光层能够对有源层进行完全遮盖，防止有源层收到光线照射造成TFT阈值电压负漂，提升TFT的稳定性。
步骤S420：在所述缓冲层上沉积一覆盖所述有源层的金属层，并且对所述金属层进行氧化处理，以形成金属氧化层。
在此步骤中，所述金属层的材料为钛或钼，对其进行氧化处理，形成二氧化钛或三氧化钼。
所述金属层经氧化后形成金属氧化层，与有源层反应，使得有源层的含氧量（稍许）降低，从而进一步提升顶栅自对准金属氧化物半导体TFT器件的电子迁移率。
步骤S430：在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层。
其中，所述栅极绝缘层为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。所述栅极金属层的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。
步骤S440：在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案。
利用黄光制程对光阻层进行图形化处理，保留下来的光阻层在所述栅极金属层上定义出栅极图案。
步骤S450：以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于所述有源层上方的栅极。
以所述光阻层为阻挡层，对所述栅极金属层进行湿刻蚀，以形成对应于有源层上方的栅极。
步骤S460：以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层。
以光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行干刻蚀。仅保留栅极下方的部分，其余部分全部均被刻蚀去除，保留的栅极绝缘层位于有源层上方。由于在步骤S450和步骤S460中，采用同一光罩，因此，在步骤S460中，保留的栅极绝缘层与所述栅极上下基本对齐，由于栅极是湿刻蚀方式形成的，栅极绝缘层是干刻蚀方式形成的，因此，在实际制备过程中，所述栅极绝缘层比所述栅极稍许宽一些。
步骤S470：以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对所述金属氧化层进行刻蚀，以形成相应的金属氧化层，所述栅极、所述栅极绝缘层、所述金属氧化层在所述有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的源极接触区和漏极接触区。
继续使用同一光罩，以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对所述金属氧化层进行刻蚀，仅保留栅极绝缘层下方的部分，其余部分被刻蚀，保留的金属氧化层位于有源层。保留的金属氧化层与保留的栅极绝缘层上下基本对齐。所述栅极、所述栅极绝缘层、所述金属氧化层在所述有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的源极接触区和漏极接触区。需说明的是，所述栅极绝缘层具有一定的厚度，且避免在对栅极绝缘层刻蚀过程中对有源层的影响，因此，未对对应于漏极接触区和源极接触区的金属氧化层进行刻蚀，具体过程如下文第二实施例所述。
由于在所述有源层上喷涂并沉积一层很薄的金属层，当对该金属层加热氧化后可阻挡后继对栅极绝缘层的化学气相沉积（例如PEVCD制程）的等离子体对有源层的伤害，从而改善顶栅自对准金属氧化物半导体TFT器件的可靠性。
步骤S480：以所述光阻层、所述栅极、所述栅极绝缘层、所述金属氧化层为阻挡层，对所述有源层进行导体化处理，在导体化制程结束之后，剥离所述光阻层。
所述有源层的厚度可以为100埃至1000埃，其材料为金属氧化物半导体材料，例如包括氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）、氧化铟镓锌锡中的一种或多种。对有源层进行导体化处理，使得源极接触区和漏极接触区的金属氧化物半导体材料变为导体，沟道区的金属氧化物半导体材料保持半导体特性。
对有源层进行导体化处理的方法为等离子体处理，降低金属氧化物半导体材料中的氧元素含量，使得金属氧化物半导体材料的电阻率下降，变为导体。所述等离子体包括氦气等离子体、氩气等离子体、氨气等离子体中的一种或多种。
在导体化制程结束后，剥离光阻层。
步骤S490：在所述缓冲层上形成一覆盖所述栅极和所述有源层的层间绝缘层；在所述层间绝缘层上形成分别对应于所述源极接触区和所述漏极接触区的一第一源极接触孔和一第一漏极接触孔。
所述层间绝缘层为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。在所述层间绝缘层上形成分别对应于所述源极接触区和所述漏极接触区的一第一源极接触孔和一第一漏极接触孔。
进一步，在步骤S490中进一步包括：在所述层间绝缘层和所述缓冲层上形成一第一接信号过孔；所述源极通过所述第一接信号过孔连接至所述遮光层。所述源极通过所述第一接信号过孔与所述遮光层相连，从而使得所述遮光层上产生稳定的电压，能够避免产生浮栅效应，保证TFT器件的工作稳定性。此外，所述第一源极接触孔和所述第一漏极接触孔以及第一接信号过孔在同一道光刻制程中形成。
步骤S4100：在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第一源极接触孔和所述第一漏极接触孔与所述源极接触区和所述漏极接触区相连。
所述源极和所述漏极的材料包括钼、铝、铜、钛中的一种或多种的合金。所述源极和所述漏极是通过沉积金属层并且进行图形化处理后得到的。
步骤S4110：在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
在层间绝缘层上形成覆盖源极和漏极的钝化层，完成顶栅自对准金属氧化物半导体TFT的制作。
当然，在步骤S4110的步骤之后，进一步包括在所述钝化层上形成平坦层，在所述平坦层上形成阳极，所述阳极为氧化铟锡（ITO）电极，在所述阳极上设置像素界定层，所述像素界定层具有开口，在开口位置设置有机发光层。这样，完成了顶栅自对准金属氧化物半导体TFT的背板制作。
参阅图5，图5为本发明的第二实施例中的顶栅自对准金属氧化物半导体TFT的方法步骤示意图。
结合图3所示，在本发明的第二实施例中，本发明提供一种顶栅自对准金属氧化物半导体TFT的制作方法，其中，所述顶栅自对准金属氧化物半导体TFT的结构如上文第二实施例中所述的TFT结构，在此不再赘述。
所述方法包括以下步骤：
步骤S510：提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层。
在此步骤中，所述衬底基板为玻璃基板，但不限于此，也可以为PI基板或其他基板。所述遮光层的材料为金属，优选的，所述遮光层的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。所述缓冲层为氧化硅（SiOx）薄膜、氮化硅（SiNx）薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成复合薄膜。
所述有源层的厚度可以为100埃至1000埃，其材料为金属氧化物半导体材料，例如包括氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）、氧化铟镓锌锡中的一种或多种。另外，所述有源层的面积小于所述遮光层，且所述遮光层在衬底基板上的正投影覆盖所述有源层在衬底基板上的正投影，从而使得所述遮光层能够对有源层进行完全遮盖，防止有源层收到光线照射造成TFT阈值电压负漂，提升TFT的稳定性。
步骤S520：在所述缓冲层上沉积一覆盖所述有源层的金属层，并且对所述金属层进行氧化处理，以形成金属氧化层。
在此步骤中，所述金属层的材料为钛或钼，对其进行氧化处理，形成二氧化钛或三氧化钼。
所述金属层经氧化后形成金属氧化层，与有源层反应，使得有源层的含氧量（稍许）降低，从而进一步提升顶栅自对准金属氧化物半导体TFT器件的电子迁移率。
步骤S530：在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层。
其中，所述栅极绝缘层为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。所述栅极金属层的材料包括钼（Mo）、铜（Cu）、钛（Ti）中的一种或多种合金。
步骤S540：在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案。
步骤S550：以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于有源层上方的栅极。
以所述光阻层为阻挡层，对所述栅极金属层进行湿刻蚀，以形成对应于有源层上方的栅极。
步骤S560：以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层，所述栅极和所述栅极绝缘层在有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的一源极接触区和一漏极接触区。
以光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行干刻蚀。仅保留栅极下方的部分，其余部分均被刻蚀去除，保留的栅极绝缘层位于有源层上方。由于所述栅极绝缘层具有一定的厚度，且避免在对栅极绝缘层刻蚀过程中对有源层的影响，因此，未对对应于漏极接触区和源极接触区的金属氧化层进行刻蚀。
由于在所述有源层上喷涂并沉积一层很薄的金属层，当对该金属层加热氧化后可阻挡后继对栅极绝缘层的化学气相沉积（例如PEVCD制程）的等离子体对有源层的伤害，从而改善顶栅自对准金属氧化物半导体TFT器件的可靠性。
步骤S570：以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对金属氧化层和有源层进行导体化处理，在导体化制程结束之后，剥离光阻层。
由于所述金属氧化层的厚度很薄，因此，可以通过对金属氧化层进行导体化处理的同时，对有源层也进行了导体化处理。所述导体化处理的方法为等离子体处理，降低金属氧化物半导体材料中的氧元素含量，使得金属氧化物半导体材料的电阻率下降，变为导体。所述等离子体包括氦气等离子体、氩气等离子体、氨气等离子体中的一种或多种。
步骤S580：在所述缓冲层上形成覆盖栅极和有源层的层间绝缘层；在所述层间绝缘层和所述金属氧化层上形成分别对应于所述源极接触区和所述漏极接触区的一第二源极接触孔和一第二漏极接触孔。
所述层间绝缘层为氧化硅薄膜、氮化硅薄膜、或氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
在步骤S580中进一步包括：在所述层间绝缘层、所述金属氧化层和所述缓冲层上形成一第二接信号过孔；所述源极通过所述第二接信号过孔连接至所述遮光层。
所述源极通过所述第二接信号过孔与所述遮光层相连，从而使得所述遮光层上产生稳定的电压，能够避免产生浮栅效应，保证TFT器件的工作稳定性。此外，所述第二源极接触孔和所述第二漏极接触孔以及第二接信号过孔在同一道光刻制程中形成。
步骤S590：在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第二源极接触孔和所述第二漏极接触孔与所述源极接触区和所述漏极接触区相连。
所述源极和所述漏极的材料包括钼、铝、铜、钛中的一种或多种的合金。所述源极和所述漏极是通过沉积金属层并且进行图形化处理后得到的。
步骤S5100：在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
在层间绝缘层上形成覆盖源极和漏极的钝化层，完成顶栅自对准金属氧化物半导体TFT的制作。
当然，在步骤S5100的步骤之后，进一步包括在所述钝化层上形成平坦层，在所述平坦层上形成阳极，所述阳极为氧化铟锡（ITO）电极，在所述阳极上设置像素界定层，所述像素界定层具有开口，在开口位置设置有机发光层。这样，完成了顶栅自对准金属氧化物半导体TFT的背板制作。
本发明的优点在于，本发明所述顶栅自对准金属氧化物半导体TFT通过新增一超薄金属层，以防止在栅极的化学气相沉积时等离子体对氧化铟镓锌造成的伤害，同时提升器件的迁移率和可靠度。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (13)

  1. 一种顶栅自对准金属氧化物半导体TFT，其包括：一有源层、一依次设置于所述有源层上方的栅极绝缘层和栅极，以及一设置在所述有源层和所述栅极绝缘层之间的第一阻挡层。
  2. 如权利要求1所述的顶栅自对准金属氧化物半导体TFT，其中所述第一阻挡层为金属氧化层；所述金属氧化层的材料为二氧化钛或三氧化钼。
  3. 如权利要求1所述的顶栅自对准金属氧化物半导体TFT，其中所述第一阻挡层的厚度范围为10埃至50埃。
  4. 如权利要求1所述的顶栅自对准金属氧化物半导体TFT，其中所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述有源层下方的第一基板，所述第一基板包括：一衬底基板、一设置与所述衬底基板上的遮光层、一设置于所述遮光层上且覆盖所述遮光层的缓冲层。
  5. 如权利要求4所述的顶栅自对准金属氧化物半导体TFT，其中所述顶栅自对准金属氧化物半导体TFT还包括：一设置在所述缓冲层上且覆盖所述栅极和所述有源层的层间绝缘层、一设置在所述层间绝缘层上的源极和漏极、一设置在在所述层间绝缘层上且覆盖所述源极和所述漏极的钝化层。
  6. 如权利要求5所述的顶栅自对准金属氧化物半导体TFT，其中所述有源层设置在所述缓冲层上且对应于所述遮光层上方，所述有源层包括：一对应于栅极的沟道区以及分别位于所述沟道区两侧的一源极接触区和一漏极接触区；所述源极和所述漏极分别与所述有源层的所述源极接触区和所述漏极接触区连接。
  7. 如权利要求6所述的顶栅自对准金属氧化物半导体TFT，其中所述层间绝缘层上设有对应于源极接触区和漏极接触区的一第一源极接触孔和一第一漏极接触孔，所述源极和所述漏极分别通过所述第一源极接触孔和所述第一漏极接触孔与所述有源层的所述源极接触区和所述漏极接触区连接。
  8. 如权利要求6所述的顶栅自对准金属氧化物半导体TFT，其中所述层间绝缘层和所述金属氧化层上设有对应于所述源极接触区和所述漏极接触区的一第二源极接触孔和一第二漏极接触孔，所述源极和所述漏极分别通过所述第二源极接触孔和所述第二漏极接触孔与所述有源层的所述源极接触区和所述漏极接触区连接。
  9. 如权利要求7所述的顶栅自对准金属氧化物半导体TFT，其中所述顶栅自对准金属氧化物半导体TFT还包括一第一接信号过孔，所述第一接信号过孔设置在所述层间绝缘层和所述缓冲层上且对应于所述遮光层的上方，所述源极通过所述第一接信号过孔与所述遮光层相连。
  10. 如权利要求8所述的顶栅自对准金属氧化物半导体TFT，其中所述顶栅自对准金属氧化物半导体TFT还包括一第二接信号过孔，所述第二接信号过孔设置在所述层间绝缘层、所述金属氧化层和所述缓冲层上且对应于所述遮光层的上方，所述源极通过所述第二接信号过孔与所述遮光层相连。
  11. 一种显示面板，其中所述显示面板包括如权利要求1所述的顶栅自对准金属氧化物半导体TFT。
  12. 一种顶栅自对准金属氧化物半导体TFT的制作方法，其中所述方法包括以下步骤：
    （1）提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层；
    （2）在所述缓冲层上沉积一覆盖所述有源层的金属层， 并且对所述金属层进行氧化处理，以形成金属氧化层；
    （3）在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层；
    （4）在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案；
    （5）以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于所述有源层上方的栅极；
    （6）以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层；
    （7）以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对所述金属氧化层进行刻蚀，以形成相应的金属氧化层，所述栅极、所述栅极绝缘层、所述金属氧化层在所述有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的源极接触区和漏极接触区；
    （8）以所述光阻层、所述栅极、所述栅极绝缘层、所述金属氧化层为阻挡层，对所述有源层进行导体化处理，在导体化制程结束之后，剥离所述光阻层；
    （9）在所述缓冲层上形成一覆盖所述栅极和所述有源层的层间绝缘层；在所述层间绝缘层上形成分别对应于所述源极接触区和所述漏极接触区的一第一源极接触孔和一第一漏极接触孔；
    （10）在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第一源极接触孔和所述第一漏极接触孔与所述源极接触区和所述漏极接触区相连；以及
    （11）在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
  13. 一种顶栅自对准金属氧化物半导体TFT的制作方法，其中所述方法包括以下步骤：
    （1）提供一衬底基板，在所述衬底基板上形成一遮光层，在所述衬底基板上形成一覆盖所述遮光层的缓冲层，在所述缓冲层上形成一对应于所述遮光层上方的有源层；
    （2）在所述缓冲层上沉积一覆盖所述有源层的金属层， 并且对所述金属层进行氧化处理，以形成金属氧化层；
    （3）在所述金属氧化层上形成一栅极绝缘层，在所述栅极绝缘层上沉积一栅极金属层；
    （4）在所述栅极金属层上形成一光阻层，并且对所述光阻层进行图形化处理，以定义出栅极图案；
    （5）以所述光阻层为阻挡层，对所述栅极金属层进行刻蚀，以形成对应于有源层上方的栅极；
    （6）以所述光阻层和所述栅极为阻挡层，对所述栅极绝缘层进行刻蚀，以形成相应的栅极绝缘层，所述栅极和所述栅极绝缘层在有源层上限定出对应所述栅极的沟道区以及分别位于沟道区两侧的一源极接触区和一漏极接触区；
    （7）以所述光阻层、所述栅极和所述栅极绝缘层为阻挡层，对金属氧化层和有源层进行导体化处理，在导体化制程结束之后，剥离光阻层；
    （8）在所述缓冲层上形成覆盖栅极和有源层的层间绝缘层；在所述层间绝缘层和所述金属氧化层上形成分别对应于所述源极接触区和所述漏极接触区的一第二源极接触孔和一第二漏极接触孔；
    （9）在所述层间绝缘层上形成一源极和一漏极，所述源极和所述漏极分别通过所述第二源极接触孔和所述第二漏极接触孔与所述源极接触区和所述漏极接触区相连；以及
    （10）在所述层间绝缘层上形成一覆盖源极和漏极的钝化层。
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