WO2020187073A1 - 阵列基板及其制造方法和显示面板 - Google Patents

阵列基板及其制造方法和显示面板 Download PDF

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WO2020187073A1
WO2020187073A1 PCT/CN2020/078390 CN2020078390W WO2020187073A1 WO 2020187073 A1 WO2020187073 A1 WO 2020187073A1 CN 2020078390 W CN2020078390 W CN 2020078390W WO 2020187073 A1 WO2020187073 A1 WO 2020187073A1
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layer
molybdenum
metal
nitride
molybdenum nitride
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PCT/CN2020/078390
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English (en)
French (fr)
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卓恩宗
杨凤云
莫琼花
张勇
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惠科股份有限公司
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Priority to US17/418,259 priority Critical patent/US20220068976A1/en
Publication of WO2020187073A1 publication Critical patent/WO2020187073A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • liquid crystal displays As the main medium for transmitting information, liquid crystal displays have been widely used in various fields of work and life. But few people know that a seemingly simple liquid crystal panel requires hundreds of processes to make.
  • a liquid crystal display panel is composed of an array substrate containing active elements such as thin film transistors, a color filter substrate containing elements such as color filters, and a liquid crystal cell sandwiched therein.
  • the transparent electrode layer on the surface of the array substrate needs to be The metal layer connection in the active switch.
  • the purpose of this application is to provide an array substrate, a manufacturing method thereof, and a display panel to improve the undercutting phenomenon of the passivation layer.
  • this application discloses a manufacturing method of an array base, which includes the steps:
  • a passivation layer is formed on the source and drain electrodes, and the passivation layer is a second nitride structure corresponding to the first nitride, or a second oxide structure corresponding to the first oxide .
  • the present application also discloses an array substrate, including: a base layer; a semiconductor layer arranged on the base layer; a metal layer arranged on the semiconductor layer and etched into source and drain electrodes, and a metal layer on the
  • the surface contains a first nitride or a first oxide; a passivation layer is arranged on the source and drain electrodes, and the passivation layer is a second nitride structure arranged corresponding to the first nitride, or the same
  • the first oxide corresponds to the second oxide structure.
  • the application also discloses a display panel, which includes a color filter substrate and an array substrate disposed oppositely, and a liquid crystal layer disposed between the color filter substrate and the array substrate.
  • the array substrate includes a base layer, a semiconductor Layer, a metal layer and a passivation layer, the semiconductor layer is provided on the base layer; the metal layer is provided on the semiconductor layer and is etched into source and drain electrodes, and the upper surface of the metal layer contains the first Nitride or a first oxide; the passivation layer is disposed on the source and drain, and the passivation layer is a second nitride structure corresponding to the first nitride, or is in combination with the first nitride The oxide corresponds to the second oxide structure.
  • the upper surface of the source and drain electrodes in this application contains the first nitride or the first oxide.
  • the second nitride structure corresponding to the first oxide or the passivation layer composed of the second oxide structure corresponding to the first oxide is deposited on the source and drain, the two nitrogen-containing structures or oxygen-containing structures will be adsorbed Therefore, the passivation layer is more closely attached to the source and drain electrodes. In this way, during etching, the bond between the passivation layer and the source and drain electrodes is not prone to undercutting, thereby improving the yield of the display panel.
  • Figure 1 is a schematic diagram of an active switch
  • Figure 2 is a schematic diagram of a passivation layer undercutting phenomenon
  • Figure 3 is a schematic diagram of another passivation layer undercutting phenomenon
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a manufacturing method of an array substrate based on FIG. 4 of the present application
  • FIG. 6 is a flowchart of another method of manufacturing an array substrate based on FIG. 4 in the present application.
  • FIG. 7 is a flowchart of another method of manufacturing an array substrate based on FIG. 6 of the present application.
  • FIG. 8 is a schematic diagram of an array substrate according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an array substrate according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram of an array substrate according to another embodiment of the present application.
  • FIG. 11 is a schematic diagram of an array substrate according to another embodiment of the present application.
  • FIG. 12 is a schematic diagram of a display panel according to another embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features; “plurality” means two or more.
  • the term “comprising” and any variations thereof means non-exclusive inclusion, the possibility of the presence or addition of one or more other features, integers, steps, operations, units, components, and/or combinations thereof.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • FIG. 1 is a schematic diagram of an array substrate 200.
  • an array substrate 200 known to the inventor includes an active switch 220, a substrate 210, and a transparent electrode layer 230.
  • the active switch 220 is disposed on the substrate 210.
  • the via hole is etched, and the transparent electrode layer 230 is connected to the drain through the via hole.
  • the via hole is prone to undercut during etching.
  • M is the undercutting phenomenon on the passivation layer 227.
  • M is the undercutting phenomenon on the passivation layer 227.
  • the undercutting phenomenon In severe cases, it may directly cause the display panel 100 to display abnormally.
  • the undercutting phenomenon When the undercutting phenomenon is slight, it may become a latent problem. In use, problems such as dark spots appear in the display of the display panel 100, which will affect the quality of the display panel 100.
  • N is the part of the transparent electrode layer 230 affected by undercutting. It can be seen from the figure that the transparent electrode is in the via hole. The thickness of the layer 230 is not uniform, and even the transparent electrode layer 230 at the undercut portion of the passivation layer 227 may be broken, which may cause problems such as abnormal display of the display panel 100.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate 200. As shown in FIG. 4, an embodiment of the present application discloses a method for manufacturing an array substrate 200, including the steps:
  • the passivation layer is a second nitride structure corresponding to the first nitride, or a second oxide structure corresponding to the first oxide.
  • the upper surface of the source and drain electrodes 226 in this application contains a first nitride or a first oxide.
  • the second nitride structure is provided corresponding to the first nitride, or the second oxide is provided corresponding to the first oxide
  • the passivation layer 227 composed of a substance structure is deposited on the source and drain electrodes 226, the nitrogen atoms in the two nitrogen-containing structures or the oxygen atoms in the two oxygen-containing structures will attract each other due to the van der Waals forces between the same atoms It is larger than the van der Waals force between dissimilar atoms, so that the passivation layer 227 and the source and drain electrodes 226 have an adsorption force, which causes the passivation layer 227 to adhere more closely to the source and drain electrodes 226. In this way, during etching, the passivation layer The joint between the 227 and the source and drain electrodes 226 is not prone to undercutting, thereby improving the yield of the display panel 100.
  • the base layer 223 includes a substrate 210, a gate metal layer 221, and a gate insulating layer 222.
  • the gate metal layer 221 is disposed on the substrate 210
  • the gate insulating layer 222 is disposed on the gate metal layer 221
  • the semiconductor The layer 224 is disposed on the gate metal layer 221, wherein the semiconductor layer 224 includes an active layer and an ohmic contact layer, or the semiconductor layer 224 only includes an active layer.
  • FIG. 5 is a method flowchart based on step S3.
  • the metal layer 225 includes a metal base layer 2251 disposed on the semiconductor layer 224, and a first nitride disposed on the metal base layer 2251
  • the first nitride layer is a molybdenum nitride layer 2254
  • the passivation layer 227 is a nitride structure
  • the step S3 includes the following steps:
  • the nitrogen atom is decomposed into nitrogen atoms through the plasma process, and the nitrogen atoms are combined with the molybdenum metal material to form a molybdenum nitride layer 2254. Because the nitrogen atoms only react with the surface of the molybdenum metal material in this process, the thickness of the molybdenum nitride layer 2254 formed is very thick. It is thin, when the entire metal layer 225 is etched, the nitride layer hardly increases the overall etching time, and does not affect the productivity of the array substrate 200. In the S32 step, the plasma process adopts plasma chemical vapor deposition (Plasma enhanced Chemical Vapor Depositon, PECVD).
  • PECVD plasma chemical vapor deposition
  • FIG. 6 is also a method flowchart based on step S3.
  • the metal layer 225 includes a metal base layer 2251 disposed on the semiconductor layer 224, and a first nitrogen layer disposed on the metal base layer 2251.
  • the first nitride layer is a molybdenum nitride layer 2254, and the passivation layer 227 is a nitride structure;
  • the step S3 includes the steps:
  • S35 etching the metal material base layer to form a metal base layer, and etching the molybdenum nitride material to form a molybdenum nitride layer.
  • the molybdenum nitride material is formed.
  • the process of generating the molybdenum nitride material does not occupy the time of depositing the metal material.
  • the process time of the entire array substrate 200 is not due to the increase in the process time of the molybdenum nitride layer 2254. If lengthened, the array substrate 200 in the present application can not only improve the undercutting phenomenon of the passivation layer 227, but also increase the production efficiency, thereby increasing the productivity.
  • the molybdenum metal material is deposited by physical vapor deposition (Physical Vapor Deposition, referred to as PVD) technology.
  • PVD Physical Vapor Deposition
  • the molybdenum metal target is laid first, and then high-speed electrons are used to hit the target to make the molybdenum atoms.
  • the target material is knocked out and the separated molybdenum atoms come into contact with nitrogen, the covalent bond between the nitrogen atom and the nitrogen atom is easily broken, so that the molybdenum atom and the nitrogen atom are connected and reacted to form molybdenum nitride.
  • the molybdenum nitride layer 2254 can also be a molybdenum oxide layer.
  • the nitrogen in step S34 is correspondingly replaced with oxygen.
  • the oxygen reacts with the molybdenum metal material to form molybdenum oxide, which is etched to form oxide
  • the molybdenum layer, and the passivation layer 227 corresponds to an oxide structure, such as silicon oxide; this can also generate an adsorption force between the metal layer 225 and the passivation layer 227, and improve the erosion of the passivation layer 227.
  • Fig. 7 is a flow chart of the method based on step S33. As shown in Fig. 7, in an embodiment, the step S33 includes the following steps:
  • S332 Depositing an aluminum metal material on the molybdenum metal material to form a metal material base layer including the molybdenum metal material and the aluminum metal material;
  • step S35 includes the steps of etching the molybdenum metal material to form a molybdenum metal layer, and etching the aluminum metal material to form an aluminum metal layer to obtain a metal base layer including a molybdenum metal layer and an aluminum metal layer.
  • the metal base 2251 is made into two metal material layers, one is the molybdenum metal layer 2252 provided on the semiconductor layer 224, and the other is the aluminum metal layer 2253 provided on the molybdenum metal layer 2252.
  • This structure is used because of aluminum The conductive effect is better, which can play a better transmission effect.
  • what is arranged on the molybdenum metal layer 2252 is not limited to the aluminum metal layer 2253.
  • metals with good conductivity are also applicable to the metal base layer 2251 of the present application, such as the copper metal layer; as for the aluminum metal layer 2253 and the semiconductor layer 224
  • the molybdenum metal layer 2252 in between and the molybdenum nitride layer 2254 above the aluminum metal layer 2253 play a role in protecting the aluminum metal layer 2253 and prevent the aluminum metal layer 2253 from being corroded. This is because the molybdenum metal material and the molybdenum nitride material It is relatively stable and hard to react. Protecting the aluminum metal layer 2253 through the molybdenum metal layer 2252 and the molybdenum nitride layer 2254 can increase the service life of the entire array substrate 200 and the display panel 100.
  • the molybdenum metal layer 2252 in this application can also be replaced with other metal layers, and any metal material that can play the same role as molybdenum can be used, such as titanium (Ti) and tantalum (Ta); correspondingly, the molybdenum in step S34
  • the metal material can also be a titanium metal material or a tantalum metal material.
  • the metal base 2251 is not limited to a two-layer structure.
  • the metal base 2251 can be a single-layer molybdenum metal layer 2252 or a single-layer aluminum metal layer 2253 or even other metal layers. In this case, only one process is required to make the metal substrate 2251 is completed, saving process steps; the metal base 2251 can also be set as three or more metal film layers, which is not limited here.
  • nitrogen can also be introduced, which can increase the concentration of nitrogen, improve the adsorption force between different layers of the metal base 2251, and avoid undercutting of different layers during etching.
  • Phenomenon for example, when forming the molybdenum metal layer 2252 and the aluminum metal layer 2253, nitrogen gas can also be introduced so that the molybdenum metal layer 2252 and the aluminum metal layer 2253 also contain nitrides to increase the gap between the molybdenum metal layer 2252 and the aluminum metal layer 2253. Adsorption.
  • the metal layer 225 of the present application can also be a molybdenum nitride layer 2254 as a whole, instead of merely forming a molybdenum nitride layer 2254 on the upper surface of the metal layer 225.
  • a molybdenum metal material is deposited on the metal material base layer, and nitrogen gas is introduced at a first flow rate at the same time.
  • a first molybdenum nitride material is formed, and nitrogen gas is introduced at a second flow rate.
  • the second molybdenum nitride material is formed, and nitrogen is introduced at a third flow rate to form the third molybdenum nitride material after the reaction;
  • the metal material base layer is etched to form a metal base layer 2251, and the molybdenum nitride material is etched to form a molybdenum nitride layer 2254.
  • the first flow rate is 200ml/min
  • the third flow rate is 1000ml/min
  • the second flow rate is less than the third flow rate.
  • the molar amount of nitrogen in the formation of molybdenum nitride is changed.
  • the nitrogen flow rate is small, the molar amount of nitrogen in the formed molybdenum nitride is lower;
  • the flow rate is larger, the molar amount of nitrogen in the formed molybdenum nitride is higher.
  • the molybdenum nitride layer 2254 and the passivation layer 227 have a better adsorption effect, which can make the metal layer 225 and the passivation layer 227 more closely adhere to each other.
  • the improvement effect of the undercutting phenomenon is better.
  • the application adjusts the flow rate of the nitrogen gas to In a controllable state, and the nitrogen flow rate is controlled between 200ml/min and 1000ml/min, this can avoid the problem that the nitrogen content is too large to cause etching difficulties or waste nitrogen, and at the same time, it can also prevent the nitrogen content from being too low.
  • the adsorption force brought by it is too weak, and the phenomenon of undercutting cannot be improved; therefore, the nitrogen introduced is controlled within a certain range, so that the reaction between nitrogen and molybdenum can be better, and it can be blunt.
  • the chemical layer 227 has a better adsorption effect.
  • the first flow rate, the second flow rate and the third flow rate here are between 200ml/min and 1000ml/min.
  • the first flow rate is not limited to 200ml/min, for example, it can be 400ml/min.
  • the third flow rate is not limited to 1000ml/min, for example, it can also be 800ml/min; the corresponding second flow rate can be 500ml/min or 600ml/min.
  • the flow rate of nitrogen gas is changed from small to large. This will result in a lower molar amount of nitrogen in the molybdenum nitride layer 2254 close to the semiconductor, and a larger molar amount of nitrogen in the molybdenum nitride layer 2254 close to the passivation layer 227.
  • the passivation layer 227 and the metal layer 225 adsorb
  • the metal layer 225 is etched, the lower the molar amount of nitrogen in the molybdenum nitride layer 2254 is, the easier the metal layer 225 is etched, which helps to improve the undercutting phenomenon and try to avoid etching too slowly And the situation that affects production efficiency.
  • This application provides two methods for changing nitrogen from small to large.
  • One is that the flow of nitrogen is gradually changed, that is, when the metal layer 225 is deposited, the flow of nitrogen is changed from small to large, and the change process is relatively slow.
  • It is not a jump increase which will result in the formation of the molybdenum nitride layer 2254 without obvious stratification boundaries, for example, with a unit of 1ml/min, gradually increase the nitrogen flow.
  • the bottom refers to the direction close to the semiconductor layer 224.
  • the upper side is the direction close to the passivation layer 227.
  • the metal layer 225 structure formed by this method is etched, since the nitrogen content is gradual, undercutting is not prone to occur, and there will be no obvious gaps.
  • the surface of the etched pattern is relatively flat.
  • the passivation layer 227 is formed on the passivation layer 227, the thickness of the passivation layer 227 will be more uniform, thereby making the thickness of the transparent electrode layer 230 above the passivation layer 227 uniform and improving the disconnection of the transparent electrode layer 230, thereby improving the display panel 100 display effect.
  • nitrogen can be introduced through more time periods, and the flow rate in each time period is equal, and the flow difference between the two adjacent time periods before and after is small, so that the nitrogen flow rate can be achieved when implemented. Gradient effect.
  • the second method is to divide the time of nitrogen gas flow into at least three time periods.
  • the flow rate of nitrogen gas in each time period is equal, and the flow rate of nitrogen gas in the later time period is compared with the previous time period.
  • the flow of nitrogen gas is large.
  • This will form a multi-layered molybdenum nitride layer 2254 structure, and the boundary between adjacent molybdenum nitride layers 2254 is relatively clear, because the molar amount of nitrogen in different molybdenum nitride layers 2254 changes in sequence, reducing the gap between the molybdenum nitride layers 2254
  • the difference in nitrogen content of the metal layer can avoid undercutting between the different layers of the metal layer itself.
  • the flow of nitrogen gas can be better controlled, and the flow of nitrogen gas only needs to be adjusted once in each time period, so it is easy to control in operation.
  • the thicknesses of the first molybdenum nitride layer 2255, the second molybdenum nitride layer 2256, and the third molybdenum nitride layer 2257 are equal.
  • the thickness as a parameter of a thin film layer can be directly set during deposition. There is no need to worry about the thickness deviation of the final film layer.
  • the first molybdenum nitride layer 2255, the second molybdenum nitride layer 2256 and the third molybdenum nitride layer 2257 The thickness of is set to be consistent, which can eliminate the two steps of adjusting the thickness parameters, that is, the thickness parameters are set when depositing the first molybdenum nitride layer 2255, and the second molybdenum nitride layer 2256 is deposited and the third molybdenum nitride layer is deposited.
  • the other three molybdenum nitride layers 2254 have the same thickness, which will make the pattern formed by the molybdenum nitride layer 2254 during etching more uniform.
  • the thickness of the first molybdenum nitride layer 2255 and the thickness of the second molybdenum nitride layer 2256 are smaller than the thickness of the third molybdenum nitride layer 2257.
  • the third molybdenum nitride layer 2257 is attached to the passivation layer 227. If it is too thin, the adsorption effect on the passivation layer 227 will be poor. Therefore, the third passivation layer 227 should be kept to a certain thickness, while the first molybdenum nitride layer The thickness requirements of 2255 and the second molybdenum nitride layer 2256 are relatively low.
  • the etching time is less.
  • the thickness parameter of the molybdenum nitride layer 2254 is set to 10 nm, which will not affect the adsorption effect between the molybdenum nitride layer 2254 and the passivation layer 227.
  • the thickness of the molybdenum nitride layer 2254 is too thin, the nitrogen The adsorption effect of the molybdenum layer 2254 and the passivation layer 227 will be reduced, so the effect of improving the undercutting phenomenon of the passivation layer 227 is not very obvious; if the thickness of the molybdenum nitride layer 2254 is too large, it will cause the molybdenum nitride layer 2254 The stress increases, and the adsorption force with the metal layer 225 or the semiconductor layer 224 under the molybdenum nitride layer 2254 decreases, so that the molybdenum nitride layer 2254 or the metal layer 225 appears etching phenomenon, and after testing, the thickness of the molybdenum nitride layer 2254 is set At this time, the molybdenum nitride layer 2254 has a better adsorption force with the passivation layer 227, and no greater stress is generated.
  • the thickness of the molybdenum nitride layer 2254 attached to the passivation layer 227 can be set to 10 nm, that is, the thickness of the third molybdenum nitride layer 2257 is 10 nm, and the first molybdenum nitride layer 2255 and the second nitride layer 2255 have a thickness of 10 nm.
  • the thickness of the molybdenum layer 2256 is less than 10 nm, which can speed up the etching rate of the molybdenum nitride layer 2254 and increase productivity; it can also make the thickness of the first molybdenum nitride layer 2255 smaller than the thickness of the second molybdenum nitride layer 2256, so that The thickness of the molybdenum layer 2254 gradually increases along the direction from the semiconductor layer 224 to the passivation layer 227, which can speed up the manufacturing process of the molybdenum nitride layer 2254.
  • FIG. 8 is a schematic diagram of an array substrate 200.
  • an array substrate 200 which includes a base layer 223, a semiconductor layer 224, a metal layer 225, and a passivation layer 227, wherein the semiconductor layer 224 is disposed on the base layer 223, the metal layer 225 is disposed on the semiconductor layer 224 and is etched into the source and drain electrodes 226, and the upper surface of the metal layer 225 contains the first nitride or the first oxide;
  • the passivation layer 227 is disposed on the source and drain electrodes 226, and the passivation layer 227 is a second nitride structure corresponding to the first nitride, or a second oxide structure corresponding to the first oxide.
  • the metal layer 225 includes a metal base layer 2251 and a molybdenum nitride layer 2254.
  • the metal base layer 2251 is disposed on the semiconductor layer 224
  • the molybdenum nitride layer 2254 is disposed on the metal base layer 2251
  • the molybdenum nitride layer 2254 is in contact with the passive
  • the passivation layer 227 is attached to each other, and the passivation layer 227 has a nitride structure.
  • the source and drain electrodes 226 are composed of a stacked metal base layer 2251 and a molybdenum nitride layer 2254, the thickness of the molybdenum nitride layer 2254 is relatively low, and a large amount of nitrogen gas is not required, which can save the cost of nitrogen; in addition, molybdenum nitride
  • the layer 2254 may also be a titanium nitride layer or a tantalum nitride layer.
  • the metal layer 225 here may also include a metal base layer 2251 and a molybdenum oxide layer.
  • the metal base 2251 is disposed on the semiconductor layer 224, the molybdenum oxide layer is disposed on the metal base layer 2251, and the molybdenum oxide layer is attached to the passivation layer 227.
  • the oxide layer 227 has an oxide structure.
  • the molybdenum oxide layer can also be a titanium oxide layer or a tantalum oxide layer.
  • FIG. 9 is a schematic diagram of another array substrate 200.
  • the metal layer 225 is a molybdenum nitride layer 2254.
  • the entire metal layer 225, as well as the entire source and drain electrodes 226, is a single-layer molybdenum nitride structure.
  • the molybdenum nitride layer 2254 is formed by introducing nitrogen gas when depositing molybdenum metal material, and the molybdenum nitride layer 2254 The process does not take up other process time and can maximize productivity.
  • the entire metal layer 225 is made of molybdenum nitride layer 2254, which has a high nitrogen content, the adsorption effect on the passivation layer 227 is good, and the passivation layer 227 The effect of improving undercutting phenomenon is better.
  • FIG. 10 is a schematic diagram of another array substrate 200.
  • the metal base layer 2251 includes a molybdenum metal layer 2252 and an aluminum metal layer 2253.
  • the molybdenum metal layer 2252 is disposed on the semiconductor layer 224.
  • the metal layer 2253 is provided on the molybdenum metal layer 2252 and the molybdenum nitride layer 2254 is provided on the aluminum metal layer 2253.
  • an aluminum metal layer 2253 in the metal base 2251 can make the signal transmission effect of the source and drain 226 better, because aluminum has a better conductive effect, and there are molybdenum metal layers 2252 and molybdenum nitride layers on both sides of the aluminum metal layer 2253 2254, can play a role in protecting the aluminum metal layer 2253, the method aluminum metal layer 2253 is corroded.
  • FIG. 11 is a schematic diagram of another array substrate 200.
  • the molybdenum nitride layer 2254 includes a first molybdenum nitride layer 2255, a second molybdenum nitride layer 2256, and a third molybdenum nitride layer 2255.
  • the first molybdenum nitride layer 2255 is disposed on the metal base layer 2251
  • the second molybdenum nitride layer 2256 is disposed on the first molybdenum nitride layer 2255
  • the third molybdenum nitride layer 2257 is disposed on the second molybdenum nitride
  • the molar amount of nitrogen in the first molybdenum nitride layer 2255 is smaller than the molar amount of nitrogen in the second molybdenum nitride layer 2256
  • the molar amount of nitrogen in the second molybdenum nitride layer 2256 is smaller than the third molybdenum nitride layer 2257
  • the molar amount of nitrogen is smaller than the third molybdenum nitride layer 2257.
  • the adsorption effect of the molybdenum nitride layer 2254 and the passivation layer 227 is better, which can make the metal layer 225 and the passivation layer 227 adhere more closely, and the passivation layer 227 can be more closely attached.
  • the improvement effect of the corrosion phenomenon is better, but the larger molar amount of nitrogen in the molybdenum nitride layer 2254 will make the etching of the metal layer 225 more difficult, which in turn will cause the etching process time of the metal layer 225 to increase, and reduce the entire array substrate 200 and the display panel 100.
  • the first molybdenum nitride layer 2255 and the second molybdenum nitride layer 2256 have a poor adsorption effect on the passivation layer 227. Therefore, the nitrogen in the first molybdenum nitride layer 2255 and the second molybdenum nitride layer 2256 The molar amount of is lower than the molar amount of nitrogen in the third molybdenum nitride layer 2257. In this case, the first molybdenum nitride layer 2255 and the second molybdenum nitride layer 2256 are easier to etch, which can increase the etching efficiency of the entire metal layer 225 and improve The productivity of the array substrate 200.
  • FIG. 12 is a schematic diagram of a display panel 100.
  • a display panel 100 which includes a color filter substrate 300, a liquid crystal layer 400, and the aforementioned array substrate 200, wherein , The color filter substrate 300 and the array substrate 200 are disposed oppositely, and the liquid crystal layer 400 is filled between the color filter substrate 300 and the array substrate 200.
  • the technical solution of the present application can be widely used in various display panels, such as twisted nematic (TN) display panels, in-plane switching (IPS) display panels, vertical alignment (Vertical Alignment, VA) ) Display panel, Multi-Domain Vertical Alignment (MVA) display panel, of course, it can also be other types of display panel, such as Organic Light-Emitting Diode (OLED) display panel.
  • TN twisted nematic
  • IPS in-plane switching
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • OLED Organic Light-Emitting Diode

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Abstract

本申请公开了一种阵列基板及其制造方法和显示面板，所述阵列基板的制造方法包括步骤：形成基底层；在所述基底层上形成半导体层；在所述半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物；将所述金属层蚀刻成源漏极；在所述源漏极上形成钝化层，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。

Description

阵列基板及其制造方法和显示面板
本申请要求于2019年3月15日提交中国专利局，申请号为CN201910197080.7，申请名称为“一种阵列基板及其制造方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
液晶显示器作为传递信息的主要媒介，已经被广泛应用于工作、生活中的各个领域。但是很少有人知道看似简单的液晶面板，其制作需要成百上千道工序。一般而言，液晶显示面板是由包含薄膜晶体管等主动元件的阵列基板、包含彩色滤光片等元件的彩膜基板以及夹置其中的液晶盒所组成，位于阵列基板表面的透明电极层需要与主动开关中的金属层连接。
在阵列基板的制作中，金属层表面的钝化层在刻蚀形成接触孔洞时，容易出现钻蚀(Passivation Undercut)现象，严重时可能直接导致液晶面板显示异常。
发明内容
本申请的目的是提供一种阵列基板及其制造方法和显示面板，以改善钝化层的钻蚀现象。
为实现上述目的，本申请公开了一种阵列基的制造方法，包括步骤：
形成基底层；
在所述基底层上形成半导体层；
在所述半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物；
将所述金属层蚀刻成源漏极；
在所述源漏极上形成钝化层，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
本申请还公开了一种阵列基板，包括：基底层；半导体层，设置在所述基底层上；金属层，设置在所述半导体层上，被蚀刻为源漏极，所述金属层的上表面含有第一氮化物或者第一氧化物；钝化层，设置在所述源漏极上，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
本申请还公开了一种显示面板，包括对向设置的彩膜基板和阵列基板，以及设置在所述彩膜基板和所述阵列基板之间的液晶层，所述阵列基板包括基底层、半导体层、金属层和钝化层，所述半导体层设置在所述基底层上；所述金属层设置在所述半导体层上，被蚀刻为源漏极，所述金属层的上表面含有第一氮化物或者第一氧化物；所述钝化层设置在所述源漏极上，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
相对于源漏极不含第一氮化物或者第一氧化物的方案来说，本申请中源漏极的上表面含有第一氮化物或者第一氧化物，当由与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构构成的钝化层沉积在源漏极上时，两种含氮结构或含氧结构会产生吸附力，从而使钝化层在源漏极上贴合更加紧密，如此，在进行蚀刻，钝化层与源漏极的贴合处不容易出现钻蚀现象，从而提高显示面板良率。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是一种主动开关的示意图；
图2是一种钝化层钻蚀现象的示意图；
图3是另一种钝化层钻蚀现象的示意图；
图4是本申请的一实施例的一种阵列基板制造方法的流程图；
图5是本申请基于图4的一种阵列基板制造方法的流程图；
图6是本申请基于图4的另一种阵列基板制造方法的流程图；
图7是本申请基于图6的另一种阵列基板制造方法的流程图；
图8是本申请的一实施例的一种阵列基板的示意图；
图9是本申请的另一实施例的一种阵列基板的示意图；
图10是本申请的另一实施例的一种阵列基板的示意图；
图11是本申请的另一实施例的一种阵列基板的示意图；
图12是本申请的另一实施例的一种显示面板的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体 实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
图1是一种阵列基板200的示意图，如图1所示，发明人了解到的一种阵列基板200，包括主动开关220、衬底210和透明电极层230，主动开关220设置在衬底210上与透明电极层230之间，沿背离衬底210的方向依次包括：栅极金属层221、栅极绝缘层222、半导体层224、源漏极226和钝化层227；其中钝化层227被蚀刻出过孔，透明电极层230通过过孔与漏极连接，然而过孔在蚀刻时容易出现钻蚀(Passivation Undercut)现象。
图2为钝化层227发生钻蚀现象的示意图，图中M为钝化层227上出现的钻蚀现象，严重时可能直接导致显示面板100显示异常，钻蚀现象轻微时，可能成为潜伏问题，在使用中导致显示面板100显示出现暗点等问题，会影响显示面板100的品质。
图3为透明电极层230铺设在发生钻蚀的钝化层227上的示意图，图中N为透明电极层230受到钻蚀现象影响的部分，从图中可以看到，在过孔中透明电极层230的厚度不均匀，甚至在钝化层227钻蚀部分的透明电极层230可能会断掉，从而会导致显示面板100的显示异常等问题。
下面参考附图和可选的实施例对本申请作进一步说明。
图4是一种阵列基板200制造方法的流程图，如图4所示，本申请实施例公布了一种阵列基板200的制造方法，包括步骤：
S1：形成基底层；
S2：在基底层上形成半导体层；
S3：在半导体层上形成金属层，金属层的上表面含有第一氮化物或者第一氧化物；
S4：将金属层蚀刻成源漏极；
S5：在源漏极上形成钝化层，钝化层为与第一氮化物对应设置的第二氮化物结构，或与第一氧化物对应设置的第二氧化物结构。
本申请中的源漏极226的上表面含有第一氮化物或者第一氧化物，当由与第一氮化物对应设置的第二氮化物结构，或与第一氧化物对应设置的第二氧化物结构构成的钝化层227沉积在源漏极226上时，两种含氮结构中的氮原子或两种含氧结构中的氧原子会相互吸引，这是由于相同原子之间的范德华力比异种原子之间的范德华力大，从而使钝化层227与源漏极226产生吸附力，导致钝化层227在源漏极226上贴合更加紧密，如此，在进行蚀刻，钝化层227与源漏极226的贴合处不容易出现钻蚀现象，从而提高显示面板100良率。
其中，基底层223包括衬底210、栅极金属层221和栅极绝缘层222，其中栅极金属层221设置在衬底210上，栅极绝缘层222设置在栅极金属层221上，半导体层224设置在栅极金属层221上，其中，半导体层224包括有源层和欧姆接触层，或半导体层224只包括有源层。
具体的，在形成含有第一氮化物层或者第一氧化物层的源漏极226时只需要一道蚀刻工序，不需要分开蚀刻金属层225和第一氮化物层或者第一氧化物层，节省整个主动开关220的制程时间。
图5是基于步骤S3的方法流程图，如图5所示，在一实施例中，金属层225包括设置在半导体层224上的金属基层2251，以及设置在金属基层2251上的第一氮化物层，第一氮化物层为氮化钼层2254，钝化层227为氮化物结构；在S3步骤中，包括步骤：
S31：在半导体层上沉积钼金属材料；
S32：在钼金属材料上通入氮气，并同时将氮气通过电浆制程分解成氮原子，氮原子沉积到钼金属材料表面反应后形成氮化钼层。
通过电浆制程将氮气分解成氮原子，氮原子与钼金属材料结合成氮化钼层2254，由于此过程中氮原子只与钼金属材料表面发生反应，最后形成的氮化钼层2254厚度非常薄，蚀刻整个金属层225时，氮化层几乎不会增加整体的蚀刻时间，不影响阵列基板200的产能。在S32步骤中，电浆制程采用的工艺是等离子体化学气相沉积(Plasma enhanced Chemical Vapor Depositon，PECVD)。
图6同样是基于步骤S3的方法流程图，如图6所示，在一实施例中，金属层225包括设置在半导体层224上的金属基层2251，以及设置在金属基层2251上的第一氮化物层，第一氮化物层为氮化钼层2254，钝化层227为氮化物结构；在S3步骤中，包括步骤：
S33：在半导体层上沉积金属材料基层；
S34：在金属材料基层上沉积钼金属材料，并同时通入氮气，反应后形成氮化钼材料；
S35：蚀刻金属材料基层形成金属基层，蚀刻氮化钼材料形成氮化钼层。
通过在沉积金属材料时通入氮气，形成氮化钼材料，生成氮化钼材料的过程不占用沉积金属材料的时间，整个阵列基板200的制程时间并没有因为增加了氮化钼层2254的制程而延长，这样的话本申请中的阵列基板200既能改善钝化层227的钻蚀现象，又能提高生产效率，进而提升产能。在S34步骤中，钼金属材料是通过物理气相沉积(Physical Vapor Deposition，简称PVD)技术沉积而成，在此过程中，先铺设钼金属靶材，然后用高速电子撞击靶材，使钼原子从靶材中被撞击出来,分离出的钼原子接触氮气时，容易使氮原子和氮原子之间的共价键发生键解，从而使钼原子和氮原子连接反应形成氮化钼。
当然，该氮化钼层2254也可以为氧化钼层，基于氧化钼层，该S34步骤中的氮气则对应更换为氧气，如此，氧气与钼金属材料反应后形成氧化钼，经过蚀刻后形成氧化钼层，而且钝化层227对应就是氧化物结构，例如氧化硅；这样也能使金属层225与钝化层227之间产生吸附力，改善钝化层227的钻蚀现象。
图7是基于步骤S33的方法流程图，如图7所示，在一实施例中，在S33步骤中，包括步骤：
S331：在半导体层上沉积钼金属材料；
S332：在钼金属材料上沉积铝金属材料以形成包括钼金属材料和铝金属材料的金属材料基层；
对应在S35步骤中，包括步骤：蚀刻钼金属材料形成钼金属层，蚀刻铝金属材料形成铝金属层以得到包括钼金属层和铝金属层的金属基层。
这里将金属基底2251做成两个金属材料层，一个是设置在半导体层224上的钼金属层2252，一个是设置在钼金属层2252上的铝金属层2253，采用这种结构是因为铝的导电效果比较好，这样能够起到较好的传输效果。当然在这里设置在钼金属层2252上的并不只限定于铝金属层2253，其它导电效果好的金属同样适用于本申请的金属基层2251，例如铜金属层；至于铝金属层2253和半导体层224之间的钼金属层2252，以及铝金属层2253上方的氮化钼层2254则起到保护铝金属层2253的作用，防止铝金属层2253被腐蚀，这是因为钼金属材料以及氮化钼材料比较稳定，不易发生反应，通过钼金属层2252和氮化钼层2254保护铝金属层2253能够提高整个阵列基板200以及显示面板100的使用寿命。当然本申请中的钼金属层2252还可以替换成其它金属层，能够起到与钼相同作用的金属材料都可以，例如钛(Ti)以及钽(Ta)；对应的，该S34步骤中的钼金属材料也可以是钛金属材料或钽金属材料，当通入的气体为氮气时，对应生成的就是氮化钛层或氮化钽层；当通入的气体为氧气时，对应生成的就是氧化钛层或氧化钽层。
另外，金属基底2251并未限定只有两层结构，可以设置金属基底2251为单层的钼金属层2252或单层的铝金属层2253甚至其它金属层，这样的话只需要一道制程就可以将金属基底2251完成，节省制程步骤；也可以设置金属基底2251为三层甚至更多层金属膜层，这里不做限定。
另外，在沉积金属基底2251的不同膜层时，同样可以通入氮气，这样能够增加氮的浓度，提高金属基层2251内不同膜层之间的吸附力，避免不同膜层在蚀刻时出现钻蚀现象，例如在形成钼金属层2252和铝金属层2253时，也可以通入氮气使得钼金属层2252和铝金属层2253同样含有氮化物，以增加钼金属层2252和铝金属层2253之间的吸附力。当然，本申请的金属层225还可以整体为一个氮化钼层2254，而不仅仅是在金属层225的上表面形成一层氮化钼层2254。
在一实施例中，在S34步骤中，在金属材料基层上沉积钼金属材料，并同时以第一流量通入氮气，反应后形成第一氮化钼材料，以第二流量通入氮气，反应后形成第二氮化钼材料，以第三流量通入氮气，反应后形成第三氮化钼材料；蚀刻金属材料基层形成金属基层2251，蚀刻氮化钼材料形成氮化钼层2254的步骤中，蚀刻第一氮化钼材料形成第一氮化钼层2255，蚀刻第二氮化钼材料形成第二氮化钼层2256，蚀刻第三氮化钼材料形成第三氮化钼层2257；第一流量为200ml/min，第三流量为1000ml/min，第二流量小于第三流量。
通过改变通入氮气流量的不同，使形成氮化钼中氮的摩尔量发生改变，当通入氮气的流量较小时，生成的氮化钼中氮的摩尔量较低；当氮气通入时的流量较大时，生成的氮化钼中氮的摩尔量较高。其中当氮化钼中氮的摩尔量较大时，氮化钼层2254与钝化层227的吸附效果比较好，能够使金属层225与钝化层227贴合更加紧密，对钝化层227钻蚀现象的改善效果更好，为了既能使金属层225与钝化层227有较好的贴合效果，且金属层225在蚀刻时比较容易，本申请将氮气通入时的流量调至可控状态，且将氮气的流量控制在200ml/min到1000ml/min之间，如此可以避免氮的含量太大而造成蚀刻困难或浪费氮气的情况，同时，又可以避免氮的含量太低而带来的吸附力太弱，而造成无法改善钻蚀现象的情况；因此将通入的氮气控制在一定的范围内，这样即能使氮气与金属钼的反应较好，又能起到与钝化层227较好的吸附效果。这里的第一流量、第二流量和第三流量在200ml/min到1000ml/min之间，第一流量并不限定于200ml/min，例如也可以为400ml/min，第三流量并不限定于1000ml/min，例如也可以为800ml/min；对应的第二流量可以为500ml/min或600ml/min等。
在一实施例中，通入氮气的流量是从小到大变化的。这样会导致靠近半导体的氮化钼层2254中氮的摩尔量较低，靠近钝化层227的氮化钼层2254中氮的摩尔量较大，这样的话钝化层227与金属层225的吸附力会比较大，在蚀刻金属层225时，越往下氮化钼层2254中氮的摩尔量越小，金属层225越容易蚀刻，有利于在改善钻蚀现象的同时，尽量避免蚀刻太 慢而影响生产效率的情况。
本申请提供两种氮气从小到大的变化方法，一种是通入氮气时的流量是渐变的，也就是在沉积金属层225时，通入氮气的流量从小变到大，且变化过程比较缓慢，不是跳跃性的增长，这样会导致形成的氮化钼层2254没有明显的分层界线，例如以1ml/min为单位，逐渐增加氮气流量。如此操作，可以看成最终只生成一层的氮化钼结构，不过该氮化钼结构中氮的摩尔量从下往上逐渐增大，这里说的下方指的是靠近半导体层224的方向，上方即靠近钝化层227的方向。这种方法形成的金属层225结构在蚀刻时，由于氮的含量是渐变的，因而不容易出现钻蚀现象，也就不会出现明显的缺口，蚀刻出的图案表面比较平整，在金属层225上形成钝化层227时，钝化层227的厚度会比较均匀，进而使得位于钝化层227上方的透明电极层230厚度均匀且改善透明电极层230断线的情况，进而提升显示面板100的显示效果。本方法具体可采用通过较多的时间段通入氮气，每个时间段内通入的流量相等，且前后两个相邻时间段通入的流量差值较小，这样实施起来能够达到氮气流量渐变的效果。
第二种方法是，将通入氮气的时间划分为至少三个时间段，每个时间段内通入氮气的流量是相等的，且较后时间段内通入氮气的流量比较前的时间段内通入氮气的流量大。这样会形成多层的氮化钼层2254结构，且相邻氮化钼层2254的界限比较清楚，因为不同氮化钼层2254中氮的摩尔量依次改变，减少各个氮化钼层2254之间的氮含量差距，从而避免金属层自身的不同膜层之间出现钻蚀现象。采用这种分层的氮化钼结构，能够较好地控制通入氮气的流量，只需要在每个时间段内调控一次氮气的流量就行，因此在操作上容易控制。
在一实施例中，第一氮化钼层2255、第二氮化钼层2256和第三氮化钼层2257的厚度相等。厚度作为一个薄膜层的参数在沉积时可以直接设置，不用担心最后形成的薄膜层厚度产生偏差，所以将第一氮化钼层2255、第二氮化钼层2256和第三氮化钼层2257的厚度设为一致，可以免去两道调设厚度参数的步骤，即在沉积第一氮化钼层2255时设置好厚度参数，在沉积第二氮化钼层2256和沉积第三氮化钼层2257时可以不需要再去进行厚度调设，节省时间，另外三个氮化钼层2254的厚度相同，会使氮化钼层2254在蚀刻时形成的图案比较均匀。
在一实施例中，第一氮化钼层2255的厚度和第二氮化钼层2256的厚度小于第三氮化钼层2257的厚度。第三氮化钼层2257与钝化层227相贴，太薄的话对钝化层227的吸附效果较差，所以要保持第三钝化层227有一定的厚度，而第一氮化钼层2255和第二氮化钼层2256的厚度要求比较低，如果第一氮化钼层2255的厚度和第二氮化钼层2256的厚度小于第三氮化钼层2257的厚度，那么在蚀刻整个氮化钼层2254时，蚀刻的时间较少。
上述实施例中，将氮化钼层2254的厚度参数设置为10nm，这样不会影响氮化钼层2254和钝化层227之间的吸附效果，如果氮化钼层2254的厚度过薄，氮化钼层2254与钝化层 227的吸附效果会降低，这样对钝化层227的钻蚀现象改善的效果不是很明显；如果氮化钼层2254的厚度过大，会造成氮化钼层2254的应力增加，与氮化钼层2254下方的金属层225或半导体层224的吸附力降低，使氮化钼层2254或金属层225出现蚀刻现象，而经过测试将氮化钼层2254的厚度设置为10nm，这时氮化钼层2254既与钝化层227之间有较好的吸附力，又不会产生较大的应力。另外还可以只将与钝化层227贴合的氮化钼层2254的厚度设置为10nm，即第三氮化钼层2257的厚度为10nm，而第一氮化钼层2255和第二氮化钼层2256的厚度小于10nm，这样能够加快氮化钼层2254的蚀刻速率，提高产能；还可以令第一氮化钼层2255的厚度比第二氮化钼层2256的厚度小，这样氮化钼层2254沿着半导体层224到钝化层227的方向，其厚度逐渐增加，能够使氮化钼层2254的制程加快。
图8是一种阵列基板200的示意图，如图8所示，作为本申请的另一实施例，公开了一种阵列基板200，包括基底层223、半导体层224、金属层225和钝化层227，其中，半导体层224设置在基底层223上，金属层225设置在半导体层224上，且被蚀刻成源漏极226，金属层225的上表面含有第一氮化物或者第一氧化物；钝化层227设置在源漏极226上，钝化层227为与第一氮化物对应设置的第二氮化物结构，或与第一氧化物对应设置的第二氧化物结构。
在一实施例中，金属层225包括金属基层2251和氮化钼层2254，金属基层2251设置在半导体层224上，氮化钼层2254设置在金属基层2251上，且氮化钼层2254与钝化层227相贴合，钝化层227为氮化物结构。由于源漏极226由堆叠的金属基层2251和氮化钼层2254构成，对氮化钼层2254的厚度要求较低，不需要通入大量的氮气，能够节省氮气的成本；另外，氮化钼层2254还可以是氮化钛层或氮化钽层。这里的金属层225还可以包括金属基层2251和氧化钼层，金属基底2251设置在半导体层224上，氧化钼层设置在金属基层2251上，且氧化钼层与钝化层227相贴合，钝化层227为氧化物结构，这样的话氧化钼层同样可以是氧化钛层或氧化钽层。
图9是另一种阵列基板200的示意图，如图9所示，在一实施例中，金属层225为氮化钼层2254。整个金属层225，还有整个源漏极226就是单层的氮化钼结构，在这一过程中，氮化钼层2254是由沉积钼金属材料时通入氮气形成的，氮化钼层2254的制程不占用其它制程时间，能够最大程度地提高产能，而且由于整个金属层225都是氮化钼层2254，含氮量较高，对钝化层227的吸附效果好，对钝化层227钻蚀现象改善的效果比较好。
图10是另一种阵列基板200的示意图，如图10所示，在一实施例中，金属基层2251包括钼金属层2252和铝金属层2253，钼金属层2252设置在半导体层224上，铝金属层2253设置在钼金属层2252上，氮化钼层2254设置在铝金属层2253上。在金属基底2251中设置铝金属层2253能够使源漏极226的信号传输效果较好，因为铝的导电效果较好，而且铝金 属层2253的两侧还有钼金属层2252和氮化钼层2254，能够起到保护铝金属层2253的作用，方法铝金属层2253被腐蚀。
图11是另一种阵列基板200的示意图，如图11所示，在一实施例中，氮化钼层2254包括第一氮化钼层2255、第二氮化钼层2256和第三氮化钼层2257；第一氮化钼层2255设置在金属基层2251上，第二氮化钼层2256设置在第一氮化钼层2255上，第三氮化钼层2257设置在第二氮化钼层2256上，第一氮化钼层2255中氮的摩尔量小于第二氮化钼层2256中氮的摩尔量，第二氮化钼层2256中氮的摩尔量小于第三氮化钼层2257中氮的摩尔量。当氮化钼中氮的摩尔量较大时，氮化钼层2254与钝化层227的吸附效果比较好，能够使金属层225与钝化层227贴合更加紧密，对钝化层227钻蚀现象的改善效果更好，但是氮化钼层2254中氮的摩尔量较大会导致金属层225的蚀刻比较困难，进而导致金属层225的蚀刻制程时间增长，降低整个阵列基板200以及显示面板100的产能，而第一氮化钼层2255和第二氮化钼层2256对钝化层227的吸附效果较差，因此可以令第一氮化钼层2255和第二氮化钼层2256中氮的摩尔量低于第三氮化钼层2257中氮的摩尔量，这样的话第一氮化钼层2255和第二氮化钼层2256比较容易蚀刻，可以增加整个金属层225的蚀刻效率，提高阵列基板200的产能。
图12是一种显示面板100的示意图，如图12所示，作为本申请的另一实施例，公开了一种显示面板100，包括彩膜基板300、液晶层400和上述阵列基板200，其中，彩膜基板300和阵列基板200对向设置，液晶层400填充在彩膜基板300和阵列基板200之间。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如扭曲向列型(Twisted Nematic，TN)显示面板、平面转换型(In-Plane Switching，IPS)显示面板、垂直配向型(Vertical Alignment，VA)显示面板、多象限垂直配向型(Multi-Domain Vertical Alignment，MVA)显示面板，当然，也可以是其他类型的显示面板，如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，均可适用上述方案。
以上内容是结合具体的可选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种阵列基板的制造方法，包括步骤：
    形成基底层；
    在所述基底层上形成半导体层；
    在所述半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物；
    将所述金属层蚀刻成源漏极；以及
    在所述源漏极上形成钝化层，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
  2. 如权利要求1所述的一种阵列基板的制造方法，其中，所述金属层包括设置在所述半导体层上的金属基层，以及设置在所述金属基层上的第一氮化物层，所述第一氮化物层为氮化钼层；
    所述在半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物的步骤中，包括步骤：
    在所述半导体层上沉积钼金属材料；以及
    在所述钼金属材料上通入氮气，并同时将氮气通过电浆制程分解成氮原子，所述氮原子沉积到钼金属材料表面反应后形成氮化钼层。
  3. 如权利要求1所述的一种阵列基板的制造方法，其中，所述金属层包括设置在所述半导体层上的金属基层，以及设置在所述金属基层上的第一氮化物层，所述第一氮化物层为氮化钼层；
    所述在半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物的步骤中，包括步骤：
    在所述半导体层上沉积金属材料基层；
    在所述金属材料基层上沉积钼金属材料，并同时通入氮气，反应后形成氮化钼材料；以及
    蚀刻金属材料基层形成金属基层，蚀刻氮化钼材料形成氮化钼层。
  4. 如权利要求1所述的一种阵列基板的制造方法，其中，所述金属层包括设置在所述半导体层上的金属基层，以及设置在所述金属基层上的第一氧化物层，所述第一氧化物层为氧化钼层；
    所述在半导体层上形成金属层，所述金属层的上表面含有第一氮化物或者第一氧化物的步骤中，包括步骤：
    在所述半导体层上沉积金属材料基层；
    在所述金属材料基层上沉积钼金属材料，并同时通入氧气，反应后形成氧化钼材料；以及
    蚀刻金属材料基层形成金属基层，蚀刻氧化钼材料形成氧化钼层。
  5. 如权利要求3所述的一种阵列基板的制造方法，其中，所述在半导体层上沉积金属材料基层的步骤中，包括步骤：
    在半导体层上沉积钼金属材料；以及
    在钼金属材料上沉积铝金属材料以形成包括钼金属材料和铝金属材料的金属材料基层；
    所述蚀刻金属材料基层形成金属基层，蚀刻氮化钼材料形成氮化钼层的步骤中，包括步骤：
    蚀刻钼金属材料形成钼金属层，蚀刻铝金属材料形成铝金属层以得到包括钼金属层和铝金属层的金属基层。
  6. 如权利要求5所述的一种阵列基板的制造方法，其中，所述在半导体层上沉积钼金属材料的步骤中，还包括在半导体层上沉积钼金属材料的同时通入氮气的步骤。
  7. 如权利要求5所述的一种阵列基板的制造方法，其中，所述在钼金属材料上沉积铝金属材料以形成包括钼金属材料和铝金属材料的金属材料基层的步骤中，还包括在钼金属材料上沉积铝金属材料的同时通入氮气的步骤。
  8. 如权利要求3所述的一种阵列基板的制造方法，其中，所述在金属材料基层上沉积钼金属材料，并同时通入氮气，反应后形成氮化钼材料的步骤中，在金属材料基层上沉积钼金属材料，并同时以第一流量通入氮气，反应后形成第一氮化钼材料，以第二流量通入氮气，反应后形成第二氮化钼材料，以第三流量通入氮气，反应后形成第三氮化钼材料；
    所述蚀刻金属材料基层形成金属基层，蚀刻氮化钼材料形成氮化钼层的步骤中，蚀刻所述第一氮化钼材料形成第一氮化钼层，蚀刻所述第二氮化钼材料形成第二氮化钼层，蚀刻所述第三氮化钼材料形成第三氮化钼层；
    所述第三流量大于所述第一流量和所述第二流量。
  9. 如权利要求8所述的一种阵列基板的制造方法，其中，所述第一流量、所述第二流量和所述第三流量都在200ml/min到1000ml/min之间。
  10. 如权利要求9所述的一种阵列基板的制造方法，其中，所述第二流量小于所述第三流量且大于所述第一流量。
  11. 如权利要求8所述的一种阵列基板的制造方法，其中，所述第一氮化钼层的厚度、所述第二氮化钼层的厚度和所述第三氮化钼层的厚度相等。
  12. 如权利要求8所述的一种阵列基板的制造方法，其中，所述第三氮化钼层的厚度大于所述第一氮化钼层的厚度和所述第二氮化钼层的厚度。
  13. 如权利要求2所述的一种阵列基板的制造方法，其中，所述氮化钼层的厚度为10nm。
  14. 一种阵列基板，包括：
    基底层；
    半导体层，设置在所述基底层上；
    金属层，设置在所述半导体层上，被蚀刻为源漏极，所述金属层的上表面含有第一氮化物或者第一氧化物；以及
    钝化层，设置在所述源漏极上，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
  15. 如权利要求14所述的一种阵列基板，其中，所述金属层包括金属基层和氮化钼层，所述金属基层设置在所述半导体层上，所述氮化钼层设置在所述金属基层上，且所述氮化钼层与所述钝化层相贴合，所述钝化层为氮化物结构。
  16. 如权利要求15所述的一种阵列基板，其中，所述金属基层包括钼金属层和铝金属层，所述钼金属层设置在所述半导体层上，所述铝金属层设置在所述钼金属层上，所述氮化钼层设置在所述铝金属层上。
  17. 如权利要求15所述的一种阵列基板，其中，所述氮化钼层包括第一氮化钼层、第二氮化钼层和第三氮化钼层；
    所述第一氮化钼层设置在所述金属基层上，所述第二氮化钼层设置在所述第一氮化钼层上，所述第三氮化钼层设置在所述第二氮化钼层上，所述第一氮化钼层中氮的摩尔量小于所述第二氮化钼层中氮的摩尔量，所述第二氮化钼层中氮的摩尔量小于所述第三氮化钼层中氮的摩尔量。
  18. 如权利要求15所述的一种阵列基板，其中，所述基底层包括依次堆叠的衬底、栅极金属层和栅极绝缘层。
  19. 一种显示面板，包括对向设置的彩膜基板和阵列基板，以及设置在所述彩膜基板和所述阵列基板之间的液晶层，所述阵列基板包括：
    基底层；
    半导体层，设置在所述基底层上；
    金属层，设置在所述半导体层上，被蚀刻为源漏极，所述金属层的上表面含有第一氮化物或者第一氧化物；以及
    钝化层，设置在所述源漏极上，所述钝化层为与所述第一氮化物对应设置的第二氮化物结构，或与所述第一氧化物对应设置的第二氧化物结构。
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