WO2011124128A1 - 阵列基板、液晶面板及其制造方法 - Google Patents

阵列基板、液晶面板及其制造方法 Download PDF

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Publication number
WO2011124128A1
WO2011124128A1 PCT/CN2011/072468 CN2011072468W WO2011124128A1 WO 2011124128 A1 WO2011124128 A1 WO 2011124128A1 CN 2011072468 W CN2011072468 W CN 2011072468W WO 2011124128 A1 WO2011124128 A1 WO 2011124128A1
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Prior art keywords
substrate
internal stress
layer
array substrate
array
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PCT/CN2011/072468
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English (en)
French (fr)
Inventor
张培林
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北京京东方光电科技有限公司
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Priority to US13/381,016 priority Critical patent/US20120113368A1/en
Publication of WO2011124128A1 publication Critical patent/WO2011124128A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/54—Arrangements for reducing warping-twist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • the present invention relates to an array substrate, a liquid crystal panel, and a method of fabricating the same. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the display principle of a liquid crystal display is mainly to control the alignment of liquid crystal molecules by an electric field, and to change the transmittance by the refractive index anisotropy of the liquid crystal, thereby performing display.
  • the main structure of the liquid crystal display is composed of an array substrate, a color filter substrate, a polarizer, a backlight, and a liquid crystal.
  • the process of forming a box that is, the array substrate and the color filter substrate are formed into a box to form a liquid crystal panel.
  • the alignment film material is first coated on the substrate and passed through a corresponding orientation process, so that the liquid crystal molecules can be arranged on the substrate in a certain manner after the formation, and then the two substrates are shaped by a vacuum-to-box process. The spacer between the two substrates controls the thickness of the box.
  • the spacers can be divided into two categories according to their shape: Ball Spacer (abbreviated as BS) and Column Spacer (PS). Since the BS is spread on the array substrate or the color filter substrate by spraying, there is a problem that the BS dispersion is random and it is difficult to control the uniformity of the density, which adversely affects the display characteristics of the display. Therefore, more LCD monitors use PS.
  • BS Ball Spacer
  • PS Column Spacer
  • the PS is formed by a photolithography process during the preparation of the color filter substrate. Therefore, the position of the PS at each pixel can be controlled very accurately, so that a series of excellent display characteristics such as improved box thickness uniformity and improved contrast can be achieved.
  • the factors affecting such bending creep mainly include the elastic modulus, density, and size of the glass substrate itself, as in the formula (1).
  • 1 shape variable
  • C constant
  • g gravity acceleration
  • u Poisson's ratio
  • L substrate length
  • p density
  • t substrate thickness
  • E elastic modulus
  • the color filter substrate 1 undergoes bending creep due to its own gravity; similarly, as shown in Fig. 2, the array substrate 2 also undergoes bending creep.
  • the sealant 3 is coated on the array substrate 2; as shown in FIG. 4, after the array substrate 2 and the color filter substrate 1 complete the process of the box, the upper and lower substrates are both
  • the deformation of gravity occurs in the direction of gravity, and the control of the thickness of the box can only be achieved by the distribution of high-density PS, that is, the column spacer 12 is supported on each sub-pixel to maintain a constant cell thickness.
  • the liquid crystal limit (the allowable deviation range of the liquid crystal amount) is larger, and the liquid crystal panel is caused by the excessive liquid crystal amount, which causes the liquid crystal to accumulate under the action of gravity (the liquid crystal accumulation causes uneven light transmission) and The smaller the amount of liquid crystal is, the less likely it is that low temperature bubbles will occur.
  • the liquid crystal limit has a direct relationship with the deformation range of the spacer under external force. The larger the deformation range of the spacer, the larger the liquid crystal limit.
  • the prior art uses a corresponding reduction in the density of the spacer to increase the deformation range of the spacer. Summary of the invention
  • An embodiment of the present invention is directed to an array substrate, including: a substrate and a multilayer array pattern formed on the substrate, wherein the multilayer array pattern includes an internal stress layer, and the internal stress layer generates internal stress to The array substrate tends to be formed into an arched structure that is convexly deformed toward one side of the array pattern.
  • Another embodiment of the present invention is directed to a method of fabricating an array substrate, comprising: forming a multilayer array pattern including an internal stress layer on a substrate, the internal stress layer generating internal stress to tend to form the array substrate as An arched structure that is convexly deformed toward one side of the array pattern.
  • a further embodiment of the present invention is directed to a liquid crystal panel comprising an array substrate and a color filter substrate, and a liquid crystal disposed between the array substrate and the color filter substrate disposed behind the cassette, wherein the array substrate comprises: a substrate And a multilayer array pattern formed on the substrate, the array pattern including an internal stress layer, the internal stress layer generating an internal stress to form the array substrate into an arch that is convexly deformed toward one side of the array pattern Shape structure.
  • a further embodiment of the present invention relates to a method of fabricating a liquid crystal panel, comprising: providing a color filter substrate; providing an array substrate including a multi-layer array pattern, the array pattern having an internal stress layer, the internal stress layer generating internal stress To tend to form the array substrate to be convex toward one side of the array pattern Forming the deformed arch structure; aligning the color film substrate and the array substrate, and bonding the color film substrate behind the box and the array substrate with a sealant.
  • FIG. 1 is a schematic structural view of a prior art color film substrate
  • FIG. 2 is a schematic structural view of a prior art array substrate
  • FIG. 3 is a schematic structural view of an array substrate coated with a sealant in the prior art
  • FIG. 4 is a schematic structural view of a liquid crystal panel formed by pairing an array substrate and a color filter substrate into a box in the prior art
  • FIG. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a color filter substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of an array substrate coated with a sealant according to an embodiment of the present invention
  • FIG. 8 is a schematic structural view of a liquid crystal panel formed by pairing an array substrate and a color filter substrate into a box according to an embodiment of the present invention
  • 9-14 are schematic diagrams showing a preparation process of a method for fabricating an array substrate according to an embodiment of the present invention. detailed description
  • the inventors have found that it has at least the following problems: Since the liquid crystal panel is manufactured, the glass substrate may be affected to some extent by gravity. Deformation (for example, an arched structure that is convex toward one side), thereby requiring a high-density spacer to ensure uniformity of the thickness of the liquid crystal panel after the cartridge, and corresponding spacing on each sub-pixel a cushion, which makes the deformation of the spacer small, so it cannot be done.
  • the density of the spacers to increase the liquid crystal limit the uniformity of the thickness of the liquid crystal panel after the cartridge is ensured.
  • the embodiment of the invention provides an array substrate, a liquid crystal panel and a manufacturing method thereof, which offset the deformation of the liquid crystal panel after the box due to gravity or external force to a certain extent, and effectively controls the uniformity of the thickness of the box.
  • the first embodiment of the present invention provides an array substrate.
  • the array substrate 2 includes: a substrate 21 and a substrate formed thereon.
  • the array pattern 22 includes, in addition to the structural layers of the gate lines (gate electrodes), the active layer, the source and drain electrodes, and the functional elements such as the data lines and the pixel electrodes, an internal stress layer, which can generate internal stress.
  • the array substrate 2 is formed into an arched structure that is convexly deformed toward the side of the array pattern 22.
  • the gate lines and the data lines cross each other to form an array of pixel cells in which a pixel electrode for driving a voltage of the liquid crystal and a thin film transistor as a switching element are formed, the thin film transistor including a gate electrode connected to the gate line
  • the inner stress layer refers to a layer having internal stress therein. When the internal stress layer is formed on the substrate, the internal stress layer applies a force to the substrate due to internal stress, thereby tending to bend the substrate in a predetermined direction.
  • the array pattern 22 may include: a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, a pixel electrode layer, and the like formed on the substrate, and a protective film may be formed on the above structure.
  • the TFT obtained as the switching element can have various structures such as a bottom gate type and a top gate type, and the present invention is not limited to the structure of the switching element.
  • Deformed internal stress layer, or the gate insulating layer or passivation layer or protective film (if any) formed in the prior art can be used to realize the function of the internal stress layer, thereby generating internal stress and tending to make the substrate in a predetermined direction Deformation occurred.
  • the substrate thus obtained has a stronger resistance against deformation in a predetermined direction than a conventional substrate even if it is not actually bent and deformed in a predetermined direction, so that, for example, gravity or an external force can be canceled.
  • the gate insulating layer may include a high speed gate insulating layer and a low speed gate insulating layer, where In this case, the internal stress is preferably provided by a high-speed gate insulating layer.
  • the high-speed gate insulating layer and the low-speed gate insulating layer according to the embodiments of the present invention are divided according to the deposition or formation rate of the gate insulating layer, and the gate insulating layer formed at a higher rate is called a high-speed gate insulating layer, The gate insulating layer formed at a lower rate is referred to as a low speed gate insulating layer.
  • the embodiment of the present invention tends to cause the array substrate to have a side toward the side on which the array pattern is formed (the side facing the color filter substrate disposed thereon in the process of the cartridge) by improving the deposition conditions of the array pattern on the array substrate. Arched structure. With such an array substrate, in a further process of the box, a lateral internal stress is generated between the color filter substrate and the array substrate, which partially offsets the deformation caused by gravity or external force, and effectively controls the deformation. The uniformity of the box thickness.
  • the embodiment of the present invention provides a liquid crystal panel.
  • the liquid crystal panel includes an array substrate 2 and a color filter substrate 1, and an array substrate 2 and color placed behind the pair of boxes. Liquid crystal between the film substrates 1.
  • the color filter substrate 1 may be curved and deformed by gravity, for example, to have an arch structure convex toward one side.
  • the array substrate 2 includes a substrate 21 and respective layer array patterns 22 formed on the substrate 21.
  • the array pattern 22 includes an internal stress layer in addition to the structural layer forming the functional component, and the internal stress layer generates internal stress to tend to
  • the array substrate 2 is formed into an arched structure that is convexly deformed toward one side of the array pattern 22. In the case of the cartridge, the convex direction of the arch structure of the array substrate 2 and the convex direction of the downward arch structure due to the gravity of the color filter substrate 1 should be reversed.
  • a columnar spacer 12 is formed on the color filter substrate 1. After the cartridge is placed, the spacer 12 is distributed on the spacer 12 between the array substrate 2 and the color filter substrate 1. The spacer 12 is used to maintain the gap between the array substrate 2 and the color filter substrate 1 (that is, the thickness of the case). ).
  • the sealant 3 is coated on the array substrate 2. Since the array substrate 2 has an arch structure, as shown in FIG. 8, the two substrates 1, 2 interact with each other, and a lateral internal stress F is generated between them, so that the color filter substrate 1 is originally caused by gravity.
  • the downward curved deformation returns to the flat state under the action of the internal stress F, and the arch of the array substrate 2 also returns to the flat state under the action of the internal stress F. Therefore, the structure is eliminated to some extent. Due to the deformation caused by the action of gravity or external force, the density of the column spacer 12 can be lowered, so that the liquid crystal limit can be further increased.
  • the liquid crystal panel provided by the embodiment of the present invention generates a lateral internal stress between the color filter substrate and the array substrate by using an array substrate having a deformed structure with an internal stress layer. Both the color film substrate and the array substrate undergo deformation opposite to the original deformation direction, which can offset the deformation caused by gravity or external force to some extent, thereby effectively controlling the uniformity of the box thickness and reducing the density of the column spacers. Increase the liquid crystal limit.
  • a spherical spacer can also be used in this embodiment.
  • the degree of bending of the array substrate in a natural state can be adjusted by controlling the stress level of the internal stress on the array substrate according to actual conditions.
  • the color film substrate and the array substrate are opposite to each other, the color film substrate is not bent downward by gravity, and a lateral internal stress F is also generated on the color filter substrate and the array substrate, which is similar to the above. Effect.
  • the deformation of the control box thickness can be offset to some extent by the action of gravity or external force, and the third embodiment of the present invention
  • a method of fabricating an array substrate comprising:
  • An array pattern including an internal stress layer is formed on the substrate, and the internal stress layer generates internal stress to tend to form the array substrate into an arch structure that is convexly deformed toward one side of the array pattern.
  • the gate insulating layer that functions as the inner stress layer can be formed by controlling the process conditions of the gate insulating layer, thereby forming an array substrate of the arch structure.
  • the method for manufacturing the array substrate provided by the third embodiment of the present invention includes:
  • Step 1001 forming a pattern of a gate electrode layer on the substrate
  • Step 1002 by controlling a process condition of the gate insulating layer (for example, controlling a gas flow ratio of silane and ammonia gas), thereby forming a gate insulating layer having stress on the substrate on which the gate electrode layer is formed, and tending to make the The substrate is shaped into an arch structure by the action of the gate insulating layer;
  • a process condition of the gate insulating layer for example, controlling a gas flow ratio of silane and ammonia gas
  • Step 1003 sequentially forming respective layer patterns of the active layer, the source/drain electrode layer, the passivation layer, and the pixel electrode layer on the substrate on which the gate insulating layer is formed.
  • a gate electrode layer 221 is deposited on the substrate 2, and a gate electrode pattern is formed by a patterning process such as exposure, development, and etching, as shown in FIG.
  • a gate insulating layer 222 is deposited on the gate electrode layer 221 by depositing a high-speed gate insulating layer 2221 and a low-speed gate insulating layer 2222 in this order, as shown in FIG.
  • the substrate 2 is placed in a heating furnace body, the temperature in the furnace body is controlled at 330 degrees Celsius, and a high electric field is applied in the furnace body, and the Si3 ⁇ 4 is simultaneously introduced.
  • the NH 3 mixed gas is used as a reaction gas, and a glow discharge generates plasma to form a film on the substrate.
  • the film formation process is divided into two steps. First, the flow ratio of Si3 ⁇ 4 and NH3 mixed gas and the deposition rate are controlled to form a high-speed gate insulating layer at a high speed, and the thickness is about 3500 angstroms. Internal stress is generated in the high-speed gate insulating layer thus formed, so that the substrate is bent toward the side of the gate insulating film with respect to the direction of gravity.
  • the gas flow ratio of Si3 ⁇ 4 and NI3 ⁇ 4 is 7:30 (700:3000), and the internal stress is controlled at 300 MPa.
  • the flow ratio and deposition rate of Si3 ⁇ 4 and NH3 are also controlled to form a low-speed gate insulating layer with a thickness of about 500 angstroms.
  • the interface layer has good uniformity due to slow deposition, and the ion mobility is good when it is in contact with the active layer in the TFT channel (if only low-speed deposition is performed, it is better to consider the production efficiency, and the high speed is used. And two methods of deposition at low speed).
  • the gate insulating layer etching process is performed, only the low-speed insulating layer in the TFT channel is left, and the low-speed insulating layer at other positions is etched away. Further, an active layer 223 is deposited on the substrate 2 on which the gate insulating layer 222 is deposited.
  • a source/drain electrode layer 224 is deposited on the substrate on which the active layer 223 is deposited, as shown in FIG. 11, and further, the above layers are subjected to patterning processes such as exposure, development, and etching to form respective layer patterns, such as Figure 12 shows.
  • a passivation layer 225 is deposited on the substrate on which the active drain electrode layer 224 is deposited, and a patterning process such as exposure, development, and etching is completed, as shown in FIG.
  • a pixel electrode layer 226 is deposited on the substrate on which the passivation layer 225 is deposited, and a patterning process such as exposure, development, and etching is completed to form a pixel electrode pattern, as shown in FIG.
  • the internal stress layer is not formed by a separate process, but the process conditions of the gate insulating layer are controlled by improving the fabrication process of the array substrate, that is, adjusting the gas flow ratio of silane and ammonia gas or other processes.
  • a gate insulating layer having internal stress is generated, which tends to cause the array substrate to have an arched structure which is convex toward the side of the gate insulating layer to some extent. Therefore, in a further process of the box, a lateral internal stress is generated between the color filter substrate and the array substrate, and the deformation of the thickness of the control box can be controlled to some extent by the deformation caused by gravity or external force. .
  • the TFT formed is exemplified as the bottom gate type, but may be formed on the array substrate.
  • a top gate type TFT is used as the switching element.
  • the gate insulating layer can also be formed as an internal stress layer, thereby obtaining the array substrate of the embodiment of the present invention.
  • the fourth embodiment is basically the same as the manufacturing method of the array substrate of the third embodiment.
  • the difference is that the function of the internal stress layer is realized by the passivation layer, that is, the blunt internal stress is generated by changing the fabrication process of the passivation layer.
  • the layer is formed into an arch shape by the passivation layer.
  • the method for manufacturing the array substrate provided in the fourth embodiment of the present invention includes:
  • Step 2001 forming a pattern of a gate electrode layer, a gate insulating layer, an active layer, and a source/drain electrode layer on the substrate;
  • Step 2002 controlling a gas flow ratio of silane and ammonia gas, thereby forming a passivation layer having internal stress on the substrate on which the source/drain electrode layer is formed, and forming the substrate into an arch shape under the action of the passivation layer ;
  • Step 2003 forming a pixel electrode layer on the substrate on which the passivation layer is formed.
  • a gate electrode layer 221 is deposited on the substrate 2, and a gate electrode pattern is formed by a patterning process such as exposure, development, and etching, as shown in FIG.
  • a gate insulating layer 222 is deposited on the gate electrode layer 221 by depositing a high-speed gate insulating layer 2221 and a low-speed gate insulating layer 2222 in this order, as shown in FIG.
  • an active layer 223 is deposited on the substrate on which the gate insulating layer 222 is deposited.
  • a source/drain electrode layer 224 is deposited on the substrate on which the active layer 223 is deposited, as shown in FIG.
  • a passivation layer 225 is deposited on the substrate on which the source/drain electrode layer 224 is deposited, and a patterning process such as exposure, development, and etching is completed, as shown in FIG. Specifically, the substrate was placed in a heating furnace body, the furnace body temperature control at 330 degrees Celsius, and applying a high electric field in the furnace body, while introducing a mixed gas of NH 3 and Si3 ⁇ 4 as a reactive gas, into the glow discharge plasma is generated on a substrate membrane.
  • internal stress is generated in the passivation layer 225 by controlling the process conditions of the passivation layer 225, that is, adjusting the gas flow ratio of Si3 ⁇ 4 and N3 ⁇ 4, so that the substrate is bent toward the side where the passivation layer 225 is formed.
  • preferably Si3 ⁇ 4 and NH 3 gas flow rate ratio is 7: 30 (700: 3000), thereby capable of generating internal stresses 300Mpa, so that the substrate to produce convex arcuate configuration forming a passivation layer side.
  • the function of the internal stress layer is realized by the gate insulating layer.
  • passivation layer 225 can be completed by only one step of the patterning process, the process of realizing the function of the internal stress layer by the passivation layer 225 is simpler. Further, passivation is deposited A pixel electrode layer 226 is deposited on the substrate of the layer 225, and a pixel electrode pattern is formed by a patterning process such as exposure, development, and etching, as shown in FIG.
  • the stress layer is not formed by a separate process step, but the function of the internal stress layer is realized by the passivation layer by improving the fabrication process of the array substrate, and by controlling the process conditions of the passivation layer, For example, adjusting the process conditions such as the gas flow ratio of silane and ammonia gas, internal stress is generated in the passivation layer, which tends to cause the array substrate to have a certain degree of arch structure bent toward the side where the passivation layer is formed. Therefore, in the further process of the box, a lateral internal stress is generated between the color filter substrate and the array substrate, and the deformation due to the action of gravity or external force can be offset to some extent, and the uniformity of the thickness of the control box can be controlled.
  • the function of the inner stress layer is realized by the gate insulating layer. Since the passivation layer can be completed by only one step of the patterning process, the process of realizing the function of the inner stress layer by the passivation layer in this embodiment is simpler.
  • the TFT formed is exemplified as the bottom gate type, but a top gate type TFT may be formed as a switching element on the array substrate, for example.
  • the passivation layer can also be formed as an internal stress layer, thereby obtaining the array substrate of the embodiment of the present invention.
  • a fifth embodiment of the present invention provides a method of manufacturing a liquid crystal panel, the method comprising: Step 3001, forming a color filter substrate.
  • the color filter substrate can cause bending deformation under the action of gravity.
  • Step 3002 forming an array substrate having an arch structure that tends to be convexly deformed toward one side of the array pattern.
  • the specific manufacturing method of the array substrate is the same as that of the third embodiment and the fourth embodiment, and details are not described herein again.
  • Step 3003 Aligning the color filter substrate and the array substrate, and sealing the color filter substrate and the array substrate behind the box with a sealant, and generating internal stress between the array substrate and the color filter substrate to form a liquid crystal panel.
  • the column substrate having the smaller density is formed in the color film substrate preparation process.
  • the insufficient portion is supplemented by the internal stress between the array substrate of the arch structure and the color filter substrate to ensure the uniformity of the thickness of the case.
  • the two substrates interact, The transverse internal stress is generated between them, so that the downward bending deformation of the color filter substrate is restored to the flat state by the internal stress F due to the gravity action, and the array substrate is also changed by the internal stress F.
  • the bottom is restored to a straight state. Therefore, the structure can be deformed to some extent by the action of gravity or external force, so that the density of the column spacer can be lowered, so that the liquid crystal limit can be further increased.
  • the process conditions of the pattern formation of the array substrate for example, adjusting the process conditions such as the gas flow ratio of silane and ammonia gas, internal stress is generated, which tends to cause the array substrate to have a certain degree. Deformation (for example, toward the side of the array pattern) to form an arched structure and reduce its density and distribution by redesigning the spacer. However, it is within the scope of the invention at this time that the array substrate is not physically deformed. In the process of the box, a lateral internal stress is generated between the color filter substrate and the array substrate, which can offset the deformation caused by gravity or external force to some extent, and control the uniformity of the thickness of the box. Further, since the density of the column spacers is reduced, the liquid crystal limit can be increased, and the liquid crystal panel is less likely to cause liquid crystal accumulation due to gravity due to excessive liquid crystal amount and low temperature bubbles due to too small liquid crystal amount. .

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Description

阵列基板、 液晶面板及其制造方法 技术领域
本发明涉及一种阵列基板、 液晶面板及其制造方法。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor-Liquid Crystal Display, 简 称 TFT-LCD )因其体积小、 功耗低和无辐射等特点， 占据了当前平板显示器 市场的主导地位。
液晶显示器的显示原理主要是利用电场对液晶分子进行取向控制， 并通 过液晶的折射率各向异性使透过率发生变化， 从而进行显示。 液晶显示器的 主要结构是由阵列基板、彩膜基板、偏光片、 背光源和液晶等几大部分组成。
在液晶显示器的制造工艺中， 最为重要的是成盒工艺， 即将阵列基板和 彩膜基板成盒形成液晶面板。 成盒过程中， 首先在基板上涂敷取向膜材料并 通过相应的取向工艺， 使得成盒后液晶分子能够在基板上以一定的方式进行 排列，然后经真空对盒过程将两基板定型， 由两基板之间的隔垫物控制盒厚。
目前， 隔垫物才艮据形状可以划分为两大类： 球状隔垫物 （Ball Spacer, 简称 BS )和柱状隔垫物（Post Spacer, 简称 PS )。 由于 BS通过喷洒方式散 布在阵列基板或者彩膜基板上， 所以存在 BS散布随机性大且难控制密度均 一性的问题， 这会对显示器的显示特性产生不良影响。 因此， 更多的液晶显 示器釆用了 PS。
PS是在彩膜基板的制备过程中， 通过光刻工艺形成的。 因此， 可以非常 精确地控制 PS在每个像素的位置， 从而可以达到提高盒厚均一性、 改善对 比度等一系列优异的显示特性。
通常， 由于重力作用或其他外力， 玻璃基板会发生弯曲蠕变， 如图 1所 示， 影响这种弯曲蠕变的因素主要有玻璃基板自身的弹性模量、 密度以及尺 寸大小， 如公式（1 )所示， 其中： 1: 形变量； C: 常量； g: 重力加速度； u: 泊松比； L: 基板长 度； p: 密度； t: 基板厚度； E: 弹性模量。
如图 1所示， 彩膜基板 1在制备和转运过程中， 由于本身的重力作用， 会发生弯曲蠕变； 同样地， 如图 2所示， 阵列基板 2也会发生弯曲蠕变。 如 图 3所示， 在对盒工艺中， 在阵列基板 2上涂覆封框胶 3; 如图 4所示， 阵 列基板 2与彩膜基板 1完成对盒工艺后， 上下两个基板均由于重力作用发生 沿重力方向的形变， 导致盒厚的控制只能通过高密度的 PS 的分布来实现， 即每一个亚像素上均有柱状隔垫物 12支撑以保持恒定盒厚。
在液晶面板对盒之后， 液晶极限 (液晶量的允许的偏差范围)越大， 则液 晶面板发生因液晶量过多而导致重力作用下的液晶累积 (液晶累积导致光透 过不均匀）和因液晶量过少发生低温气泡的可能性就越小。而液晶极限与隔垫 物在外力作用下的形变范围有直接的关系， 隔垫物的形变范围越大， 液晶极 限就越大。现有技术釆用相应减少隔垫物的密度， 以增加隔垫物的形变范围。 发明内容
本发明的一个实施例涉及一种阵列基板， 包括： 基板以及形成在所述基 板上的多层阵列图形， 其中， 所述多层阵列图形包括内应力层， 所述内应力 层产生内应力以趋于使所述阵列基板形成为向所述阵列图形一侧凸起形变的 拱形结构。
本发明的另一个实施例涉及一种阵列基板的制造方法， 包括： 在基板上 形成包括内应力层的多层阵列图形， 所述内应力层产生内应力以趋于使所述 阵列基板形成为向所述阵列图形一侧凸起形变的拱形结构。
本发明的再一个实施例涉及一种液晶面板， 包括阵列基板和彩膜基板， 以及置于对盒后的所述阵列基板和彩膜基板之间的液晶， 其中， 所述阵列基 板包括： 基板以及形成在所述基板上的多层阵列图形， 所述阵列图形包括内 应力层， 所述内应力层产生内应力以使所述阵列基板形成为向所述阵列图形 一侧凸起形变的拱形结构。
本发明的又一个实施例涉及一种液晶面板的制造方法， 包括： 提供彩膜 基板； 提供包括多层阵列图形的阵列基板， 所述阵列图形具有内应力层， 所 述内应力层产生内应力以趋于使所述阵列基板形成为向所述阵列图形一侧凸 起形变的拱形结构； 将所述彩膜基板和所述阵列基板对盒， 并用封框胶将对 盒后的所述彩膜基板和所述阵列基板结合。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附 图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创 造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为现有技术彩膜基板的结构示意图；
图 2为现有技术阵列基板的结构示意图；
图 3为现有技术涂敷有封框胶的阵列基板的结构示意图；
图 4为现有技术将阵列基板和彩膜基板对盒形成的液晶面板的结构示意 图；
图 5为本发明实施例阵列基板的结构示意图；
图 6为本发明实施例彩膜基板的结构示意图；
图 7为本发明实施例涂敷有封框胶的阵列基板的结构示意图； 图 8为本发明实施例将阵列基板和彩膜基板对盒形成的液晶面板的结构 示意图；
图 9-14为本发明实施例阵列基板制造方法的制备过程示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创 造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
在如图 4所示的情形， 如果要实现通过减少隔垫物的密度来提高液晶极 限时， 发明人发现其至少存在以下问题： 由于液晶面板制作工艺中， 玻璃基 板会因重力作用发生一定程度的形变（例如变为朝一侧凸起的拱形结构）， 由 此需要高密度的隔垫物来保证液晶面板对盒之后的盒厚均一性， 且在每个亚 像素上均需对应有隔垫物， 这就使得隔垫物的形变范围很小， 因此无法做到 通过减少隔垫物的密度以提高液晶极限的同时， 保证液晶面板对盒之后的盒 厚均一性。
本发明实施例提供一种阵列基板、 液晶面板及其制造方法， 在一定程度 上抵消了对盒后的液晶面板由于重力作用或者外力作用发生的形变， 有效地 控制了盒厚的均一性。
实施例一
为了在对盒时， 克服液晶面板由于重力作用或者外力作用发生的形变， 本发明实施例一提供一种阵列基板， 如图 5所示， 该阵列基板 2包括： 基板 21以及形成在所述基板 21上的各层阵列图形 22。阵列图形 22除了形成栅线 (栅电极）、有源层、源漏电极及数据线、像素电极等功能元件的结构层之外， 还包括内应力层， 该内应力层可产生内应力以趋于使该阵列基板 2形成为向 阵列图形 22—侧凸起形变的拱形结构。在阵列基板上，栅线和数据线彼此交 叉形成像素单元的阵列， 在像素单元中形成用于驱动液晶的电压的像素电极 以及作为开关元件的薄膜晶体管， 薄膜晶体管包括与栅线连接的栅电极、 与 数据线相连的源漏电极之一和与像素电极相连的源漏电极中另一个， 这些图 形结构通过堆叠的薄膜进行构图得到且通过绝缘层彼此间隔开， 所得到的多 层图形结构即为阵列图形。 本发明实施例一所述之内应力层， 是指其中具有 内应力的层。 当内应力层形成到基板上后， 该内应力层由于内部的应力而对 基板施加力， 从而趋于使基板朝预定方向弯曲。
上述阵列图形 22可以包括： 在所述基板上形成的栅电极层、 栅绝缘层、 有源层、 源漏电极层、 钝化层和像素电极层等， 还可以在上述结构之上形成 保护膜。 所得到作为开关元件的 TFT可以为底栅型、 顶栅型等多种结构， 本 发明不限于开关元件的结构。 形变的内应力层， 或者可以利用现有工艺中形成的栅绝缘层或钝化层或保护 膜（如果有的话） 实现内应力层的功能， 从而产生内应力并趋于使基板向预 定方向发生形变。而且， 由此得到的基板即便没有向预定方向实际弯曲变形， 也具有比传统的基板更强的抵抗与预定方向相反变形的能力， 从而可以抵消 例如重力作用或者外力作用。
进一步地， 所述栅绝缘层可以包括高速栅绝缘层和低速栅绝缘层， 在此 情况下， 所述内应力优选以高速栅绝缘层提供。 本发明实施例所述的高速栅 极绝缘层和低速栅极绝缘层是根据栅极绝缘层的沉积或形成速率划分， 以较 高速率形成的栅极绝缘层称为高速栅极绝缘层， 以较低速率形成的栅极绝缘 层称为低速栅绝缘层。
本发明实施例通过改善阵列基板上阵列图案的沉积条件， 趋于使得阵列 基板具有向形成有阵列图案的一侧 (对盒工艺中面对设置在其上的彩膜基板 的一侧） 凸出的拱形结构。 釆用这样的阵列基板， 在进一步的对盒工艺中， 在彩膜基板和阵列基板之间产生横向的内应力作用， 一定程度上抵消了由于 重力作用或者外力作用发生的形变， 有效地控制了盒厚的均一性。
实施例二
本发明实施例提供一种液晶面板， 如图 5、 图 6、 图 7和图 8所示， 该液 晶面板包括阵列基板 2和彩膜基板 1 , 以及置于对盒后的阵列基板 2和彩膜 基板 1之间的液晶。 彩膜基板 1在重力作用下可能弯曲形变， 例如变为具有 向一侧凸起的拱形结构。 阵列基板 2包括基板 21以及形成在所述基板 21上 的各层阵列图形 22, 阵列图形 22除形成功能部件的结构层之外， 还包括内 应力层，该内应力层产生内应力以趋于使该阵列基板 2形成为向阵列图形 22 一侧凸起形变的拱形结构。 对盒时， 阵列基板 2的拱形结构的凸起方向与彩 膜基板 1由于重力导致向下的拱形结构的凸起方向应该相反。
进一步地， 彩膜基板 1上形成有柱状隔垫物 12。 对盒之后， 隔垫物 12 分布于阵列基板 2和彩膜基板 1之间的隔垫物 12, 隔垫物 12用于保持阵列 基板 2和彩膜基板 1之间的间隙 （也即盒厚）。
在本实施例的技术方案中， 阵列基板 2在与彩膜基板 1对盒时， 如图 7 所示， 在阵列基板 2上涂覆封框胶 3。 由于阵列基板 2为拱形结构， 如图 8 所示， 对盒后两块基板 1、 2相互作用， 在它们之间产生横向的内应力 F的 作用， 使得彩膜基板 1原本由于重力作用造成向下的弯曲形变在内应力 F的 作用下向上恢复为平直状态， 阵列基板 2拱形也在内应力 F作用下恢复为平 直状态， 因此， 该结构在一定程度上 ·ί氏消了由于重力作用或外力作用造成的 形变， 因此可以降低柱状隔垫物 12的密度， 从而能够进一步增加液晶极限。
本发明实施例提供的液晶面板通过釆用具有内应力层的换形结构的阵列 基板， 在对盒工艺中， 彩膜基板和阵列基板之间产生横向的内应力作用， 使 彩膜基板和阵列基板都发生与原形变方向相反的形变， 一定程度上可以抵消 由于重力作用或者外力作用发生的形变， 从而有效控制盒厚的均一性， 同时 可以减少柱状隔垫物的密度， 增大液晶极限。 在该实施例中也可以使用球状 间隔物。
另外， 可以根据实际情况通过控制阵列基板上的内应力的应力水平来调 整阵列基板自然状态下的弯曲程度。 实际上， 当彩膜基板和阵列基板对盒时 彩膜基板未因重力而向下弯曲时， 此时同样会在彩膜基板和阵列基板上产生 横向的内应力 F, 达到与以上所述类似的效果。 这种情况同样适用于本发明 的其他实施例。
实施例三
为了在对盒工艺中，在彩膜基板和阵列基板之间产生横向的内应力作用， 一定程度上可以抵消由于重力作用或者外力作用发生的形变， 控制盒厚的均 一性， 本发明实施例三提供一种阵列基板的制造方法， 该方法包括：
在基板上形成包括内应力层的阵列图形， 内应力层产生内应力以趋于使 将阵列基板形成为向阵列图形一侧凸起形变的拱形结构。
将阵列基板形成为向阵列图形一侧凸起形变的拱形结构有多种实现方 式。 优选地， 可以通过控制栅绝缘层的工艺条件， 形成实现内应力层的功能 的栅绝缘层， 从而形成拱形结构的阵列基板。 具体地， 本发明实施例三的提 供的阵列基板的制造方法包括：
步骤 1001、 在基板上形成栅电极层的图形；
步骤 1002、 通过控制栅绝缘层的工艺条件（例如控制硅烷和氨气的气体 流量比 ),从而在形成了所述栅电极层的基板上形成具有应力的栅绝缘层，并 趋于使所述基板在栅绝缘层的作用下形变为拱形结构；
步骤 1003、 在形成有栅绝缘层的基板上依次形成有源层、 源漏电极层、 钝化层和像素电极层的各层图形。
具体地， 在一个示例中， 首先， 在基板 2上沉积栅电极层 221 , 通过曝 光、 显影和刻蚀等构图工艺形成栅电极图形， 如图 9所示。 接下来， 在栅电 极层 221上沉积栅绝缘层 222, 沉积方式可以为依次沉积高速栅绝缘层 2221 和低速栅绝缘层 2222, 如图 10所示。 具体地， 将基板 2放置在加热炉体内， 炉体内温度控制在 330摄氏度， 并在炉体内施加高电场， 同时通入 Si¾与 NH3混合气体作为反应气体， 辉光放电生成等离子体以在基板上成膜。 成膜 工艺分两步，首先控制 Si¾和 NH3混合气体流量比以及沉积速度进行高速沉 积形成高速栅绝缘层，厚度大概在 3500埃。如此形成的高速栅绝缘层中产生 内应力， 使得基板发生相对于重力方向朝栅绝缘膜一侧凸出的弯曲。 在本实 施例中， 优选 Si¾和 NI¾的气体流量比为 7: 30 ( 700:3000), 内应力控制在 300MPa。 实验证明， 釆用如上所述的沉积工艺条件能使阵列基板趋于向上变 形成为拱形的结构， 在后续的对盒工艺中， 可在彩膜基板和阵列基板之间产 生横向的内应力作用， 更加有效地抵消由于重力作用或者外力作用发生的形 变， 使对盒后的阵列基板和彩膜基板都趋于平直状态， 从而确保了盒厚的均 一性。 此时内应力层的功能由高速栅绝缘层实现， 同时为了保证 TFT的特性 需要在已经沉积的高速栅绝缘层上再沉积一层界面层 (低速栅绝缘层）。 同样 控制 Si¾和 NH3的流量比和沉积速度形成低速栅绝缘层，厚度在 500埃左右。 该界面层由于沉积緩慢而具有良好的均一性， 在 TFT 沟道内与有源层接触 时， 离子的迁移率好（如果只进行低速沉积会更好， 只是考虑到生产效率， 釆用了分高速和低速两次沉积的方法)。在进行栅绝缘层刻蚀工艺的时候只保 留了 TFT沟道内的低速绝缘层， 其他位置的低速绝缘层会被刻蚀掉。 进一步 地， 在沉积有栅绝缘层 222的基板 2上沉积有源层 223。 进一步地， 在沉积 有有源层 223的基板上沉积源漏电极层 224, 如图 11所示， 并进一步地将上 述各层完成曝光、 显影和刻蚀等构图工艺， 形成各层图形， 如图 12所示。 进 一步地， 在沉积有源漏电极层 224的基板上沉积钝化层 225, 完成曝光、 显 影和刻蚀等构图工艺，如图 13所示。 进一步地，在沉积了钝化层 225的基板 上沉积像素电极层 226, 完成曝光、 显影和刻蚀等构图工艺， 形成像素电极 图形， 如图 14所示。
本发明实施例的技术方案中， 内应力层不是通过单独的工艺形成， 而是 通过改善阵列基板的制作工艺， 控制栅绝缘层的工艺条件， 即调整硅烷和氨 气的气体流量比或其他工艺条件， 产生具有内应力的栅绝缘层， 趋于使得阵 列基板发生一定程度上向栅绝缘层一侧凸起的拱形结构。 从而， 在进一步的 对盒工艺中， 在彩膜基板和阵列基板之间产生横向的内应力作用， 一定程度 上可以 ·ί氏消由于重力作用或者外力作用发生的形变， 控制盒厚的均一性。
在上述描述中以形成的 TFT为底栅型为例，但是也可以在阵列基板上形 成例如顶栅型 TFT作为开关元件。 在形成顶栅型 TFT时， 同样可以将栅绝 缘层形成为内应力层， 从而得到本发明实施例的阵列基板。
实施例四
本实施例四与实施例三阵列基板的制造方法基本相同， 它们的区别之处 在于， 由钝化层实现内应力层的功能， 即通过改变钝化层的制作工艺， 产生 具有内应力的钝化层， 使基板在钝化层的作用下形变为拱形。 具体地， 本发 明实施例四提供的阵列基板的制造方法包括：
步骤 2001、 在基板上形成栅电极层、 栅绝缘层、 有源层和源漏电极层的 图形；
步骤 2002、控制硅烷和氨气的气体流量比， 从而在形成所述源漏电极层 的基板上形成具有内应力的钝化层， 并使所述基板在钝化层的作用下形变为 拱形；
步骤 2003、 在形成有所述钝化层的基板上形成像素电极层。
具体地， 在一个示例中， 首先， 在基板 2上沉积栅电极层 221 , 通过曝 光、 显影和刻蚀等构图工艺形成栅电极图形， 如图 9所示。 接下来， 在栅电 极层 221上沉积栅绝缘层 222,沉积方式为依次沉积高速栅绝缘层 2221和低 速栅绝缘层 2222, 如图 10所示。 进一步地， 在沉积了栅绝缘层 222的基板 上沉积有源层 223。 进一步地， 在沉积有有源层 223的基板上沉积源漏电极 层 224, 如图 11所示， 并进一步地将上述各层完成曝光、 显影和刻蚀等构图 工艺， 形成各层图形， 如图 12 所示。 进一步地， 在沉积了源漏电极层 224 的基板上沉积钝化层 225,完成曝光、显影和刻蚀等构图工艺，如图 13所示。 具体地， 将基板放置在加热炉体内， 炉体内温度控制在 330摄氏度， 并在炉 体内施加高电场， 同时通入 Si¾与 NH3混合气体作为反应气体，辉光放电生 成等离子体在基板上成膜。 在该步骤中， 通过控制钝化层 225的工艺条件， 即调整 Si¾和 N¾的气体流量比等工艺条件， 在钝化层 225中产生内应力， 使得基板向形成钝化层 225的一侧弯曲。 在本实施例中， 优选 Si¾和 NH3 的气体流量比为 7: 30 ( 700:3000), 从而能产生 300Mpa的内应力， 使得基 板产生向形成钝化层一侧凸起的拱形结构。 区别于上一实施例由栅绝缘层来 实现内应力层的功能， 由于钝化层 225只需一步构图工艺即可完成， 因此由 钝化层 225实现内应力层的功能的工艺更加简单。 进一步地， 在沉积了钝化 层 225的基板上沉积像素电极层 226, 通过曝光、 显影和刻蚀等构图工艺形 成像素电极图形， 如图 14所示。
本发明实施例的技术方案中， 应力层不是通过单独的工艺步骤形成， 而 是通过改善阵列基板的制作工艺， 由钝化层来实现内应力层的功能， 通过控 制钝化层的工艺条件， 例如调整硅烷和氨气的气体流量比等工艺条件， 在钝 化层中产生内应力， 趋于使得阵列基板发生一定程度的向形成钝化层的一侧 弯曲的拱形结构。 从而， 在进一步的对盒工艺中， 在彩膜基板和阵列基板之 间产生横向的内应力作用， 一定程度上可以抵消由于重力作用或者外力作用 发生的形变， 控制盒厚的均一性。 区别于上一实施例由栅绝缘层来实现内应 力层的功能， 由于钝化层只需一步构图工艺即可完成， 因此本实施例由钝化 层实现内应力层的功能的工艺更加简单。
在上述描述中以形成的 TFT为底栅型为例，但是也可以在阵列基板上形 成例如顶栅型 TFT作为开关元件。 在形成顶栅型 TFT时， 同样可以将钝化 层形成为内应力层， 从而得到本发明实施例的阵列基板。
实施例五
本发明实施例五提供了一种液晶面板的制造方法， 该方法包括： 步骤 3001、 形成彩膜基板。 该彩膜基板在重力作用下可造成弯曲形变。 步骤 3002、形成具有趋于向阵列图形一侧凸起形变的拱形结构的阵列基 板。
阵列基板的具体制作方法与实施例三和实施例四所述的方法相同， 在此 不再赘述。
步骤 3003、 将彩膜基板和阵列基板对盒， 并用封框胶将对盒后的所述彩 膜基板和所述阵列基板封闭， 阵列基板与彩膜基板之间产生内应力， 形成液 晶面板。
由于在将彩膜基板置于阵列基板之上以进行对盒时， 釆用了步骤 3002 所述形成的拱形结构的阵列基板， 在彩膜基板制备过程中， 只需形成密度较 小的柱状隔垫物， 以克服重力或其他作用力对对盒后的基板所造成的形变。 不足的部分由拱形结构的阵列基板与该彩膜基板之间的内应力补充， 以保证 盒厚的均一性。
用封框胶将对盒后的彩膜基板和阵列基板封闭时， 两块基板相互作用， 在它们之间产生横向的内应力的作用， 使得彩膜基板原本由于重力作用造成 向下的弯曲形变在内应力 F的作用下向上恢复为平直状态， 阵列基板换形也 在内应力 F作用下恢复为平直状态。 因此， 该结构在一定程度上 ·ί氐消了由于 重力作用或外力作用造成的形变， 因此可以降低柱状隔垫物的密度， 从而能 够进一步增加液晶极限。
本发明实施例通过改善阵列基板的制作工艺， 通过控制阵列基板图形形 成的工艺条件， 例如调整硅烷和氨气的气体流量比等工艺条件， 来产生内应 力， 趋于使得阵列基板发生一定程度的形变（例如向着阵列图形一侧） 以形 成拱形结构， 并通过重新设计隔垫物， 降低其密度和分布。 但是， 此时阵列 基板即便没有发生实际的变形， 也在本发明的范围之内。 在对盒工艺中， 在 彩膜基板和阵列基板之间产生横向的内应力作用， 一定程度上可以抵消由于 重力作用或者外力作用发生的形变， 控制盒厚的均一性。 进一步地， 由于减 少了柱状隔垫物的密度， 即可增大液晶极限， 降低了液晶面板发生因液晶量 过多而导致重力作用下的液晶累积和因液晶量过少发生低温气泡的可能性。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以权利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板； 以及
形成在所述基板上的多层阵列图形，
其中， 所述多层阵列图形包括内应力层， 所述内应力层产生内应力以趋 于使所述阵列基板形成为向所述阵列图形一侧凸起形变的拱形结构。
2、根据权利要求 1所述的阵列基板， 其中， 所述内应力层为所述多层阵 列图形中的栅绝缘层。
3、根据权利要求 2所述的阵列基板， 其中， 所述栅绝缘层包括堆叠的高 速栅绝缘层和低速栅绝缘层， 所述高速栅绝缘层产生所述内应力。
4、根据权利要求 1所述的阵列基板， 其中， 所述内应力层为所述多层阵 列图形中的钝化层。
5、 一种阵列基板的制造方法， 包括：
在基板上形成包括内应力层的多层阵列图形， 所述内应力层产生内应力 以趋于使所述阵列基板形成为向所述阵列图形一侧凸起形变的拱形结构。
6、根据权利要求 5所述的方法， 其中， 所述内应力层为所述多层阵列图 形中的栅绝缘层。
7、根据权利要求 6所述的方法， 其中，控制形成所述栅绝缘层时的硅烷 和氨气的气体流量比， 从而使形成的所述栅绝缘层中产生内应力。
8、根据权利要求 6所述的方法， 其中， 所述栅绝缘层包括： 堆叠的高速 栅绝缘层和低速栅绝缘层， 所述高速栅绝缘层产生所述内应力。
9、根据权利要求 8所述的方法， 其中，控制形成所述高速栅绝缘层时的 硅烷和氨气的气体流量比，从而使在形成的所述高速栅绝缘层中产生内应力。
10、 根据权利要求 5所述的方法， 其中， 所述内应力层为所述多层阵列 图形中的钝化层， 在形成有所述钝化层的基板上形成像素电极层。
11、根据权利要求 10所述的方法， 其中， 通过控制形成所述钝化层的硅 烷和氨气的气体流量比， 从而在所述钝化层中产生内应力。
12、 一种液晶面板， 包括：
阵列基板； 彩膜基板， 以及
置于对盒后的所述阵列基板和彩膜基板之间的液晶，
其中，所述阵列基板包括：基板以及形成在所述基板上的多层阵列图形， 所述阵列图形包括内应力层， 所述内应力层产生内应力以趋于使所述阵列基 板形成为向所述阵列图形一侧凸起形变的拱形结构。
13、根据权利要求 12所述的液晶面板，还包括分布于所述阵列基板和所 述彩膜基板之间的隔垫物， 所述隔垫物用于保持所述阵列基板和所述彩膜基 板之间的间隙。
14、 一种液晶面板的制造方法， 包括：
提供彩膜基板；
提供包括多层阵列图形的阵列基板， 所述阵列图形具有内应力层， 所述 内应力层产生内应力以趋于使所述阵列基板形成为向所述阵列图形一侧凸起 形变的拱形结构；
将所述彩膜基板和所述阵列基板实现对盒， 并用封框胶将对盒后的所述 彩膜基板和所述阵列基板结合。
15、根据权利要求 14所述的方法， 其中， 隔垫物分布于所述阵列基板和 所述彩膜基板之间， 所述隔垫物用于保持所述阵列基板和所述彩膜基板之间 的间隙。
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Publication number Priority date Publication date Assignee Title
CN104282235A (zh) * 2014-11-03 2015-01-14 京东方科技集团股份有限公司 曲面显示面板、装置及其制造方法
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CN110634389B (zh) * 2019-08-30 2021-10-12 昆山工研院新型平板显示技术中心有限公司 一种基板的制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167125A (en) * 1980-05-28 1981-12-22 Hitachi Ltd Liquid crystal display element and its manufacture
JPH02159766A (ja) * 1988-12-13 1990-06-19 Fujitsu Ltd 薄膜トランジスタ
JPH02211672A (ja) * 1989-02-10 1990-08-22 Fujitsu Ltd 薄膜トランジスタ
JPH1096905A (ja) * 1996-09-20 1998-04-14 Seiko Epson Corp 液晶素子およびその製造方法
JP2002328362A (ja) * 2001-04-27 2002-11-15 Casio Comput Co Ltd 液晶表示素子
CN1953189A (zh) * 2005-10-21 2007-04-25 三星电子株式会社 薄膜晶体管、薄膜晶体管基板及其制造方法
CN1989622A (zh) * 2004-07-06 2007-06-27 应用材料股份有限公司 具有控制应力的氮化硅膜
CN101132011A (zh) * 2006-07-20 2008-02-27 三星电子株式会社 阵列基板及其制造方法和具有阵列基板的显示器件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11153788A (ja) * 1997-11-20 1999-06-08 Victor Co Of Japan Ltd 液晶駆動用基板及びその製造方法
KR100982494B1 (ko) * 2003-10-21 2010-09-16 엘지디스플레이 주식회사 액정표시장치의 제조방법
JP2009003049A (ja) * 2007-06-20 2009-01-08 Mitsubishi Electric Corp 液晶表示装置およびその製造方法
JP5251087B2 (ja) * 2007-11-29 2013-07-31 カシオ計算機株式会社 液晶表示パネルの製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167125A (en) * 1980-05-28 1981-12-22 Hitachi Ltd Liquid crystal display element and its manufacture
JPH02159766A (ja) * 1988-12-13 1990-06-19 Fujitsu Ltd 薄膜トランジスタ
JPH02211672A (ja) * 1989-02-10 1990-08-22 Fujitsu Ltd 薄膜トランジスタ
JPH1096905A (ja) * 1996-09-20 1998-04-14 Seiko Epson Corp 液晶素子およびその製造方法
JP2002328362A (ja) * 2001-04-27 2002-11-15 Casio Comput Co Ltd 液晶表示素子
CN1989622A (zh) * 2004-07-06 2007-06-27 应用材料股份有限公司 具有控制应力的氮化硅膜
CN1953189A (zh) * 2005-10-21 2007-04-25 三星电子株式会社 薄膜晶体管、薄膜晶体管基板及其制造方法
CN101132011A (zh) * 2006-07-20 2008-02-27 三星电子株式会社 阵列基板及其制造方法和具有阵列基板的显示器件

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