WO2020175209A1 - スパイク生成回路、情報処理回路、電力変換回路、検出器および電子回路 - Google Patents

スパイク生成回路、情報処理回路、電力変換回路、検出器および電子回路 Download PDF

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Publication number
WO2020175209A1
WO2020175209A1 PCT/JP2020/006045 JP2020006045W WO2020175209A1 WO 2020175209 A1 WO2020175209 A1 WO 2020175209A1 JP 2020006045 W JP2020006045 W JP 2020006045W WO 2020175209 A1 WO2020175209 A1 WO 2020175209A1
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WIPO (PCT)
Prior art keywords
circuit
input
node
spike
signal
Prior art date
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Ceased
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PCT/JP2020/006045
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English (en)
French (fr)
Japanese (ja)
Inventor
赳彬 矢嶋
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Japan Science and Technology Agency
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Japan Science and Technology Agency
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Application filed by Japan Science and Technology Agency filed Critical Japan Science and Technology Agency
Priority to JP2021501979A priority Critical patent/JP7620982B2/ja
Priority to CN202080017237.4A priority patent/CN113508386B/zh
Publication of WO2020175209A1 publication Critical patent/WO2020175209A1/ja
Priority to US17/408,599 priority patent/US11444605B2/en
Anticipated expiration legal-status Critical
Priority to US17/880,821 priority patent/US11671077B2/en
Priority to US17/881,034 priority patent/US11757433B2/en
Priority to US18/227,473 priority patent/US12476623B2/en
Priority to JP2025000099A priority patent/JP7778427B2/ja
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/48—Analogue computers for specific processes, systems or devices, e.g. simulators
    • G06G7/60—Analogue computers for specific processes, systems or devices, e.g. simulators for living beings, e.g. their nervous systems ; for problems in the medical field
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

Definitions

  • the present invention relates to a spike generation circuit, an information processing circuit, a power conversion circuit, a detector and an electronic circuit.
  • a spike generation circuit such as a Nitron circuit used in a neural network is known (for example, Patent Documents 1, 2, and 6).
  • a circuit that connects a plurality of inverters in multiple stages is known (for example, Patent Documents 3 to 5).
  • Patent Document 1 Japanese Patent Laid-Open No. 2001 _ 1 486 1 9
  • Patent Document 2 JP 2006-243877 A
  • Patent Document 3 Japanese Patent Laid-Open No. 201-44265
  • Patent Document 4 Japanese Patent Laid-Open No. 8-242 1 48
  • Patent Document 5 JP 2000 _ 1 0652 1
  • Patent Document 6 International Publication No. 201 8/1 00790
  • the present invention has been made in view of the above problems, and an object thereof is to reduce power consumption.
  • the present invention is an intermediate node connected to an input terminal for inputting an input signal. ⁇ 02020/175209 2 ( ⁇ 171?2020/006045
  • the output node is connected to one node, and the 1st/ 1st/ 3rd inverter connected between the first power supply and the second power supply and the first power supply and the second power supply are connected between the first power supply and the second power supply.
  • a switch connected in series with an inverter, a first inverting circuit that outputs an inverted signal of the signal from the first node to the control terminal of the switch, and a signal that delays from the first node
  • the spike generation circuit includes: a delay circuit that outputs the signal to the input node of the 1st IV! 3 inverter and outputs the output spike signal to the output terminal.
  • the first inverting circuit outputs an inversion signal of the signal of the first node to a control terminal of the switch and a second node
  • the delay circuit includes the first inverting circuit described above, A second inverting circuit that outputs an inverted signal of the signal of the second node to the input node of the first 101/1/3 inverter and the third node to which the output terminal is connected, and be able to.
  • the first inverting circuit is connected between the first node and the second node in one or more stages, and an input node is connected to the first node and the second node is connected.
  • the output node is connected to an odd number of 2 in 1 and 1 in 3 inverters, and the second inverting circuit is arranged in one or more stages between the second node and the third node. It may be configured to include an odd number of 3101 ⁇ /1/3 inverters connected to each other, an input node connected to the second node, and an output node connected to the third node.
  • the second inverting circuit may be configured to include three or more thirty-first to ten-thirty-three impedances.
  • one end is connected to the fourth node between the three or more third 0 ⁇ 3 inverters, and the other end is connected to the first reference potential terminal. It can be configured to include a capacitive element.
  • the capacitance value of the first capacitive element is set to be equal to or more than the gate capacitance value of one Mita in the three or more 3rd 1 ⁇ /1/3 inverters. You can
  • one end is connected to the first node and the other end is connected to the second reference voltage.
  • ⁇ 02020/175209 3 ((171?2020/006045
  • It may be configured to include a second capacitive element connected to the terminal.
  • the present invention relates to a first 101//1 03 inverter in which an output node is connected to a first node and is connected between a first power supply and a second power supply, the first power supply and the first power supply.
  • the first switch connected in series with the (1) 1 ⁇ /1 (3) inverter between the power supply and the power supply, and the inverted signal of the signal of the 1st node described above is output to the control terminal of the 1st switch.
  • a delay circuit for delaying the signal of the first node and outputting the delayed signal to the input node of the first 101/103 inverter and outputting the output spike signal to the output terminal.
  • a middle node connected to the input terminal to which the input signal is input, and a spike generation circuit.
  • the 1st 101 ⁇ /103 inverter outputs a first level which is one of a high level and a mouth level, and a second level which is the other of the high level and the mouth level.
  • the first switch is turned on when the first level is input to the control terminal, and is turned off when the second level is input to the control terminal, and the inverting circuit is configured such that the first node changes from the first level to the first level.
  • a first inverting circuit that outputs the first level to the control terminal of the first switch at the second level, and a second level to the control terminal of the first switch when the output of the delay circuit reaches the second level.
  • a second inverting circuit that outputs, wherein the intermediate node may be provided in the second inverting circuit.
  • the second inverting circuit has a control terminal connected to the output of the delay circuit, and when the delay circuit outputs the second level, the intermediate node and the initial level of the input signal are supplied. It is possible to adopt a configuration including a second switch for connecting to a power supply that is used.
  • an input node may be connected to the intermediate node, and an output node may be provided with a 20th IV!0 3 inverter connected to a control terminal of the first switch.
  • a control terminal is connected to the first node, and when the first node is at the second level, the control terminal of the first switch and the first level are Includes a third switch to connect to the power supply ⁇ 02020/175209 4 (:171?2020/006045
  • the first level is supplied to the first node. It can be configured to include a fourth switch connected to the power supply.
  • the voltage of the second power supply is higher than the voltage of the first power supply
  • the switch is a 1 ⁇ 1 channel transistor, and is connected between the first node and the first power supply.
  • it may be a channel transistor and connected between the first node and the second power supply.
  • the output circuit includes a voltage conversion circuit that outputs a signal obtained by converting the voltage of the input signal to the intermediate node, and the delay circuit includes the output spike signal when the voltage of the input signal is within a predetermined range.
  • the delay circuit includes the output spike signal when the voltage of the input signal is within a predetermined range.
  • a time constant circuit that lengthens the time constant of the rise of the input signal and outputs the time constant to the intermediate node
  • the delay circuit is configured such that after the input signal is input, the time constant of the time constant circuit is
  • the output spike signal may be output after a delay time related to.
  • an input circuit that changes the voltage of the intermediate node according to the amount of change of the input signal with respect to time is provided, and the delay circuit has an amount of change of the input signal with respect to time within a predetermined range.
  • the output spike signal may be output.
  • the spike generation circuit processes the input signal and outputs the processed signal to the spike generation circuit so that the spike generation circuit outputs the output spike signal. ⁇ 02020/175209 5 ((171?2020/006045
  • a spike processing circuit that processes the output spike signal output from the spike generation circuit, and an information processing circuit.
  • the present invention is a power conversion circuit comprising: a switch element; and a control circuit including the spike generation circuit, the control circuit controlling ON/OFF of the switch element.
  • the present invention provides a time constant circuit that lengthens the time constant of rising of an input signal that is input to an input terminal and outputs the time constant from an output node to an intermediate node, and the voltage at the intermediate node corresponds to a threshold voltage.
  • An output circuit that outputs a single output spike signal to an output terminal and resets the voltage of the intermediate node; and the output circuit has a time constant of the time constant circuit after the input signal is input. It is a spike generation circuit that outputs the output spike signal after an associated delay time.
  • the time constant circuit includes a capacitor having one end connected to the output node, the other end connected to a first reference potential terminal, and the _ end connected to the input terminal and the other end.
  • a constant current element or a constant current circuit that is connected to the output node and that generates a constant current corresponding to a voltage difference between both ends of the output node can be provided.
  • one of a current input terminal and a current output terminal is connected to the input terminal, and the other terminal of the current input terminal and the current output terminal is the output terminal.
  • the first transistor connected to the node and one of the current input terminal and the current output terminal is connected to the input terminal via the first diode connected in the forward direction, and the current input terminal and the current
  • the other terminal of the output terminal is connected to the second reference potential terminal via the second diode connected in the reverse direction
  • the control transistor is connected to the control terminal of the first transistor.
  • the constant current element is a diode connected in a reverse direction or a transistor having a control terminal to which a voltage is applied so as to be in an ON state.
  • ⁇ 02020/175209 6 boxes (: 171?2020/006045
  • the present invention provides a voltage conversion circuit that outputs a signal obtained by converting a voltage of an input signal input to an input terminal to an intermediate node, and an output terminal that responds to the voltage of the intermediate node becoming a threshold voltage.
  • An output circuit that outputs a single output spike signal and resets the voltage of the intermediate node, the output circuit generating spike output that does not output the output spike signal when the voltage of the input signal is within a predetermined range. Circuit.
  • the voltage conversion circuit includes a capacitor having one end connected to the intermediate node and the other end connected to a first reference potential terminal.
  • the product of the resistance value of the resistor and the capacitance value of the capacitor may be greater than the width of the above-described cascade signal.
  • the present invention increases the voltage of the intermediate node by an amount corresponding to the input cascade signal when the input spike signal is input to the input terminal, and/or the voltage of the intermediate node when the input spike signal is input to the input terminal.
  • Input circuit that lowers the output signal by an amount corresponding to the input spike signal, and outputs a single output spike signal to the output terminal in response to the threshold voltage of the intermediate node and outputs the voltage of the intermediate node.
  • an output circuit for resetting the input spike signal the output circuit outputs the output spike signal when the frequency of input of the input spike signal falls within a predetermined range, and when the input spike signal is not input to the input terminal.
  • the voltage of the intermediate node is a spike generation circuit that gradually decreases or increases over a period longer than the width of the input spike signal.
  • the voltage of the intermediate node is increased by an amount corresponding to the input spike signal, and/or the plurality of inputs.
  • the voltage at the intermediate node corresponds to the height of the incoming spike signal.
  • An input circuit for lowering the voltage of the intermediate node an output circuit for outputting a single output spike signal to the output terminal in response to the threshold voltage of the intermediate node, and resetting the voltage of the intermediate node,
  • the output circuit outputs the output spike signal during a period in which the input spike signal is input to at least two input terminals of the plurality of input terminals, and outputs the output spike signal to the input terminals.
  • the spike generation circuit gradually lowers or increases the voltage of the intermediate node over a period longer than the width of the input spike signal when the pike signal is not input.
  • the present invention relates to an input circuit that changes the voltage of an intermediate node according to the amount of change of an input signal input to the input terminal with respect to time, and to correspond to that the voltage of the intermediate node becomes a threshold voltage.
  • An output circuit that outputs a single output spike signal and resets the voltage of the intermediate node, wherein the output circuit outputs the output spike signal when the change amount of the input signal with respect to time falls within a predetermined range.
  • the present invention provides a first switch that conducts and blocks a first path through which a first current flows between a first end and a second end, and a disconnection period in which the first switch blocks the first path.
  • the second path in which the second current complementary to the first current flows between the third end complementary to the first end and the fourth end complementary to the second end.
  • a second switch for connecting and disconnecting, and the cut-off period is a period for which the first switch cuts off the first path and the second switch cuts off the second path,
  • the detection circuit is configured to detect the first voltage based on the first voltage and a second voltage on an end side of the second switch which is complementary to one of the third end and the fourth end. It can be configured to detect the direction of current flow.
  • the parasitic capacitance on the one end side of the first path is CO, where the second voltage is V ref, the absolute value of the first current is
  • the present invention is a power conversion circuit comprising: the above detector; and a switch element for controlling ON and OFF based on a detection result of the detector.
  • the present invention provides the above detector, and when the detector detects a direction in which the first current flows is a first direction, connects the second end to a first power supply terminal and disconnects from the second power supply terminal. And the fourth end is connected to the second power supply terminal and cut off from the first power supply terminal, and the detector detects a direction in which the first current flows as a second direction opposite to the first direction. And a switch circuit that connects the second end to the second power supply terminal and shuts off from the first power supply terminal and connects the fourth end to the first power supply terminal and shuts off from the second power supply terminal. , A power conversion circuit including.
  • the present invention outputs a high-level or mouth-level single-shot spike signal to the output terminal when the internal state that depends on the history of the input current input to the input terminal reaches the threshold value, and sets the internal state to the initial value.
  • the level of the first output terminal is held at one of the above levels.
  • a plurality of memory circuits wherein the one or more memory circuits are the first memory in which the first output terminal is connected to the input terminal of the first spike generating circuit of the one or more spike generating circuits. It is an electronic circuit including a circuit.
  • the one or more memory circuits may include a second memory circuit in which a first input terminal is connected to an output terminal of the first spike generation circuit.
  • the one or more memory circuits hold the level of the first output terminal at a high level and output the level of the second output terminal when a high level is input to the first input terminal.
  • -Level and the high level is input to the second input terminal, the level of the first output terminal is maintained at the mouth level and ⁇ 02020/175209 9 boxes (:171?2020/006045
  • the one or more spike generation circuits may include a second spike generation circuit in which an input terminal is connected to a second output terminal of the first memory circuit.
  • the one or more memory circuits include a second memory circuit in which the first input terminal is connected to an output terminal of the first spike generating circuit, and the one or more spike signal generating circuits. May include a third spike generation circuit having an output terminal connected to a second input terminal of the second memory circuit.
  • the output terminal of the first spike generation circuit may be connected to the second input terminal of the first memory circuit.
  • one end is connected to the first output terminal of the first memory circuit, the other end is connected to the input terminal of the first spike generation circuit, and the voltage difference between the one end and the other end is
  • the spike generation circuit may be configured to output a spike signal when the integrated value of the current input to the input terminal reaches a threshold value.
  • a high level or a mouth level is input to one or more input terminals, and a high level or a mouth uniquely determined by the input of the one or more input terminals to one or more output terminals.
  • Output level the first output terminal of the first memory circuit is connected to at least one of the one or more input terminals, and the input terminal of the first spike generation circuit is the one or more output terminals.
  • the configuration may include a combinational circuit connected to at least one of the terminals.
  • FIG. 1 (3) and FIG. 1 ( ⁇ ) are circuit diagrams of the spike generation circuit according to the first embodiment and the first modification thereof. ⁇ 02020/175209 10 boxes (: 171?2020/006045
  • FIG. 2 Fig. 2 ( 3 ) shows the circuit diagram of the spike generation circuit according to the second modification of the first embodiment, and Fig. 2 ( ⁇ ) shows the voltage of the node 1 ⁇ !
  • FIG. 3 Fig. 3 ( 3 ) is a circuit diagram of the spike generation circuit according to the modification 3 of the embodiment 1, and Fig. 3 (is the node 1 ⁇ ! and 1 ⁇ ! 1 and the output terminal It is a figure which shows a voltage.
  • FIG. 4 Fig. 4 ( 3 ) is a circuit diagram of the spike generation circuit according to the modification 4 of the first embodiment, and Fig. 4 ( ⁇ ) shows the voltage of the node 1 ⁇ !
  • FIG. 5 Fig. 5 ( 3 ) is a circuit diagram of the spike generation circuit according to the modified example 5 of the first embodiment, and Fig. 5 (is the node 1 ⁇ ! It is a figure which shows a voltage.
  • FIG. 6 ( 3 ) is a circuit diagram of the spike generation circuit according to the second embodiment
  • FIG. 6 ( ⁇ ) is a diagram showing each voltage with respect to time.
  • FIG. 7 ( 3 ) is a circuit diagram of the spike generation circuit according to the first modification of the second embodiment
  • FIG. 7 (13) is a diagram showing each voltage with respect to time.
  • FIG. 8 is a circuit diagram of a spike generation circuit according to a third embodiment.
  • FIG. 9(a) and FIG. 9( ⁇ ) are diagrams showing the voltage of each node with respect to time in Example 3.
  • FIG. 10 (3) and FIG. 10 ( ⁇ ) are diagrams showing the input voltage, the output voltage, and the current consumption with respect to time in the third embodiment.
  • FIG. 11 Fig. 11 (3) to Fig. 11 ( ⁇ ) are diagrams showing the output voltage with respect to time in Example 3.
  • FIG. 12 (a) to FIG. 12 () are diagrams showing the output voltage with respect to time in Example 3.
  • Fig. 13 Fig. 13 ( 3 ) to Fig. 13 ( ⁇ 0 are diagrams for explaining the function of the capacitor 02.
  • FIG. 14 (3) and FIG. 14 ( ⁇ ) are circuit diagrams of the spike generation circuit according to the third embodiment.
  • Fig. 15 Fig. 15(a) and Fig. 15( ⁇ ) show spike generation in Example 3. ⁇ 02020/175209 11 ⁇ (: 17 2020/006045
  • Figs. 16 (3) to 16 ( ⁇ ) are graphs showing the output voltage with respect to the time of the spike generation circuit in the third embodiment.
  • FIG. 17 is a circuit diagram of a spike generation circuit according to a first modification of the third embodiment.
  • FIG. 18 is a diagram showing the voltage of each node with respect to time in the first modification of the third embodiment.
  • Fig. 19 is a circuit diagram showing another example of the spike generation circuit according to the first modification of the third embodiment, and Fig. 19 (b) and Fig. 19 ( ⁇ ) are respectively implemented.
  • 14 is a circuit diagram of a spike generation circuit according to Modifications 2 and 3 of Example 3.
  • FIG. 20(a) and FIG. 20( ⁇ ) are diagrams showing the voltage of each node with respect to time in the third modification of the third embodiment.
  • FIG. 21 is a circuit diagram of a spike generation circuit according to Modification 4 of Embodiment 3.
  • FIG. 22(a) and FIG. 22( ⁇ ) are circuit diagrams of the spike generation circuit according to the fourth embodiment.
  • FIG. 23(a) and FIG. 23( ⁇ ) are circuit diagrams of the spike generation circuit according to the fourth embodiment.
  • FIG. 24 is a diagram showing the voltage of each terminal and node with respect to time in the fourth embodiment.
  • FIG. 25 is a diagram showing each voltage with respect to time in the case where the knife 91 is not provided.
  • FIG. 26 ( 3 ) and FIG. 26 ( ⁇ ) are circuit diagrams of the sub-king circuit according to the first modification of the fourth embodiment.
  • Fig. 27 Fig. 27 ( 3 ) and Fig. 27 ( ⁇ ) are circuit diagrams of the sub-cycle generation circuit according to the second modification of the fourth embodiment.
  • FIG. 28(a) and FIG. 28( ⁇ ) are circuit diagrams of a sub-cycle generation circuit according to a third modification of the fourth embodiment.
  • Fig. 29 Fig. 29(a) and Fig. 29( ⁇ ) show the sub-space according to the modification 4 of the embodiment 4. ⁇ 02020/175209 12 boxes (:171?2020/006045
  • FIG. 30(a) and FIG. 30( ⁇ ) are circuit diagrams of the sub-cycle generation circuit according to the fifth modification of the fourth embodiment.
  • FIG. 31 is a circuit diagram of a spike generation circuit according to a fifth embodiment.
  • FIG. 32 (a) to FIG. 32 (6) are diagrams showing the voltage and the output voltage of the node 1 ⁇ 11 with respect to time in the fifth embodiment.
  • FIG. 33 (a) to FIG. 33 () are diagrams showing the voltage and the output voltage of the node 1 ⁇ 11 with respect to time in the fifth embodiment.
  • FIG. 34 (a) and FIG. 34 ( ⁇ ) are diagrams showing the frequency and period with respect to the input voltage in Example 5, respectively.
  • FIG. 35 is a circuit diagram of a spike generation circuit according to a first modification of the fifth embodiment.
  • FIG. 36 ( 3 ) is a circuit diagram of the spike generation circuit according to the second modification of the fifth embodiment
  • FIG. 36 ( ⁇ ) is a timing chart of the second modification of the fifth embodiment.
  • FIG. 37 is a circuit diagram of a spike generation circuit according to a third modification of the fifth embodiment.
  • FIG. 38 (a) and FIG. 38 ( ⁇ ) are diagrams showing the voltage and the output voltage of the node 1 with respect to time in the modification 3 of the fifth embodiment.
  • FIG. 39 is a circuit diagram of a spike generation circuit according to a fourth modification of the fifth embodiment.
  • FIG. 40( a) and FIG. 40( ⁇ ) are diagrams showing the voltage and the output voltage of the node 1 with respect to time in the modified example 4 of the fifth embodiment.
  • FIG. 41 is a circuit diagram of a spike generation circuit according to a fifth modification of the fifth embodiment.
  • FIG. 42 ( 3 ) is a circuit diagram of the spike generation circuit according to the modified example 6 of the fifth embodiment
  • FIG. 42 ( ⁇ ) is a timing chart of the modified example 6 of the fifth embodiment.
  • Figs. 43 ( 3 ) to 43 ( ⁇ ) are block diagrams of the information processing circuit according to the sixth embodiment. ⁇ 02020/175209 13 ⁇ (: 171?2020/006045
  • FIG. 44 is a block diagram of a power conversion circuit according to a seventh embodiment.
  • FIG. 45 is a diagram for explaining the operation of the determination circuit in the seventh embodiment.
  • Figs. 46(a) to 46( ⁇ ) are diagrams showing symbols of the spike generation circuit in the seventh embodiment.
  • Figs. 47(a) to 47( ⁇ ) are diagrams showing the operation of the flip-flop circuit in the seventh embodiment.
  • FIG. 48 is a circuit diagram of a determination circuit according to the seventh embodiment.
  • FIG. 49 is a diagram showing the voltage of each node of the determination circuit with respect to time in the seventh embodiment.
  • FIG. 50 is a circuit diagram showing a rectifier circuit according to a seventh embodiment.
  • Fig. 51 Fig. 51 ( 3 ) to Fig. 51 ( ⁇ ) are schematic diagrams of the step-down circuit in the seventh embodiment.
  • FIG. 52 is a circuit diagram of a step-down circuit according to the seventh embodiment.
  • FIG. 53 is a diagram showing the voltage of each node of the step-down circuit with respect to time in the seventh embodiment.
  • FIG. 54 is a diagram showing the voltages of the nodes 8 and 8 with respect to time in the seventh embodiment.
  • FIGS. 55(a) to 55( ⁇ ) are schematic diagrams of the synchronous rectification circuit in the seventh embodiment.
  • FIG. 56 is a circuit diagram of a synchronous rectification circuit according to the seventh embodiment.
  • FIG. 57 is a diagram showing the voltage of each node of the synchronous rectification circuit with respect to time in the seventh embodiment.
  • FIG. 58 is a diagram showing a charging voltage of the capacitor by the synchronous rectification circuit with respect to time in the seventh embodiment.
  • FIG. 59 is a diagram showing a generated current and a voltage of a capacitor with respect to time in Example 7.
  • FIG. 60 (a) and FIG. 60 ( ⁇ ) are circuit diagrams of the spike generation circuits according to the eighth embodiment and its first modification, respectively. ⁇ 02020/175209 14 ⁇ (: 17 2020 /006045
  • Fig. 61 Fig. 61 (a) and Fig. 61 (6) are circuit diagrams of spike generation circuits according to modified examples 18 and 1 of Example 8 used for simulation, respectively.
  • FIG. 62(a) to FIG. 62() are diagrams showing voltage with respect to time showing simulation results of the modified example 18 of the eighth example.
  • Figs. 63(a) to 63() are diagrams showing voltage with respect to time, showing the simulation result of the first modification of the eighth embodiment.
  • Figs. 64(a) to 64( ⁇ ) are circuit diagrams of spike generation circuits according to Modifications 2 to 4 of the eighth embodiment, respectively.
  • FIG. 65 is a circuit diagram of a spike generation circuit according to a fifth modification of the eighth embodiment.
  • FIG. 66 (a) and FIG. 66 () are circuit diagrams of spike generation circuits according to Modifications 5 and 5 of Embodiment 8 which are used for simulation.
  • FIG. 67(a) and FIG. 67( ⁇ ) are diagrams showing the voltage with respect to time showing the simulation result of the modified example 5 of the eighth example.
  • 67( ⁇ ) and 67( ⁇ 0) are diagrams showing the voltage with respect to time showing the simulation result of the modified example 5 of the eighth example.
  • Figs. 68(a) to 68( ⁇ ) are circuit diagrams of spike generation circuits according to Modifications 6 to 8 of Example 8, respectively.
  • Figs. 69(a) to 69( ⁇ ) are circuit diagrams of spike generation circuits according to Modifications 9 to 11 of Example 8, respectively.
  • FIG. 70(a) and FIG. 70( ⁇ ) are diagrams showing respective voltages with respect to time in Modification 9 of Example 8.
  • FIG. 71 is a block diagram of a detector according to a ninth embodiment.
  • Fig. 72 Fig. 72 ( 3 ) and Fig. 72 ( ⁇ ) are diagrams showing each voltage with respect to time of the detector according to the ninth embodiment.
  • FIG. 73 is a block diagram of a detector according to a first modification of the ninth embodiment. ⁇ 02020/175209 15 ((171?2020/006045
  • FIG. 74 is a diagram showing each voltage with respect to time of the detector according to the first modification of the ninth embodiment.
  • FIG. 75 is a circuit diagram of a synchronous rectification circuit according to a third modification of the ninth embodiment.
  • FIG. 76 is a diagram showing the voltage of each node of the synchronous rectifier circuit with respect to time in the synchronous rectifier circuit of the third modification of the ninth embodiment.
  • Fig. 77 Fig. 77 ( 3 ) and Fig. 77 ( ⁇ ) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10.
  • Fig.78 (3) is a diagram showing the spike generation circuit
  • Fig.78(b) and Fig.78( ⁇ ) are diagrams showing the internal state 3 and the output voltage V ⁇ 1:1 with respect to time, respectively. ..
  • Fig. 79 Fig. 79(a) and Fig. 79( ⁇ ) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10.
  • FIG. 80(3) and FIG. 80( ⁇ ) are diagrams showing an example of an electronic circuit according to Example 10.
  • FIG. 81(a) and FIG. 81( ⁇ ) are block diagrams of electronic circuits according to Modifications 1 and 2 of Example 10, respectively.
  • Fig. 82 Fig. 82 ( 3 ) and Fig. 82 ( ⁇ ) are block diagrams of an electronic circuit according to Modification 3 of Example 10, and Fig. 82 ( ⁇ ) is a modification 3 of Example 10. It is a figure which shows the symbol of the said electronic circuit.
  • FIG. 83(a) and FIG. 83( ⁇ ) are diagrams showing an example of the spike signal input to the electronic circuit in the modified example 3 of the embodiment 10.
  • FIG. 84(a) and FIG. 84( ⁇ ) are diagrams showing a circuit example in which the spike signal output from the electronic circuit in Modification 3 of Example 10 is used.
  • FIG. 85 (a) and FIG. 85 ( ⁇ ) are circuit diagrams showing an example in which the spike signal output from the electronic circuit in Modification 3 of Example 10 is used, FIG. 85 (b) and FIG. 85. ( ⁇ is a diagram showing the magnitude of the electromagnetic wave output from the antenna.
  • FIG. 86 is a schematic diagram of a network circuit according to Modification 4 of Example 10. is there.
  • FIGS. 1(a) and 1(b) are circuit diagrams of a subsystem generation circuit according to the first embodiment and its first modification.
  • the spike generation circuit 130 of the first embodiment includes an inverter 12, FET (Field Effect Transistor) 14 and an inverting circuit 16 and a delay circuit 17.
  • the inverter 12 is a CM 0 S (Complementary Meta I Oxide Semiconductor) inverter, and is provided with N F E T 13 a (N channel F E T) and P F E T 13 b (P channel F E T ).
  • the source of N F E T 1 3 a is connected to the ground line 26, and the drain is a node.
  • N 1 It is connected to N 1 and its gate is connected to node N 0.
  • the source of P FET 1 3 b is connected to the power supply line 28, the drain thereof is connected to the node N 1, and the gate thereof is connected to the node N 0.
  • Nodes N 0 and N 1 are the ingress node and the egress node of the inverter 12 respectively.
  • F ET 1 4 is P F ET and is connected in series with P F E T 1 3 b between the node N 1 and the power line 28.
  • the source of F E T 1 4 is connected to the power line 28 via P F E T 13 3 b, and the drain is connected to the node N 1.
  • the inverting circuit 16 inverts the level of the node N 1 and outputs it to the gate of F ET 1 4.
  • the delay circuit 17 delays the level of the node N 1 and outputs it to the node N 3.
  • the node N 3 is connected to the input node N 0 of the inverter 12 and the output terminal T ⁇ u t.
  • the inverting circuit 1 6 and F ET 1 4 form a positive feedback loop 1 5.
  • the input terminal T in is connected to the intermediate node N i in the positive feedback loop 15.
  • F ET 1 4 is NF ET, and between the node N 1 and the ground line 26. ⁇ 02020/175209 17 ⁇ (: 171?2020/006045
  • FEJ ]33 is connected in series.
  • the source of FEJ] 4 is Connected to ground line 26, and the drain is connected to node 1 ⁇ 1 1.
  • the other configuration is the same as that of the first embodiment, and the description is omitted.
  • the second modification of the first embodiment is an example in which the intermediate node in the first embodiment is a node 1 ⁇ 11.
  • FIG. 2 ( 3 ) is a circuit diagram of the spike generation circuit according to the second modification of the first embodiment
  • FIG. 2 ( ⁇ ) is a diagram showing the voltage of the node 1 ⁇ ! 1 and the output terminal 1:1. ..
  • the input terminal n is connected to nodes 1 ⁇ 1 1 and 1 ⁇ 1.
  • the input signal is input to node 1.
  • Other configurations are the same as those in the first embodiment, and the description is omitted.
  • the voltage of the node 1 ⁇ ! 1 increases uniformly with time.
  • the output of the inverting circuit 16 is at high level
  • the output of the delay circuit 17 is at mouth level
  • the output terminal Voltage of 1 keeps mouth level.
  • Inverter 1 2 starts. Since the voltage at the output terminal is 1-level, the inverter 12 sets the voltage at node 1 ⁇ 11 to the high level (V 0).
  • the output of the delay circuit 17 becomes high level.
  • Inverter 1 2 has node 1 ⁇ 1 1 as the mouth level.
  • the output of the inverting circuit 1 6 goes high, turning off Mita 1 4.
  • the voltage at node 1 ⁇ ! 1 returns to the mouth level.
  • the delay circuit 17 sets the voltage at the output terminal 0:1 to the mouth level.
  • the spike signal 52 having the pulse width corresponding to the delay time of the delay circuit 17 is output from the output terminal I I.
  • Modification 3 of the first embodiment is an example in which the intermediate node 1 ⁇ ! in the first embodiment is included in the inverting circuit 16.
  • Fig. 3 ( 3 ) shows the circuit diagram of the spike generation circuit according to the modification 3 of the first embodiment
  • Fig. 3 ( ⁇ ) shows the voltage of the node 1 ⁇ ! It is a figure.
  • the input terminal pin n is connected to the intermediate node 1 ⁇ 1 in the inverting circuit 16.
  • the other configuration is the same as that of the first embodiment, and the description is omitted.
  • Fig. 3 As shown in Fig. 3 (13), at time 1:0, the voltage of the node 1 ⁇ 1 is at the mouth level and the gate of the Mending tool 14 is at the high level. Ming 14 is off and the voltage at node 1 ⁇ 1 1 is mouth-level. The voltage at the output terminal is level. The voltage of node 1 ⁇ 1 increases uniformly with time. At time 1, when the voltage of node 1 ⁇ ! ⁇ Gate 4 is mouth-level. As the Ming 14 turns on and the Inverter 12 works, the node 1 ⁇ 1 1 goes high. At time 2 delayed by the delay circuit 17 from time I 1 at time 2, when the voltage at the output terminal 0 becomes 1: high, the inverter 1 2 causes the node 1 ⁇ 11 to go high. At time 3, the output terminal output I becomes mouth level. After that, the operation is the same as that of the second modification of the first embodiment, and the description is omitted. ⁇ 02020/175209 19 ((171?2020/006045
  • the modification 4 of the embodiment 1 is an example in which the intermediate node 1 ⁇ ! ⁇ in the modification 1 of the embodiment 1 is a node 1 ⁇ 11.
  • FIG. 4 (3) is a circuit diagram of the spike generation circuit according to the modification 4 of the first embodiment
  • FIG. 4 ( ⁇ ) is a diagram showing the voltage of the node 1 ⁇ 11 and the output terminal output 1 1. ..
  • the input terminal pin n is connected to the nodes 1 ⁇ 1 1 and 1 ⁇ 1.
  • the input signal is input to node 1 ⁇ 1 1.
  • the other configurations are the same as those of the first modification of the first embodiment, and the description thereof will be omitted.
  • the voltage of the node 1 ⁇ ! 1 uniformly decreases with time.
  • the output of the inverting circuit 16 is at the level
  • the output of the delay circuit 17 is at the high level
  • the output terminal ⁇ The voltage of 1_
  • the inverting circuit 16 When the voltage at the node 1 ⁇ 11 reaches the threshold voltage V I of the inverting circuit 16 at time I 1, the inverting circuit 16 outputs a high level. Inverter 1 2 starts up because Ming 14 turns on. Since the voltage at the output terminals is high level, the inverter 12 sets the voltage at node 1 ⁇ 11 1 to the output level (0 V).
  • a modified example 5 of the first embodiment is an example in which the intermediate node 1 ⁇ 1 in the modified example 1 of the first embodiment is inside the inversion circuit 16.
  • Fig. 5 ( 3 ) is the circuit diagram of the spike generation circuit according to the modified example 5 of the first embodiment
  • Fig. 5 ( ⁇ ) is the voltage of the node 1 ⁇ ! FIG.
  • the input terminal gate n is connected to the inside of the inverting circuit 1 6.
  • Other configurations are the same as those in the first modification of the first embodiment, and the description thereof will be omitted.
  • the inverter 12 (1st IV!3rd inverter) is connected between the ground line 26 and the power line 28 (first power source and second power source). Output node is connected to node N 1 (first node).
  • F E J ]4 switch or first switch
  • the inversion circuit 1 6 (first inversion circuit) outputs the inversion signal of the signal of node 1 ⁇ ! 1 to the gate (control terminal) of Ming 14.
  • the delay circuit 17 delays the signal of the node 1 ⁇ 11 and outputs it to the input node of the inverter 12 and outputs the output spike signal 52 to the output terminal.
  • the node 1 ⁇ 1 1 is an intermediate node ! ⁇ 1 1 connected to the input terminal gate n through which an input signal is input. ⁇ 0 2020/175209 21 ⁇ (: 171? 2020/006045
  • the rising and falling edges of spike signal 52 become steep, and spike signal 52 with a narrow pulse width can be generated. Also, by turning off the Ming 14, the current flowing from the power line 28 to the ground line 26 can be suppressed. This can reduce power consumption.
  • the inversion circuit 16 and the delay circuit 17 may share a part or all of them.
  • Example 2 is a specific example of Modifications 2 and 4 of Example 1, and is an example of a spike generation circuit used in a neuron circuit or the like.
  • FIG. 6C is a circuit diagram of the spike generation circuit according to the second embodiment, and FIG. 6C is a diagram showing each voltage with respect to time.
  • the spike generation circuit 100 according to the second embodiment includes an input circuit 10, an inverter 12, a Ming 14, and inverting circuits 16 and 18.
  • the inverting circuits 16 and 18 form a delay circuit 17.
  • Input circuit 1 0 ⁇ 02020/175209 22 ((171?2020/006045
  • the inverter 12 is a 0/1/03 inverter, and is provided with a Ming 13 3 and a Ming 13.
  • the source of Mending 1 3 3 is connected to the ground line 26, and the drain is the node.
  • the source of Ming 13 13 is connected to the power line 28, the drain is connected to node 1 ⁇ 11, and the gate is connected to node 1 ⁇ ! 0.
  • Nodes 1 ⁇ 1 0 and 1 ⁇ 1 1 are the ingress and egress nodes of invertor 12 respectively.
  • the Ming 14 is a Ming, and is connected in series with the Ming 13 and between the Node 1 ⁇ 1 1 and the power line 28.
  • the source of FEJ ]4 is connected to the power line 28 via the FEJ ]3 and the drain is connected to node 1 ⁇ 1 1.
  • the inverting circuit 16 inverts the level of the node 1 ⁇ ! 1 and outputs it to the gate of the Mending machine 14 and the node N2.
  • the inverting circuit 18 inverts the level of the node 2 and outputs it to the node 3.
  • Node 3 is connected to input node 1 ⁇ 10 and output terminal I of inverter 12 2.
  • Fig. 6 ( ⁇ ) is a diagram showing the voltage of the input terminal gate n, the node N 1 and the output terminal gate line with respect to time.
  • the input circuit 10 an integrator circuit that integrates the input signal input to the input terminal and outputs it to the node 1 ⁇ 1 1 will be described as an example.
  • the voltage of the input terminal pin n and the output terminal pin I in the steady state is the voltage ( ⁇ ) of the ground line 26.
  • the voltage of node 1 ⁇ 11 is 0 V.
  • Node 2 is at high level and node 3 is at mouth level.
  • the gates of Mending 14 are at high level and Mending 14 is off. Imp ' — Evening 1 2 input node is mouth level and node 1 4 is off, so node 1 ⁇ 1 1 is disconnected from ground line 2 6 and power line 2 8. Therefore, the voltage of node 1 ⁇ 1 1 is maintained.
  • the spike signal 50 is input to the input terminal pin n in time series as an input signal.
  • the voltage of the input terminal Ding ⁇ n becomes higher than 0 V V ⁇ n.
  • Input circuit 1 ⁇ 02020/175209 23 ((171?2020/006045
  • the voltage of node 1 ⁇ 11 exceeds the threshold voltage VI.
  • the inversion circuit 16 brings node 2 from high to mouth level. Since the gate level is applied to the gate of Mending 14, the Mending 14 is turned on and a positive feedback is applied to the node N 1. As a result, the node N 1 rises to a high level (voltage V ⁇ ⁇ of the power supply line 28.
  • the inverting circuit 18 changes the node N 3 from the high level to the high level when the node 2 goes from the high level to the high level. Since the input node 1 ⁇ 1 0 of the inverter 12 becomes high level, negative feedback is applied to the node N 1 and the node N 1 falls to the gate level (ground line voltage ⁇ ). 2 and node 3 become high level and mouth level, and spike signal 52 with a narrow pulse width is output to output terminal 1-l. Turns off, and node 1 ⁇ 1 1 is cut off from ground line 26 and power line 28.
  • the spike signal 52 is output to the output terminal 0:1.
  • the negative feedback is applied immediately after the positive feedback is applied to the node N 1, the spike signal 5 2 with a narrow pulse width can be generated.
  • the negative feedback turns the Ming 13 on.
  • the negative feedback simultaneously turns off the counter 13 and the current flowing from the power supply line 28 to the ground line 26 can be suppressed. As a result, power consumption can be suppressed.
  • FIG. 7 ( 3 ) is a circuit diagram of the spike generation circuit according to the first modification of the second embodiment, and FIG. 7 (bath) shows each voltage with respect to time.
  • the Ming 14 is a Ming and is connected to the node N 1 and ⁇ 02020/175209 24 ((171?2020/006045
  • Fig. 7 ( ⁇ ) is a diagram showing the voltage of the input terminal gate n, the node N 1 and the output terminal gate 1:1 with respect to time.
  • the voltage of the input terminal and output terminal in the steady state is the voltage of the power line 28, 0 1 ⁇ 1.
  • the voltage of node 1 ⁇ ! 1 is V.
  • spike signals are input to input terminal pin n in time series.
  • the spike signal 50 When the spike signal 50 is input, the voltage at the input terminal pin n becomes Vn which is lower than Vn.
  • the input circuit 10 integrates the spike signal 50 and outputs it to the node N 1. This causes the voltage at node 1 ⁇ ! 1 to gradually decrease.
  • the voltage of the node 1 ⁇ 1 1 is higher than the threshold voltage V I of the inverting circuit 16, node 2 is at the high level and node 3 is at the high level. Therefore, the voltage of the output pin 1 is kept at V 1.
  • the case where the voltage is low is the rising edge
  • the case where the voltage is high is the falling edge.
  • the voltage of the node 1 ⁇ 11 becomes lower than the threshold voltage VI.
  • the inverting circuit 16 brings the node 2 from the mouth level to the high level. Since a high level is applied to the gate of Mending 1 4, Mending 14 turns on and positive feedback is applied to node N 1. This brings node 1 ⁇ 1 1 up to mouth level.
  • the inversion circuit 18 shifts the node 3 from the high level to the mouth-level when the node N2 goes from the mouth level to the high level. Since the input node 1 ⁇ 1 0 of the inverter 1 2 is the input level, Negative feedback is applied to 1 and node 1 ⁇ 1 1 falls to high level. As a result, a spike signal 52 with a narrow pulse width is output to the output terminal.
  • the spike signal with a narrow pulse width is provided.
  • ⁇ 02020/175209 25 box (: 171?2020/006045
  • No. 52 can be generated.
  • the power consumption can be suppressed by using the 1/3 cup.
  • the spike signal 50 is described as an example of the input signal, but the input signal may have an arbitrary waveform.
  • the input circuit 10 may be any circuit that converts the input signal so that the voltage at the node 1 ⁇ 11 reaches the threshold voltage V I II when the conditions for generating the spike signal 52 are met.
  • the input signal is input to the input terminal tab n .
  • Inverter 1 2 No. 1 1 ⁇ /1 No. 3 impedance
  • Inverter 1 2 has its output node connected to node 1 ⁇ 1 1 (1st node) connected to input terminal tab n, and ground line 2 6 (1st node).
  • Power supply and the power line 28 (second power supply with a voltage higher than the voltage of the first power supply).
  • the Ming 14 switch
  • the inverting circuit 1 6 (first inverting circuit) outputs the inverted signal of the signal of node 1 ⁇ ! 1 to the gate (control terminal) of Mending 1 4.
  • the delay circuit 17 delays the signal of node 1 ⁇ ! 1 and outputs it to the input node 1 ⁇ 10 of the inverter 1 2 and outputs the spike signal 5 2 (output spike signal) to the output terminal.
  • the inverting circuit 16 outputs an inverted signal of the signal of the node 1 ⁇ ! 1 to the gate of the Mending 14 and the node N 2 (second node).
  • the delay circuit 17 includes an inverting circuit 16 and an inverting circuit 18 for outputting an inverted signal of the signal of the node 2 to the input node 1 ⁇ ! 0 of the inverter 12 and the node N 3 (third node). Equipped with.
  • the inverting circuit 1 6 positively feeds back the signal of the node 1 ⁇ 1 1 to the gate of the Ming 1 4 and the inverting circuit 1 8 inputs the signal of the node 1 ⁇ 1 1 to the input node 1 ⁇ 1 0 of the inverter 1 2. Can be negatively fed back to.
  • a positive spike signal 52 can be generated as shown in Fig. 6 (13).
  • Fig. 7 (3) when the Mine 14 is a Mine (1 ⁇ 1 channel transistor), the Mine 14 is connected between the node 1 ⁇ 1 1 and the ground line 26. This makes it possible to generate a spike signal 52 in the negative direction as shown in Fig. 7 (10).
  • the third embodiment is a specific example of the spike generation circuit of the second embodiment and its modification.
  • FIG. 8 is a circuit diagram of the spike generation circuit according to the third embodiment.
  • the input circuit 10 is a capacitor ⁇ having one end connected to the node 1 ⁇ ! 1 and the other end connected to the ground line 26.
  • the inverting circuit 16 is an inverter 20 having an input node connected to 1 ⁇ ! 1 and an output node connected to node 2.
  • the inverter 20 is a 0/1/1/3 inverter, and is equipped with a Mending machine 21 3 and a Mending machine 21.
  • the source of Mingda 2 1 3 is connected to ground line 26, the drain is connected to node 2, and the gate is connected to node 1 ⁇ 1 1.
  • the source of Ming 2 1 is connected to power line 28, the drain is connected to node 2, and the gate is connected to node 1 ⁇ ! 1.
  • the inverting circuit 18 includes inverters 2 2 3 to 2 2 0 and a capacitor 0 2.
  • Inverters 2 2 3 to 2 2 0 are connected in multiple stages between nodes 2 and 3. That is, they are connected in series with each other between nodes 2 and 3.
  • Inverters 2 2 3 to 2 2 0 are 0 1 ⁇ /1 0 3 inverters, each equipped with a Ming 2 3 3 and a F 2 7 2 3 stool.
  • the source of Ming 2 3 3 is connected to the ground line 26, the drain is connected to the output node, and the gate is connected to the input node.
  • the source of the battery is connected to the power line 28, the drain is connected to the output node, and the gate is connected to the input node.
  • inverter 2 28 The input node of inverter 2 28 is connected to node N 2 and the output node is connected to node 4.
  • the input node of the inverter 2 2 is connected to the node N 4, and the output node is connected to the node 5.
  • Inverter 2 The input node of 2 c is connected to node N 5, and the output node is connected to node N 3.
  • One end of the capacitor C 2 is connected to the node N 4 and the other end is connected to the ground line 26.
  • Other configurations are the same as those in the second embodiment, and the description thereof is omitted.
  • Example 3 Each voltage of Example 3 was simulated using S P I CE (Simulation Program with Integrated Circuit Emphasis). The simulation conditions are as follows.
  • N channel using SO I Si I icon on Insulator M ⁇ S
  • Gate length 100 nm
  • Gate width 100 nm
  • Threshold voltage + 0.8 V
  • Gate capacity 1 f F
  • Capacitor C 2 Capacitance value: 4 f F
  • Ground wire 26 Voltage: 0 V
  • Power line 28 Voltage V d d: 1 V
  • a constant current of 1 pA was applied to the input terminal T in.
  • FIG. 9(a) and FIG. 9(b) are diagrams showing the voltage of each node with respect to time in the third embodiment.
  • Fig. 9(b) is an enlarged view of the spike signal 52 and its vicinity in Fig. 9(a).
  • the first scale on the horizontal axis in Fig. 9(b) describes 1 0599000 ns, which corresponds to the time in Fig. 9(a), and only the last two digits are described on subsequent scales. The same applies to subsequent enlarged views.
  • the voltage increases from 0.5 V to 0.8 V.
  • the voltage at the node N 1 increases sharply on the time axis of Fig. 9(a), but gradually increases on the time axis of Fig. 9(b).
  • the time I 1 corresponds to the time before the time 1 0599000 n s.
  • the voltage of node 2 changes slowly from high level to mouth-level.
  • the voltage of the node N4 changes from the mouth level to the high level between the time 1 and the time 2 slightly faster than that of the node N 2.
  • the voltage at node N5 changes from high level to mouth-level much faster than at node N4.
  • the voltage at node N 3 changes very rapidly from mouth level to high level at time 2.
  • the voltage changes sharply as the nodes N 1, N 2, N 4, N 5 and N 3 are visited.
  • the spike signal 52 rises and falls sharply.
  • ⁇ 1 ⁇ /1 ⁇ 3 In the inverter, a through current flows from the power line 28 to the ground line 26 during the voltage transition period. And by reducing the leak current of Mitsuo, this through current can be sufficiently reduced and power consumption can be suppressed. Since the spike signal 52 rises and falls sharply as in the third embodiment, the power consumption of the spike generation circuit 104 can be further suppressed.
  • FIG. 10 (3) and Fig. 10 ( ⁇ ) are diagrams showing the input voltage, the output voltage, and the current consumption with respect to time in Example 3.
  • FIG. 10 (13) is an enlarged view around the spike signal 52 in FIG. 10 (a).
  • the voltage V 1 at node 1 ⁇ 11 gradually increases from time 0 3 to 5 3 and when the voltage VI reaches 0.5 V, the voltage V 1 suddenly increases to 0.8. And then ⁇ . Times of Day In Fig. 5, the voltage V ⁇ li 1: of the output terminal is 1 V and the spike signal 52 is output. Current consumption during 3 is 1
  • Spike signal 52 is output. Current is approximately 1 XI ⁇ - 6 eight at time 2, the largest. In the spike generator circuit 104, almost all the power is consumed when the spike signal 52 is generated. When the power supply voltage is 1 V, the energy consumption per sub-cycle is about 15°. In this way, the power consumption (energy consumption) for generating spikes can be made extremely small.
  • Example 3 The function of the capacitor 02 in Example 3 will be described.
  • the capacitance value of the capacitor 02 was changed to simulate the output voltage V0I I with respect to time.
  • FIG. 11 (3) to FIG. 12 () are graphs showing the output voltage with respect to time in the third embodiment.
  • the capacitance value of the capacitor ⁇ 2 is 0, 1°, 2°, 3°, respectively.
  • the width of the spike signal 52 is about 2 n 3, which is the minimum, and the rising edge becomes steeper.
  • Fig. 12 (a) when the capacitance value of capacitor 02 is 4, the width of spike signal 52 is approximately 2 The minimum is 3, and the rising edge becomes steeper.
  • Fig. 12 ( ⁇ ) when the capacitance value of the capacitor ⁇ 2 is 6, the width of the spike signal 52 is slightly larger, about 2.5 n 3, and the rise is about the same. The descent becomes a little slower.
  • Fig. 12 ( ⁇ ) when the capacitance value of the capacitor 0 2 is 10°, the width of the spike signal 5 2 becomes about 3 n 3 and becomes larger, and the rising edge becomes slightly gentle.
  • Fig. 12 ( ⁇ 1) when the capacitance value of capacitor 0 2 is 20°, the width of spike signal 5 2 is approximately ⁇ 02020/175209 30 units (: 171?2020/006045
  • the width of the spike signal 52 can be narrowed and the rising and falling can be made small. Therefore, the power consumption can be further suppressed.
  • the gate capacitance value of Mitsumi and Mitsucho is 0. 1 degree, and the capacitance value of the capacitor 02 is preferably 1 time or more, more preferably 2 times or more, and further preferably 3 times or more of the gate capacity value.
  • the capacitance value of the capacitor 02 is preferably 100 times or less, more preferably 50 times or less, the gate capacity value.
  • FIGs. 13(a) to 13() are diagrams for explaining the function of the capacitor 02.
  • Figure 13 (3) is a schematic diagram showing the current flowing through the output node when the inverter reverses with time. As shown in Fig. 13 (a), when the inverter is inverted, a small current is supplied to the output node. _ Flows. After that, a large current of 1 ⁇ 1 flows. Assuming the current I! _ And I 1 ⁇ 1 constant, and Ding! _ And Ding 1 to 1 a period in which the current I! _ And ⁇ 1 to 1 flows.
  • FIG. 13 ( ⁇ ) When the capacitance of capacitor 02 is small, the voltage rise at node 4 is determined by the charging time of the gate capacitance of inverter 22. Since the current I !_ is small in the period D !_, the voltage V 4 of the node 4 increases gently in the period D !_. In the period 1 to 1, the current V 1 to 1 is large and the voltage V 4 rapidly increases. When the voltage V 4 exceeds the threshold voltage VI in the period !_, the inversion of the inverter 22 will occur slowly. Therefore, the rising and falling of the spike signal 52 becomes gradual. Also, when the capacitance value of the capacitor 02 is small, the timing of the negative feedback is too early, which hinders the positive feedback, and the rising becomes slower.
  • the width of the spike signal 52 can be narrowed and the rising and falling can be made steep. Therefore, power consumption can be suppressed.
  • capacitor C 2 As the capacitor C 2, a MOS capacitor and a M S (Meta I Insulator Semiconductor) capacitor can be used.
  • the capacitor C 2 may use the parasitic capacitance of MOS F E T.
  • FIG. 14(a) to 15(b) are circuit diagrams of the spike generation circuit according to the third embodiment.
  • the inverting circuit 18 has one inverter 22a and capacitor C2.
  • the capacitor C 2 is connected to the node N 4 in the latter stage of the inverter 22a.
  • the inverting circuit 18 includes three inverters 22a to 22c, as in FIG. 8 of the third embodiment.
  • the capacitor C 2 is connected to the node N 4 between the inverters 22a and 22b.
  • the 8 has five inverters 22a to 22e.
  • the capacitor C2 is connected to the node N4 between the inverters 22a and 22b.
  • the inverting circuit 18 has seven inverters 22a to 22g.
  • Capacitor C 2 is the inverter ⁇ 02020/175209 32 units (: 171?2020/006045
  • Fig. 16 (3) to Fig. 16 ( ⁇ are graphs showing the output voltage with respect to time of the spike generation circuit in Example 3.
  • spike generation was performed.
  • the spike signal 52 rises gently, and the spike signal 52 has a wide width.
  • the spike signal 52 rises steeply as shown in Fig. 16 (13).
  • the width of the spike signal 52 is about 2 n 3.
  • the width of the spike signal 52 is slightly wide, but the rising edge is steep.
  • the spike signal 52 has a slightly wider width, the rising edge is steep.
  • the spike generation circuit can be realized by setting the number of inverters of the inverting circuit 18 to an odd number.
  • the number of the inverters 223 to 229 is preferably three or more. Number from the inverter 223 22 9 3 is more preferable.
  • FIG. 17 is a circuit diagram of the spike generation circuit according to the first modification of the third embodiment.
  • the spike generation circuit 106 of the first modification of the third embodiment does not include the capacitor 02.
  • the number of inverters in the inverting circuit 18 is an odd number, for example, seven.
  • the node between the inverters 223 and 22 is 4, the node between the inverters 22 and 22 is 5, the node between the inverters 22 and 22 is 6, the node between the inverters 22 and 226 is N 7, the node between inverters 226 and 22 is 8 and the node between inverters 22 and 229 is 9.
  • the other configuration is the same as that of the third embodiment, and the description is omitted.
  • FIG. 18 is a diagram showing the voltage of each node with respect to time in the first modification of the third embodiment. Nodes N 1, N 2, N 4, N 5, N 6, N 7 as shown in Figure 18 ⁇ 02020/175209 33 ⁇ (: 171?2020/006045
  • the rise and fall of the spike signal 52 can be made steep.
  • FIG. 19 ( 3 ) is a circuit diagram showing another example of the spike generation circuit according to the first modification of the third embodiment. As shown in Fig. 19 (a), the spike generation circuit 1 0 6 3 has only one inverter 2 2 3 in the feedback circuit 8.
  • the number of inverters 2 2 3 may be an odd number.
  • the number of the inverters 2 2 3 to 2 2 9 is preferably 3 or more, more preferably 5 or more, in order to make the rising and falling of the spike signal 52 sharp. , 7 or more is more preferable.
  • FIG. 19 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the second modification of the third embodiment.
  • spike generator circuit 108 one end of capacitor 02 is connected to power supply line 28 and the other end is connected to node N4, as shown in Fig. 19 ( ⁇ ).
  • the other configuration is the same as that of the third embodiment, and the description is omitted.
  • the capacitor 02 may be connected to the power supply line 28.
  • the capacitor 02 may be connected to a reference potential terminal to which a constant potential other than the ground line 26 and the power supply line 28 is supplied.
  • FIG. 19 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the third modification of the third embodiment. As shown in Fig. 19 ( ⁇ ), in the spike generator circuit 110, one end of the capacitor ⁇ 1 is connected to the power line 28 and the other end is connected to the node 1 ⁇ ! 1.
  • Ming 1 4 is a Ming, whose source is connected to ground wire 26 and ⁇ 02020/175209 34 ⁇ (: 171?2020/006045
  • the in is connected to node N 1 through F EJ ]33 and the gate is connected to node 2.
  • the other configuration is the same as that of the third embodiment, and the description is omitted.
  • FIG. 20(a) and Fig. 20( ⁇ ) are diagrams showing the voltage of each node with respect to time in the modified example 3 of the third embodiment.
  • Figure 20 (13) is an enlarged view of the spike signal 52 and its vicinity in Figure 20 (a).
  • the voltage at each node 1 ⁇ ! 1 to 5 has a waveform obtained by inverting the voltage in FIG. 9(b) of the third embodiment.
  • the width of the spike signal 52 is about 2 n 3, which is about the same as that of the third embodiment, and the rising and falling edges are as steep as those of the third embodiment.
  • the capacitor 0 1 may be connected to the power supply line 28.
  • the capacitor 0 1 may be connected to a reference potential terminal to which a constant potential other than the ground line 26 and the power supply line 28 is supplied.
  • FIG. 21 is a circuit diagram of a spike generation circuit according to Modification 4 of Example 3.
  • the inversion circuit 16 includes an inverter 20 and a knife 24.
  • the Ming 24 is a Ming and is connected between the inverter 20 and the power line 28.
  • the gate of Mending 24 and the gate of Mending 14 are connected to node 1 ⁇ 110.
  • Node 1 ⁇ ! 10 is connected to the drain of Mending 24.
  • the mats 14 and 24 form a current-current mirror circuit.
  • the inverting circuit 18 is provided with an inverter 22, a capacitor 02, and a knife 293 and a pump 229.
  • the capacitor 02 is connected between the node 2 and the ground line 26.
  • the input node of inverter 2 2 is connected to node 2, and the output node is connected to node 3.
  • Mending 2 9 3 is connected between node 3 and Mending 2 3 3.
  • ⁇ 29 is connected between the node N 3 and the input node 1 ⁇ ! 0 of the inverter 20.
  • the gates of Mita 2 9 3 and 2 9 13 are connected to the power line 2 8.
  • the capacitor 0 3 has one end connected to the node 1 ⁇ 10 and the other end connected to the ground line 26.
  • Capacitor ⁇ 3, ⁇ 2 93 and 2 9 ⁇ function as a resistor to delay the negative feedback.
  • the inverting circuit 18 applies negative feedback to the node 1 ⁇ 1 1.
  • the output node 2 of the inverter 20 does not have to be connected to the gate of the Mending 14 as in the fourth modification of the third embodiment.
  • the inverting circuit 16 may output the inverted signal of the node 1 ⁇ ! 1 to the gate of the Mending 1 4 when the level of the inverter 20 changes.
  • the inverting circuit 16 is connected in series between the node N 1 and the node 2 and the input node is connected to the node 1 ⁇ 1 1 as a node. Includes an odd number of inverters 2 0 (No. 21 ⁇ /1 No. 3 inverters) with output nodes connected to 2.
  • the inverting circuit 18 is connected in series with each other between nodes 2 and 3 and has an odd number of inverters 2 2 3 to 2 2 9 with an input node connected to node 2 and an output node connected to node 3. (No. 31 ⁇ 103 inverter) is included.
  • the inverting circuit 16 can perform positive feedback and the inverting circuit 18 can perform negative feedback.
  • the inverting circuit 16 may include three or more inverters 20. However, the number of the inverters 20 is preferably one for downsizing.
  • the inverting circuit 18 includes three or more inverters 2 2 3 to 2 2 9. to this ⁇ 02020/175209 36 ⁇ (: 171?2020/006045
  • the width of the spike signal 52 can be narrowed and the rising and falling edges can be made steep.
  • One or more is connected to the node N 4 (4th node) between three or more inverters 2 2 3 to 2 2 9 and the other end is ground line 2 6 or power line 2 8 (1st reference). It is equipped with a capacitor ⁇ 2 (first capacitance element) connected to the potential terminal.
  • ⁇ 2 first capacitance element
  • the capacitance value of capacitor 02 is greater than or equal to the gate capacitance value of one of the inverters 2 2 3 to 2 2 9. This makes it possible to narrow the width of the spike signal 52 and make the rising and falling edges steep.
  • the capacitance value of the capacitor 0 2 is set to be equal to or higher than the gate capacitance value of the Mitsuko, which has the smallest gate capacitance value among the inverters 2 2 3 to 2 2 9.
  • the input circuit 10 has one end connected to the node 1 ⁇ 11 and the other end connected to the ground line 2 6 or the power supply line 2 8 (second reference potential terminal). (Second capacitance element). As a result, the input signals input to the input terminal T n can be integrated and output to node 1 ⁇ ! 1.
  • the threshold voltage of each knife is preferably 0.3 XV (voltage of power line 28-voltage of ground line 26) or more, more preferably 0.5 XV or more, and 0.8 The above is more preferable. It should be noted that the threshold voltage of 0.3% or more means +0.3% or more for a knife and 100.3 X V or less for a knife. The same applies to the threshold voltages of the other dens.
  • a voltage higher than the gate level (voltage of the ground line 26) (eg, slightly lower than the threshold voltage V 1 * 1) is applied to the node N 1 for a long time. Therefore, in Ming where the leakage current is most likely to increase, the input node is connected to the node ! ⁇ 11. ⁇ 02020/175209 37 ⁇ (: 171?2020/006045
  • the threshold voltage of the swallow is preferably 0.3 XV or more, more preferably 0.5 XV or more, and further preferably 0.8 ⁇ or more.
  • the maximum leakage current allowed in the spike generation circuit during a time other than the spike generation operation is ⁇ .
  • the power consumption of the spike generation circuit should be less than the desired power when a voltage of about 2 is applied for a long time.
  • the leak current of the spike generation circuit is almost the leak current of the inverter 20
  • the leak current of the inverter 2 0 3 and F £ 7 2 1 is set to I ⁇ or less, the consumption of the spike generation circuit is reduced.
  • the electric power can be less than or equal to the desired electric power.
  • the leakage current of the channel Let the gate voltage of the sagger be I ⁇ and 1 (I ), respectively. At this time
  • the power consumption can be kept below the desired power.
  • the desired power is 1
  • the leakage current is ⁇ 1 x 10 _ 9 8 /.
  • lay preferred to leakage current ⁇ wo 5 1 Yes Yes / less, and more preferably in the 2 X 1 0 _ 1 0 / below.
  • a Ming using a substrate. Since this Ming has a small leakage current between the source and the drain, the power consumption can be suppressed. For example, one Ming It is possible to reduce the leak current in the case of 18 or less.
  • Example 4 is a specific example of Modifications 3 and 5 of Example 1.
  • FIG. 22 ( 3 ) to FIG. 23 ( ⁇ ) are circuit diagrams of the spike generation circuit according to the fourth embodiment.
  • the spike generation circuit 1336 of the fourth embodiment includes a flip-flop circuit 90, a delay circuit 17 and a knife 91.
  • Delay circuit ⁇ 02020/175209 38 ⁇ (: 17 2020 /006045
  • Reference numeral 17 denotes a circuit in which even-numbered stages of inverters are cascade-connected like the delay circuit 17 having the inverting circuits 16 and 18 of the second embodiment and its modification 1, for example.
  • the flip-flop circuit 90 sets the output node 900 to a high level when the input node 903 becomes a high level, and maintains the output node 900 to a high level until a high level is input to the input node 90.
  • the flip-flop circuit 90 sets the output node 900 to a high level when the input node 90 goes high, and maintains the output node 900 level to a high level until the input node 908 inputs a high level.
  • the input node 903 is connected to the intermediate node 1 ⁇ 1 which is connected to the input terminal.
  • Input node 9013 is connected to node 3.
  • the output node 900 is connected to the input node of the delay circuit 17 and the output node of the delay circuit 17 is connected to the node 3.
  • Ming 9 1 is a Ming, whose source, drain and gate are connected to ground line 26, intermediate node 1 ⁇ ! ⁇ and node N 3, respectively.
  • Mita 92 to 92 and Mita 933 to 93 are used as the flip-flop circuit 90 of FIG. 22(a).
  • Mitsumi 920 and Mitsuo 930 can be deleted. An example of deletion is shown below.
  • the spike generation circuit 138 does not include the Mitsuko 92 ⁇ and the Mitsuo 930.
  • Ming 92 and Ming 93 are equivalent to F o 7 ]33 and F o 7 ]3 stiles, respectively.
  • o 71 33 and Ming 13 are connected in series between the power line 28 and the ground line 26 to form a 0 1 1/3 inverter 12.
  • Mending 93 is equivalent to Mending 14.
  • Ming 14 is F between node 1 ⁇ ! 1 and power line 28. .. ⁇ 4 has its gate connected to node 9.
  • Ming 92 is equivalent to Ming 95.
  • inversion circuit 1 6 is provided with an inverting circuit 1 6 3 and 1 6 spoon. Inversion circuit 1
  • the inverting circuit 1 6 s contains a shunt 9 1 and an inverter 9 4.
  • the spike generator circuit 1 339 has the spike generator circuit 1 3 8 in Fig. 23 (a) with the knives 920 in Fig. 2 2 ( ⁇ ).
  • Mite 9 20 is equivalent to Mine 9 6.
  • the source, drain, and gate of the Mitsumi 96 are connected to the ground line 26, node 1 ⁇ 11 and node 9, respectively.
  • node 1 ⁇ 1 1 becomes floating when Mine 14 is defeated.
  • the counter 9 6 is turned on, so that the node 1 ⁇ 1 1 is at the first level. This can prevent node 1 ⁇ 1 1 from floating.
  • Example 4 may be any of the circuits shown in FIG. 22(a) to FIG. 23(well).
  • FIG. 23 is a diagram showing the voltage of each terminal and node with respect to time in Example 4, in which node 9, which corresponds to the gate of node 1 ⁇ 1 and node N 14, node N 1, and output terminal 0 (Ie node N 3) voltage is shown.
  • the voltage of node 1 ⁇ 1 is ⁇
  • the voltage of node 9 is high level (V ⁇ ⁇
  • the voltage of node N 1 is gate-level (0 V)
  • the voltage of output terminal is
  • the input node 0 of the inverter 1 2 is the output level and the node 9 is the high level.
  • Inverters 1 and 2 do not open because they are off.
  • node 9 ⁇ ! 1 becomes the mouth level because Mitsumi 96 is turned on.
  • the delay circuit 17 delays from time t1 and sets the output terminal T oo t to the high level. Since the gate of FET 91 goes high, FET 91 turns on and the voltage at node N i becomes 0 V. The node N g goes high. Node N 1 is mouth-level because F ET 14 is turned off and F ET 96 is turned on. In this way, the F ET 91 and the inverter 94 function as an inverting circuit 16 b that sets the node N g to the high level and the node N 1 to the gate level when the node N 3 goes to the high level.
  • the delay circuit 17 delays from time t2 and sets the output terminal T o u t to the mouth-level. As a result, the spike signal 52 having a pulse width of t 4 -t 2 is output to the output terminal T o u t.
  • Fig. 23(b) consider the case where the inverter 94 is not provided and the control terminal of the FET 14 and the node N i are connected.
  • the positive feedback loop from node N 1 through F ET 95 and 14 includes node N i.
  • the node N i is kept in the mouth-level state.
  • the inverter 94 is provided between the intermediate node N i and the gate of the FET 14. ⁇ 02020/175209 41 ⁇ (: 171?2020/006045
  • FIG. 25 is a diagram showing each voltage with respect to time when F E J 9] is not provided. As shown in Fig. 25, even if the output pin level goes high at time 2, the voltage at node 1 ⁇ 1 does not become 0 V but continues to rise. The positive feedback via the output terminal 9 5 and the negative feedback via the delay circuit 17 are alternately applied. Therefore, the voltage of the node N 1 repeats the normal level and the high level, and the spike signal is output from the output terminal output terminal 1. 5 2 is repeatedly output. As described above, when the gate of Mending 14 is not set to the mouth level even when the inversion circuit 1 63 3 becomes high level at node 1 ⁇ 11, it is preferable to provide Mending 9 1.
  • 26A and 26B are circuit diagrams of the spike generation circuit according to the first modification of the fourth embodiment.
  • a flip-flop circuit 90 is provided with a latch having eight circuits 913 and 91.
  • the Ming 9 1 is a Ming and the source of the Ming 9 1 is connected to the power line 28.
  • the other configurations are the same as those of the spike generation circuit 1336 shown in Fig. 22 (a), and the description is omitted.
  • the flip-flop circuit 90 is disassembled into Ming and the deletable Ming is deleted.
  • the Ming 1 4 is a Ming, and is connected in series with the Ming 1 1 3 between the node 1 ⁇ 1 1 and the ground line 2 6.
  • Mending 9 5 and 9 6 are Mending.
  • the sources of Ming 9 5 and 9 6 are connected to the power line 28.
  • the delay circuit 17 from the inverter 94 forms a circuit 98.
  • the other configuration is the same as the spike generation circuit 1339 in Fig. 23 (b) and its explanation is omitted.
  • the input signal input to the input terminal pin n is
  • the mouth-level spike signal 52 is output from the output terminal block 1:.
  • the spike generation circuit 1 35 of Modification 5 of the first embodiment can be realized by using the Mending tool 14 as a signature.
  • the spike generation circuit 142 includes inverters 94 3 and 94 in addition to the spike generation circuit 140 of FIG. 26(a).
  • the inverter 943 is connected between the node 1 ⁇ 1 and the input node 903 of the flip-flop circuit 90, and the inverter 94 is connected between the node N 3 and the gate of the knife 91.
  • the Ming 91 is a Ming and the source is connected to the ground line 26.
  • the other configuration is the same as that of the spike generation circuit 140 of FIG. 26(a), and the description thereof is omitted.
  • the flip-flop circuit 90 is disassembled into Mending, and erasable Mending is deleted.
  • the spike generator circuit 1 4 1 and circuit 98 in Fig. 26 ( ⁇ ) are the same.
  • the Ming 91 is a Ming and is provided with inverters 943 and 94.
  • the reversing circuit 16 includes the inverters 94, 943, 94 and o79 ⁇ .
  • the other configuration is the same as that of the spike generation circuit 1 4 1 in Fig. 26(b), and the description is omitted.
  • the input signal input to the input terminal selector n is a signal that rises from the mouth level to the high level like the signal of the input terminal selector_1 of Fig. 3(b) of the third modification of the first embodiment.
  • Inverter 94 3 converts the input signal into a signal falling from the high level to the mouth Reberu as input terminals Ding _1 signal of Figure 5 of a modification 5 of Example 1 (b).
  • a mouth-level spike signal 52 as shown in Fig. 5 (10) is output from the output terminal.
  • Inverter 94 inverting the signal of node 3 and outputting it to the gate of F EJ 9 ].
  • the input signal may be inverted. This place ⁇ 02020/175209 43 ⁇ (: 171?2020/006045
  • node 1 ⁇ 1 1 can be reset by installing an inverter 94.
  • FIG. 28(a) and FIG. 28( ⁇ ) are circuit diagrams of the spike generation circuit according to Modification 3 of Example 4.
  • the spike generation circuit 144 uses a flip-flop circuit 90 with a latch having 1 ⁇ 10 circuit 9100 and 80 circuit 91 circuits.
  • Inverters 9 4 ⁇ 1 and 9 4 ⁇ are provided in the loop. Inverter 9 43 is not provided. Other configurations are the same as the spike generation circuit 1 4 2 in Fig. 27 (a), and description thereof is omitted.
  • the flip-flop circuit 90 is disassembled into mittens, and erasable mites are deleted.
  • the Ming 9 5 is the Ming.
  • the inverter 940 inverts the signal of node 1 ⁇ 1 1 and outputs it to the gate of Mending 9 5.
  • the drain of Ming 9 5 is connected to node 9 2 between inverters 9 4 3 and 9 4.
  • the inverter 9 4 inverts the signal of the node 9 2 and outputs it to the node N 9.
  • the inverting circuit 1 63 includes inverters 9 4 and 9 40 and Ming 9 5.
  • the inverting circuit 1 6 includes an inverter 9 4, 9 4 3, 9 4 and a knife 9 1.
  • the other configurations are the same as those of the spike generation circuit 143 shown in Fig. 27 (nozzle), and the description is omitted.
  • the input signal is a signal that rises from the mouth level to the high level.
  • Signal 2 is a signal that drops from high level to mouth level.
  • the circuit 9 9 of the delay circuit 17 from the inverter 9 4 outputs the mouth-level spike signal 5 2 like the spike generation circuit 1 35 of the modification 5 of the first embodiment.
  • the inverting circuit 1 63 may include inverters 9 4 and 94 0 in addition to the counter 9 5.
  • the inverting circuits 1 63 and 1 6 may share some circuit elements (eg, inverter 9 4 ).
  • Fig. 29 (a) and Fig. 29 (well) show spikes according to the fourth modification of the fourth embodiment. ⁇ 02020/175209 44 ⁇ (: 171?2020/006045
  • FIG. 29 (a) It is a circuit diagram of a generation circuit. As shown in Fig. 29 (a), the spike generator circuit 1 46 has a flip-flop circuit.
  • Inverters 9 4 and 9 4 6 are provided in the loop of 1.
  • An inverter 943 is provided between the node 1 ⁇ 1I and the input node 9033 of the flip-flop circuit 90, and the inverter 944 is provided between the output terminal block 1 and the gate of the counter 91. No slag is provided.
  • Other configurations are the same as those of the spike generation circuit 1 4 4 shown in Fig. 28 (a), and description thereof is omitted.
  • an inverter 94 is provided between the inverters 9 4 3 and 9 4 and an inverter is provided between the node N 3 and the gate of the knife 9 1.
  • Ming 9 6 is a Ming
  • Ming 1 4 and 9 5 are Ming.
  • the inverting circuit 1 63 includes inverters 9 4 and 9 40 and Ming 9 5.
  • Inversion circuit 1 6 sq. is inverter 9 4, 9 4 3,
  • the input signal is a signal that rises from the mouth level to the high level.
  • Signal 2 is a signal that rises from mouth level to high level.
  • the circuit 993 of the delay circuit 17 from the inverter 94 outputs the spike signal 52 of high level like the spike generation circuit 1333 of the modification 35 of the first embodiment.
  • the inverting circuits 1 6 3 and 1 6 13 may optionally include an inverter.
  • FIG. 30( a) and FIG. 30( ⁇ ) are circuit diagrams of the spike generation circuit according to Modification 5 of Example 4.
  • the flip-flop circuit 90 uses latches having 1 ⁇ 1 circuits 9 10 and 9 1.
  • Complementary to output node 900 of flip-flop circuit 90 ⁇ 02020/175209 45 ⁇ (: 171?2020/006045
  • An inverter 94 is connected in series with the delay circuit 173 between the common output nodes 90 and 3.
  • the output node 90 outputs a signal complementary to the output node 900. Therefore, by providing the inverter 9 4 NOTE before or after the delay circuit 1 7 3, same function as when connected to Kanodo 9 0_Rei exits delay circuit 1 7 3 is obtained.
  • Spike generators 1 3 6, 1 3 8, 1 4 0, 1 4 2, 1 4 4 and 1 4 6 also have delay circuits between the complementary output node of output node 900 and node 3. 7 3 and the inverter 9 4 can be connected.
  • the other configurations are the same as those of the spike generation circuit 1336 shown in Fig. 22 (a), and description thereof is omitted.
  • the flip-flop circuit 90 is disassembled into Mending, and erasable Mending is deleted.
  • the input node of the delay circuit 1 73 is connected to the node N 9 (that is, the drain of the mine 9 5) and the delay circuit 1 7 3
  • the output is connected to node 3 via inverter 94.
  • Ming 9 5 ,delay circuit 1 7 3 and inverter 9 4 function as delay circuit 1 7.
  • the other configurations are the same as those of the spike generation circuit 139 shown in Fig. 23 (b), and a description thereof will be omitted.
  • the inverting circuit 163 and the delay circuit 17 may share a part of the circuit element (for example, Ming 985).
  • the inverter 12 outputs the first level (one of the high level and the mouth-level) and the second level (the other of the high level and the mouth-level).
  • Mita 1 4 first switch
  • the Ming 14 is a Ming
  • the first level and the second level are the high level and the mouth level, respectively.
  • the first and second levels are mouth-level and high-level, respectively.
  • the inverting circuit 1 63 (first inverting circuit) has node N 1 from the first level to the second level. ⁇ 02020/175209 46 ⁇ (:171?2020/006045 When the bell is reached, the 1st level is output to the gate of Mending 1 4.
  • Fig. 2 3 ( ⁇ ), Fig. 29 ( ⁇ ) and Fig. 30 In (spike) spike generators 1 3 9 ,1 4 7 and 1 449, when node 1 ⁇ ! 1 goes from the mouth level to the high level, the inversion circuit 1 6 3 connects to the gate of Mending 1 4 with the mouth level. Is output.
  • the inverting circuit 16 s (second inverting circuit) outputs the second level to the gate of the counter 14 when the output of the delay circuit 17 reaches the second level.
  • Figure 2 3
  • the inverting circuit 1 6 In the spike generator circuits 1 3 9, 1 4 7 and 1 4 9 shown in Fig. 29 (Case) and Fig. 30 (Case), when the node 3 goes high, the inverting circuit 1 6 Outputs high level to 4 gate. In the spike generator circuits 1 4 1, 1 4 3 and 1 4 5 in Fig. 26 (Coop), Fig. 27 (Coop) and Fig. 28 (Coop), the inverting circuit 1 6 Coop when node 3 becomes the mouth level. Outputs the mouth level to the gate of Mending 14. The intermediate node 1 ⁇ 1 is installed in the inverting circuit 16.
  • the inverting circuit 16 has a gate (control terminal) with the output of the delay circuit 17 (node
  • the Mitsumi 91 connects the intermediate node 1 ⁇ 1 and the power supply to which the initial level of the input signal is supplied.
  • the Mine 9 1 is a Mine
  • the intermediate node is connected to the ground line 2 6.
  • the Mending 9 1 is a Ming and the intermediate node 1 ⁇ ! ⁇ is connected to the power line 2 8. This will reset the intermediate node 1 ⁇ 1 and make node 9 the second level.
  • Inverter 9 4 (No. 21 ⁇ /1 ⁇ 3 Inverter) has an input node connected to node 1 ⁇ 1 and an output node connected to the gate of node 14 (node N 9). ⁇ 02020/175209 47 ⁇ (:171?2020/006045
  • the positive feedback loop 15 does not include the node S, and the voltage at the node 9 can change with the input signal.
  • the inverting circuit 1 63 has a gate connected to the node 1 ⁇ 1 1 and when the node 1 ⁇ 1 1 becomes the second level, the gate (node N 9) of the Mending machine 14 and the first level are supplied. It is equipped with a Ming 9 5 (third switch) for connecting to a power source. As a result, the counter 9 5 can be used as the inverting circuit 1 63.
  • Mite 9 6 (4th switch) has a gate (node 4)
  • the high level at the same node (or terminal) may be higher than the mouth level, the high level between different nodes (or terminals) may not be the same voltage, and the mouth level may not be the same voltage. May be.
  • the input circuit 10 according to the second and third embodiments and its modification may be provided between the input terminal gate n and the intermediate node 1 ⁇ 1 according to the fourth embodiment and its modification.
  • FIG. 31 is a circuit diagram of the spike generation circuit according to the fifth embodiment. As shown in FIG. 31, in the spike generation circuit 1 1 1 4 of the fifth embodiment, the voltage conversion circuit 3 0 is connected between the capacitor 0 1 and the input terminal gate n.
  • the input circuit 10 includes a capacitor O 1 and a voltage conversion circuit 30.
  • the voltage conversion circuit 30 is provided with a counter 311 and a counter 311.
  • the source and gate of the Mita 3 1 3 are connected to the ground line 26, and the drain is connected to the node 1 ⁇ 1 1 1.
  • the source of the switch 3 1 is connected to the node 1 ⁇ 1 1 1, the gate is connected to the ground line 26, and the drain is connected to the input terminal pin n.
  • Ming 3 1 3 and 3 1 turns off and acts as a high resistance between the source and drain.
  • the input signal input to the input terminal is F It is divided by 3 ⁇ 3 and 3 1 and output to node ! ⁇ 1 1 1 ⁇ 02020/175209 48 ⁇ (: 171?2020/006045
  • the other configuration is the same as that of the third embodiment, and the description is omitted.
  • FIG. 32 (a) to Figure 33 ( ⁇ ) are graphs showing the voltage and output voltage of node 1 ⁇ 11 with respect to time in Example 5.
  • Figures 32 (a) to 33 ( ⁇ 1) are The input signal is a signal with a constant voltage V ⁇ n.
  • the voltage V ⁇ n is 0.9 V, 1.0 V, 1.2 V, 1.5 V, 2 V, 3 V, 5 V, respectively. It is set to 7 V and 10 V.
  • the voltage conversion circuit 30 divides the voltage of the input terminal pin n into about 1/2.
  • FIG. 34(a) and FIG. 34( ⁇ ) are diagrams showing frequency and period with respect to the input voltage in Example 5, respectively.
  • the higher the voltage V In the higher the frequency of the spike signal 52.
  • the higher the voltage V ⁇ n the shorter the cycle in which the spike signal 52 is generated. If the voltage V ⁇ n is smaller than the threshold voltage V ⁇ n t, the spike signal 52 is not generated.
  • V ⁇ n 1 is about 1 V.
  • the voltage of the input signal to be input is the threshold voltage V ⁇ n
  • the spike generation circuit 1114 functions as a determination circuit that determines the voltage of the input terminal gate n.
  • the number of input spike signals for outputting the spike signal 52 can be set by setting the capacitance value of the capacitor ⁇ 1.
  • the spike generation circuit 1 1 1 4 functions as a circuit that converts the voltage of the input terminal pin n into the frequency of the spike signal 5 2.
  • the threshold voltage V ⁇ n 1 II can be arbitrarily set by the ratio of the resistance values of the mating plates 3 1 3 and 3 1 of the voltage conversion circuit 30.
  • the voltage conversion circuit 30 may be a circuit other than the resistance voltage dividing circuit as long as it is a circuit that divides the voltage of the input signal.
  • the voltage conversion circuit 30 outputs a signal obtained by dividing the voltage of the input signal to the node 1 ⁇ 11.
  • the inverting circuit 18 outputs the spike signal 52 when the absolute value of the voltage of the input signal is larger than the threshold voltage V ⁇ n 1 II (specified value), and spikes when the voltage of the input signal is V ⁇ n 1 II or less. Do not output signal 52. In this way, a voltage determination circuit with low power consumption can be realized. ⁇ 02020/175209 50 units (: 171?2020/006045
  • FIG. 35 is a circuit diagram of the spike generation circuit according to the first modification of the fifth embodiment. As shown in FIG. 35, in the spike generation circuit 1 1 14 3 of Modification 1 of Embodiment 5, the spike generation circuit of Modification 3 of Embodiment 3 is provided with the voltage conversion circuit 30. The other configuration is the same as that of the fifth embodiment, and the description is omitted.
  • the inverting circuit 18 outputs the spike signal 5 2 when the absolute value of the voltage of the input signal is smaller than the threshold voltage, and the voltage of the input signal is V ⁇ n 1 * When 1 or more, spike signal 52 is not output.
  • FIG. 36 ( 3 ) is a circuit diagram of the spike generation circuit according to the second modification of the fifth embodiment. As shown in Fig. 36 ( 3 ), in the spike generator circuit 1 1 4 of the second modification of the fifth embodiment, one end of the capacitor 0 1 is connected to the input terminal pin n and the capacitor (3 1 The end is connected to the node 1 ⁇ ! 1. The other configuration is the same as that of the third embodiment, and the description is omitted.
  • FIG. 36 (distance) is a timing chart of the second modification of the fifth embodiment.
  • the voltage of the input signal input to the input terminal pin n changes with time.
  • the low frequency component of the input signal is 3.5V.
  • the low frequency component of the voltage at node 1 ⁇ 1 1 is blocked by capacitor ⁇ 3 1.
  • the voltage at node 1 ⁇ 1 1 becomes the amount of change in the input signal (voltage excluding the DC component).
  • the size of node 1 ⁇ 11 can be set arbitrarily according to the size of capacitor ⁇ 1. That is, the capacitor 0 1 functions as a voltage conversion circuit.
  • the amount of change from the low-frequency component of the input signal reaches 3 V at time 130, the voltage at node 1 ⁇ 11 becomes V I. As a result, a spike signal is output from the output terminal.
  • the inverting circuit 18 generates the spike signal 52 when the amount of change from the low frequency component of the input signal is within the predetermined range, and outputs the spike signal 52 when the change is outside the predetermined range. Do not generate spike signal 52.
  • the voltage conversion circuit 30 (or ⁇ 02020/175209 51 ⁇ (: 171?2020/006045
  • Is a capacitor ⁇ 1) outputs the signal which converted the voltage of the input signal to node 1 ⁇ ] 1.
  • the inverting circuit 18 does not output the spike signal 52 when the voltage of the input signal is within the predetermined range, and outputs the spike signal 52 when the voltage of the input signal is outside the predetermined range. As a result, a low power consumption voltage determination circuit can be realized.
  • FIG. 37 is a circuit diagram of the spike generation circuit according to the third modification of the fifth embodiment.
  • the knife 3 3 is connected between the capacitor ⁇ 1 and the input terminal hinge n. Since Mitsumi 33 is turned off, it functions as a high resistance between the source and drain.
  • the counter 3 3 and the capacitor 0 1 form a time constant circuit 3 2 which is the input circuit 10.
  • the time constant circuit 3 2 long rise time constant of the input signal input to the input terminal Ding ⁇ n.
  • the time constant for the rise of the voltage at node 1 ⁇ 11 is the time constant determined by Ming 3 3 and capacitor O 1.
  • the other configuration is the same as that of the third embodiment, and the description is omitted.
  • An input signal was input to the input terminal pin n to simulate the voltage of the node 1 ⁇ ! 1 and the spike signal 52 output to the output terminal pin.
  • the capacitance value of the capacitor 0 1 is set to 5.75.
  • As the input signal a signal that changes from the mouth level to the high level in a sufficiently short time compared to the time constant of the time constant circuit 32 was input.
  • FIG. 38(a) and FIG. 38( ⁇ ) are diagrams showing the voltage and the output voltage of the node 1 ⁇ 11 with respect to time in the third modification of the fifth embodiment.
  • Figure 38 (Small) is an enlarged view of Figure 38 (a).
  • the voltage of node N 1 rises with the time constant of time constant circuit 32.
  • the spike signal 52 is output to the output terminal.
  • the spike signal is shown in Fig. 38 (10).
  • the rising and falling edges are steep.
  • the spike generation circuit 1 16 has the high level at the input terminal pin n. ⁇ 02020/175209 52 Approximately (:171?2020/006045 Functions as a delay circuit that outputs spike signal 5 2 after delaying for a predetermined time after the signal is input.
  • the output spike signal 52 is short and steep.
  • the time constant circuit 3 2 may be a circuit other than ⁇ 3 as long as it is a circuit that lengthens the time constant of rising and/or falling of the input signal. It can be set arbitrarily by changing the time constant of 3 2.
  • the time constant circuit 32 lengthens the rising time constant of the input signal and outputs it to the node 1 ⁇ 11.
  • the output terminal outputs a spike signal 52 after a delay time related to the time constant of the time constant circuit 32 after the input signal is input.
  • a modified example 4 of the fifth embodiment is an example in which the second and third modified examples and the modified examples thereof are used in the frequency decrease detection circuit that generates the spike signal 52 when the frequency of the incoming spike signal 50 decreases.
  • FIG. 39 is a circuit diagram of the spike generation circuit according to the fourth modification of the fifth embodiment. As shown in FIG. 39, in the spike generation circuit 1 18 of Modification 4 of Example 5, the suppression circuit 3 4 is connected between the capacitor 0 1 and the input terminal gate.
  • the input circuit 10 includes a suppression circuit 34 and a capacitor (3 1 ).
  • the suppression circuit 34 is provided with knives 353, 335 and knives 305.
  • Ming 35, 35 and Ming 3500 are connected in series between the ground line 26 and the power line 28.
  • Node 1 ⁇ 1 1 2 between Mending 3 5 6 and Mending 3 5 0 is connected to Capacitor 0 1.
  • the gate of Mending 3 5 3 is connected to the drain and the gate of Mending 3 5 3 is connected to the source.
  • Mending 3 5 3 and Mending 3 5 0 function as loads.
  • the input terminal ⁇ n is connected to the gate of the shunt.
  • the suppression circuit 34 functions as a source ground circuit.
  • the capacitor 0 1 is charged by the current flowing from the power line 28 to the capacitor 0 1 via the Ming 3 0 5.
  • the switch 3 5 turns on and the voltage of the node ! ⁇ 1 1 2 drops.
  • the voltage of the node 1 ⁇ 1 1 2 (that is, 1 ⁇ 1 1) drops moderately, so that the voltage of the node 1 ⁇ 1 1 does not reach the threshold voltage V I.
  • the frequency of the spike signal 50 decreases, the voltage of the node 1 ⁇ 1 12 increases and the threshold voltage V 1: II is reached.
  • the spike signal 5 0 was input to the input terminal pin n at a constant frequency, and the voltage of the node N 1 and the spike signal 5 2 output to the output terminal pin I were simulated.
  • Fig. 40 (a) and Fig. 40 ( ⁇ ) are diagrams showing the voltage and the output voltage of the node 1 ⁇ 11 with respect to time in the modified example 4 of the fifth example.
  • FIG. 40 (a) and FIG. 40 (extent) are diagrams when the frequencies of the incoming spike signal are 2 0 0 1 to 1 and 1 0 0 1 to 1, respectively.
  • the spike generation circuit 1 1 ⁇ 02020/175209 54 ⁇ (: 171?2020/006045
  • the spike signal 5 2 When the frequency of the Iku signal 50 becomes low, the spike signal 5 2 is output to the output terminal.
  • the frequency of the input spike signal 50 which is the threshold value for outputting the spike signal 52, can be set arbitrarily.
  • the suppression circuit 34 reduces the voltage of the node 1 ⁇ 11 when the input cascade signal 50 is input as the input signal.
  • the output terminal 1 outputs the spike signal 52 when the frequency of the input spike signal 50 becomes lower than the predetermined frequency.
  • the frequency of the incoming spike signal 50 decreases, it is possible to realize a frequency decrease detection circuit that generates the strike signal 52.
  • the suppression circuit 34 when the incoming spike signal 50 is a positive spike, when the suppression circuit 34 receives the incoming spike signal 50 as in the second modification of the fifth embodiment. , Lower the voltage of node 1 ⁇ 1 1. As in the modified example 1 of the second embodiment, when the incoming signal spike signal 50 is a spike in the negative direction, the suppression circuit 34 receives the incoming signal spike signal 50, and if the voltage of the node 1 ⁇ 11 is increased. Good.
  • FIG. 41 is a circuit diagram of a spike generation circuit according to Modification 5 of Example 5.
  • the activation circuit 3 4 3 includes the Ming 3 5 5, the Ming 3 5 6, 3 5 ⁇ and the inverter. It has 3 59. Ming 3 5? Ming 3 5 6 and Ming 3 5 5 are connected in series between ground line 2 6 and power line 2 8.
  • Node 1 ⁇ ! 1 2 between Mending 3 5 and Mending 3 5 6 is connected to Capacitor 0 1.
  • the gate of Ming 35 is connected to the source and the gate of Ming 35 is connected to the drain.
  • Ming 35 and Ming 35 serve as loads.
  • the input terminal hinge n is connected to the gate of the counter 356 through the inverter 359.
  • Capacitor ⁇ 1 is charged by the current flowing from node 1 ⁇ ! 1 2 to the ground line via Mending 35.
  • Ming 3 5 6 turns on and the voltage of node ! ⁇ 1 1 2 rises.
  • the voltage of node 1 ⁇ 1 1 2 rises reasonably, so that the voltage of node 1 ⁇ 1 1 reaches the threshold voltage V 1 and the spike signal 5 2 Is generated.
  • the frequency of the spike signal 50 becomes low, the voltage of the node N 1 2 becomes low, and the voltage of the node 1 ⁇ 1 1 does not reach the threshold voltage V 1.
  • the activation circuit 3 4 when the input Kasupaiku signal 5 0 is inputted as an input signal, to increase the node 1 ⁇ 1 1 voltage.
  • the output terminal output outputs the spike signal 52 when the frequency of the input spike signal 50 becomes higher than the predetermined frequency.
  • the suppression circuit 34 and the activation circuit 343 receive the input spike signal 50 as an input signal. Increase or decrease the voltage of 1.
  • the inverting circuit 18 outputs the spike signal 52 when the frequency of input of the spike signal 50 is within the predetermined range, and does not output the spike signal 52 when the frequency is outside the predetermined range. In this way, it is possible to realize a frequency detection circuit that generates the spike signal 52 based on the frequency of the spike signal 50.
  • FIG. 42 ( 3 ) is a circuit diagram of the spike generation circuit according to the modified example 6 of the fifth embodiment.
  • the input circuit 10 has a capacitor ⁇ 1 and a knife 3 3 3.
  • the source of Ming 3 3 3 is connected to ground line 26 and the drain is connected to node N 1.
  • the gate of Mitsumi 3 3 3 is connected to the source.
  • Ming 3 3 3 functions as a resistor through which a leak current flows.
  • the rest of the configuration is the same as that of the second modification of the fifth embodiment, and the description is omitted.
  • FIG. 42 (distance) is a timing chart of the modified example 6 of the fifth embodiment.
  • Figure 4
  • the voltage of the terminal 1 ⁇ 11 becomes V I, and the spike signal 52 is output.
  • the input circuit 10 changes the voltage of the node 1 ⁇ 11 according to the amount of change of the input signal with time.
  • the inverting circuit 18 generates the spike signal 52 when the change amount of the input signal with respect to time is within the predetermined range, and does not generate the spike signal 52 when the change amount is outside the predetermined range. In this way, it is possible to realize a circuit that generates the spike signal 52 based on the amount of change of the spike signal 50 over time.
  • the spike generation circuit has low power consumption, and can reduce the voltage of the input signal, the frequency of the spike signal, the period after the input signal is input, and the time of the input signal.
  • a spike signal 52 can be generated based on the rate of change.
  • the sixth embodiment is an example of an information processing circuit using the first to fourth embodiments and their modifications.
  • FIG. 43 ( 3 ) to FIG. 43 ( ⁇ ) are block diagrams of the information processing circuit according to the sixth embodiment.
  • the node circuit 45 includes a condition setting circuit 42, a spike generation circuit 40, and a spike processing circuit 4 4.
  • the condition setting circuit 42 receives one or more signals V 1 (I) to 2 (I) depending on the time I.
  • the condition setting circuit 42 is a circuit that sets the conditions under which the spike generation circuit 40 outputs a spike signal. The signal output from the input signals VI (I) and V 2 (I) etc. to the spike generation circuit 40. Generates (voltage V ⁇ ).
  • the condition setting circuit 42 includes, for example, the input circuits 10 as in the second to third embodiments and their modifications.
  • the spike generation circuit 40 is, for example, the strike generation circuit of the second to third embodiments and their modifications.
  • the spike signal 52 is output based on the voltage V ⁇ n.
  • the spike processing circuit 44 is a circuit that processes the spike signal 52, and includes a logic circuit such as an inverter or a binary arithmetic circuit and/or a flip-flop.
  • the spike processing circuit 4 4 processes the spike signal 5 2 and outputs a spike signal or a signal 4 4 8 such as !-/! ⁇ 1 (mouth level and high level) signal. ⁇ 0 2020/175 209 57 ⁇ (: 17 2020/006045
  • the node circuits 45 3 to 45 5 are connected to each other, as shown in Figure 4 3 (bath).
  • the node circuits may be connected in multiple stages like the node circuits 4 5 3 to 4 5.
  • the output of the node circuit 4513 may be branched into a plurality of node circuits 450 and 45, like the node circuit 4513.
  • the outputs of a plurality of node circuits 45 and 456 may be input. In this way, the node circuits 4 5 3 to 45 form a network.
  • the signal 4 6 3 output from the node circuit 45 is input to the flip-flop 4 6.
  • Signals 468 are spike signals or mouth-level/high-level signals (ie, mouth-level or high-level binary signals).
  • the flip-flop 4 6 outputs the signal 4 6 which is a high level/high level signal based on the signal 4 6 3.
  • the V 9 generation circuit 47 generates the signal 4 73 to be output to the gate of the counter 4 8 based on the signal 46.
  • the V 9 generation circuit 47 includes, for example, a logic circuit and a booster circuit. Mingda 48 is turned on or off based on signal 478.
  • condition setting circuit 42 processes the input signal.
  • the condition that the spike generation circuit 40 outputs the spike signal is set.
  • the spike processing circuit 4 4 processes the spike signal 5 2 output from the spike generation circuit 40.
  • Such node circuits 45 are connected in a network. As a result, it is possible to realize an information processing circuit that can perform various types of information processing with low power consumption.
  • the spike signal 52 output from the spike generation circuit 40 is the event generation information indicating that the event has occurred and the event has occurred. It will include timing information indicating the time of day.
  • the spike signal 52 includes event generation information and timing information and is sent to the spike generation circuit 40 or spike processing circuit 4 4 in the next stage. ⁇ 02020/175209 58 ⁇ (: 171?2020/006045
  • the seventh embodiment is an example in which the spike generation circuits of the first to fourth embodiments and their modifications are used in the power conversion circuit as the information processing circuit of the sixth embodiment.
  • environmental power generation such as vibration power generation, which generates power by vibration
  • the current from the power generation circuit is not constant, but changes every moment.
  • Voltage of storage circuit eg capacitor
  • the output impedance of the power generation circuit is 1:1. For this reason, a mismatch occurs between the output impedance I of the power generation circuit and the input impedance I of the storage circuit.
  • impedance matching between the power generation circuit and the storage circuit is realized with low power consumption.
  • FIG. 44 is a block diagram of a power conversion circuit according to the seventh embodiment.
  • the power conversion circuit 120 is equipped with rectifier circuits 6 2 and 6 4, a judgment circuit 6 5 and a step-down circuit 6 6.
  • a power generation circuit 60 is connected to the power terminals 6 1 3 and 6 1.
  • the power generation circuit 60 generates AC power.
  • Rectifier circuits 6 2 and 6 4 are connected to the power terminals 6 1 3 and 6 1.
  • the rectifier circuits 6 2 and 6 4 rectify the output power of the generator circuit 60.
  • the step-down circuit 6 6 steps down the output of the rectifier circuit 6 2 and outputs it to the storage circuit 6 8.
  • the rectifier circuit 64 rectifies the output power of the power generation circuit 60 and outputs it to the storage circuit 68.
  • the storage circuit 68 stores electric power.
  • the determination circuit 65 determines whether to operate the rectification circuits 6 2 or 6 4 based on the output of the rectification circuit 6 2.
  • the decision circuit 6 5 operates the rectifier circuit 6 2 and the step-down circuit 6 6, and the rectifier circuit 6 5 operates. ⁇ 02020/175209 59 ⁇ (: 171?2020/006045
  • the judgment circuit 6 5 operates the rectification circuit 6 4 and does not operate the rectification circuit 6 2 and the step-down circuit 6 6.
  • FIG. 45 is a diagram for explaining the operation of the determination circuit in the seventh embodiment.
  • the output impedance of the power generation circuit 60 ⁇ ri 1: is, for example, from 1 ⁇ ⁇ to 1 in the case of vibration power generation using piezo materials or electret materials. , But here is 1.
  • the power generation current of the power generation circuit 60 is 10 1 ⁇ 8 and 1 0 1 ⁇ 8.
  • the input impedance ⁇ n of the power conversion circuit 1 20 is Becomes
  • the input impedance I of the power conversion circuit 1 2 0 is and Becomes
  • the determination circuit 6 5 causes the rectification circuit 6 4 to operate.
  • the rectifier circuit 64 rectifies at 1 V.
  • the input impedance n of the power conversion circuit 120 becomes 1 0 0 1 ⁇ /10.
  • the rectified power is stored in the storage circuit 68.
  • the decision circuit 6 5 operates the rectifier circuit 6 2 and the step-down circuit 6 6.
  • the rectifier circuit 6 2 rectifies the power with 10.
  • the input impedance n of the power converter circuit 120 becomes 1.
  • the step-down circuit 6 6 steps down the rectified 10 V power to 1 V.
  • the reduced power is stored in the storage circuit 68.
  • the input impedance of 1 20 can be matched.
  • a diode predge circuit is used as the rectifier circuit 62. Since the rectifier circuit 62 rectifies a high voltage (for example, 10 ), power consumption is low due to the diode turn-on voltage. Since the rectifier circuit 64 rectifies low voltage, power consumption increases due to the diode on-voltage of the diode if a ridge circuit is used. Therefore, a synchronous rectifier circuit is used as the rectifier circuit 64. ⁇ 02020/175209 60 box (: 171?2020/006045
  • FIG. 46 (3) to FIG. 46 (o) are diagrams showing the symbols of the spike generation circuit in the seventh embodiment. 4 6 (3), the terminal under the spike generation circuit 7 4 3 Ri input terminal 7 5 3 der, terminals above are output terminals 7 6 3.
  • Spike generation circuit 7 4 3 is a voltage determining circuit of Embodiment 5.
  • the 8 V in the circle indicates that the threshold voltage V ⁇ n I is 8 V.
  • the lower terminal of the spike generator 74 is the input terminal 75, and the upper terminal is the output terminal 76.
  • the spike generator 74 is a delay circuit of the first modification of the fifth embodiment. 1 0 0 n 3 in the circle is the delay time Is shown.
  • the lower terminal of the spike generation circuit 74 0 is the input terminal 75 0, and the upper terminal is the output terminal 7 60.
  • the spike generation circuit 740 is the frequency drop detection circuit of the second modification of the fifth embodiment. Within the circle It shows that the circuit is a low frequency detection circuit.
  • FIGS. 47(a) to 47(o) are diagrams showing the operation of the flip-flop circuit in the seventh embodiment.
  • the flip-flop circuit () 70 has input terminals 7 1 3 , 7 1 and output terminals 7 2 3 and 7 2.
  • the circuit 70 when the signal 7 3 is input to the input terminal 7 1 3, the circuit 70 outputs high level to the output terminal 7 2 3 and high level to the output terminal 7 2 3. Output.
  • the signal 73 is a positive spike signal or a high level signal.
  • the circuit 70 keeps the output terminal 7 2 3 at the mouth level and the output terminal 7 2 at the high level until the signal 7 3 is input to the input terminal 7 1 next time.
  • FIG. 48 is a circuit diagram of the determination circuit according to the seventh embodiment.
  • FIG. 49 is a diagram showing the voltage of each node of the determination circuit with respect to time in the seventh embodiment.
  • node No. 1 is the output of rectifier circuit 62.
  • Node M4 outputs the step-down operation spike.
  • Node 2.8 outputs a switching spike signal that stops the operation of step-down circuit 6 6 and starts the operation of rectifier circuit 6 4.
  • the node 129 outputs a switching signal which is high level when the rectifying circuit 62 and the step-down circuit 6 6 are operated and is high level when operating the rectifying circuit 64.
  • the rectifier circuit 6 2 and the step-down circuit 6 6 are operating, and the rectifier circuit 6 4 is stopped.
  • the voltages of nodes No. 4, No. 2 6, No. 2 7 and No. 2 7 and No. 2 8 are at the high level, and the voltage of No. 2 9 is at the high level.
  • the spike generation circuit X 4 outputs the spike signal 8 0 to the node node 4 as the step-down operation spike signal.
  • the number of times node No. 1 becomes 8 V or more decreases.
  • the frequency of spike signal 80 at node #4 decreases.
  • the spike generation circuit 38 When the frequency of the spike signal 80 of the node node 4 drops below a predetermined level, the spike generation circuit 38 outputs the spike signal 8 1 to the node node 26 at time 0 2.
  • the circuit 40 which receives the spike signal 81, outputs a high level to the node 275. As a result, the input of the spike generation circuit 41 goes from the mouth level to the high level.
  • the spike generation circuit X 4 1 outputs the spike signal 8 2 to the node node 2 8 at time I 0 3 1 0 0 n 3 after the node node 2 7 becomes high level.
  • the circuit 40 to which the spike signal 8 2 is input changes the node node 2 7 from high level to mouth level.
  • the circuit 3 7 to which the spike signal 8 2 is input has the node 2 9 as the mouth level.
  • Switching spike signal and switching signal can be generated using the spike generator circuit of
  • the determination circuit that determines whether the voltage of the node 1 is equal to or higher than a predetermined voltage can be realized by using a comparator or the like. However, using a comparator in the decision circuit increases power consumption. In the seventh embodiment, the determination circuit is realized by using the second to third embodiments and their modifications, so that the power consumption can be reduced.
  • FIG. 50 is a circuit diagram showing a rectifier circuit 62 according to the seventh embodiment. As shown in Figure 50, Has a gate connected to the drain and functions as a diode.
  • the rectifier circuit 62 is a diode bridge circuit.
  • the input terminal of the diode bridge circuit is connected to the power terminals 6 1 3 and 6 1.
  • Power terminals 6 1 3 and 6 1 have a current source of AC current I 1 and 1 corresponding to the generator circuit 60. Is connected.
  • the output of the diode bridge circuit is connected to node No. 1 in Fig. 48 (corresponding to node 8 in Fig. 5 1 (a) described later).
  • FIG. 5 1 (3) to FIG. 5 1 ( ⁇ ) are schematic diagrams of the step-down circuit according to the seventh embodiment.
  • the output of the rectifier circuit 6 2 is node 8.
  • Capacitor ⁇ 1 and ⁇ 1 ⁇ / 14 are connected in series between node 8 and ground.
  • Capacitor ⁇ 1 is the primary capacitor. Micho 1/14 is a switch.
  • Inductor !_ 1 and capacitor 0 4 are connected in series between node 8 and ground.
  • Capacitor ⁇ 4 is a secondary capacitor and corresponds to power storage circuit 68.
  • Ming 1/13 is connected as a switch between the inductor !_ 1 and the capacitor 04.
  • a switch 1//12 is connected as a switch.
  • capacitors ⁇ 1 and ⁇ 4 are set to 100 and 10 nF, respectively, and the inductance of inductor !_ 1 is 0.3 0.3! ⁇ 1 Micho! ⁇ /1 4 ⁇ 02020/175209 63 ⁇ (: 171?2020/006045
  • FIG. 52 is a circuit diagram of the step-down circuit according to the seventh embodiment.
  • Figure 53 shows an example
  • FIG. 7 is a diagram showing the voltage of each node of the step-down circuit with respect to time in 7.
  • FIG. As shown in Figures 52 and 53, at times I 1 1 to 1: 12 the voltage at node 8 has not reached 8 V. During this time, node ⁇ is at mouth level. When node ⁇ is at the mouth level, Ming 1/13 is turned off, and when node ⁇ is at the high level, Ming 1/13 is turned on. Therefore, between time I 1 1 and 1: 1 2, Mending 1 ⁇ /1 3 is off. Current I passing right through inductor !- 1 1 is 0. The output of the rectifying circuit 62 charges the capacitor ⁇ 1, and the voltage at node 8 increases. ⁇ 02020/175209 64 ⁇ (: 171?2020/006045
  • Mending 1/13 The operation of Mending 1/13 will be described.
  • the threshold voltage of Mending 1 ⁇ /1 3 and 1 ⁇ /1 7 is 0.4 V.
  • Ming 1/17 functions as a forward direction node from node ⁇ .
  • the gate of Mending 1 ⁇ /1 3 is about 10 V lower than the voltage at the node at one end of capacitor 04, which is equivalent to the diode turn-on voltage. Therefore, Mincho 1 ⁇ /1 3 is turned off.
  • the decision circuit 65 outputs the step-down operation spike signal 80 to the node NO.
  • Circuit X 24 outputs a high level to node ⁇ .
  • the gate of Mending 1 ⁇ /1 3 is about +0.7 V higher than the voltage at node [3 ⁇ 4, and Mending 1 ⁇ /1 3 turns on. This allows the current to flow through inductors 1-1. Begins to flow.
  • the step-down operation spike signal 80 is input to the node C of the circuit X21.
  • Circuit X 21 outputs a high level to node ⁇ and a mouth level to one end of capacitor ⁇ 2.
  • the spike generation circuit 2 8 outputs the spike signal 8 3 to the node 1 3 after the time 1 1 2 to 1 3 when the node ⁇ becomes high level.
  • the circuit X 21 outputs a high level to the node ⁇ and a high level to one end of the capacitor ⁇ 2.
  • node ⁇ goes high during the period 1/X between times 12 and 1:13, and goes high during other periods.
  • Node 0 is connected to ground through the Ming IV! 6 which functions as a diode.
  • Nordro becomes a negative voltage between time 12 and 1:13, and becomes ⁇ in other periods (including time 13 and after).
  • Ming 1//1 4 whose gate is connected to Nordro is turned on between times I 1 2 and 1:1 3.
  • Mite 1 ⁇ /1 4 and Mite 1 ⁇ /1 3 are turned on at the same time, resulting in the connection relationship shown in Fig. 5 1 (13).
  • the charge stored in the capacitor ⁇ 1 flows to the node 8 as a current ⁇ - ⁇ 1.
  • the current value ⁇ 1 becomes the current value that passes through the inductor 1-1, and charges the capacitor ⁇ 4.
  • Ding 1 ⁇ /1 1 is a switch for operating the step-down circuit 66, but its explanation is omitted.
  • Mingda 1 ⁇ /1 1 0 and 1 ⁇ /1 1 1 function as voltage limiters to prevent node 8 from a negative high voltage and breaking the circuit.
  • the circuit X34 sets the node to the high level.
  • the spike generation circuit X 3 2 outputs a spike signal 8 4 to the node ⁇ at time I 1 4 delayed by 13 from time I 1 3 when the node becomes high level.
  • the node is high level and nodes 1 to 1 are mouth level, so the X ⁇ circuit X 23 outputs high level to the node ⁇ 3 ⁇ .
  • the spike signal 84 is input to the circuit 26 at time 14 the circuit 26 outputs a high level to the nodes 1 to 1.
  • the X ⁇ ⁇ circuit X 2 3 Output mouth level to ⁇ .
  • Inverter X 3 5 is node ⁇ 3
  • the signal of ⁇ is inverted and output to one end of the capacitor ⁇ 5.
  • the node connected to the other end of the capacitor 05 is connected to the ground through Ming 1/18, which functions as a diode. Therefore, the node voltage is ⁇ when the node ⁇ 3 I 6 is at the mouth level, and is a negative voltage when the node ⁇ 3 16 is at the high level. That is, the node voltage becomes a negative voltage between time 13 and 1:14, and the node voltage becomes 0 V between time I14 and 1:15.
  • Mincho 1 ⁇ /15 connected to I turns on between times I 13 and 1:1 4 and turns off between times 14 and 1:1 5.
  • Circuit X 29 is node ⁇ and node ⁇ 02020/175209 66 ⁇ (:171?2020/006045
  • Mincho 1 ⁇ /19 is connected to a constant voltage source V 22 of 1 V.
  • V 22 of 1 V.
  • Ming 1/19 is turned off, and in the other period, Ming 1/19 is turned on.
  • Ming IV! 9 turns on and the node” becomes high level (IV).
  • the capacitor 06 has one end connected to the node 8 and the other end connected to the node ".
  • the capacitor 0 6 is charged by the potential difference between node 8 and.
  • the node becomes a negative voltage.
  • the inverter X 36 inverts the voltage of the node "and outputs it to the node ⁇ .
  • the spike generation circuit X 30 sends spike signal 8 5 to the node when the voltage of the node ⁇ becomes 0.5 V or higher! -Output to.
  • ⁇ [3 ⁇ 4 Circuit 3 1 is a node! -And output ⁇ [3 ⁇ 4 of node 1 ⁇ 1 to circuit X 26. At time I 15 the voltage on node ⁇ is about 10.
  • the voltage at node ⁇ is above +0.5 V.
  • the spike generation circuit 30 outputs the spike signal 8 5
  • ⁇ [3 ⁇ 4 circuit 3 1 outputs the spike signal 8 5 to the circuit 2 6.
  • the circuit 26 sets the nodes 1 to 1 to the mouth level. Node ⁇ 8 ⁇ becomes high level.
  • the node ⁇ 3 16 goes high during the period of 13 and the period from when the PF o 1/19 is turned off until the node becomes approximately 10.5 V or less. It becomes a mouth level. While the current of inductor !_ 1 -1 — 1 is flowing, node ⁇ 3 ⁇ repeats high level and mouth level.
  • the spike generation circuit X 27 outputs the spike signal 86 to the node 1 ⁇ 1.
  • the circuit 24 outputs the mouth level to the node ⁇ . Ming 1/13 turns off and the step-down operation of step-down circuit 6 6 ends.
  • Fig. 54 is a diagram showing the voltages of the nodes 8 and 8 with respect to time in Example 7.
  • Fig. 53 shows, for example, the operation within the range of Fig. 54.
  • the step-down operation starts between time 1 1 1 and 1: 1 7.
  • the voltage of node 8 decreases and the voltage of node increases.
  • the step-down operation starts.
  • the charge is accumulated in the capacitor ⁇ 1 and the voltage of the node 8 rises.
  • the voltage of the node rises and the capacitor ⁇ 4 is charged.
  • FIG. 55 (a) to 55 (o) are schematic diagrams of the synchronous rectification circuit in the seventh embodiment.
  • Fig. 5 5 (10) and Fig. 5 5 ( ⁇ ) electrical connections are shown by solid lines, and electrical interruptions are shown by broken lines.
  • the power terminal 6 1 3 is connected to the positive terminal 6 8 3 of the capacitor ⁇ 4 via the pass gate X9, and the power gate 6 8 3 is connected. It is connected to the negative terminal 68 (eg ground) of capacitor 04 via X 10.
  • the power terminal 6 1 13 is connected to the positive side terminal 6 8 3 of the capacitor ⁇ 4 via the pass gate X 1 2 and to the negative side terminal 6 8 13 of the capacitor ⁇ 4 via the pass gate XI 1. ⁇ 02020/175209 68 ⁇ (: 171?2020/006045
  • Passgates X9 and XI1 turn on when voltages V3 and V4 are mouth level and high, respectively, and turn off when voltages V3 and V4 are high level and mouth-level, respectively. .. Passgates X I 0 and X I 2 turn on when voltages V 3 and V 4 are high and mouth-level, respectively, and turn off when voltages V 3 and V 4 are mouth-level and high, respectively.
  • FIG. 56 is a circuit diagram of the synchronous rectification circuit in the seventh embodiment.
  • FIG. 57 is a diagram showing the voltage of each node of the synchronous rectification circuit with respect to time in Example 7. As shown in Fig. 5 6 and Fig. 5 7, after time I2 1, the alternating current ⁇ 1 from the generator circuit 60 is at the power terminals 6 1 8 and 6 1. To enter. The terminal resistance between the power terminals 6 1 8 and 6 1 Is.
  • the spike generation circuit X 5 spontaneously sets 1 Every 3 spike signal 8 7 voltage V
  • the circuit X 2 sets the voltages V 5 and V 6 to the high level and the mouth-level, respectively. This turns off passgates X 13 and X 15 and turns on passgates X 7 and X 8.
  • the power terminals 6 1 3 and 6 1 are positive and negative, respectively.Therefore, when the pass gates X 1 3 and X 15 are turned off, the voltage V 1 rises due to the current input from the generator circuit 60. Voltage 2 ⁇ 02020/175209 69 ⁇ (: 171?2020/006045
  • the spike generation circuit 3 When the voltage V I exceeds 0.5 V, the spike generation circuit 3 outputs the spike signal 88 to the voltage V I 0 at time I 23. The spike generation circuit 4 does not output the spike signal.
  • ⁇ [3 ⁇ 4 Circuit 6 outputs spike signal 88 to circuit X 2. As a result, the circuit 2 sets the voltages 5 and 6 to the high level and the high level, respectively. Passgates X I 3 and X I 5 turn on and passgates X 7 and X 8 turn off. For example, between 10 22 and 1 23 is 10 0 3.
  • the spike generation circuit 3 outputs the spike signal 88, and the spike generation circuit X 4 does not output the spike signal. Therefore, the circuit X 1 outputs the voltages V 3 and V 4, respectively. -Maintain high level and high level.
  • the power terminals 6 13 and 6 1 become negative voltage and positive voltage, respectively.
  • the pass gates X I 3 and X I 5 are turned off, the voltage V 2 rises and the voltage V 1 falls due to the current input from the generator circuit 60.
  • the spike generation circuit 4 outputs the spike signal 89 to the voltage V 11 1.
  • the spike generation circuit X 3 does not output the spike signal.
  • the spike signal 89 output from the spike generation circuit X 4 is input to the circuit X 1. ⁇ 02020/175209 70 ⁇ (:171?2020/006045
  • Circuit X 1 then raises voltages V 3 and V 4 to high and mouth level, respectively.
  • Passgates X 9 and X I 1 turn off and passgates X I 0 and X 1 2 turn on.
  • the power terminals 6 1 3 and 6 1 are connected to the negative terminal 6 8 and the positive terminal of the capacitor 0 4, respectively.
  • pass gates X13 and X15 turn on, such as between time 26 and 27, the current of capacitor ⁇ 4 flows and capacitor ⁇ 4 flows. 4 is charged. After that, when the power terminals 6 13 and 6 1 become positive voltage and negative voltage, respectively, repeat from time 1 2 2.
  • FIG. 58 is a diagram showing the charging voltage of the capacitor by the synchronous rectification circuit with respect to time in Example 7.
  • the voltage of the capacitor 04 was simulated by using the current from the power generation circuit 60 as an alternating current with a maximum amplitude of 108. As shown in Fig. 58, even with a very small current with a maximum amplitude of 10 1!
  • the power converter circuit of Example 7 was simulated.
  • the simulated circuit is a circuit including the decision circuit 65, the rectifier circuits 6 2 and 6 4, the step-down circuit 6 6 and the storage circuit 6 8 which have been described, and has 18 spike generator circuits and 17 circuit circuits. Includes approximately 340 Mitsuba.
  • Fig. 59 is a diagram showing a generated current and a voltage of a capacitor with respect to time in Example 7.
  • the generator circuit 60 generates an alternating current ⁇ 1 with a maximum amplitude of 500 n 8 in periods 1 and 3, and a maximum amplitude of 40 8 in period 2. Generates 1 AC current of.
  • the decision circuit 6 5 operates the rectifier circuit 6 2 and the step-down circuit 6 6.
  • the voltage of the capacitor ⁇ 4 in the storage circuit 68 increases and is stored in the storage circuit 68.
  • the input impedance of the rectifier circuit 62 becomes higher than the output impedance of the generator circuit 60 because the current generated by the generator circuit 1 becomes small. Therefore, the determination circuit 65 switches from the rectifier circuit 6 2 to the synchronous rectifier circuit 6 4 spontaneously. As a result, the input impedance of the synchronous rectification circuit 64 and the output impedance of the power generation circuit 60 are almost matched. Therefore, the electricity is stored in the electricity storage circuit 68 as indicated by an arrow 58 in the period T 2.
  • the input impedance of the synchronous rectifier circuit 64 becomes lower than the output impedance of the generator circuit 60 because the current generated by the generator circuit 1 becomes large. Therefore, the decision circuit 65 switches spontaneously from the synchronous rectification circuit 6 4 to the rectification circuit 6 2. As a result, the input impedance of the rectification circuit 62 and the output impedance of the power generation circuit 60 are almost matched. Therefore, in the period T 3, electricity is stored in the electricity storage circuit 68.
  • the power for controlling the power conversion circuit can be reduced to 1 nW or less.
  • This control power is three orders of magnitude lower than when a similar power conversion circuit is implemented using control C (Integ rated Circuit). Therefore, even if the power generated by the power generation circuit 60 is as small as a few nW, it is possible to realize a power conversion circuit capable of storing electricity.
  • the rectifier circuits 62 and 64 rectify the input power.
  • the determination circuit 65 includes the spike generation circuits of the first to third embodiments and their modifications, and causes one of the rectification circuits 62 and 64 to rectify the power.
  • the spike generation circuits of the second to third embodiments and their modifications it is possible to realize the determination circuit 65 with low power consumption. Therefore, it is possible to rectify a minute electric power of about nW.
  • the control circuit for controlling the ON/OFF of the NFETs M3 to M5 includes the spike generation circuits of Examples 2 to 3 and their modifications.
  • the control circuits for controlling the on/off states of the pass gates X9 to X12 are the same as those in Examples 2 to 4 and ⁇ 02020/175209 72 ((171?2020/006045
  • the step-down circuit 6 6 and the synchronous rectification circuit 6 4 have been described as an example of the power conversion circuit using the spike generation circuits of Examples 2 to 3 and the modifications thereof. It may be a step-down circuit, a step-up circuit, a DC/AC power conversion circuit or an AC/DC power conversion circuit having the configuration.
  • Example 8 and its modification 1 are examples in which the spike generation circuits according to Examples 1 to 4 and its modification are used for a threshold value judgment circuit (voltage judgment circuit).
  • the single-shot spike signal is a signal in which the interval of the spike signal is sufficiently wide with respect to the pulse width of the spike signal, and for example, the pulse width is 1 with respect to the interval of the spike signal. It is less than or equal to 10 and less than or equal to 1/100.
  • FIG. 60 (3) is a circuit diagram of the spike generation circuit according to the eighth embodiment.
  • the spike generation circuit 1 5 1 includes an input circuit 1 0 and an output circuit 1 5 0.
  • the input circuit 10 has a voltage conversion circuit 30 3 and a capacitor 0 1.
  • Voltage conversion circuit 3 0 3 is element 3 7 3 7 sip and resistance
  • Has 3 70 The elements 37 3 and 37 are connected in series between the input terminal gate n and the ground wire 26. Elements 3 7 3 and 3 7 A resistor 370 is connected between the node 1 ⁇ 1 1 between and and the output node 1 ⁇ ] ⁇ of the input circuit 10. Capacitor ⁇ 1 is connected between output node 1 ⁇ ! ⁇ and ground line 26.
  • the output circuit 150 is, for example, the spike generation circuit of the first embodiment and its modification.
  • the output node 1 ⁇ ! ⁇ of the input circuit 10 is connected to the intermediate node 1 ⁇ 1 ⁇ of the output circuit 150.
  • the voltage of the input signal input to the input terminal pin n is divided by the elements 3 7 3 and 37, and the divided voltage is output to the node 1 ⁇ ! 1 1 and the output node 1 ⁇ 1 ⁇ Is output.
  • the voltage conversion circuit is the same as in the fifth embodiment and its first modification. ⁇ 02020/175209 73 ⁇ (: 171?2020/006045
  • the output circuit 150 outputs a single spike signal when the voltage of the input signal is equal to or higher than the predetermined voltage, and does not output the spike signal when the voltage of the input signal is lower than the predetermined voltage.
  • the output circuit 150 outputs a single-shot spike signal when the voltage of the input signal is equal to or lower than the predetermined voltage, and does not output the spike signal when the voltage of the input signal is higher than the predetermined voltage.
  • the devices 373 and 37 may be any device that divides the voltage of the input signal, and for example, a resistor, a diode or a transistor can be used. Also, the element 3 7 3 may function as a constant current element.
  • the parasitic capacitance of the devices 3 7 3 and 37 is large, a spike signal with a clean waveform may not be generated. Therefore, by providing the resistor 370, the parasitic capacitance of the elements 373 and 37 can be made difficult to see from the output circuit 150. Therefore, a spike signal with a clean waveform can be generated.
  • the product of the capacitance value of the capacitor 0 1 and the resistance value of the resistor 37 0 is the spike output by the output circuit 1 50. It is preferably larger than the width of the signal.
  • FIG. 60 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the first modification of the eighth embodiment.
  • the voltage conversion circuit 300 has the diodes 376, 379 and the knife 370.
  • Two diodes 3 7 9 are connected in the forward direction between the input terminal gate n and the node N 1 1, and the diode 3 7 6 is connected between the node 1 ⁇ 1 1 1 and the ground line 2 6. Is connected in the forward direction.
  • Diode 3 7 6 and 3 7 9 may be a transistor diode connected to the gate of Mihinoto source.
  • Input signal inputted to the input terminal Ding ⁇ n is resistively divided by the diode 3 7 9 3 7 6 with.
  • One or both of the source and drain of Mita 3 7 are connected to node 1 ⁇ 1 1 1 and the other of the source and drain are connected to node 1 ⁇ 1 10.
  • the gate is connected to the power line 28.
  • Mincho 3 7 functions as a resistance.
  • the other structure is the same as that of the eighth embodiment, and the description is omitted. ⁇ 02020/175209 74 ⁇ (:171?2020/006045
  • each diode 3 7 6 and 3 7 9 Since the voltage applied to both ends of each diode 3 7 6 and 3 7 9 When than sufficiently small forward voltage of the diode (voltage drop), the current flowing through each diode 3 7 6 and 3 7 9 very small
  • the power consumed by the voltage conversion circuit 300 can be reduced to n W or less. For example-out maximum voltage 1 V Noto input signal, when the forward voltage of the diode 3 7 6 and 3 7 9, ⁇ . About 8 V, the current through the diode 3 7 6 and 3 7 9 becomes very small ..
  • Each of the diodes 3 7 6 and 3 7 9 may be connected opposite direction. However, the forward current of the diode has a small variation due to the element, and the reverse current has a large variation due to the element. Therefore, it is preferable to connect the diodes 376 and 379 in the forward direction. Resistor elements may be used as the elements 373 and 37 of Example 8. However, it is difficult to manufacture a resistance element having high resistance. Therefore, it is preferable to use the forward-connected diodes 3 7 6 and 3 7 9 as in the first modification of the eighth embodiment.
  • the resistance 3700 of Example 8 is formed of a resistance element, it is difficult to manufacture the high resistance resistor 3700.
  • the on-resistance of Mingcho as resistance 3700, it is possible to realize resistance 3700 with an appropriate resistance value. For example, assuming that the number 37 is the source, and the voltage of the power line 28 is 1 V, and the threshold voltage of the source 3 is about 0.8, the source and drain of the source 3 7 Resistance between 1 Is over
  • FIG. 61 ( ⁇ ) and FIG. 61 (10) are circuit diagrams of spike generation circuits according to Modifications 1 and 1 of Example 8 used for simulation, respectively.
  • the voltage conversion circuit 30 of the modified example 1 of the eighth embodiment does not have a knife 37, and nodes N 1 1 and 1 ⁇ 1 Is directly connected to.
  • the output circuit 150 circuit is It is the same as the spike generation circuit in Fig. 8 of the third embodiment except that the connection of is reversed.
  • the voltage conversion circuit 30 ⁇ 02020/175209 75 ⁇ (: 171?2020/006045
  • ⁇ has 37 swords.
  • the circuit configuration of the output circuit 150 is the same as that of FIG. 61 (a) of the modification 18 of the eighth embodiment.
  • the capacity values of Kyapacita 0 1 and 0 2 were set to 2 and 4 respectively.
  • the conditions of each knife and the voltages of the power supply line 28 and the ground line 26 are the same as those in the simulation of the third embodiment.
  • FIGS. 62(a) to 62() are diagrams showing the voltage with respect to time showing the simulation result of the modified example 18 of the eighth example.
  • Figure 62 (3) shows the voltage of the output terminal, I, and I with respect to time
  • Figure 62 (I) shows the voltage of the input terminal, I, and node 1 ⁇ 11 with respect to time.
  • Fig. 62 ( ⁇ ) and Fig. 62 ( ⁇ are enlarged views of Fig. 62 (a) and Fig. 62 (b) around the time when the spike signal is output.
  • Fig. 62 ( ⁇ ) gradually increase the voltage of the input terminal gate n with respect to time.
  • the voltage of node 1 ⁇ 11 gradually increases with time.
  • the spike signal 52 is output as shown in Fig. 62(a).
  • the spike signal 52 rises gently and the waveform of the spike signal 52 is distorted. Moreover, the height of the spike signal 52 does not reach 1 V. As shown in Fig. 62 (), the voltage of the node N 1 is close to 0.5, which is different from the voltage when the normal spike signal 52 shown in Fig. 9 (b) is generated. In the modified example 18 of the example 8, it is considered that the parasitic capacitance of the diodes 376 and 379 influences the output circuit 150 and the normal spike signal 52 is not generated.
  • Figs. 63(a) to 63() are diagrams showing the voltage with respect to time showing the simulation result of the first modification of the eighth embodiment.
  • Figure 63 (3) shows the voltage at the output terminal, and the voltage at the input terminal, I, and node 1 ⁇ 11 with respect to time, as shown in Figure 63 (3).
  • Fig. 63 ( ⁇ ) and Fig. 63 ( ⁇ 1) are enlarged views of Fig. 63 (a) and Fig. 63 (well) near the time when the spike signal is output. ⁇ 02020/175209 76 ⁇ (: 171?2020/006045
  • the spike signal 52 has a steep rising edge, and the waveform of the spike signal 52 is almost the same as that of Fig. 9(a). Is. The height of spike signal 52 reaches 1 V. As shown in Fig. 63 ( ⁇ 1), the voltage of the node N 1 drops below 0.2 V after exceeding 0.8 V, and the voltage of the node 1 ⁇ ! 1 in Fig. 9 (13) decreases. It is the same as the behavior. As described above, in the first modification of the eighth embodiment, the parasitic capacitance of the diodes 3 7 6 and 3 7 9 affects the output circuit 1 5 0 by using the resistor 3 7 0 as the resistor 3 70. And a normal spike signal 52 is generated.
  • one end of the capacitor ⁇ 1 is connected to the node 1 ⁇ 11 (intermediate node), and the other end is connected to the ground line 26 (first reference potential terminal).
  • the conversion circuit 3 0 3 is composed of an element 3 7 3 (first element) and an element 3 7 (1st) connected in series between the input terminal gate n and the ground line 26 (second reference potential terminal). 2 elements) and one end connected to node 1 ⁇ 1 1 1 between elements 3 7 3 and 3 7 and the other end connected to node N 0 (output node) and a resistor 37 0.
  • Prepare The resistor 370 can suppress the influence of the parasitic capacitance of the elements 373 and 37 of the output circuit 150. Therefore, the spike signal 52 having an appropriate waveform can be generated.
  • the resistor 3 70 connected between the node N 1 1 and 1 ⁇ ! ⁇ may be a knife 37 as shown in FIG. 60 ( ⁇ ) of the first modification of the eighth embodiment.
  • the resistor 370 has almost no reactance component, and may be an element (which is called a resistance element) that passes a current that increases almost linearly with the voltage difference across the resistor.
  • the product of the resistance value of resistor 370 and the capacitance value of capacitor (31 is preferably larger than the width of spike signal 52.
  • the product of the resistance value of resistor 370 and the capacitor (capacity value of 3 1 Is more preferably 10 times or more the width of the spike signal 52, more preferably 50 times or more.
  • Example 8 the output circuit 150 has a ⁇ 02020/175209 77 ⁇ (: 171?2020/006045
  • the voltage conversion circuits 30 3 and 300 of Example 8 and its modification 1 With the voltage conversion circuit 30 of FIG. 35 of Modification 1 of Example 5, the voltage of the input signal is equal to or higher than a predetermined voltage. It is possible to realize a threshold discriminating circuit that does not output the spike signal 52 when.
  • Example 5 and its modified example 1 and Example 8 and its modified example 1 the spike generation circuits according to Examples 1 to 4 and their modified examples were used as the output circuit, but the output circuit 15 0 outputs a single output spike signal 5 2 to the output terminal output I in response to the node 1 ⁇ 1 (intermediate node) becoming a predetermined potential, and resets the voltage of node 1 ⁇ 1 ⁇ .
  • the output circuit 15 0 outputs a single output spike signal 5 2 to the output terminal output I in response to the node 1 ⁇ 1 (intermediate node) becoming a predetermined potential, and resets the voltage of node 1 ⁇ 1 ⁇ .
  • any output circuit that does not output the spike signal 52 when the voltage of the input signal is within the predetermined range is sufficient.
  • FIG. 64 ( 3 ) is a circuit diagram of the spike generation circuit according to the second modification of the eighth embodiment.
  • the spike generation circuit 1 5 4 has a constant current element or a constant current circuit 3 3 and a capacitor 0 1 as the time constant circuit 3 2.
  • the time constant circuit 3 2 causes the spike generation circuit 1 5 4 to function as a delay circuit as in the third modification of the fifth embodiment.
  • the constant current element or constant current circuit 313 is an element or circuit that generates a constant current corresponding to the voltage difference between both ends.
  • the preferred circuit configuration of the constant current element or constant current circuit 33 is a time constant circuit 3
  • Modification 3 of Example 8 is an example in which the time constant of the time constant circuit 32 is lengthened, and the time constant is set to, for example, 1 second or more.
  • FIG. 64 ( ⁇ ) is a circuit diagram of a spike generation circuit according to Modification 3 of Example 8. As shown in Fig. 64 (b ), the constant current element of the time constant circuit 32 is connected in the reverse direction as a constant current element or constant current circuit. ⁇ 02020/175209 78 ⁇ (: 171?2020/006045
  • Iodine 3300 is used. Since the reverse current of diode 330 is small, the time constant can be lengthened. The reverse current of the diode 330 does not change as much as the forward current even if the voltage across the diode 330 changes. Therefore, even if the capacitor 0 1 is charged and the voltage of the node 0 rises, the current value of the diode 33 0 does not decrease and charging does not stop midway.
  • the time constant can be designed with a capacitance value of ⁇ 31. Even if the threshold voltage of the inverter at the next stage of the node varies due to the variation of the threshold voltage of the output circuit 150, the change of the time constant of the time constant circuit 3 2 can be reduced. ..
  • the diode 3300 may be a transistor diode in which the gate of the Mingda is connected to the source.
  • the modification 4 of the embodiment 8 is an example in which the time constant of the time constant circuit 32 is shortened, and the time constant is, for example, 1 second or less.
  • FIG. 64 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the fourth modification of the eighth embodiment.
  • the spike generation circuit 158 uses the Ming 3 3 as the constant current element or the constant current circuit of the time constant circuit 3 2.
  • the gate of Mending 3 3 is connected to the ground line 26, and Mating 3 3 is in the ON state.
  • the time constant of the time constant circuit 3 2 can be shortened by using the ON current of the Ming Ding as the constant current of the constant current element. Also, the on-current of the Ming does not change significantly even if the voltage across the Ming changes.
  • the time constant can be designed based on the current value of and the capacitance of the capacitor. Micho 3 3 It may be Mitsuo.
  • the current flowing through the Mending machine 3 3 is larger than the current that resets the node 1 ⁇ ! ⁇ (for example, the current flowing through the Mending machine of the next stage inverter of the node 1 ⁇ ! ), the node 1 ⁇ ! You will not be able to reset the hen. Therefore, it is preferable that the current flowing through the counter 3 33 is sufficiently smaller than the current when resetting the node 1 ⁇ 1 of the output circuit 150. ⁇ 02020/175209 79 ⁇ (: 171?2020/006045
  • the fifth modification of the eighth embodiment is an example in which the time constant of the time constant circuit 32 is medium, and the time constant is, for example, 10 seconds to 10 seconds.
  • FIG. 65 is a circuit diagram of a spike generation circuit according to Modification 5 of Example 8.
  • the constant current circuit 3 36 of the time constant circuit 3 2 includes a current mirror circuit 36, and diodes 360 and 36.
  • the current mirror circuit 36 includes a shunt 3 636 and a shunt 36.
  • the gate of Mending 3 6 3 and the gate of Mending 3 6 are connected.
  • the gate and drain of Mingda 3 6 3 are connected.
  • the source of the battery is connected to the input terminal, and the drain is connected to node 1 ⁇ 10.
  • the diode 363 is connected in the forward direction between the input terminal ⁇ n and the source of the mine 363. That is, the anode and the cathode are respectively connected to the sources of the input terminal hinge n and the edge counter 363.
  • the die board 3 6 is connected in the reverse direction between the drain of the Ming 3 6 3 and the ground wire 26. That is, the anode and cathode are connected to the drains of ground line 26 and Mending 3 63, respectively.
  • the diode 360 is connected in the forward direction between the input terminal tab n and the counter tab 36 3. Therefore, the voltage of the source of Mending 3 6 3 is lower than the voltage of the source of Ming 3 6 3 by the voltage drop V 3 of diode 3 6 0. As a result, a larger current corresponding to V 3 flows in the counter 36 than the reverse current of the diode 36. For example, a current that is 1 to 6 orders of magnitude higher than the current of the diode 3 6 ⁇ 1 flows in Ming 3 613.
  • the constant current circuit 336 can flow a current that is one to six orders of magnitude larger than the diode 333 in FIG. 64 (slung) of the third modification of the eighth embodiment. Therefore, the time constant circuit 32 can have a time constant that is 1 digit to 6 digits smaller than that of the third modification of the eighth embodiment.
  • a constant current element or a constant current circuit that supplies a current value between the reverse current of the diode 3300 of the third modification of the eighth embodiment and the ON current of Mita of the fourth modification of the eighth embodiment.
  • a diode connected in the forward direction can be considered as the one. But carried out ⁇ 02020/175209 80 ⁇ (: 171?2020/006045
  • the forward current of the diode exponentially increases with respect to the voltage across the diode. Therefore, when the capacitor ⁇ 1 is charged and the voltage of node 1 ⁇ 1 ⁇ rises, the current value of the constant current element or constant current circuit 3 3 ⁇ decreases exponentially, and the voltage of node 1 ⁇ 1 ⁇ becomes Trying to saturate.
  • the saturation voltage of the node N 0 is close to the threshold voltage of the output circuit 150, the time constant becomes divergently long and is easily affected by variations in the threshold voltage of the transistor. As a result, the time constant of the time constant circuit 32 varies, for example, by three digits.
  • the current flowing through the constant current circuit 3 36 is the diode 3
  • FIG. 6 ( ⁇ ) and Figure 6 6 (10) are circuit diagrams of spike generation circuits according to Modifications 5 and 5 of Example 8 used for simulation, respectively.
  • the constant current circuit 33 of the time constant circuit 32 of the modified example 58 of Example 8 does not have the diode 360.
  • a Mitsuko 36 with the source and gate connected is used as the diode 36.
  • the circuit of the output circuit 150 is the same as FIG. 61 (b) of the modification 1 of the eighth embodiment.
  • Other circuit configurations are the same as in Fig. 65.
  • the constant current circuit 3 39 of the time constant circuit 3 2 is a diode 360, and its drain and gate are connected. Use Ding 3 6 9 .
  • the circuit configuration of the output circuit 150 is the same as that of Fig. 61 (Case).
  • the other circuit configurations are the same as in Fig. 65.
  • the capacitors (3 1 and 0 2 have capacitance values of 2 and 4 respectively.
  • the conditions of each knife, the voltage of the power supply line 28 and the ground line 26 are the same as those of the modification 3 of the embodiment 5. Same as Syon. ⁇ 0 2020/175209 81 ⁇ (: 171? 2020/006045
  • Fig. 67 (a) and Fig. 67 ( ⁇ ) are diagrams showing the voltage with respect to time, showing the simulation result of the modified example 58 of the eighth example.
  • Figure 67 (3) shows the voltage at the output terminal memory 1: with respect to time
  • Figure 67 (I) shows the voltage at node 1 with respect to time.
  • the delay time is about 1 second.
  • diode (Mihinoto 3 6 1:) The same magnitude of current and the magnitude of the reverse current is due to constant current circuit 3 3 NOTE is a current supplied. Since the reverse current of the diode (Mita 36) is small, the current supplied by the constant current circuit 33 becomes small and the time constant of the time constant circuit 32 becomes long. If the width of the transistor channel of the Ming 3 6 3 is wider than that of the Ming 3 6 3 , the current value can be increased and the time constant can be shortened. However, at the same time, the parasitic capacitance of node 1 ⁇ 10 also increases. For this reason, it is not preferable to widen the transistor channel width of the counter 363 compared to the counter 363.
  • Fig. 67 ( ⁇ ) and Fig. 67 () are graphs showing the voltage with respect to time showing the simulation result of the fifth modification of the eighth embodiment.
  • Figure 67 ( ⁇ ) shows the voltage of the output terminal output 1: as a function of time
  • Figure 67 () shows the voltage of the node N 1 with respect to time.
  • the delay time is about 20 seconds. This is, ? Mihinoto 3 6 9 Mihinoto 3 6 8 source voltage Mihinoto 3 6 13 source voltage drop V 8 lower to order than in of the constant current circuit 3 3 9 current supplied by the diode (Mihinoto This is because it becomes larger than the reverse current of (36). As a result, the delay time can be moderate.
  • the time constant circuit 3 2 has one end connected to the node N 0 (output node) and the other end connected to the ground line 2 6 (first reference potential terminal). And a constant current element or constant current circuit 3 313 having one end connected to the input terminal gate n and the other end connected to the node ⁇ . to this ⁇ 02020/175209 82 ⁇ (:171?2020/006045
  • the time constant of the time constant circuit 3 2 can be set, and the delay circuit You can set the delay time.
  • the constant current circuit 3 36 is a current mirror circuit 3 6 provided with the counters 3 63 and 36.
  • PFE J36 b first transistor
  • the source one of the current input terminal and the current output terminal
  • the drain the other of the current input terminal and the current output terminal
  • PFE J36 a second transistor
  • the source is connected to the input terminal pin n via the diode 360 (first diode) connected in the forward direction, and the drain is connected in the reverse direction. It is connected to the ground line 26 (second reference potential terminal) via the diode.
  • the gates (control terminals) of Ming 3 6 3 and 3 6 are connected to each other. As a result, it is possible to realize a delay circuit with a small variation in delay time.
  • the constant current element or the constant current circuit may be a diode 330 connected in the reverse direction, and a voltage is applied to the control terminal (gate) so that the diode is turned on. It may be a transistor.
  • the spike generation circuits according to Embodiments 1 to 4 and their modifications are used as the output circuit, but the output circuit 1 50 outputs a single output spike signal 52 to the output terminal I in response to the node voltage becoming the threshold voltage and resets the voltage at node 1 ⁇ 1_1. Any output circuit that outputs the spike signal 52 after the input signal is input and after a delay time related to the time constant of the time constant circuit 32 is sufficient.
  • FIG. 68 (3) is a circuit diagram of a spike generation circuit according to Modification 6 of Example 8. As shown in Fig. 6 8 (3), the spike generator circuit 1 6 1 has an input circuit 3 4 ⁇ 02020/175209 83 ⁇ (: 171?2020/006045
  • the power supply line 28 and the ground line 26 are connected to each other in series with the constant current source 38 and the constant current element 380.
  • the node 1 ⁇ 1 12 between the constant current element 380 and the constant current element 380 is connected to the node 1 ⁇ 100.
  • the input terminal ⁇ n is connected to the gate of the ⁇ 38 via the inverter 383.
  • the constant current element 380 a transistor, a diode or a resistor can be used.
  • the input circuit 34 increases the voltage of the node spike by an amount corresponding to the height of the incoming spike signal.
  • the voltage of the node ⁇ gradually decreases with a time constant longer than the width of the input spike signal.
  • the charge of the node 1 ⁇ ] leaks to the ground line 26 through the knives of the inverter next to the node 1 ⁇ ], and the voltage of the node 1 ⁇ 1 gradually decreases.
  • the spike generation circuit 161 functions as a frequency determination circuit that outputs a spike signal when the frequency of the input spike signal increases, as in the fifth modification of the fifth embodiment.
  • FIG. 68 ( ⁇ ) is a circuit diagram of a spike generation circuit according to Modification 7 of Example 8.
  • the input circuit 3 40 is used as a power supply line 2 8 and a ground line 2 6 with a knife 3 8 6 and a constant current element 3 80 are connected in series.
  • the node 1 ⁇ 1 1 2 between the constant current element 380 and Mitsune 3 86 is connected to the node 1 ⁇ 10.
  • the input terminal ⁇ n is connected to the gate of N ⁇ 3 86.
  • the constant current element 380 a transistor, a diode or a resistor can be used.
  • the input circuit 340 lowers the voltage of the node drop by an amount corresponding to the height of the input spike signal.
  • the voltage of the node rises gradually with a time constant longer than the width of the input spike signal.
  • the spike generation circuit 1662 functions as a frequency determination circuit that outputs a spike signal when the frequency of the input spike signal decreases, as in the fourth modification of the fifth embodiment.
  • FIG. 68 ( ⁇ ) is a circuit diagram of a spike generation circuit according to Modification 8 of Example 8.
  • the power supply line 2 8 and the ground line 2 6 are connected between the power supply line 3 8 and the power supply line 3 8 6.
  • Node 1 ⁇ 1 1 2 between Mending 3 8 13 and Mending 3 8 6 is connected to node ⁇ .
  • the input terminal tab n 1 is connected to the gate of the counter 3 8 through the inverter 3 8 3, and the input terminal tab 2 is connected to the gate of the counter 3 8 6.
  • the input circuit 3 4 raises the voltage of the node 1 ⁇ 1 when the input spike signal is input to the input terminal pin n 1 by the amount corresponding to the height of the input spike signal, and the input pin I I.
  • the voltage at node 1 ⁇ 1 is lowered by the amount corresponding to the input spike signal.
  • the spike generation circuit 163 generates the spike signal at the output circuit 150 when the spike signal input to the input terminal pin n1 has a high frequency and the voltage at the node ⁇ rises. If the frequency of the spike signal input to the input pin n 2 is low, the voltage of the node rises and the output circuit 150 easily generates the spike signal. In this way, the output circuit 150 functions as a frequency determination circuit that outputs the spike signal depending on the balance of the spike signals input to the input terminals Gn1 and Gn2.
  • any one of the input circuits 3 4 to 3 4 is provided, and the output circuit 150 has the voltage of the node 1 ⁇ !
  • the output spike signal is output. Is output.
  • the output circuit 150 is the spike generation circuit of the modified examples 2 and 3 of the first embodiment in which the incoming spike signal is a forward signal
  • the incoming cascade signal is not input to the input terminal pin n. Then the voltage at node 1 ⁇ ! ⁇ gradually decreases with a time constant longer than the width of the incoming spike signal.
  • the output circuit 150 has a negative input spike signal in the modified examples 4 and 5 of the first embodiment. ⁇ 02020/175209 85 ⁇ (: 171-12020/006045
  • the voltage at node 1 ⁇ 1 gradually increases with a time constant longer than the width of the input spike signal. .. In this case, do not connect the inverter 3 8 3 between the input terminal D n or D n 1 and the gate of Mn 3 8 but the input terminal D I n or D n 2 and Mn 3 8 Connect the inverter to the gate of the slag.
  • the spike generation circuits according to Embodiments 1 to 4 and the modifications thereof are used as the output circuit, but the output circuit 150 has a node node voltage of Corresponding to the threshold voltage, a single output cascade signal 52 is output to the output terminal 0:1 and the voltage of the node 1 ⁇ 1 is reset, and the frequency of the input cascade signal is changed. Any output circuit that outputs the output spike signal in a predetermined range may be used.
  • FIG. 69 (3) is a circuit diagram of the spike generation circuit according to the ninth modification of the eighth embodiment.
  • the spike generation circuit 1 6 4 has a plurality of knives 3 9 3 connected in parallel between the power supply line 2 8 and the node ⁇ as the input circuit 10. There is.
  • Each of the input terminals D3 to I3 is connected to the gate of the M3 3 via the inverter 39.
  • Capacitor ⁇ 1 is connected between node 1 ⁇ 1 ⁇ and ground line 26. Node ⁇ is connected to node 1 ⁇ 1 of output circuit 150.
  • Fig. 70(a) and Fig. 70( ⁇ ) are diagrams showing each voltage with respect to time in Modification 9 of Example 8.
  • Fig. 70 (a ) at the times 41, 4 2 and 1 4 3, the input terminal 1 And spike signal 50 is input to each door. If the interval from time 1 41 to 1 4 3 is smaller than the time when the voltage of node 1 ⁇ 1 1 drops, the voltage of node 1 ⁇ 1 ⁇ exceeds the threshold voltage VI at time I 43. This causes the output circuit 150 to switch to the output terminal 1:1. ⁇ 02020/175209 86 ⁇ (: 171?2020/006045
  • the time I 43 when the spike signal 50 is input to the input terminal n n is away from the time I 42.
  • Spike signal 5 0 is input adjacent to time 4 1 and I 4 2.
  • the voltage at node 1 ⁇ 1 does not exceed the threshold voltage V I.
  • the voltage at node 1 ⁇ 1 drops gradually from time I 4 2 to I 4 3, and the voltage at node 1 becomes almost 0 V at time 1 4 4.
  • the output circuit 150 does not output the spike signal 52 to the output terminal I I.
  • the spike generation circuits of the modified examples 2 and 3 of the embodiment 1 are used, and the input circuit 10 is provided with at least one of the plurality of input terminal pens na and nc.
  • the input spike signal 50 When the input spike signal 50 is input, the voltage at node 1 ⁇ 1 is increased by spike signal 50.
  • the voltage of the node 1 ⁇ ! ⁇ gradually decreases over a period longer than the width of the input spike signal.
  • the output circuit 150 outputs a single output spike signal 52 to the output terminal in response to the node voltage becoming the threshold voltage VI.
  • the spike generation circuit 1 6 4 outputs the spike signal 5 2 when the multiple positive-direction spike signals 5 0 input from the multiple input terminal sources na are input within a certain period. Function as a timing circuit.
  • FIG. 69 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the modified example 10 of the eighth embodiment.
  • Fig. 6 9 (b) in the spike generator 1 655, as the input circuit 10, multiple knives 390 are connected in parallel between the ground wire 26 and the node 1 ⁇ 10. It is connected.
  • the input terminals, n 3 to n, are connected to the gates of M 3 90, respectively.
  • the other configurations are the same as those of the ninth modification of the eighth embodiment, and the description thereof will be omitted.
  • the spike generation circuits of Modifications 4 and 5 of Embodiment 1 ⁇ 02020/175209 87 ⁇ (: 171?2020/006045
  • the input circuit 10 lowers the voltage of the node 1 ⁇ 1 when multiple negative input spike signals 50 are input from at least one of the input terminals to the input nc.
  • the voltage at node 1 ⁇ 1 rises gradually over a period longer than the width of the input spike signal.
  • the output circuit 150 outputs a single output spike signal 52 to the output terminal and resets the voltage of the node 1 ⁇ 1 in response to the voltage of the node 1 ⁇ ! .
  • the spike generation circuit 165 outputs the spike signal 5 2 when the plurality of negative-direction spike signals 5 0 input from the multiple input terminals Dna to D n are input within a certain period. Functions as an output timing circuit.
  • FIG. 69 ( ⁇ ) is a circuit diagram of the spike generation circuit according to the modified example 11 of the eighth embodiment.
  • Fig. 6 9 ( ⁇ ) in the spike generator circuit 1 6 6, as the input circuit 10, multiple knives 3 9 3 are connected in parallel between the power supply line 28 and the node N 0. Has been done.
  • Each of the input terminal tabs n a to T in is connected to the gate of the counter 39 3 via an inverter 39 3.
  • Multiple Ming 390 are connected in parallel between the ground line 26 and the node 1 ⁇ 100.
  • the input terminals ng n to ng n 6 are connected to the gate of Ming 390.
  • the rest of the configuration is the same as that of the ninth modification of the eighth embodiment, and a description thereof will be omitted.
  • the spike generation circuits of the modified examples 2 and 3 of the embodiment 1 are used, and the input circuit 10 is provided with at least one of the plurality of input terminal pens na to nc.
  • the input spike signal 50 is input, the voltage of the node 1 ⁇ 1 is increased, and when the input spike signal 5 0 is input to at least one of the multiple input terminals D- n to D- n 6 , the voltage of the node Lower.
  • the input spike signal is not input from multiple input terminals to na 6 to n6, the voltage of the node gradually decreases over a period longer than the width of the input spike signal.
  • the output circuit 150 outputs a single output spike signal 5 2 to the output terminal 0 1 1 in response to the node 1 ⁇ 1 voltage becoming the threshold voltage VI. This allows the spike generation circuit ⁇ 02020/175209 88 ⁇ (: 171?2020/006045
  • 1 6 5 should be input within a certain period when there are multiple positive spike signals 50 that are input from multiple input terminal sources na to source n 0, and within the same period multiple input terminal sources Ind and It functions as a timing circuit that outputs spike signal 5 2 when the number of positive spike signals 5 0 input to n 6 is less than a certain number.
  • the inverter 3 9 is provided between the input terminal hinge na ⁇ T inc and the gate of the nut 3 9 3. Connect the inverter 39 between the input terminals, n and n6, and the gate of 390, without connecting the slag.
  • the input spike signal is not input from multiple input terminals 7 ⁇ 3 to gate n 6, the voltage of the node rises gradually over a period longer than the width of the input spike signal.
  • the spike generation circuit 5 is input within a period of time a plurality of spikes signals 5 0 negative direction to be input to a plurality of input terminals Ding ⁇ nd and Ding ⁇ n e, a plurality of input in the same period Functions as a timing circuit that outputs spike signal 5 2 when the number of negative spike signals 5 0 input from terminal pin n 3 to pin n 0 is less than a certain number.
  • the output circuit of the input circuit 10 may be a circuit other than those of Embodiments 1 to 4 and its modifications.
  • the output circuit responds to the voltage at node 1 ⁇ ! ⁇ becoming the threshold voltage, outputs a single output spike signal to the output terminal, and resets the voltage at node 1 ⁇ 1 ⁇ When the amount of change with respect to time falls within a predetermined range, an output spike signal may be output.
  • Example 9 is an example of a detector that detects the direction of current flow.
  • FIG. 71 is a block diagram of a detector according to the ninth embodiment. As shown in Fig. 71, in the detector 170, a path !_ 1 1 through which the current ⁇ 11 flows is provided between the end knives 11 and 12. The current flowing from the edge 1 1 to the edge 1 2 is positive. There is a 1 ⁇ 1 channel Mending machine 1 ⁇ /1 1 on the track !_ 1 1.
  • Multivibrator circuit X 5 3 outputs signal V 9 1 to the gate of Mending! ⁇ /1 1 ⁇ 02020/175209 89 ⁇ (:171?2020/006045
  • the comparator X 50 compares the voltage V 1 1 of the node N 1 1 on the end side 1 1 side of the path !_ 11 with the reference voltage V 6 6 and outputs the output voltage V 0 I.
  • the comparator 50 sets the output voltage V ⁇ I to a high level when V 1 1 is V ⁇ 6° or more, and outputs the output voltage V ⁇ I when V 11 is less than V ⁇ 6°. In this way, the comparator X50 detects the direction in which the current 11 flows from the comparison result of the voltage V11 and the voltage V6.
  • Fig. 7 2 ( 3 ) and Fig. 7 2 ( ⁇ ) are diagrams showing each voltage with respect to time of the detector according to the ninth embodiment.
  • Fig. 7 2 ( 3 ) shows the case where the current ⁇ 11 is a positive current (current flowing from the end knives 11 to 12 ), and
  • Fig. 7 2 ( ⁇ ) shows the current ⁇ 11 is a negative current (end The current flowing from Ding 12 to Ding 11) is shown.
  • a mouth-level pulse is output at cycle 5 for a high-level base voltage.
  • the width of the pulse is 4 periods.
  • 9 1 is at a high level, Mihinoto 1 ⁇ / 1 1 is to conduct a route! _ 1 1.
  • Current ⁇ 1 1 is positive.
  • the voltage of the node N 11 is almost 0 V, and the output voltage V ⁇ of the comparator X 50 is at the mouth level.
  • V ⁇ ri keeps the mouth level.
  • a resistor is provided at 1 and the voltage across the resistor is compared, and the direction of current flow is detected based on the magnitude relationship of the voltage across the resistor. However, if a resistance is added to path !- 1 1, loss due to resistance will occur.
  • the current 1 1 ( The first current) flows.
  • Ming 1//11 (1st switch) connects and disconnects the path !_ 1 1.
  • the comparator X50 (detection circuit) is at the end of Mending 1 ⁇ /11 The direction of the current I 1 1 is detected based on the voltage V 1 1 (first voltage) of the path !_ 1 1 on the side of either or both of the 2nd end).
  • Example 9 In Example 9, almost no loss occurs except in period 4. Therefore, if period 4 is shorter than period 5, the loss can be suppressed.
  • the period D 4 is preferably 1/10 or less of the period D 5, and more preferably 1/100 or less.
  • FIG. 73 is a block diagram of a detector according to Modification 1 of Example 9.
  • the detector 1 71 is provided with a path !_ 1 2 through which the current ⁇ 1 2 flows between the end knives 21 and 22.
  • the current flowing from the edge 21 to the edge 22 is positive.
  • the path !_ 1 2 is provided with a 1 ⁇ 1 channel Mending machine 1 ⁇ /12. AC power is applied between the end plates 1 and 12.
  • the current I 1 1 and the current 1 12 are complementary. That is, at a certain time, the currents 1 1 and 1 1 2 flow in opposite directions, and the absolute value of the current I 1 1 and the absolute value of the current 1 1 2 are almost the same.
  • the multivibrator circuit X 5 3 outputs the signal V 9 2 to the gate of Mending 1 ⁇ /12.
  • Comparator X 50 has a voltage V 1 1 at node N 1 1 on the edge 1 1 side of path !_ 1 1 and a voltage V 1 at node 1 ⁇ 1 1 2 on the edge 1 2 side of path !_ 1 2. 1 Compares with 2 and outputs output voltage V ⁇ I. Comparator X50 sets the output voltage V ⁇ i I to high level when V 1 1 is higher than V 12 and sets the output voltage V ⁇ i to mouth level when V 1 1 is lower than V 1 2. In this way, the detector 171 detects the flowing direction of the current 1 1. The rest of the configuration is the same as that of the ninth embodiment and will not be described.
  • Fig. 74 is a diagram showing each voltage with respect to time of the detector according to the first modification of the ninth embodiment. As shown in Fig. 74, at time 50, the current value 1 1 is positive and the current value 1 2 is negative. Since the difference between the voltage V 1 1 at the node 1 ⁇ 1 1 1 and the voltage V 1 2 at the node 1 ⁇ 1 1 2 is 0 or very small, the output voltage V ⁇ i of the comparator X 50 is unstable.
  • path !_ 1 2 (second path) includes edge 1 1 and complementary edge 2 1 (3rd edge) and edge 1 2 A current ⁇ 1 1 and a complementary current ⁇ 1 2 (second current) flow between the complementary knives 2 2 (4th end).
  • Mite 1 ⁇ /1 1 and Mite 1 ⁇ /1 2 (second switch) shut off routes !_ 1 1 and !_ 1 2 respectively.
  • Comparator X 5 0 (detection circuit) detects the voltage V 1 1 (1st voltage) of node 1 ⁇ 1 1 1 on the side of edge 1 1 from 1/1/1 and 1/1/2 from 1/1.
  • the modified example 2 of the ninth embodiment is an example in which the modified example 1 of the ninth embodiment is used in the power conversion circuit, and is the synchronous rectifying circuit 64 of FIG. As shown in Figure 5 6 and Figure 5 7, pass gate XI 5 ⁇ 02020/175209 93 ⁇ (: 171-12020/006045
  • pass gate X 13 blocks the path from power terminal 61 to pass gates X 11 and X 1 2.
  • I 1 positive, such as between times I 2 2 and I 2 3
  • voltage V 1 rises and voltage V 2 falls.
  • direction of current ⁇ 1 is negative, such as between times 1 2 5 and 1 2 6, voltage V 1 drops and voltage V 2 rises.
  • Circuit X I has voltage 3 at high level and voltage 4 at mouth level. As a result, the pass gates 9 and X 1 1 are cut off, and the pass gates X 1 0 and X 1 2 are turned on.
  • pass gates XI5, X13, spike generation circuits 3, X4, and circuit X1 function as the detector of the first modification of the ninth embodiment.
  • Passgate X 1 5 serves as the first switch and passgate X 1 3 serves as the second switch.
  • the spike generation circuits 3, 4, and X 1 function as a detection circuit that detects the direction of the current.
  • Modification 3 of Example 9 is another example in which Modification 1 of Example 9 is used in a power conversion circuit.
  • FIG. 75 is a circuit diagram of a synchronous rectification circuit according to Modification 3 of Example 9.
  • FIG. 76 is a diagram showing the voltage of each node of the synchronous rectifier circuit with respect to time in the synchronous rectifier circuit according to the third modification of the ninth embodiment.
  • the multivibrator circuit X 5 3 outputs the output voltage V 6.
  • Inverter X 52 inverts voltage V 6 to obtain voltage V 5.
  • the voltage V 1 ⁇ 02020/175209 94 ((171?2020/006045
  • V 1 0 and V 1 1 are approximately the voltages V 1 and V 2, respectively.
  • the pass gates X 7 and X 8 are turned off.
  • V 1 0 and V 11 are almost 0.
  • the power terminal 61 3 corresponds to the kitchen knife 11 and the node branching to the pass gate 9 and X10 corresponds to the kitchen knife 12 2.
  • the path between the edge 1 1 and the edge 1 2 corresponds to the path !_ 1 1.
  • the current flowing from path 1 to edge 1 1 to edge 1 2 corresponds to current 1 1.
  • the power terminal 6 1 is equivalent to the kitchen knife 21 and the node branching to the path X 1 1 and X 1 2 is the kitchen knife 2 2.
  • the path between the edge 21 and the edge 22 corresponds to the path !_ 1 2.
  • the current flowing from the path !_ 1 2 from the end 21 to the tool 22 corresponds to the current 1 12.
  • Passgates X 15 and X 13 correspond to the first switch and the second switch, respectively.
  • the pass gates X 15 and XI 3 and the comparator X 50 function as the detector of the first modification of the ninth embodiment.
  • the pass gates XI 5, XI 3 and the comparator X 50 function as the first switch, the second switch and the detection circuit, respectively.
  • the switch element turns on and off based on the detection result of the detector (that is, voltage V 4 ).
  • the detector can detect the direction of the current with a small loss, so that a power conversion circuit with a small loss can be realized.
  • the voltage and power generated are small. Therefore, if the loss in power conversion is large, it is difficult to use it as a power conversion circuit for energy harvesting.
  • the pass gates X9 to X1 For 2 (switch circuit), connect the end knives 12 to the power terminal knives 3 1 (first power terminal), disconnect from the ground terminal knives 3 2 (second power terminal), and connect the end knives 2 2 to the ground terminal knives. Connect to 3 2 and disconnect from power supply terminal 31.
  • the pass gate 9 to X 1 2 Connects the kitchen knife 1 2 to the ground terminal knife 3 2 and disconnects it from the power terminal knife 3 1 and connects the kitchen knife 2 2 to the power terminal knife 3 1 and disconnects it from the ground terminal knife 3 2. This allows it to operate as a synchronous rectification circuit.
  • a synchronous rectification circuit was described as an example of the power conversion circuit using the detector according to Example 9 and Modification 1 thereof, but the power conversion circuit is It may be a step-down circuit, a step-up circuit, a DC/AC power conversion circuit, or an AC/DC power conversion circuit.
  • the detectors of Example 9 and its modification 1 can also be used in electric circuits and electronic circuits other than the power conversion circuit.
  • Example 10 is an example of an electronic circuit using a spike generation circuit.
  • Fig. 7 7
  • FIG. 77 ( ⁇ ) are block diagrams of the electronic circuits according to Comparative Example 1 and Example 10. As shown in Fig. 7 7 (a), in the electronic circuit 1 73 of Comparative Example 1, the input terminal of the combinational circuit 7 7 is connected to the output terminal 7 2 of the circuit 7 03. ⁇ 02020/175209 96 ⁇ (: 171?2020/006045
  • the input terminal 7 13 of the circuit 70 is connected to the output terminal of the combinational circuit 7 7.
  • the input terminal of the combinational circuit 7 7 3 is connected to the output terminal 7 2 of 7 03.
  • the input terminal 7 5 of the spike generation circuit 7 4 is connected to the output terminal of the combinational circuit 7 73.
  • the input terminal of the combination circuit 7 7 is connected to the output terminal 7 6 of the spike generation circuit 7 4.
  • the input terminal 7 13 of the circuit 70 is connected to the output terminal of the combination circuit 7 7.
  • the combination circuit 7 73 does not have to be connected between the circuit 70 3 and the spike generation circuit 7 4, and the combination circuit 7 7 13 may be provided between the spike generation circuit 7 4 and the circuit 70. It does not have to be connected.
  • the combination circuits 7 7 3 and 7 7 means that a high level or a mouth level is input to one or more input terminals and one or more inputs are input to one or more output terminals, respectively.
  • This is a circuit that outputs a high level or mouth level that is uniquely determined by the input of a terminal. For example, it is an N 0 circuit, a 0 circuit, a 80 circuit, a B circuit, a 1/100 circuit, a 80 circuit, and a circuit including a combination thereof.
  • the circuits 703 and 70 are the circuits 70 described in the seventh embodiment with reference to Figs. 47(a) to 47( ⁇ ).
  • the circuit 70 is, for example, a [3 ⁇ 4 3 flip-flop circuit, input terminals 7 1 3 and 7 1 are set terminals and reset terminals, and output terminals 7 2 and 7 2 3 are output terminals. And complementary output terminal ⁇ .
  • the circuit 70 is a latch circuit, which is a memory circuit that holds the level of the output terminal 7 2 13 at the one level when either the high level or the mouth level is input to the input terminal 7 18. If
  • Fig. 7 8 (3) shows the spike generation circuit
  • Fig. 7 8 ( ⁇ ) and Fig. 7 8 ( ⁇ ) show the internal state 3 and the output voltage V ⁇ Ri 1: with respect to time, respectively.
  • input terminal 7 of spike generation circuit 7 4 ⁇ 02020/175209 97 ⁇ (:171?2020/006045
  • the internal state 3 is a state that depends on the history of the current and temperature.
  • internal state 3 is the voltage of the intermediate node.
  • Internal state 3 changes according to the history of current I. For example, in FIG. 8 of Example 3, the voltage of the node 1 ⁇ 1 1 (corresponding to the intermediate node 1 ⁇ 1 ⁇ ) is proportional to the integrated value of the current ⁇ n input to the input terminal 7 5 (7 n ). ..
  • the spike generation circuit 74 outputs the spike signal 5 2 as the voltage V ⁇ I.
  • the spike signal 52 is a voltage pulse having no meaning in width and meaning only in timing.
  • internal state 3 is reset.
  • the internal state 3 may be the internal state of the switch element described in Patent Document 6, for example.
  • the internal state 3 may be the temperature that is the integral value of the Joule heat generated by the current.
  • Fig. 7 8 Then, the internal state 3 changes to the positive side depending on the history of the current ⁇ 1!, and when the positive threshold state 3 I II is reached, the spike signal 52 is output.
  • the internal state 3 may change to the negative side depending on the history of the current current 1!, and the spike signal 52 may be output when the negative threshold state 3 1 is reached.
  • Fig. 78 ( ⁇ ) the voltage V ⁇ R1: is 0 V, and the spike signal 52 of the power supply voltage V00 is output, but the voltage V ⁇ R1: is V0 0, A spike signal 52 of 0 may be output.
  • the spike generation circuit 7 4 has a high-level or mouth-level single-shot spike when the internal state 3 depending on the history of the input current input to the input terminal 7 5 reaches the threshold state 3 1. This circuit outputs signal 52 and resets internal state 3 to the initial value.
  • FIG. 7 is a diagram in which the electronic circuits of a) and FIG. 77 (13) are connected in a network.
  • Fig. 7 7 A combinational circuit may be provided between the plurality of circuits 70 in a) and between the circuit 70 and the spike generation circuit 7 4 in FIG. ⁇ 02020/175209 98 ⁇ (: 171?2020/006045
  • the spike generation circuit 74 is not provided between the output terminal of 0 and the circuit 70 of the next stage.
  • Each circuit 70 has a clock signal To enter.
  • Circuit 70 is clock signal
  • the data is output to the circuit 70 in the next stage in synchronization with.
  • the signal transmitted between the circuits 70 is a mouth-level/high-level bit signal.
  • a spike generation circuit 74 is provided between the output terminal of 70 and the circuit 70 of the next stage. Do not input the clock signal ⁇ !_ [ ⁇ to each circuit 70. The signal transmitted from the spike generation circuit 74 to the next stage circuit 70 is a spike signal.
  • the control circuit that controls the power conversion circuit used for energy harvesting is required to reduce power consumption.
  • the charge/discharge current is supplied to the ⁇ 1 ⁇ /1 ⁇ 3 circuit each time the clock signal 0 !_ ⁇ is switched between the high level and the high level. Flowing. Therefore, standby power is generated.
  • the time required for control is relatively long, for example, more than a second. Therefore, the clock signal It is not necessary to move the electronic circuit 1 7 5 in synchronization with.
  • the output terminal 7 2 of the circuit 7 0 3 (first memory circuit) is a spike generation circuit 7 4 It is connected to the input terminal 75 of (1st spike generation circuit). Spike generation times ⁇ 02020/175209 99 ⁇ (: 171?2020/006045
  • the path 7 4 outputs a spike signal when the internal state 3 reaches the threshold state 3 I regardless of the output of the circuit 70 3 in the previous stage. Therefore, the circuit 70 0 (second memory circuit) in which the input terminal 7 1 3 (first input terminal) is connected to the output terminal 7 6 of the spike generation circuit 7 4 causes the spike generation circuit 7 4 to generate the spike signal 5 Unless 2 is output, the state of the circuit 70 in the subsequent stage cannot be rewritten.
  • the control circuits in the rectifier circuits 6 2 and 6 4, the judgment circuit 6 5 and the step-down circuit 6 6 are operated when the operation is required. Then, the spike generation circuit in each control circuit generates a spike signal, and the control circuit operates. On the other hand, when the control circuit does not have to operate, the spike generation circuit in the control circuit does not generate the spike signal. If the spike signal is not generated, the standby power of the control circuit is hardly generated. Therefore, power consumption can be suppressed.
  • the output terminal 7 2 spoon circuit 7 0 3, the combination circuit 7 7 3 1 or at least one may be connected to a plurality of input terminals.
  • the input terminal 7 5 of the spike generation circuit 7 4 may be connected to one or more output terminals of the combinational circuit 7 73.
  • the multiple output terminals of the combinational circuit 7 73 are connected to the spike generation circuit 7 Connected to input terminal 7 5 of 7 4.
  • the output terminal 7 6 of the spike generation circuit 7 4 is connected to at least one of the one or more input terminals of the combination circuit 7 7 and the input terminal 7 1 3 of the circuit 70 0 is connected to the combination circuit 7 7 It may be connected to one or more output terminals.
  • FIG. 80 (a) and FIG. 80 (well) are diagrams showing an example of an electronic circuit according to Example 10. Circuit 7 0 3 of the output terminal 7 2 spoon input terminal 7 5 (first output terminal) spike generation circuit 7 4 are connected, the circuit 7 0 3 of the output terminals 7 2 3 ⁇ 02020/175209 100 units (: 171?2020/006045
  • Input terminal 7 5 (second output terminal) spike generation circuit 7 4 3 (second spike generating circuit) may be connected.
  • a combinational circuit may be provided between the circuit 7 03 and the spike generation circuits 7 4 and 7 43. The rest of the configuration is the same as in FIG.
  • the input terminal 7 1 3 (first input terminal) of the circuit 70 0 is connected to the output terminal 7 6 of the spike generation circuit 7 4, and the input terminal 7 1 3 Output terminal 7 6 of spike generator 74 (3rd spike generator) is connected to (second input terminal).
  • spike generator 74 3rd spike generator
  • a combinational circuit may be provided between the circuit 70 and the spike generators 74 and 74. The rest of the configuration is the same as in FIG.
  • FIG. 81 (3) is a block diagram of an electronic circuit according to Modification 1 of Example 10.
  • the spike signal from the spike generation circuit 7 4 3 is input to the input terminal 7 1 3 of the circuit 7 03. input.
  • the output terminal 72 of the circuit 7 03 is connected to the input terminal 75 of the spike generation circuit 7 4.
  • the output terminal 7 6 of the spike generation circuit 7 4 is connected to the input terminal 7 1 of the circuit 7 03.
  • the circuit 7 03 When the spike generation circuit 7 43 outputs a spike signal, the circuit 7 03 outputs a high level to the spike generation circuit 7 4. When the spike generation circuit 7 4 outputs the spike signal 52, the circuit 7 03 outputs a single level to the spike generation circuit 7 4. As a result, the level of the input terminal 75 of the spike generation circuit 74 is reset.
  • FIG. 81 ( ⁇ ) is a block diagram of an electronic circuit according to Modification 2 of Example 10.
  • one end of the element or the circuit 79 is connected to the output terminal 72 of the circuit 703, and the other end is spike-generated.
  • the element or circuit 79 sends a current according to the voltage difference between one end and the other end.
  • the element or circuit 79 is, for example, a transistor, a resistor, or a leak current element, and is the constant current element or the constant current circuit 33 s of FIG. 64 ( 3 ) in the second modification of the eighth embodiment.
  • the spike generation circuit 74 outputs the spike signal 52 when the integrated value of the current input to the input terminal 75 reaches the threshold value.
  • the threshold value For example, it is the capacity 01 and output circuit 150 in Figure 64(a).
  • the other circuit configuration is the same as that of the modification 1 of the embodiment 10, and the description thereof is omitted.
  • FIG. 82 ( 3 ) and FIG. 82 ( ⁇ ) are block diagrams of the electronic circuit according to Modification 3 of Example 10.
  • the electronic circuit 1 78 includes circuits 70 ⁇ to 70 s, a spike generation circuit 74, 74 ⁇ , and a combination circuit 80 circuit 783,
  • each circuit has 78 circuits and ⁇ circuits 780 and 78.
  • the power supply voltage of each circuit is, for example, the same voltage V 00.
  • spike signals 52 and 52 are input to the input terminals 7 1 3 and 7 1 of the circuit 70 0, respectively.
  • the circuit 70 ⁇ will output a bit signal to the output terminal 72 when a spike signal 52
  • spike signal 52 ⁇ is input, ⁇ 02020/175209 102 ⁇ (:171?2020/006045
  • Output terminal 7 2 Outputs the mouth level as bit signal 1 to the end.
  • ⁇ [3 ⁇ 4 Circuit 7 80 receives spike signals 5 2 and 5 26. ⁇ [3 ⁇ 4 circuit
  • the output of 780 is input to the input terminal 7 13 of the circuit 701. in this way,
  • ⁇ Spike signals from multiple paths may be input to the input terminal 7 13 of one circuit 70 using a combination circuit such as the circuit 780.
  • Circuit 7 0 receives a spike signal at input terminal 7 13 and outputs a bit signal at output terminal 7 2! -Outputs high level as / 1 ⁇ 1 2.
  • the spike generation circuit 7 4 outputs the spike signal 5 2 after a predetermined time elapses from when both the circuits 700 and 70 become high level. Circuit 70, 70 and 80 Circuit 7
  • the input to the spike generation circuit 7 4 may be made to wait until a certain condition is satisfied by using a combination circuit such as 8 3 etc.
  • the spike signal 52 is sent to the input terminal 7 of the circuit 7 0 via the ⁇ [3 ⁇ 4 circuit 7 8
  • the circuit 70 outputs the bit level to the output terminal 7 2 as a bit signal !- / 1 ⁇ 12. That is, a bit signal! -/ 1 ⁇ 1 2 are reset.
  • Spike signals are applied to the input terminals 7 1 3 and 7 1 of the circuit 7 06, respectively.
  • the circuit 706 receives the spike signal 52, it outputs a bit signal to the output terminal 72! -Outputs high level as / 1 to 1 3, and when spike signal 5 2 9 is input, bit signal is output to output terminal 7 2. And outputs the mouth level.
  • Bit signal! -/ 1 to 1 3 are input to ⁇ [3 ⁇ 4 circuit 7 8 via spike generation circuit 7 40 with short time constant. This allows the bit signal to be output even if the spike signal 52 is not output. If 3 goes high, a bit signal! -/ 1 ⁇ 1 2 are reset.
  • the spike generation circuit 74 continues to output the spike signal 52 at regular intervals. like this ⁇ 02020/175209 103 ⁇ (:171?2020/006045
  • the spike signal 52 may be continuously output until a certain condition is satisfied.
  • FIG. 82 (O) is a diagram showing symbols of an electronic circuit according to Modification 3 of Example 10.
  • the input terminal Spike signal 5 2 to 5 2 ⁇ is input.
  • the spike signal 5 2 is output from the output terminal of the electronic circuit 1 78.
  • Bit signal from the output terminal Will output.
  • the electronic circuit 178 outputs one or more spike signals and one or more bit signals when one or more spike signals are input.
  • the electronic circuit 1 7 8 receives at least one signal of one or more bit signals and one or more spike signals when one or more spike signals are input. Should be output.
  • FIG. 83 (3) and FIG. 83 ( ⁇ ) are diagrams showing an example of the spike signal input to the electronic circuit in the modification 3 of the embodiment 10.
  • the spike signal 52" may be the signal output from the sensor 7933.
  • Fig. 83 ( ⁇ ) ⁇ 02020/175209 104 ⁇ (: 171?2020/006045
  • the comparator 79 is a bit signal to the input terminal of the electronic circuit 790! -/ 1 ⁇ 1 is output.
  • Electronic circuit 7900 is a bit signal! -/ Spike signal 5 2" is output at the rising and falling edges of 1 ⁇ 1.
  • the spike signal 52" may be a signal output at the rising and falling edges of the bit signal 1_/1 to 1.
  • FIG. 84 (a) and FIG. 84 ( ⁇ ) are diagrams showing a circuit example in which the spike signal output from the electronic circuit according to the modified example 3 of the embodiment 10 is used.
  • the spike signal 52 and/or bit signal output by the electronic circuit 178 is output to the control terminal of the transistor 79.
  • -/ 1 ⁇ 1 is input.
  • Bit signal output from the circuit 7 0 arm by inputting the spike signal 5 2 output from the electronic circuit 1 7 8 to the input terminal 7 1 3 or 7 1 arm of the circuit 70 arm It may be input to the control terminal of transistor 79.
  • the spike signal 5 2 and/or the bit signal! -/ 1 ⁇ 1 may control the transistor 7 91 1.
  • the spike signal 5 2 output from the electronic circuit 1 7 8 is input to the input terminal 7 1 3 or 7 1 of the circuit 70.
  • the spike signal 52 output from the electronic circuit 178 may be used for rewriting the circuit 780.
  • FIG. 85 (a) and FIG. 85 ( ⁇ ) are circuit diagrams showing an example in which the spike signal output from the electronic circuit in Modification 3 of Example 10 is used, and FIG. ) And FIG. 85 ( ⁇ 1) are diagrams showing the magnitude (electric field) of the electromagnetic wave output from the antenna.
  • the power amplifier 79 amplifies the spike signal 52 output from the electronic circuit 178.
  • Antenna 7 9 6 outputs a spike signal which is amplified as an electromagnetic wave.
  • the spike signal corresponding to the spike signal 52 is output from the antenna 796.
  • the bandpass filter 7 9 is the power amplifier 7
  • Bandpass filter 7 9 ⁇ ⁇ 02020/175209 105 ⁇ (: 171?2020/006045
  • a signal corresponding to a specific frequency band is output from the antenna 796 among the spike signals 52.
  • the spike signal 52 output from the electronic circuit 178 may be used for impulse communication as shown in Figs. 85(a) to 85( ⁇ ).
  • FIG. 86 is a schematic diagram of a network circuit according to Modification 4 of Example 10.
  • An electronic circuit that receives one or more spike signals and outputs one or more spike signals and one or more bit signals as in Modification 4 of Example 10 is represented by the symbol in Figure 82 ( ⁇ ). .. This electronic circuit inputs the spike signal from the left side, outputs the spike signal to the right side, and outputs the bit signal to the upper side.
  • Electronic circuits 178 may be networked, as shown in FIG.

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PCT/JP2020/006045 2019-02-28 2020-02-17 スパイク生成回路、情報処理回路、電力変換回路、検出器および電子回路 Ceased WO2020175209A1 (ja)

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US17/408,599 US11444605B2 (en) 2019-02-28 2021-08-23 Spike generation circuit, information processing circuit, power conversion circuit, detector, and electronic circuit
US17/880,821 US11671077B2 (en) 2019-02-28 2022-08-04 Detector and power conversion circuit
US17/881,034 US11757433B2 (en) 2019-02-28 2022-08-04 Electronic circuit
US18/227,473 US12476623B2 (en) 2019-02-28 2023-07-28 Electronic circuit
JP2025000099A JP7778427B2 (ja) 2019-02-28 2025-01-06 電子回路

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023276707A1 (ja) * 2021-07-02 2023-01-05 国立研究開発法人科学技術振興機構 スパイキングニューロン回路システムおよびスパイキングニューロン回路
US12308745B2 (en) 2021-03-30 2025-05-20 Japan Science And Technology Agency Switching circuit and power supply circuit
US12328115B2 (en) 2021-03-25 2025-06-10 Japan Science And Technology Agency Switching circuit and power supply circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020175209A1 (ja) * 2019-02-28 2020-09-03 国立研究開発法人科学技術振興機構 スパイク生成回路、情報処理回路、電力変換回路、検出器および電子回路
CN117200779A (zh) * 2023-03-27 2023-12-08 电子科技大学 一种双隔离电平转换电路结构
US12615040B2 (en) 2023-10-06 2026-04-28 Cornell University Quasi true time delay

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0950051A (ja) * 1995-08-09 1997-02-18 Ykk Corp エレクトロクロミック素子の駆動方法
JPH10341588A (ja) * 1997-04-29 1998-12-22 St Microelectron Srl 誘導負荷の電流ゼロ交差検出および電圧モードｐｗｍ駆動の最適化
JP2001148619A (ja) * 1999-09-29 2001-05-29 Lucent Technol Inc スパイキングニューロン回路
JP2002100961A (ja) * 2000-09-21 2002-04-05 Mitsumi Electric Co Ltd 半導体集積装置の積分回路
WO2011030848A1 (ja) * 2009-09-11 2011-03-17 国立大学法人九州工業大学 情報処理装置及びプログラム
US20140032460A1 (en) * 2012-07-25 2014-01-30 Hrl Labroratories, Llc Spike domain neuron circuit with programmable kinetic dynamic, homeostatic plasticity and axonal delays
JP2014523592A (ja) * 2011-07-21 2014-09-11 クゥアルコム・インコーポレイテッド 発振を使用したメモリのためのロバストなニューラル時間符号化、学習、およびセル・リクルートメントの方法および装置
WO2018100790A1 (ja) * 2016-11-30 2018-06-07 国立研究開発法人科学技術振興機構 ニューロン回路、システムおよびスイッチ回路
JP2019022047A (ja) * 2017-07-14 2019-02-07 株式会社明電舎 光通信システムおよびそのデータ通信方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5014265A (enExample) * 1973-06-06 1975-02-14
US4594650A (en) * 1983-04-19 1986-06-10 Mitsubishi Denki Kabushiki Kaisha Inverter device
US4723114A (en) * 1986-07-07 1988-02-02 Texas Instruments Incorporated Method and circuit for trimming the frequency of an oscillator
JP3409938B2 (ja) 1995-03-02 2003-05-26 株式会社東芝 パワーオンリセット回路
JP2000106521A (ja) 1998-09-29 2000-04-11 Oki Micro Design Co Ltd 発振回路
JP2000221764A (ja) 1999-01-28 2000-08-11 Kyocera Mita Corp トナー補給装置
DE10120142B4 (de) * 2001-04-25 2010-12-30 Nxp B.V. Detektorschaltung zur Detektion von Spannungs-Spikes
JP2006243877A (ja) 2005-03-01 2006-09-14 Matsushita Electric Ind Co Ltd 加算素子及びその駆動方法
US20070024317A1 (en) * 2005-07-29 2007-02-01 Hansen James E Apparatus for obtaining precision integrated resistors
JP4350133B2 (ja) 2007-02-19 2009-10-21 富士通株式会社 送信回路および無線伝送装置
JP5143874B2 (ja) 2010-08-12 2013-02-13 株式会社半導体理工学研究センター 位相変調回路
US8432214B2 (en) * 2011-03-21 2013-04-30 Freescale Semiconductor, Inc. Programmable temperature sensing circuit for an integrated circuit
US20160364643A1 (en) * 2012-03-08 2016-12-15 Hrl Laboratories Llc Scalable integrated circuit with synaptic electronics and cmos integrated memristors
US11501143B2 (en) * 2013-10-11 2022-11-15 Hrl Laboratories, Llc Scalable integrated circuit with synaptic electronics and CMOS integrated memristors
US20150220829A1 (en) * 2014-02-04 2015-08-06 Qualcomm Incorporated Equivalent delay by shaping postsynaptic potentials
US10003265B2 (en) * 2014-07-28 2018-06-19 Rohm Co., Ltd. Switching power supply device
US9540736B2 (en) * 2014-07-29 2017-01-10 Applied Materials, Inc. Methods of etching films with reduced surface roughness
EP3259735B1 (en) * 2015-02-16 2024-07-31 HRL Laboratories, LLC Spike domain convolution circuit
CN106374887A (zh) * 2015-07-20 2017-02-01 马利峰 一种新型BiCMOS电压峰值锁存电路设计
CN106549653A (zh) * 2015-09-16 2017-03-29 胡荣炎 一种新型峰值锁存电路设计
WO2017100078A1 (en) 2015-12-08 2017-06-15 Rambus Inc. Low power signaling interface
US10516420B1 (en) * 2018-06-12 2019-12-24 Mitsubishi Electric Research Laboratories, Inc. High speed digital bit generator for optical frontal interface
KR102092233B1 (ko) * 2018-07-12 2020-03-23 서울대학교 산학협력단 뉴런 회로
CN109102071B (zh) * 2018-08-07 2020-12-11 中国科学院微电子研究所 一种神经元电路以及神经网络电路
WO2020175209A1 (ja) * 2019-02-28 2020-09-03 国立研究開発法人科学技術振興機構 スパイク生成回路、情報処理回路、電力変換回路、検出器および電子回路
CN112447218B (zh) * 2019-08-29 2025-05-06 台湾积体电路制造股份有限公司 存储器电路和方法
US10930992B1 (en) * 2019-12-03 2021-02-23 At&T Intellectual Property I, L.P. Method and apparatus for communicating between waveguide systems
US11566950B2 (en) * 2020-04-06 2023-01-31 Realtek Semiconductor Corp. Process and temperature tracking reference load and method thereof
US11443827B2 (en) * 2021-01-13 2022-09-13 Winbond Electronics Corp. Memory device and method for error detection

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0950051A (ja) * 1995-08-09 1997-02-18 Ykk Corp エレクトロクロミック素子の駆動方法
JPH10341588A (ja) * 1997-04-29 1998-12-22 St Microelectron Srl 誘導負荷の電流ゼロ交差検出および電圧モードｐｗｍ駆動の最適化
JP2001148619A (ja) * 1999-09-29 2001-05-29 Lucent Technol Inc スパイキングニューロン回路
JP2002100961A (ja) * 2000-09-21 2002-04-05 Mitsumi Electric Co Ltd 半導体集積装置の積分回路
WO2011030848A1 (ja) * 2009-09-11 2011-03-17 国立大学法人九州工業大学 情報処理装置及びプログラム
JP2014523592A (ja) * 2011-07-21 2014-09-11 クゥアルコム・インコーポレイテッド 発振を使用したメモリのためのロバストなニューラル時間符号化、学習、およびセル・リクルートメントの方法および装置
US20140032460A1 (en) * 2012-07-25 2014-01-30 Hrl Labroratories, Llc Spike domain neuron circuit with programmable kinetic dynamic, homeostatic plasticity and axonal delays
WO2018100790A1 (ja) * 2016-11-30 2018-06-07 国立研究開発法人科学技術振興機構 ニューロン回路、システムおよびスイッチ回路
JP2019022047A (ja) * 2017-07-14 2019-02-07 株式会社明電舎 光通信システムおよびそのデータ通信方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12328115B2 (en) 2021-03-25 2025-06-10 Japan Science And Technology Agency Switching circuit and power supply circuit
US12308745B2 (en) 2021-03-30 2025-05-20 Japan Science And Technology Agency Switching circuit and power supply circuit
WO2023276707A1 (ja) * 2021-07-02 2023-01-05 国立研究開発法人科学技術振興機構 スパイキングニューロン回路システムおよびスパイキングニューロン回路
JPWO2023276707A1 (enExample) * 2021-07-02 2023-01-05
JP7858212B2 (ja) 2021-07-02 2026-05-14 国立研究開発法人科学技術振興機構 スパイキングニューロン回路システムおよびスパイキングニューロン回路

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