WO2020172769A1 - 数据转换器以及相关模数转换器、数模转换器及芯片 - Google Patents

数据转换器以及相关模数转换器、数模转换器及芯片 Download PDF

Info

Publication number
WO2020172769A1
WO2020172769A1 PCT/CN2019/076055 CN2019076055W WO2020172769A1 WO 2020172769 A1 WO2020172769 A1 WO 2020172769A1 CN 2019076055 W CN2019076055 W CN 2019076055W WO 2020172769 A1 WO2020172769 A1 WO 2020172769A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital
analog
analog conversion
converter
conversion units
Prior art date
Application number
PCT/CN2019/076055
Other languages
English (en)
French (fr)
Inventor
黄思衡
王文祺
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201980000254.4A priority Critical patent/CN109997308A/zh
Priority to PCT/CN2019/076055 priority patent/WO2020172769A1/zh
Priority to JP2020538793A priority patent/JP2021517377A/ja
Priority to EP19888242.5A priority patent/EP3731415A4/en
Priority to US16/889,316 priority patent/US11245413B2/en
Publication of WO2020172769A1 publication Critical patent/WO2020172769A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/001—Analogue/digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0614—Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
    • H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
    • H03M1/0668—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging the selection being based on the output of noise shaping circuits for each element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/462—Details relating to the decimation process
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation

Definitions

  • This application relates to a converter, in particular to a data converter and related analog-to-digital converters, digital-to-analog converters and chips.
  • the current common solution is to add an additional digital-to-analog converter unit to the digital-to-analog converter.
  • This technology is called incremental data weighted average technology.
  • the incremental data weighted average technology can make the selection pattern of the digital-to-analog converter unit less likely to produce repetitiveness, thereby eliminating single-tone spurs.
  • the selection pattern of the digital-to-analog converter unit will still be repetitive, resulting in single-tone spurs.
  • One of the objectives of the present application is to disclose a data converter, particularly a data converter, an analog-to-digital converter, a digital-to-analog converter, and related chips to solve the above-mentioned problems.
  • An embodiment of the application discloses a data converter.
  • the data converter includes an input terminal, a digital-to-analog converter, and a mapping unit.
  • the input terminal is used to receive input signals.
  • the digital-to-analog converter includes a plurality of digital-to-analog conversion units for generating output signals.
  • the mapping unit is coupled between the input terminal and the digital-to-analog converter, and is used to enable the plurality of digital-to-analog conversion units to perform data processing in the plurality of digital-to-analog conversion units according to specific electrical characteristics of the plurality of digital-to-analog conversion units.
  • the multiple digital-to-analog conversion units are equivalently arranged in a relative order in which they are gated to perform digital-to-analog conversion.
  • An embodiment of the application discloses an analog-to-digital converter for converting an analog signal into a digital signal.
  • the analog-to-digital converter includes an input terminal, a low-pass filter, a quantizer and a feedback loop.
  • the input terminal is used to receive the analog signal.
  • the low-pass filter is coupled to the input terminal and generates a low-pass signal according to the analog signal.
  • the quantizer is used to generate a quantized signal according to the low-pass signal.
  • the feedback loop is used to feed back the quantized signal to the output end of the low-pass filter.
  • the feedback loop includes the data converter.
  • An embodiment of the present application discloses a digital-to-analog converter for converting digital signals into analog signals.
  • the digital-to-analog converter includes an input terminal, an up-sampling filter, a quantizer, and the data converter.
  • the input terminal is used to receive the digital signal.
  • the up-sampling filter is coupled to the input terminal and generates an up-sampling signal according to the digital signal.
  • the quantizer is used to generate a quantized signal according to the up-sampled signal.
  • the data converter is used to generate the analog signal according to the quantized signal.
  • An embodiment of the application discloses a chip.
  • the chip includes the data converter.
  • An embodiment of the application discloses a chip.
  • the chip includes the analog-to-digital converter.
  • An embodiment of the application discloses a chip.
  • the chip includes the digital-to-analog converter.
  • the data converter, analog-to-digital converter, digital-to-analog converter, and related chips disclosed in the present application can effectively suppress single-tone spurs when the selection pattern of the digital-to-analog conversion unit produces repeatability, thereby improving the signal-to-noise distortion ratio .
  • FIG. 1 is a schematic block diagram of an embodiment of a multi-bit delta-sigma analog-to-digital converter of this application.
  • FIG. 2 is a block diagram of an embodiment of the data converter of this application.
  • FIG. 3 is a histogram of the amplitudes of specific electrical characteristics of multiple digital-to-analog conversion units of this application.
  • FIG. 4 is a schematic diagram of the gating situation of each digital-to-analog conversion unit of this application.
  • FIG. 5 is a histogram of the amplitude values related to FIG. 3 before and after being arranged equivalently in this application.
  • 6A is a schematic diagram of a first embodiment of a method for arranging an even number of digital-to-analog conversion units according to this application.
  • 6B is a schematic diagram of a first embodiment of a method for arranging an odd number of digital-to-analog conversion units according to this application.
  • Fig. 6C is a histogram of the amplitudes related to Fig. 5 after being equivalently arranged according to the method shown in Fig. 6B.
  • Fig. 7 is a frequency spectrum diagram of the digital signal output by the multi-bit delta-sigma analog-to-digital converter of this application.
  • FIG. 8A is a schematic diagram of a second embodiment of a method for arranging an even number of digital-to-analog conversion units according to this application.
  • FIG. 8B is a schematic diagram of a second embodiment of a method for arranging an odd number of digital-to-analog conversion units according to this application.
  • Fig. 8C is a histogram of the amplitudes related to Fig. 5 after being equivalently arranged according to the method shown in Fig. 8B.
  • the waveform diagrams of FIG. 9 respectively illustrate the signal-to-noise distortion ratio of the multi-bit delta-sigma analog-to-digital converter including and excluding the data converter of the present application.
  • FIG. 10 is a block diagram of an embodiment of a multi-bit delta-sigma digital-to-analog converter according to the present application.
  • first and second features are in direct contact with each other; and may also include
  • additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • present disclosure may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing
  • the relationship between one component or feature relative to another component or feature is shown.
  • these spatially relative terms also cover a variety of different orientations in which the device is in use or operation.
  • the device may be placed in other orientations (for example, rotated by 90 degrees or in other orientations), and these spatially-relative description words should be explained accordingly.
  • FIG. 1 is a block diagram of an embodiment of a multi-bit delta-sigma (sigma-delta) analog-to-digital converter 10 of the present application.
  • a multi-bit delta-sigma analog-to-digital converter 10 is used to convert an analog signal into a digital signal.
  • the multi-bit delta-sigma analog-to-digital converter 10 includes an input terminal 98, a low pass filter (LPF) 100, a loop filter (loop filter) 102, a quantizer 104, and a decimation filter (decimation filter) 106 1.
  • LPF low pass filter
  • loop filter loop filter
  • quantizer 104 quantizer
  • decimation filter decimation filter
  • Incremental data weighted averaging (IDWA) circuit 110 data converter 112 and logic unit 118, wherein the incremental data weighted averaging circuit 110 and data converter 112 are located on the feedback loop 108.
  • the incremental data weighted average circuit 110 is coupled between the quantizer 104 and the data converter 112.
  • the input terminal 98 is used to receive an analog signal.
  • the low-pass filter 100 is coupled to the input terminal 98 and generates a low-pass signal LPF_A according to the analog signal.
  • the loop filter 102 is used to generate the loop filter signal LF_A according to the low-pass signal LPF_A and the output Sout of the feedback loop 108.
  • the quantizer 104 is coupled to the loop filter 102 and used to generate quantization according to the loop filter signal LF_A Signal Q_D.
  • the decimation filter 106 is used to provide a multi-bit digital signal based on the quantized signal Q_D.
  • the feedback loop 108 is used to feed back the quantized signal Q_D to the output terminal of the low-pass filter 100.
  • the incremental data weighted average circuit 110 is used to provide the input signal Sin required by the data converter 112 based on the quantized signal Q_D.
  • the data converter 112 is used to generate an output signal Sout to the logic unit 118 based on the input signal Sin.
  • the logic unit 118 is used to subtract the output signal Sout from the low-pass signal LPF_A and provide it to the loop filter 102.
  • this application is not limited to the incremental data weighted average circuit 110.
  • the incremental data weighted average circuit 110 can be implemented by other circuits with similar functions. For example, it can also be used A data weighted average circuit replaces the incremental data weighted average circuit 110.
  • FIG. 2 is a block diagram of an embodiment of the data converter 112 of this application.
  • the data converter 112 includes an input terminal 120 for receiving a multi-bit input signal Sin, an output terminal 122 for outputting an output signal Sout, a mapping unit 114, and a digital-to-analog converter 116.
  • the digital-to-analog converter 116 includes digital-to-analog conversion units 20_1, 20_2, ... 20_N, where N is a positive integer.
  • the digital-to-analog converter 116 is used to generate the output signal Sout.
  • the digital-to-analog converter 116 may be any circuit unit that can be used to convert a digital signal into an analog signal form, such as current, charge, or voltage.
  • the digital-to-analog converter 116 may include a current source, a capacitor, a resistor, or any other electronic components that meet the above definition.
  • the mapping unit 114 coupled between the input terminal 120 and the digital-to-analog converter 116, is used to make the digital-to-analog conversion units 20_1, 20_2,...20_N multiply according to the specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2,...20_N
  • the digital-to-analog conversion units 20_1, 20_2,... 20_N are equivalently arranged in a relative order in which they are gated to perform digital-to-analog conversion. Specifically, the equivalent arrangement does not mean that the digital-to-analog conversion units 20_1, 20_2, ... 20_N are arranged on the circuit layout diagram according to the specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2, ... 20_N, but through the mapping unit 114 To configure the connection relationship between the digital-to-analog conversion units 20_1, 20_2,... 20_N and the incremental data weighted average circuit 110.
  • the specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2,... 20_N can be measured and multiple measurement results can be generated when the data converter 112 is shipped from the factory or each time it is powered on, and then based on the multiple measurement results.
  • the measurement result is used to program the mapping unit 114, but the application is not limited thereto.
  • the mapping unit 114 can effectively suppress the single-tone spurious of the multi-bit delta-sigma analog-to-digital converter 10, and thereby obtain a better signal-to-noise distortion ratio.
  • the specific electrical characteristics are related to current characteristics.
  • the digital-to-analog conversion units 20_1, 20_2,... 20_N include current sources
  • the specific electrical characteristics include the current provided by the current sources.
  • the method of measuring current characteristics can be implemented using any existing technology.
  • the specific electrical characteristics are related to voltage characteristics.
  • the digital-to-analog conversion units 20_1, 20_2,... 20_N include capacitors
  • the specific electrical characteristics include the voltage-related charges stored by the capacitors.
  • the method of measuring voltage characteristics can be implemented using any existing technology.
  • the value of N is set to 33, that is, the digital-to-analog converter 116 includes 33 digital-to-analog conversion units 20_1, 20_2, ... 20_33.
  • FIG. 3 is a histogram of the amplitude of specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2, ... 20_33 of the application.
  • the horizontal axis represents the positions of the digital-to-analog conversion units 20_1, 20_2, ... 20_33 before being equivalently arranged, that is, the original arrangement sequence, from positions A 1 to A 33.
  • the numbers are not marked in Fig. 3 Out.
  • the first input signal Sin1 received by the data converter 112 at the beginning will enable a certain number of digital-to-analog conversion units starting from the position A 1 to be strobed, for example, a number of the positions A 1 to A 10
  • the digital-to-analog conversion unit is determined according to the magnitude of the first input signal Sin1.
  • the second input signal Sin2 received by the data converter 112 will enable a certain number of digital-to-analog conversion units starting at position A 11 to be strobed, for example, a number of digital-to-analog conversion units at positions A 11 to A 30 , according to the first It depends on the magnitude of the two input signals Sin2.
  • the third input signal Sin3 received by the data converter 112 will cause a certain number of digital-to-analog conversion units starting at position A 31 to be strobed, and if it exceeds position A 33, it will jump back to position A 1 to continue strobing.
  • Analog conversion unit the third input signal Sin3 will enable a certain number of digital-to-analog conversion units from positions A 31 to A 33 and then from positions A 1 to A 6 to be gated, and the subsequent operations are analogous to this.
  • the vertical axis of FIG. 3 represents the normalized amplitude of the specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2, ... 20_33, and the value 1 is used as the normalized reference value. Due to changes in the manufacturing process, there are component adaptation errors among the digital-to-analog conversion units 20_1, 20_2, ... 20_33, so the specific electrical characteristics will be slightly different. In other words, the specific electrical characteristic of each digital-to-analog conversion unit 20_1, 20_2,... 20_33 has an electrical characteristic difference value with the reference value 1.
  • the multi-bit delta-sigma analog-to-digital converter 10 does not include the mapping unit 114, and the digital-to-analog conversion units 20_1, 20_2,... 20_33 are directly controlled by the incremental data weighted average circuit 110.
  • the digital-to-analog conversion units 20_1, 20_2,... 20_33 include several digital-to-analog conversion units located at A 1 to A 17 and several digital-to-analog conversion units located at A 18 to A 33 .
  • the sum of specific electrical characteristics of the several digital-to-analog conversion units located at A 1 -A 17 is relatively large, while the sum of specific electrical characteristics of several digital-to-analog conversion units located at A 18 -A 33 is relatively large.
  • the ground is small.
  • FIG. 4 is a schematic diagram of the gating situation of the digital-to-analog conversion units 20_1, 20_2, ... 20_33 of this application.
  • the code (1) shown in the vertical column represents that the quantizer 104 initially generates the quantized signal Q_D according to the first low-pass signal LPF_A; then, the code (2) represents that the quantizer 104 generates the second low-pass signal LPF_A.
  • the quantized signal Q_D and so on.
  • the value after the equal sign of code (1) represents the value of the quantized signal Q_D.
  • the selected digital-to-analog conversion units and the digital signal input sequence are code (1) and code (2).
  • Several digital-to-analog conversion units are the same. Therefore, the choice of style produces repeatability. For example, in the case as described above (the sum of specific electrical characteristics of several digital-to-analog conversion units located at A 1 to A 16 is relatively large, the sum of specific electrical characteristics of several digital-to-analog conversion units located at A 17 to A 33 Relatively small), single-tone spurs will be particularly significant, which will worsen the SNR.
  • the digital-to-analog conversion units 20_1, 20_2,...20_33 are equivalently arranged according to the electrical characteristic difference value corresponding to each of the digital-to-analog conversion units 20_1, 20_2,...20_33. Therefore, the single-tone spurious of the multi-bit delta-sigma analog-to-digital converter 10 can be effectively suppressed, and a better signal-to-noise distortion ratio can be obtained.
  • FIG. 5 is a histogram of the amplitude values related to FIG. 3 before and after being arranged equivalently in this application.
  • the horizontal axis represents the positions of the digital-to-analog conversion units 20_1, 20_2, ... 20_33 before and after the equivalent arrangement, from positions I 1 to I 33 , which are not all marked in FIG. 5 for the sake of brevity.
  • the digital-to-analog conversion unit at position A 16 is arranged at the first position I 1 ; similarly, the digital-to-analog conversion unit at position A 30 in Fig. 3 is arranged at the last position I 33 .
  • the mapping unit 114 arranges the specific electrical characteristics in order from small to large.
  • mapping unit 114 can relatively easily determine the specific electrical characteristics of the digital-to-analog conversion units 20_1, 20_2, ... 20_33, so as to relatively conveniently execute the subsequent program of equivalently arranging the digital-to-analog conversion units 20_1, 20_2, ... 20_33 . It should be noted that this operation is optional. In some embodiments, this operation may be omitted.
  • 6A is a schematic diagram of a first embodiment of a method for arranging an even number of digital-to-analog conversion units according to this application.
  • the digital-to-analog conversion unit at position I 1 with the smallest specific electrical characteristic is equivalently arranged at the first position in the relative order, and the digital-to-analog conversion unit at position I 33 with the largest specific electrical characteristic is arranged
  • the conversion unit is equivalently arranged in the second position in the relative order; then, the digital-to-analog conversion unit with the second smallest specific electrical characteristic is arranged in the third position in the relative order, and the second largest specific electrical characteristic
  • the digital-to-analog conversion unit is arranged in the fourth position in the relative order, and so on.
  • the magnitude of the specific electrical characteristics of the digital-to-analog conversion unit whose 2K-1 bit is gated is among the multiple digital-to-analog conversion units 20_1, 20_2, ... 20_33 Ranked Kth in the magnitude of specific electrical characteristics
  • the magnitude of the specific electrical characteristics of the digital-to-analog conversion unit whose 2k position is gated is in the magnitude of specific electrical characteristics of the multiple digital-to-analog conversion units 20_1, 20_2, ... 20_33
  • the value ranks N-K+1, where N is the number of multiple digital-to-analog conversion units 20_1, 20_2, ... 20_33, in this embodiment, N is 33, and where K ⁇ 1 and K ⁇ N.
  • the equivalent sorting is performed according to the amplitude of the relevant voltage of the digital-to-analog conversion unit, that is, the digital-to-analog conversion unit with the largest and smallest relevant voltage amplitude in the digital-to-analog conversion unit is placed first. And the second position, and then place the second largest and second smallest digital-to-analog conversion units in the third and fourth positions, and so on, the k-th and N-k+1-th digital-to-analog conversion units are placed At 2k-1 and 2k positions.
  • Fig. 6B is a schematic diagram of a first embodiment of a method for arranging an odd number of digital-to-analog conversion units according to this application.
  • the logic of equivalently arranging an odd number of digital-to-analog conversion units is the same as that of equivalently arranging an even number of digital-to-analog conversion units, and will not be repeated here.
  • Fig. 6C is a histogram of the amplitudes related to Fig. 5 after being equivalently arranged according to the method shown in Fig. 6B.
  • the horizontal axis represents the positions of the digital-to-analog conversion units 20_1, 20_2, ... 20_33 after being equivalently arranged, from positions C 1 to C 33 , which are not all marked in FIG. 6C for the sake of brevity.
  • the first input signal Sin1 received by the data converter 112 at the beginning will cause a certain number of digital-to-analog conversion units starting from position C 1 to be strobed, for example, several positions located from C 1 to C 10
  • the digital-to-analog conversion unit is determined according to the magnitude of the first input signal Sin1.
  • the second input signal Sin2 received by the data converter 112 will enable a certain number of digital-to-analog conversion units starting at position C 11 to be strobed, for example, a number of digital-to-analog conversion units at positions C 11 to C 30 , according to the first It depends on the magnitude of the two input signals Sin2.
  • the third input signal Sin3 received by the data converter 112 will cause a certain number of digital-to-analog conversion units starting at position C 31 to be strobed, and if it exceeds position C 33, it will jump back to position C 1 to continue strobing.
  • the analog conversion unit, the subsequent operations are analogous.
  • the position of the digital-to-analog conversion unit at position A 16 before being arranged equivalently is arranged to position C 1 after being arranged equivalently ;
  • the position of the digital-to-analog conversion unit at the position A 30 before the equivalent arrangement is arranged to the position C 2 after the equivalent arrangement.
  • the amplitudes of specific electrical characteristics of several digital-to-analog conversion units arranged in odd positions for example, positions C 1 , C 3 , C 5
  • the amplitudes of specific electrical characteristics of several digital-to-analog conversion units arranged in even-numbered positions for example, positions C 2 , C 4 , and C 6 ) descending sort.
  • the present disclosure is not limited to this.
  • the amplitudes of specific electrical characteristics of the several digital-to-analog conversion units arranged at odd positions are arranged in descending order; and, equivalently In the arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33, the amplitudes of specific electrical characteristics of the several digital-to-analog conversion units arranged in even positions are arranged in ascending order.
  • several digital-to-analog conversion units in the first half of the equivalently arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33 are located at positions C 1 to C 17 .
  • the sum of the electrical characteristic difference values corresponding to each of the several digital-to-analog conversion units located at the positions C 1 to C 17 is the third sum.
  • Several digital-to-analog conversion units in the latter half of the equivalently arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33 are located at positions C 18 to C 33 .
  • the sum of the electrical characteristic difference values corresponding to each of the several digital-to-analog conversion units located at positions C 18 to C 33 is the fourth sum.
  • the difference between the third total and the fourth total is smaller than the difference between the first total and the second total.
  • the difference between the electrical characteristics of the first half of the digital-to-analog conversion units of the equivalently arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33 and the difference between the electrical characteristics of the second half of the digital-to-analog conversion units The difference is relatively small. Accordingly, even if the repeatability shown in FIG. 4 is produced in the selected pattern, the single-tone spur of the multi-bit delta-sigma analog-to-digital converter 10 can be effectively suppressed, and a better signal-to-noise distortion ratio can be obtained.
  • FIG. 6C other embodiments of the present application also include an arrangement derived from FIG. 6C.
  • position C 1 is translated one position backward
  • position C 2 is also translated one position backward accordingly, and so on.
  • the position C 33 is translated to the current position C 1 position.
  • the number of translations is only one example. In the present disclosure, the number of positions to be translated may be any number.
  • FIG. 7 is a frequency spectrum diagram of the digital signal output by the multi-bit delta-sigma analog-to-digital converter 10 of this application.
  • the horizontal axis is frequency (Hz); and the vertical axis is amplitude (decibel).
  • the single-tone spurious of the multi-bit delta-sigma analog-to-digital converter 10 can be effectively suppressed.
  • FIG. 8A is a schematic diagram of a second embodiment of a method for arranging an even number of digital-to-analog conversion units according to this application.
  • the digital-to-analog conversion unit at position I 1 with the smallest specific electrical characteristic is equivalently arranged at the first position in the relative order
  • the digital-to-analog conversion unit at position I 33 with the largest specific electrical characteristic is equivalently arranged.
  • the conversion unit is equivalently arranged in the second position in the relative order; then, the digital-to-analog conversion unit with the second smallest specific electrical characteristics is equivalently arranged in the second-to-last position in the relative order, and will have the second largest
  • the digital-to-analog conversion unit with specific electrical characteristics is equivalently arranged at the last position in the relative order, and so on.
  • FIG. 8B is a schematic diagram of a second embodiment of a method for arranging an odd number of digital-to-analog conversion units according to this application.
  • the logic of equivalently arranging an odd number of digital-to-analog conversion units is the same as that of equivalently arranging an even number of digital-to-analog conversion units, which will not be repeated here.
  • Fig. 8C is a histogram of the amplitudes related to Fig. 5 after being equivalently arranged according to the method shown in Fig. 8B.
  • the horizontal axis represents the positions of the digital-to-analog conversion units 20_1, 20_2,... 20_33 after being equivalently arranged, from positions D 1 to D 33 , which are not all marked in FIG. 8C for the sake of brevity.
  • a data converter 112 receives a first start signal Sin1 pen will be gated from several number of position D 1 starting digital to analog conversion means, for example, located several of D 1 to D 10
  • the digital-to-analog conversion unit is determined according to the magnitude of the first input signal Sin1.
  • a second pen input signal received by the data converter 112 will be gated from Sin2 certain number of start position D 11 digital to analog conversion means, for example, located several D 11 to D 30 digital-analog conversion unit, according to the first It depends on the magnitude of the two input signals Sin2.
  • the third input signal Sin3 received by the data converter 112 will cause a certain number of digital-to-analog conversion units starting at position D 31 to be strobed, and if it exceeds position D 33, it will jump back to position D 1 to continue strobing.
  • the analog conversion unit, the subsequent operations are analogous.
  • some digital-to-analog conversion units arranged in odd positions have specific electrical characteristics.
  • the values are arranged in ascending order, and the amplitudes of the specific electrical characteristics of the other digital-to-analog conversion units arranged in odd positions are arranged in descending order.
  • some digital-to-analog conversion units arranged in even-numbered positions have specific electrical characteristics.
  • the values are arranged in descending order, and the amplitudes of specific electrical characteristics of a number of digital-to-analog conversion units arranged in even-numbered positions are arranged in ascending order.
  • this application is not limited to this.
  • Several digital-to-analog conversion units in the first half of the equivalently arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33 are located at positions D 1 to D 17 .
  • the sum of the electrical characteristics corresponding to each difference value is located at a position a plurality of digital to analog conversion means D 1 to D. 17 is a fifth of the sum.
  • Several digital-to-analog conversion units in the latter half of the equivalently arranged digital-to-analog conversion units 20_1, 20_2, ... 20_33 are located at positions D 18 to D 33 .
  • the sum of the electrical characteristic difference values corresponding to each of the several digital-to-analog conversion units located at positions D 18 to D 33 is the sixth sum.
  • the difference between the fifth total and the sixth total is smaller than the difference between the first total and the second total. In some specific embodiments, the difference between the fifth total and the sixth total is smaller than the difference between the third total and the fourth total.
  • the mapping unit 114 Even though the repetitiveness shown in FIG. 4 is produced by the mapping unit 114 in the selected pattern, the single-tone spur of the multi-bit delta-sigma analog-to-digital converter 10 can be effectively suppressed, and a better signal-to-noise distortion ratio can be obtained. .
  • FIG. 8C other embodiments of this application also include an arrangement derived from FIG. 8C.
  • the position D 1 is shifted backward by one position, and the position D 2 is also shifted backward by one position accordingly, and so on.
  • Position D 33 is shifted to the current position D 1 position.
  • the number of translations is only one example. In this application, the number of shifted positions can be any number.
  • the waveform diagrams of FIG. 9 respectively illustrate the signal-to-noise distortion ratio of the multi-bit delta-sigma analog-to-digital converter including and excluding the data converter 10 of the present application.
  • the horizontal axis is amplitude (decibel); and the vertical axis is signal-to-noise distortion ratio (decibel).
  • Figure 9 shows the curves Cf_1, Cf_2, Cf_3 and Cf_4.
  • the curve Cf_1 represents the signal-to-noise distortion ratio under ideal conditions.
  • the curve Cf_2 represents the signal-to-noise distortion ratio of the multi-bit delta-sigma analog-to-digital converter excluding the data converter 10 of the present application.
  • the curve Cf_3 represents the signal-to-noise distortion ratio of the mapping unit 114 of the present disclosure using the arrangement of the first embodiment of the present disclosure.
  • the curve Cf_4 represents the signal-to-noise distortion ratio of the mapping unit 114 of the present disclosure using the arrangement manner of the second embodiment of the present disclosure. It can be observed from FIG. 9 that through the mapping unit 114, the multi-bit delta-sigma analog-to-digital converter 10 can obtain a better signal-to-noise distortion ratio
  • a chip includes the data converter 112.
  • the chip may be a semiconductor chip implemented by a different process.
  • a chip includes a multi-bit delta-sigma analog-to-digital converter 10, for example, the chip may be a semiconductor chip implemented by a different process.
  • FIG. 10 is a block diagram of an embodiment of a multi-bit delta-sigma digital-to-analog converter 30 according to the present application.
  • the multi-bit delta-sigma digital-to-analog converter 30 is similar to the multi-bit delta-sigma analog-to-digital converter 10 of FIG. 1, except that the multi-bit delta-sigma digital-to-analog converter 30 includes an upsampling filter 300 and Feedback loop 302.
  • the feedback loop 302 is used to feed back the output terminal of the quantizer 104 to the output terminal of the upsampling filter 300.
  • the input terminal 98 is used to receive a digital signal, and the up-sampling filter 300 is coupled to the input terminal 98 and generates an up-sampling signal U_D according to the digital signal.
  • the loop filter 102 is used to generate the loop filter signal LF_A according to the up-sampled signal U_D and the quantized signal Q_D of the feedback loop 302.
  • the quantizer 104 is coupled to the loop filter 102 and is used to generate the loop filter signal LF_A Quantize signal Q_D.
  • the incremental data weighted average circuit 110 is used to provide the input signal Sin required by the data converter 112 based on the quantized signal Q_D.
  • the data converter 112 is used to generate an output signal Sout as an analog signal based on the input signal Sin.
  • the mapping unit 114 can effectively suppress the single-tone spurious of the multi-bit delta-sigma digital-to-analog converter 30, and thereby obtain a better signal-to-noise distortion ratio.
  • a chip includes a multi-bit delta-sigma digital-to-analog converter 30.
  • the chip may be a semiconductor chip implemented by a different process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

本申请公开了一种数据转换器(112)。所述数据转换器包括输入端(98)、数模转换器(116)以及映射单元(114)。所述输入端用来接收输入信号。所述数模转换器包括多个数模转换器单元用来产生输出信号。所述映射单元，耦接于所述输入端以及所述数模转换器之间，用来使所述多个数模转换器单元依据所述多个数模转换器单元的特定电气特性来在所述多个数模转换器单元被选通的一相对顺序上等效地排列以进行数字模拟转换。本申请另提供模数转换器、数模转换器及相关芯片。

Description

数据转换器以及相关模数转换器、数模转换器及芯片 技术领域
本申请涉及一种转换器，尤其涉及一种数据转换器以及相关模数转换器、数模转换器及芯片。
背景技术
在多比特Δ-Σ模数转换器及数模转换器中，为解决组件适配误差问题，数据加权平均技术被提出，以对组件适配误差进行一阶噪声整形(1st-order noise shaping)，藉此大幅度地改善信噪失真比。然而，在当输入信号的幅值相对小(例如幅值约为-50dBFS)时，数据加权平均技术在数模转换器单元的选择样式上会产生重复性，并折迭回频带内，产生单音杂散(spurious tone)，仍会使信噪失真比变差。
目前常用的解决方式是在数模转换器中额外加入一个数模转换器单元，此技术称为递增式数据加权平均技术。在当输入信号的幅值相对小时，通过采用递增式数据加权平均技术能使数模转换器单元的选择样式不易产生重复性，进而消除单音杂散。然而，在输入信号的幅值在约1LSB附近时，仍会使数模转换器单元的选择样式产生重复性，进而产生单音杂散。
有鉴于此，需要进一步改良及创新以改善上述情况。
发明内容
本申请的目的之一在于公开一种数据转换器，尤其涉及一种数据转换器、模数转换器、数模转换器以及相关芯片，来解决上述问题。
本申请的一实施例公开了一种数据转换器。所述数据转换器包括输入端、数模转换器以及映射单元。所述输入端用来接收输入信号。所述数模转换器包括多个数模转换单元用来产生输出信号。所述映射单元，耦接于所述输入端以及所述数模转换器之间，用来使所述多个数模转换单元依据所述多个数模转换单元的特定电气特性来在所述多个数模转换单元被选通的一相对顺序上等效地排列以进行数字模拟转换。
本申请的一实施例公开了一种模数转换器，用来将模拟信号转换为数字信号。所述模数转换器包括输入端、低通滤波器、量化器以及反馈环路。所述输入端用来接收所述模拟信号。所述低通滤波器，耦接于所述输入端，并依据所述模拟信号产生低通信号。所述量化器用来依据所述低通信号产生量化信号。所述反馈环路用来将所述量化信号反馈至所述低通滤波器的输出端。所述反馈环路包括所述数据转换器。
本申请的一实施例公开了一种数模转换器，用来将数字信号转换为模拟信号。所述数模转换器包括输入端、上采样滤波器、量化器以及所述数据转换器。所述输入端用来接收所述数字信号。所述上采样滤波器，耦接于所述输入端，并依据所述数字信号产生上采样信号。所述量化器用来依据所述上采样信号产生量化信号。所述数据转换器用来根据所述量化信号产生所述模拟信号。
本申请的一实施例公开了一种芯片。所述芯片包括所述数据转换器。
本申请的一实施例公开了一种芯片。所述芯片包括所述模数转换器。
本申请的一实施例公开了一种芯片。所述芯片包括所述数模转换器。
本申请所公开的数据转换器、模数转换器、数模转换器以及相关芯片在数模转换单元的选择样式上产生重复性时仍能够有效抑制单 音杂散，藉此改善信噪失真比。
附图说明
图1为本申请多比特Δ-Σ模数转换器的实施例的方块示意图。
图2为本申请数据转换器的实施例的方块示意图。
图3为本申请多个数模转换单元的特定电气特性的幅值的柱状图。
图4为本申请的各数模转换单元的选通情况的示意图。
图5为本申请相关于图3的各幅值在等效地排列前及整理后的柱状图。
图6A为本申请排列偶数个数模转换单元的方法的第一实施例的示意图。
图6B为本申请排列奇数个数模转换单元的方法的第一实施例的示意图。
图6C为相关于图5的各幅值按照图6B所示的方法在等效地排列后的柱状图。
图7为本申请多比特Δ-Σ模数转换器输出的数字信号的频谱图。
图8A为本申请排列偶数个数模转换单元的方法的第二实施例的示意图。
图8B为本申请排列奇数个数模转换单元的方法的第二实施例的示意图。
图8C为相关于图5的各幅值按照图8B所示的方法在等效地排列后的柱状图。
图9的波形图分别图式说明包括及不包括本申请的数据转换器的多比特Δ-Σ模数转换器的信噪失真比。
图10为本申请多比特Δ-Σ数模转换器的实施例的方块示意图。
其中，附图标记说明如下：
10                                 多比特Δ-Σ模数转换器
98                                 输入端
100                                低通滤波器
102                                环路滤波器
104                                量化器
106                                抽取滤波器
108                                反馈环路
110                                递增式数据加权平均电路
112                                数据转换器
114                                映射单元
116                                数模转换器
118                                逻辑单元
120                                输入端
122                                输出端
LPF_A                              低通信号
LF_A                               环路滤波信号
Q_D                                量化信号
Sin                                输入信号
Sout                               输出信号
20_1-20_N                          数模转换单元
A 1-A 33                             位置
B 1-B 33                             位置
C 1-C 33                             位置
D 1-D 33                             位置
Cf_1                               曲线
Cf_2                               曲线
Cf_3                               曲线
Cf_4                               曲线
30                                 多比特Δ-Σ数模转换器
300                                上采样滤波器
302                         反馈环路
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因 此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
图1为本申请多比特Δ-Σ(sigma-delta)模数转换器10的实施例的方块示意图。参照图1，多比特Δ-Σ模数转换器10用来将模拟信号转换为数字信号。多比特Δ-Σ模数转换器10包括输入端98、低通滤波器(low pass filter，LPF)100、环路滤波器(loop filter)102、量化器104、抽取滤波器(decimation filter)106、递增式数据加权平均(incremental data weighted averaging，IDWA)电路110、数据转换器112及逻辑单元118，其中，递增式数据加权平均电路110和数据转换器112是位於反馈环路108上。递增式数据加权平均电路110耦接于量化器104和数据转换器112之间。
输入端98用來接收模拟信号，低通滤波器100耦接至输入端98，并依据模拟信号产生低通信号LPF_A。环路滤波器102用来依据低通信号LPF_A以及反馈环路108的輸出Sout來产生环路滤波信号LF_A，量化器104耦接至环路滤波器102，並用来依据环路滤波信号LF_A产生量化信号Q_D。抽取滤波器106用来基于量化信号Q_D提供多比特的数字信号。反馈环路108用来将量化信号Q_D反馈至低通滤波器100的输出端。详言之，递增式数据加权平均电路110用来基于量化信号Q_D提供数据转换器112所需的输入信号Sin。数据转换器112用来基于输入信号Sin产生输出信号Sout至逻辑单元118。逻辑单元118用来將低通信号LPF_A減去输出信号Sout後提供至环路滤波器102。應注意的是，本申請不以递增式数据加权平均电路110為限，在一些实施例中，递增式数据加权平均电路110可改用其他類似功能的電路來實現，舉例來說，亦可使用数据加权平均电路来代替递增式数据加权平均电路110。
图2为本申请数据转换器112的实施例的方块示意图。参照图2， 数据转换器112包括用来接收多比特的输入信号Sin的输入端120、用来输出输出信号Sout的输出端122、映射单元114以及数模转换器116。
数模转换器116包括数模转换单元20_1、20_2、…20_N，其中N为正整数。数模转换器116用来产生输出信号Sout。数模转换器116可以是任何可用于将数字信号转换成模拟信号形式，例如电流、电荷或电压的电路单元。举例来说，数模转换器116中可包括电流源、电容器、电阻器、或其他任何符合上述定义的电子组件。
映射单元114，耦接于输入端120以及数模转换器116之间，用来使数模转换单元20_1、20_2、…20_N依据数模转换单元20_1、20_2、…20_N的特定电气特性来在多个数模转换单元20_1、20_2、…20_N被选通的一相对顺序上等效地排列以进行数字模拟转换。具體來說，等效地排列并非指使数模转换单元20_1、20_2、…20_N依据数模转换单元20_1、20_2、…20_N的特定电气特性來在电路布局图上排列，而是透过映射单元114來配置数模转换单元20_1、20_2、…20_N与递增式数据加权平均电路110之间的连接關係。
举例来说，可以在数据转换器112出厂或每次上电时，分别量测数模转换单元20_1、20_2、…20_N的特定电气特性并产生多个量测结果，再依据所述多个量测结果来对映射单元114进行程式设计，但本申请不以此限。通過映射单元114可以有效地抑制多比特Δ-Σ模数转换器10的单音杂散，并进而得到较佳的信噪失真比。
在一些实施例中，特定电气特性是相关于电流特性。举例来说，当数模转换单元20_1、20_2、…20_N包括电流源时，特定电气特性包括所述电流源提供的电流。量测电流特性的方式可采用任何现有技术来实施。
在一些实施例中，特定电气特性是相关于电压特性。举例来说，当数模转换单元20_1、20_2、…20_N包括电容器时，特定电气特性包括所述电容器储存的与电压相关的电荷。量测电压特性的方式可采用任何现有技术来实施。
在本公开中，为了方便讨论，在下文中，N值设定为33，亦即数模转换器116包括33个数模转换单元20_1、20_2、…20_33。
图3为本申请数模转换单元20_1、20_2、…20_33的特定电气特性的幅值的柱状图。参照图3，横轴代表数模转换单元20_1、20_2、…20_33在等效地排列前的位置，即原始的排列顺序，从位置A 1至A 33，为了图式简洁未于图3全数标出。在启始状态时，数据转换器112一开始收到的第一笔输入信号Sin1会使从位置A 1开始的若干数量的数模转换单元被选通，例如位置位于A 1至A 10的若干数模转换单元，依据第一笔输入信号Sin1的大小而定。接着数据转换器112收到的第二笔输入信号Sin2会使从位置A 11开始的若干数量的数模转换单元被选通，例如位置位于A 11至A 30的若干数模转换单元，依据第二笔输入信号Sin2的大小而定。接着数据转换器112收到的第三笔输入信号Sin3会使从位置A 31开始的若干数量的数模转换单元被选通，若超过位置A 33则会跳回位置A 1开始继续选通数模转换单元，第三笔输入信号Sin3会使从位置A 31至A 33以及接著从位置A 1至A 6的若干数量的数模转换单元被選通，之後的操作則依此類推。
图3的纵轴則代表数模转换单元20_1、20_2、…20_33的特定电气特性的归一化幅值，以数值1为归一化参考值。由于製造過程變化的存在，各数模转换单元20_1、20_2、…20_33间存在组件适配误差，因此特定电气特性的大小會略有差異。换言之，每一数模转换单元20_1、20_2、…20_33的特定电气特性与参考值1具有电气特性差异值。
参回至图1。假设多比特Δ-Σ模数转换器10不包括映射单元114，而使数模转换单元20_1、20_2、…20_33直接受控于递增式数据加权平均电路110。再参照图3，数模转换单元20_1、20_2、…20_33包括位置位于A 1至A 17的若干数模转换单元以及位置位于A 18至A 33的若干数模转换单元。在一种情况中，位置位于A 1-A 17的若干数模转换单元的特定电气特性的总和相对地大，而位置位于A 18-A 33的若干数模转换单元的特定电气特性的总和相对地小。在上述假设下，一旦数模转 换单元20_1、20_2、…20_33的选择样式产生重复性(详细描述于图4)，单音杂散将特别地显著，进而使信噪失真比变差。
图4为本申请的数模转换单元20_1、20_2、…20_33的选通情况的示意图。参照图4，纵栏显示的码(1)代表量化器104一开始依据第一笔低通信号LPF_A产生量化信号Q_D；接着，码(2)代表量化器104依据第二笔低通信号LPF_A产生量化信号Q_D，依此类推。码(1)等号后的数值代表量化信号Q_D的数值。举例来说，码(1)＝16代表量化信号Q_D为16，此意味着依据第一笔低通信号LPF_A选通十六个数模转换单元。在启始状态时，从位置位于A 1开始的若干数量的数模转换单元被选通。在本实施例中，位置位于A 1至A 16的若干数模转换单元被选通。因为递增式数据加权平均电路110的功能，当码(2)＝17，将从位于位置A 16之后的位置A 17开始的若干数模转换单元被选通，直到选到位置位于A 33的数模转换单元。当码(3)＝17，将跳回位置A 1开始选通，位置位于A 1至A 17的若干数模转换单元被选通。同理，当码(4)＝16，位置位于A 18至A 33的若干数模转换单元被选通。当码(5)＝16，将跳回位置A 1开始选通，位置位于A 1至A 16的若干数模转换单元被选通。当码(6)＝17，位置位于A 17至A 33的若干数模转换单元被选通。
如图4所示，当数字信号输入序列为码(5)及码(6)，被选通的若干数模转换单元与数字信号输入序列为码(1)及码(2)时被选通的若干数模转换单元相同。因此，选择样式产生重复性。在例如如上所述的情况(位置位于A 1至A 16的若干数模转换单元的特定电气特性的总和相对地大，位置位于A 17至A 33的若干数模转换单元的特定电气特性的总和相对地小)，单音杂散将特别地显著，进而使信噪失真比变差。
通過映射单元114使数模转换单元20_1、20_2、…20_33等效地依据数模转换单元20_1、20_2、…20_33的每一个对应的所述电气特性差异值来排列。因此，可以有效地抑制多比特Δ-Σ模数转换器10的单音杂散，并进而得到较佳的信噪失真比。
图5为本申请相关于图3的各幅值在等效地排列前及整理后的柱状图。参照图5，横轴代表数模转换单元20_1、20_2、…20_33在等效地排列前及整理后的位置，从位置I 1至I 33，为了图式简洁未于图5全数标出。在图3中位于位置A 16的数模转换单元经整理后位于第一个位置I 1；类似地，在图3中位于位置A 30的数模转换单元经整理后位于最后一个位置I 33。映射单元114将特定电气特性从小至大依序排列。据此，映射单元114能相对容易判断出数模转换单元20_1、20_2、…20_33的特定电气特性大小，以相对方便地执行之后的等效地排列数模转换单元20_1、20_2、…20_33的程序。需注意的是，本操作为可选择的。在一些实施例中，可省略本操作。
图6A为本申请排列偶数个数模转换单元的方法的第一实施例的示意图。参照图6A，先将具有最小特定电气特性的位于位置I 1的数模转换单元等效地排列在相对顺序上的第一个位置，以及将具有最大特定电气特性的位于位置I 33的数模转换单元等效地排列在相对顺序上的第二个位置；接着，将具有次小特定电气特性的数模转换单元排列在相对顺序上的第三个位置，以及将具有次大特定电气特性的数模转换单元排列在相对顺序上的第四个位置，依此类推。简言之，经等效地排列后，在相对顺序中，第2K-1位被选通的数模转换单元的特定电气特性的幅值在多个数模转换单元20_1、20_2、…20_33的特定电气特性的幅值中排名第K名，以及第2k位被选通的数模转换单元的特定电气特性的幅值在多个数模转换单元20_1、20_2、…20_33的特定电气特性的幅值中排名第N-K+1名，其中N为多个数模转换单元20_1、20_2、…20_33的数量，在本实施例中，N为33，以及其中K≥1且K≤N。例如：一实施例中是根据数模转换单元的相关电压的幅值进行等效的排序，即先将数模转换单元中相关电压的幅值最大与最小的数模转换单元摆放在第一与第二个位置，接着把次大与次小的数模转换单元摆放在第三与第四个位置，以此类推大小排序第k与第N-k+1的数模转换单元摆放在第2k-1与第2k个位置。
图6B为本申请排列奇数个数模转换单元的方法的第一实施例的 示意图。参照图6B，等效地排列奇数个数模转换单元的逻辑与等效地排列偶数个数模转换单元的逻辑相同，于此不再赘述。
图6C为相关于图5的各幅值按照图6B所示的方法在等效地排列后的柱状图。参照图6C，横轴代表数模转换单元20_1、20_2、…20_33在等效地排列后的位置，从位置C 1至C 33，为了图式简洁未于图6C全数标出。在启始状态时，数据转换器112一开始收到的第一笔输入信号Sin1会使从位置C 1开始的若干数量的数模转换单元被选通，例如位置位于C 1至C 10的若干数模转换单元，依据第一笔输入信号Sin1的大小而定。接着数据转换器112收到的第二笔输入信号Sin2会使从位置C 11开始的若干数量的数模转换单元被选通，例如位置位于C 11至C 30的若干数模转换单元，依据第二笔输入信号Sin2的大小而定。接着数据转换器112收到的第三笔输入信号Sin3会使从位置C 31开始的若干数量的数模转换单元被选通，若超过位置C 33则会跳回位置C 1开始继续选通数模转换单元，之後的操作則依此類推。
如图6C所示，等效地排列数模转换单元20_1、20_2、…20_33后，在等效地排列前位于位置A 16的数模转换单元的位置在等效地排列后排列至位置C 1；以及，在等效地排列前位于位置A 30的数模转换单元的位置在等效地排列后排列至位置C 2。
此外，等效地排列后的数模转换单元20_1、20_2、…20_33中，排列于奇数位置(例如位置C 1、C 3、C 5)的若干数模转换单元的特定电气特性的幅值呈升序排列。此外，等效地排列后的数模转换单元20_1、20_2、…20_33中，排列于偶数位置(例如位置C 2、C 4、C 6)的若干数模转换单元的特定电气特性的幅值呈降序排列。然而，本公开不限定于此。在其他实施例中，等效地排列后的数模转换单元20_1、20_2、…20_33中，排列于奇数位置的若干数模转换单元的特定电气特性的幅值呈降序排列；以及，等效地排列后的数模转换单元20_1、20_2、…20_33中，排列于偶数位置的若干数模转换单元的特定电气特性的幅值呈升序排列。
参回至图3，等效地排列前的数模转换单元20_1、20_2、…20_33 的前半部分的若干数模转换单元位于位置A 1至A 17。位于位置A 1至A 17的若干数模转换单元的每一个对应的电气特性差异值的总和為第一总和。等效地排列前的数模转换单元20_1、20_2、…20_33的后半部分的若干数模转换单元位于位置A 18至A 33。位于位置A 18至A 33的若干数模转换单元的每一个对应的电气特性差异值的总和為第二总和。
参回至图6C，等效地排列后的数模转换单元20_1、20_2、…20_33的前半部分的若干数模转换单元位于位置C 1至C 17。位于位置C 1至C 17的若干数模转换单元的每一个对应的电气特性差异值的总和為第三总和。等效地排列后的数模转换单元20_1、20_2、…20_33的后半部分的若干数模转换单元位于位置C 18至C 33。位于位置C 18至C 33的若干数模转换单元的每一个对应的电气特性差异值的总和為第四总和。第三总和及第四总和的差小于第一总和及第二总和的差。换言之，等效地排列后的数模转换单元20_1、20_2、…20_33的前半部份的若干数模转换单元的电气特性差异值与后半部份的若干数模转换单元的电气特性差异值的差异相对小。据此，即使在选择样式上产生如图4所示的重复性，仍可以有效地抑制多比特Δ-Σ模数转换器10的单音杂散，并进而得到较佳的信噪失真比。
此外，本申请的其他实施例还包括图6C所衍生的排列方式。举例来说，位置C 1向后平移一个位置、位置C 2也据此向后平移一个位置、依此类推。位置C 33则平移到目前位置C 1的位置。此种排列方式亦不脱离第一实施例的范畴。此外，在上述示例中，平移的数量为一个仅是示例。在本公开中，平移的位置的数量可为任意数量。
图7为本申请多比特Δ-Σ模数转换器10输出的数字信号的频谱图。参照图7，横轴为频率(赫兹)；以及，纵轴为幅值(分贝)。如图7的频谱图所证实，可以有效地抑制多比特Δ-Σ模数转换器10的单音杂散。
图8A为本申请排列偶数个数模转换单元的方法的第二实施例的示意图。参照图8A，先将具有最小特定电气特性的位于位置I 1的数模转换单元等效地排列在相对顺序上的第一个位置，以及将具有最大 特定电气特性的位于位置I 33的数模转换单元等效地排列在相对顺序上的第二个位置；接着，将具有次小特定电气特性的数模转换单元等效地排列在相对顺序上的倒数第二个位置，以及将具有次大特定电气特性的数模转换单元等效地排列在相对顺序上的最后一个位置，依此类推。
图8B为本申请排列奇数个数模转换单元的方法的第二实施例的示意图。参照图8B，等效地排列奇数个数模转换单元的逻辑与等效地排列偶数个数模转换单元的逻辑相同，于此不再赘述。
图8C为相关于图5的各幅值按照图8B所示的方法在等效地排列后的柱状图。参照图8C，横轴代表数模转换单元20_1、20_2、…20_33在等效地排列后的位置，从位置D 1至D 33，为了图式简洁未于图8C全数标出。在启始状态时，数据转换器112一开始收到的第一笔输入信号Sin1会使从位置D 1开始的若干数量的数模转换单元被选通，例如位置位于D 1至D 10的若干数模转换单元，依据第一笔输入信号Sin1的大小而定。接着数据转换器112收到的第二笔输入信号Sin2会使从位置D 11开始的若干数量的数模转换单元被选通，例如位置位于D 11至D 30的若干数模转换单元，依据第二笔输入信号Sin2的大小而定。接着数据转换器112收到的第三笔输入信号Sin3会使从位置D 31开始的若干数量的数模转换单元被选通，若超过位置D 33则会跳回位置D 1开始继续选通数模转换单元，之後的操作則依此類推。
如图8C所示，等效地排列数模转换单元20_1、20_2、…20_33后，在等效地排列前位于位置A 16的数模转换单元的位置在等效地排列后改动至位置D 1；以及，在等效地排列前位于位置A 30的数模转换单元的位置在等效地排列后改动至位置D 2。
此外，等效地排列后的数模转换单元20_1、20_2、…20_33中，部份排列于奇数位置(例如位置D 1、D 3、D 5)的若干数模转换单元的特定电气特性的幅值呈升序排列，其余部份排列于奇数位置的若干数模转换单元的特定电气特性的幅值呈降序排列。
又，等效地排列后的数模转换单元20_1、20_2、…20_33中，部 份排列于偶数位置(例如位置D 2、D 4、D 6)的若干数模转换单元的特定电气特性的幅值呈降序排列，其余部份排列于偶数位置的若干数模转换单元的特定电气特性的幅值呈升序排列。然而，本申请不以此限。
等效地排列后的数模转换单元20_1、20_2、…20_33的前半部分的若干数模转换单元位于位置D 1至D 17。位于位置D 1至D 17的若干数模转换单元的每一个对应的电气特性差异值的总和為第五总和。等效地排列后的数模转换单元20_1、20_2、…20_33的后半部分的若干数模转换单元位于位置D 18至D 33。位于位置D 18至D 33的若干数模转换单元的每一个对应的电气特性差异值的总和為第六总和。第五总和及第六总和的差小于第一总和及第二总和的差。在一些特定的实施例中，第五总和及第六总和的差小于第三总和及第四总和的差。
通過映射单元114即使在选择样式上产生如图4所示的重复性，仍可以有效地抑制多比特Δ-Σ模数转换器10的单音杂散，并进而得到较佳的信噪失真比。
此外，本申请的其他实施例还包括图8C所衍生的排列方式。举例来说，位置D 1向后平移一个位置、位置D 2也据此向后平移一个位置、依此类推。位置D 33则平移到目前位置D 1的位置。此种排列方式亦不脱离第二实施例的范畴。此外，在上述示例中，平移的数量为一个仅是示例。在本申请中，平移的位置的数量可为任意数量。
图9的波形图分别图式说明包括及不包括本申请的数据转换器10的多比特Δ-Σ模数转换器的信噪失真比。参照图9，横轴为幅值(分贝)；以及，纵轴为信噪失真比(分贝)。图9显示曲线Cf_1、Cf_2、Cf_3及Cf_4。曲线Cf_1代表理想情况下的信噪失真比。曲线Cf_2代表不包括本申请的数据转换器10的多比特Δ-Σ模数转换器的信噪失真比。曲线Cf_3代表本公开的映射单元114采用本公开第一实施例的排列方式的信噪失真比。曲线Cf_4代表本公开的映射单元114采用本公开第二实施例的排列方式的信噪失真比。从图9可观察出，通過映射单元114，多比特Δ-Σ模数转换器10可得到较佳的信噪失真比
在一些实施例中，一种芯片包括数据转换器112，舉例來說該芯片可以是不同工藝實現的半導體芯片。
在一些实施例中，一种芯片包括多比特Δ-Σ模数转换器10，舉例來說該芯片可以是不同工藝實現的半導體芯片。
图10为本申请多比特Δ-Σ数模转换器30的实施例的方块示意图。参照图10，多比特Δ-Σ数模转换器30类似于图1的多比特Δ-Σ模数转换器10，差别在于，多比特Δ-Σ数模转换器30包括上采样滤波器300以及反馈环路302。反馈环路302用来将量化器104的输出端反馈至上采样滤波器300的输出端。
输入端98用來接收数字信号，上采样滤波器300耦接至输入端98，并依据数字信号产生上采样信号U_D。环路滤波器102用来依据上采样信号U_D以及反馈环路302的量化信号Q_D來产生环路滤波信号LF_A，量化器104耦接至环路滤波器102，並用来依据环路滤波信号LF_A产生量化信号Q_D。递增式数据加权平均电路110用来基于量化信号Q_D提供数据转换器112所需的输入信号Sin。数据转换器112用来基于输入信号Sin产生输出信号Sout做为模拟信号。
通過映射单元114可以有效地抑制多比特Δ-Σ数模转换器30的单音杂散，并进而得到较佳的信噪失真比。
在一些实施例中，一种芯片包括多比特Δ-Σ数模转换器30，舉例來說該芯片可以是不同工藝實現的半導體芯片。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (18)

  1. 一种数据转换器，其特征在于，所述数据转换器包括:
    输入端，用来接收输入信号；
    数模转换器，包括多个数模转换单元，用来产生输出信号；以及
    映射单元，耦接于所述输入端以及所述数模转换器之间，用来使所述多个数模转换单元依据所述多个数模转换单元的特定电气特性在所述多个数模转换单元被选通的相对顺序上等效地排列以进行数字模拟转换。
  2. 如权利要求1所述的数据转换器，其中所述特定电气特性是相关于电流特性及电压特性的一者。
  3. 如权利要求1或2所述的数据转换器，其中每一数模转换单元的所述特定电气特性与参考值具有电气特性差异值，所述映射单元使所述多个数模转换单元等效地依据所述多个数模转换单元的每一个对应的所述电气特性差异值来排列。
  4. 如权利要求3所述的数据转换器，其中等效地排列前的所述多个数模转换单元的前半部分的每一个对应的所述电气特性差异值的总和為第一总和，等效地排列前的所述多个数模转换单元的后半部分的每一个对应的所述电气特性差异值的总和為第二总和，等效地排列后的所述多个数模转换单元的前半部分的每一个对应的所述电气特性差异值的总和為第三总和，等效地排列后的所述多个数模转换单元的后半部分的每一个对应的所述电气特性差异值的总和為第四总和，且所述第三总和与所述第四总和的差小于所述第一总和与所述第二总和的差。
  5. 如权利要求3所述的数据转换器，其中等效地排列后的所述多个数模转换单元中，排列于奇数位置的所述多个数模转换单元的所述特定电气特性的幅值呈升序排列；等效地排列后的所述多个数 模转换单元中，排列于偶数位置的所述多个数模转换单元的所述特定电气特性的幅值呈降序排列。
  6. 如权利要求3所述的数据转换器，其中在所述相对顺序中，第2K-1位被选通的数模转换单元的所述特定电气特性的幅值在所述多个数模转换单元的所述特定电气特性的幅值中排名第K名，以及第2k位被选通的数模转换单元的所述特定电气特性的幅值在所述多个数模转换单元的所述特定电气特性的幅值中排名第N-K+1名，其中N为所述多个数模转换单元的数量，以及其中K≥1且K≤N。
  7. 如权利要求3所述的数据转换器，其中等效地排列后的所述多个数模转换单元中，排列于奇数位置的所述多个数模转换单元的所述特定电气特性的幅值呈降序排列；等效地排列后的所述多个数模转换单元中，排列于偶数位置的所述多个数模转换单元的所述特定电气特性的幅值呈升序排列。
  8. 一种模数转换器，用来将模拟信号转换为数字信号，其特征在于，所述模数转换器包括:
    输入端，用来接收所述模拟信号；
    低通滤波器，耦接于所述输入端，并依据所述模拟信号产生低通信号；
    量化器，用来依据所述低通信号产生量化信号；以及
    反馈环路，用来将所述量化信号反馈至所述低通滤波器的输出端，其中所述反馈环路包括：
    如权利要求1-7中任一项所述的数据转换器。
  9. 如权利要求8所述的模数转换器，更包括：
    数据加权平均电路，耦接于所述量化器和所述数据转换器之间，用来基于所述量化信号提供所述输入信号至所述数据转换器的所述输入端。
  10. 如权利要求8所述的模数转换器，更包括：
    递增式数据加权平均电路，耦接于所述量化器和所述数据转换器之间，用来基于所述量化信号提供所述输入信号至所述数据转换器的所述输入端。
  11. 如权利要求8-10任一项中所述的模数转换器，更包括：
    抽取滤波器，用来基于所述量化信号提供所述数字信号。
  12. 一种数模转换器，用来将数字信号转换为模拟信号，其特征在于，所述数模转换器包括:
    输入端，用来接收所述数字信号；
    上采样滤波器，耦接于所述输入端，并依据所述数字信号产生上采样信号；
    量化器，用来依据所述上采样信号产生量化信号；以及
    如权利要求1-7中任一项所述的数据转换器，用来根据所述量化信号产生所述模拟信号。
  13. 如权利要求12所述的数模转换器，更包括：
    数据加权平均电路，耦接于所述量化器和所述数据转换器之间，用来基于所述量化信号提供所述输入信号至所述数据转换器的所述输入端。
  14. 如权利要求12所述的数模转换器，更包括：
    递增式数据加权平均电路，耦接于所述量化器和所述数据转换器之间，用来基于所述量化信号提供所述输入信号至所述数据转换器的所述输入端。
  15. 如权利要求12-14任一项中所述的数模转换器，更包括：
    反馈环路，用来将所述量化信号反馈至所述上采样滤波器的输出端。
  16. 一种芯片，其特征在于，所述芯片包括：
    如权利要求1-7任一项中所述的数据转换器。
  17. 一种芯片，其特征在于，所述芯片包括：
    如权利要求8-11任一项中所述的模数转换器。
  18. 一种芯片，其特征在于，所述芯片包括：
    如权利要求12-15任一项中所述的数模转换器。
PCT/CN2019/076055 2019-02-25 2019-02-25 数据转换器以及相关模数转换器、数模转换器及芯片 WO2020172769A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201980000254.4A CN109997308A (zh) 2019-02-25 2019-02-25 数据转换器以及相关模数转换器、数模转换器及芯片
PCT/CN2019/076055 WO2020172769A1 (zh) 2019-02-25 2019-02-25 数据转换器以及相关模数转换器、数模转换器及芯片
JP2020538793A JP2021517377A (ja) 2019-02-25 2019-02-25 データ変換器と、関連するアナログ−デジタル変換器、デジタル−アナログ変換器およびチップ
EP19888242.5A EP3731415A4 (en) 2019-02-25 2019-02-25 DATA CONVERTER, ASSOCIATED ANALOGUE-DIGITAL CONVERTER AND DIGITAL-ANALOGUE CONVERTER AND CHIPS
US16/889,316 US11245413B2 (en) 2019-02-25 2020-06-01 Data converter and related analog-to-digital converter, digital-to-analog converter and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/076055 WO2020172769A1 (zh) 2019-02-25 2019-02-25 数据转换器以及相关模数转换器、数模转换器及芯片

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/889,316 Continuation US11245413B2 (en) 2019-02-25 2020-06-01 Data converter and related analog-to-digital converter, digital-to-analog converter and chip

Publications (1)

Publication Number Publication Date
WO2020172769A1 true WO2020172769A1 (zh) 2020-09-03

Family

ID=67136932

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/076055 WO2020172769A1 (zh) 2019-02-25 2019-02-25 数据转换器以及相关模数转换器、数模转换器及芯片

Country Status (5)

Country Link
US (1) US11245413B2 (zh)
EP (1) EP3731415A4 (zh)
JP (1) JP2021517377A (zh)
CN (1) CN109997308A (zh)
WO (1) WO2020172769A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111884727B (zh) * 2020-07-15 2021-11-16 杭州电子科技大学 一种基于数字映射的高速光子数模转换方法及系统
US11394395B1 (en) 2021-01-26 2022-07-19 Nxp B.V. Techniques for linearizing digital-to-analog converters in sigma-delta analog-to-digital converters
US11463101B2 (en) 2021-01-26 2022-10-04 Nxp B.V. Techniques for high-speed excess loop delay compensation in sigma-delta analog-to-digital converters

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479416B (en) * 2001-05-28 2002-03-11 Advanic Technologies Inc Multibit sigma-delta modulators with reduced based tonal problem by using dynamic element matching technique
CN101562454A (zh) * 2009-05-12 2009-10-21 凌阳多媒体股份有限公司 动态元件匹配的数字/模拟转换系统及积分三角调制装置
US20130268572A1 (en) * 2012-04-10 2013-10-10 Electronics And Telecommunications Research Institute Accumulator and data weighted average device including the accumulator
CN106899304A (zh) * 2017-01-19 2017-06-27 电子科技大学 一种基于数据权重平均化方法的多比特sigma‑delta调制器及调制方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0575456A (ja) * 1991-09-13 1993-03-26 Nec Corp Ａ／ｄ変換器
JP3771006B2 (ja) * 1997-07-09 2006-04-26 株式会社ルネサステクノロジ Ｄ／ａコンバータ
US6118398A (en) * 1998-09-08 2000-09-12 Intersil Corporation Digital-to-analog converter including current sources operable in a predetermined sequence and associated methods
WO2002023727A2 (en) * 2000-09-11 2002-03-21 Broadcom Corporation Method and apparatus for mismatch shaping of an oversampled converter
KR20060135074A (ko) * 2004-04-20 2006-12-28 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 디지털-아날로그 변환기에서의 에러 감소율 개선 방법 및디지털-아날로그 변환기
US8212700B2 (en) * 2009-07-09 2012-07-03 Stellamar Llc Delta-sigma-delta modulator
US8022850B2 (en) * 2009-09-25 2011-09-20 Freescale Semiconductor, Inc. Multiple-bit, digital-to-analog converters and conversion methods
EP2993787B1 (en) * 2014-09-05 2020-07-15 Dialog Semiconductor (UK) Ltd Generalized data weighted averaging method for equally weighted multi-bit D/A elements
CN110663188B (zh) * 2017-06-21 2023-04-04 德州仪器公司 分段式数/模转换器
US10615821B2 (en) * 2018-04-30 2020-04-07 Microchip Technology Incorporated Charge-based digital to analog converter with second order dynamic weighted algorithm

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479416B (en) * 2001-05-28 2002-03-11 Advanic Technologies Inc Multibit sigma-delta modulators with reduced based tonal problem by using dynamic element matching technique
CN101562454A (zh) * 2009-05-12 2009-10-21 凌阳多媒体股份有限公司 动态元件匹配的数字/模拟转换系统及积分三角调制装置
US20130268572A1 (en) * 2012-04-10 2013-10-10 Electronics And Telecommunications Research Institute Accumulator and data weighted average device including the accumulator
CN106899304A (zh) * 2017-01-19 2017-06-27 电子科技大学 一种基于数据权重平均化方法的多比特sigma‑delta调制器及调制方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3731415A4 *

Also Published As

Publication number Publication date
US20210203350A1 (en) 2021-07-01
CN109997308A (zh) 2019-07-09
EP3731415A1 (en) 2020-10-28
JP2021517377A (ja) 2021-07-15
EP3731415A4 (en) 2021-11-24
US11245413B2 (en) 2022-02-08

Similar Documents

Publication Publication Date Title
CN107819467B (zh) 具有可编程的相位的时间交错式adc
CN106685424B (zh) 用于模数转换器的微处理器辅助校准
CN106253908B (zh) 过采样δ-σ调制器的超低功耗双量化器架构
WO2020172769A1 (zh) 数据转换器以及相关模数转换器、数模转换器及芯片
US8587464B2 (en) Off-line gain calibration in a time-interleaved analog-to-digital converter
US8760335B1 (en) Externally controlled data converter with configurable functions
US9258004B2 (en) Customized data converters
CN109586720A (zh) 模数转换器及其工作方法
US5905453A (en) Dithered sigma delta modulator having programmable full scale range adjustment
US20180026781A1 (en) Data handoff between randomized clock domain to fixed clock domain
TWI645680B (zh) 類比至數位轉換裝置及其類比至數位轉換器校正方法
TW202127803A (zh) 具有校正功能之連續近似暫存器類比至數位轉換器及其校正方法
US20070236377A1 (en) Digital-to-analog converter
US11424754B1 (en) Noise-shaping analog-to-digital converter
CN102624398A (zh) 多比特数模转换器和三角积分模数转换器
WO2020181485A1 (zh) 模数转换器以及相关芯片
Kosonocky et al. Analog-to-digital conversion architectures
CN105322968B (zh) 一种应用于σδ模数转换器调制器的动态元件匹配方法
CN110739968B (zh) 适用于过采样sar adc的电容失配误差整形开关电路及方法
Jiang et al. Built-in Self-Calibration of On-chip DAC and ADC
TWI419475B (zh) 類比數位轉換器的測試系統與測試方法
CN113131933B (zh) 具校正功能连续近似缓存器模拟至数字转换器及校正方法
US10298257B1 (en) SNDR improvement through optimal DAC element selection
JPS5986328A (ja) アナログ／デジタルコンバ−タ
Lan et al. A 93.4-dB SNDR single-ended SAR ADC with a hybrid R–C DAC

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020538793

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2019888242

Country of ref document: EP

Effective date: 20200616

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19888242

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE