TW479416B

TW479416B - Multibit sigma-delta modulators with reduced based tonal problem by using dynamic element matching technique

Info

Publication number: TW479416B
Application number: TW90112817A
Authority: TW
Inventors: Tai-Hau Guo; Da-Huei Li
Original assignee: Advanic Technologies Inc
Priority date: 2001-05-28
Filing date: 2001-05-28
Publication date: 2002-03-11

Abstract

A technique which is referred to as ""advanced data weighted averaging"" for reducing baseband tonal problem and intermodulation distortions in multibit sigma-delta modulators employing data weighted averaging (DWA) is disclosed. An multibit analog-to-digital converter includes an analog loop filter, an (N+1)-level quantizer, a stepping element selection election logic, an internal (N+1)-level digital-to-analog converter (DAC), and a decimation filter, where N is an integer greater than one. This technique can shift the mismatch tones and intermodulation distortions outside the baseband by changing the starting element of each rotation orderly. According to the principle of this technique and the output of the (N+1)-level quantizer, the stepping element selection logic produces a set of control signals to select the N unit elements in the internal (N+1)-level DAC. This technique can also be applied to a multibit sigma-delta digital-to analog converter.

Description

479416 A7 B7 五、發明說明（1 ) 發明之領域 (請先閱讀背面之注意事項再填寫本頁) 此發明主要是關於超取樣轉換器，特別是採用動態元件匹配技術之多位元積分三角轉換器。發明之背景積分三角調變是近年來高解析度資料轉換之主流方式，其藉由超取樣、雜訊重整（noise shaping)及濾波機制來獲致高解析度。此技術已成功應用於直流量測、數位聲頻 (digital audio)及通訊系統等。由於通訊系統上的應用日趨廣泛，傳統單位元積分三角調變器已不適用於低超取樣比率、高信號頻寬的應用；因此，多位元積分三角調變器成爲解決此一問題的方式。然而，對多位元積分三角調變器而言，任何內部數位 /類比轉換器的誤差皆會在不經雜訊重整的情形下直接影響積分三角轉換器，故多位元內部迴授對線性度之要求甚高。經濟部智慧財產局員工消費合作社印製內部多位元數位/類比轉換器通常以數個單位元件實現，如：電容、電阻與電流開關。而元件變化會使得內部數位/類比轉換器之轉移函數呈現非線性，此效應反應在頻率域中將造成信號頻率之諧波失真。爲了解決此問題，各種技術被陸續提出；其中又以資料加權平均（data weighted averaging)的方式可將非理想內部數位/類比轉換器所產生之失真移往高頻且實現電路相對精簡而廣爲使用。然而，當此技術應用於多位元內部數位/類比轉換器時，會產生基 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479416 A7 B7 五、發明說明（2 ) (請先閱讀背面之注意事項再填寫本頁) 頻帶諧波及互調失真，進而影響整個積分三角轉換器的效能。因此，必須加入抖動信號（dither)以隨機化基頻帶諧波，但會造成整體基頻帶雜訊上升而減少其動態範圍，甚至有可能造成轉換器不穩定。爲了解決資料加權平均的問題，近年來提出了許多技術來解決這個問題；不過大多付出了信號 /雜訊失真比（signal-to-(noise and distortion) ratio, SNDR)降低的代價。然而，其中以Kuan-Dar Chen及 Tai-Haur Kuo 於其論文“An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither,” IEEE Transactions on Circuits and Systems II， pp. 63-68 (Jan. 1999)所提出之 improved DWA(IDWA)和 Morteza Vadipour 於其論文 “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in479416 A7 B7 V. Description of the invention (1) Field of invention (please read the notes on the back before filling this page) This invention is mainly about oversampling converters, especially multi-bit integral delta conversion using dynamic component matching technology Device. Background of the invention Integral triangular modulation is the mainstream method of high-resolution data conversion in recent years. It achieves high resolution through oversampling, noise shaping, and filtering mechanisms. This technology has been successfully used in DC measurement, digital audio and communication systems. Due to the increasing application of communication systems, traditional single-element integral delta modulators are no longer suitable for applications with low oversampling ratios and high signal bandwidths; therefore, multi-bit integral triangular modulators have become a way to solve this problem. . However, for a multi-bit integral delta-sigma modulator, the error of any internal digital / analog converter will directly affect the integral delta-converter without noise reshaping, so the multi-bit internal feedback pair The linearity requirements are very high. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Internal multi-bit digital / analog converters are usually implemented with several unit components, such as capacitors, resistors, and current switches. And the component changes will make the transfer function of the internal digital / analog converter appear non-linear. This effect reflects that it will cause harmonic distortion of the signal frequency in the frequency domain. In order to solve this problem, various technologies have been proposed successively; among them, the data weighted averaging method can be used to move the distortion generated by the non-ideal internal digital / analog converter to high frequencies and achieve relatively simple and widely used circuits. use. However, when this technology is applied to a multi-bit internal digital / analog converter, it will produce a basic 4-size paper that conforms to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 479416 A7 B7 V. Description of the invention (2) (Please read the notes on the back before filling this page) Band harmonics and intermodulation distortion, which will affect the performance of the integral delta-converter. Therefore, a dither signal must be added to randomize the baseband harmonics, but it will cause the overall baseband noise to rise and reduce its dynamic range, and may even cause the converter to be unstable. In order to solve the problem of data weighted average, many techniques have been proposed to solve this problem in recent years; however, most of them have paid the price of reducing the signal-to-noise and distortion ratio (SNDR). However, Kuan-Dar Chen and Tai-Haur Kuo in their thesis "An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither," IEEE on Circuits and Systems II, pp. 63 -68 (Jan. 1999) proposed improved DWA (IDWA) and Morteza Vadipour in their paper "Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in

Sigma-Delta Modulators，” IEEE Transactions on Circuits and 經濟部智慧財產局員工消費合作社印製Sigma-Delta Modulators, "printed by IEEE Transactions on Circuits and Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative

Systems II，pp.l 1 37-1 144 (Nov. 2000)所提出之 offset DWA (〇DWA)採用了”諧波移轉，，（tone-shifting)的觀念，可以在保有較好信號/雜訊失真比的狀態下，解決上述問題。不過，IDWA和ODWA在輸入信號含有特定直流成份時’ 仍有機會受到基頻帶諧波的影響。發明要旨此發明提出一名爲”步進式資料加權平均法，，(Advanced DWA)之技術，能減少採用資料加權平均法t -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479416 A7 B7____ 五、發明說明（3 ) (請先閱讀背面之注意事項再填寫本頁) 多位元積分三角調變器的基頻帶諧波及互調失真，而不犧牲信號/雜訊失真比’並且不易受輸入信號直流成份之影響，根據此發明’基頻帶諧波可被移往商頻，再藉由遽波器將之濾除。經濟部智慧財產局員工消費合作社印製本發明之（N+1)準位積分三角類比/數位轉換器包含一積分三角調變器及一降頻濾波器。該積分三角調變器包含一迴路濾波器、一（N+1)準位量化器、一步進式元件選擇邏輯、及一內部（N+1)準位數位/類比轉換器，其中N是大於一之整數。其中，內部（N+1)準位數位/類比轉換器有N個具元件不匹配的單位元件，初始以循環方式選取單位元件（如傳統資料加權平均法）來產生對應於內部（N+1)準位量化器的數位輸出之類比輸出信號，當完成一個循環後，將下一個循環開始的起始元件向前移動固定個數S，而接下來完成每次循環後，均將下一個循環開始的起始元件向前移動固定個數S，如此便可將多位元積分三角調變器之諧波移至基頻帶外，進而得到較佳之信號/雜訊失真比。如此的選擇方式是由步進式元件選擇邏輯所產生的信號來控制，而控制信號則是根據步進式元件選擇邏輯所接收之（N+1)準位量化器輸出及其內部循環起始元件位址所產生。本發明亦可應用於（N+1)準位積分三角數位/類比轉換器，包含一升頻濾波器、一（N +1)準位數位積分三角調變器、一步進式元件選擇邏輯、一內部（N + 1)準位數位/類比轉換器及一後級類比濾波器，其中N是大於一之整數。其中，內部（N+1)準位數位/類比轉換器有N個具元件不匹配的 • 6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479416 A7 B7_ 五、發明說明（4 ) (請先閱讀.t面之注意事項再填寫本頁) 單位元件，初姶以循環方式選取單位元件(如傳統資料加權平均法）來產生對應於內部（N + 1)準位量化器的數位輸出之類比輸出信號，當完成一個循環後，將下一個循環開始的起始元件向前移動固定個數S，而接下來完成每次循環後，均將下一個循環開始的起始元件向前移動固定個數S，如此便可將多位元積分三角調變器之諧波移至基頻帶外，進而得到較佳之信號/雜訊失真比。如此的選擇方式是由步進式元件選擇邏輯所產生的信號來控制，而控制信號則是根據步進式元件選擇邏輯所接收之（N+1)準位量化器輸出及其內部循環起始元件位址所產生。於上述兩種應用中，起始元件前移個數（步進個數）S 的預設値爲1至N之整數，可藉由S之預設値的訂定來使多位元積分三角調變器適切於不同效能要求之應用。附圖槪述圖一爲無採用動態元件匹配技術之先前技藝的多位元積分三角類比/數位轉換器的方塊圖。經濟部智慧財產局員工消費合作社印製圖二爲本發明之多位元積分三角類比/數位轉換器的方塊圖。圖三爲圖二中之步進式元件選擇邏輯的細部功能方塊圖。圖四爲無採用動態元件匹配技術之先前技藝的多位元積分三角數位/類比轉換器的方塊圖。圖五爲本發明之多位元積分三角數位/類比轉換器的 -7- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）經濟部智慧財產局員工消費合作社印製 479416 A7 B7 五、發明說明（5 ) 方塊圖。圖六爲依本發明之三階九準位多路徑迴授架構之積分三角類比/數位轉換器實例的方塊圖。圖七爲採用傳統資料加權平均法之三階九準位多路徑迴授架構之積分三角類比/數位轉換器的輸出頻譜’最大元件誤差設爲0.5%、輸入頻率爲取樣頻率之1/1024，輸入大小分別爲（a)-6dB (c)-45dB (e)-85dB，（b) (d)⑴分別爲相對應的數位類比轉換器雜訊頻譜。圖八爲依本發明之三階九準位多路徑迴授架構之積分三角類比/數位轉換器的輸出頻譜，最大元件誤差設爲 0.5%、輸入頻率爲取樣頻率之1/1024，輸入大小分別爲 U)-6dB (c)-45dB (e)-85dB，（b) (d)⑴分別爲相對應的數位類比轉換器雜訊頻譜。圖九爲依本發明之三階九準位多路徑迴授架構之積分三角類比/數位轉換器的信號/雜訊失真比圖。圖十爲依本發明之三階九準位多路徑迴授架構之積分三角類比/數位轉換器的基頻帶諧波總能量圖。圖十一爲依本發明之相關柱狀圖，在與圖七至圖十相同之狀況下，輸入大小爲-45dB，U)爲信號/雜訊失真比之改善柱狀圖（b)爲基頻帶諧波總能量之改善柱狀圖。圖十二爲比較輸入直流成份（由0LSB變化到1LSB)造成採用本發明技術及採用IDWA、ODWA之三階九準位多路徑迴授架構之積分三角類比/數位轉換器的信號/雜訊失真比降低程度的比較圖。本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----：----------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 479416 A7 B7___ 五、發明說明（6 ) 本發明之詳細描述 (請先閱讀背面之注音？事項再填寫本頁) 本發明提出一使用於（N+1)準位積分三角類比/數位轉換器之積分三角調變器，N爲大於一之整數，包含：一迴路濾波器用於接收其（N+1)準位積分三角類比/ 數位轉換器之類比輸入信號減去一內部類比迴授信號的一加總信號以產生一濾波信號；一（N +1)準位量化器用於量化一取樣頻率爲fs之濾波信號而產生一數位輸出碼；一步進式元件選擇邏輯用於產生一組對應於由（N+1) 準位量化器所接收的數位輸出碼之步進式控制信號S()、 S 1、…、S ( N · 1 )，及 --內部（N+1)準位數位/類比轉換器內含N個單位元件，而單位元件之間存有不匹配，其功能爲根據從歩進式元件選擇邏輯所接收的控制信號S()、Sj、…、S(N.n，來產生該內部類比迴授信號。經濟部智慧財產局員工消費合作社印製該（N+1)準位積分三角類比/數位轉換器包含一降頻濾波器用於將（N+1)準位量化器所產生之數位輸出碼降回基頻數位信號，而此信號即爲（N+1)準位積分三角類比/數位轉換器之數位輸出。該步進式元件選擇邏輯包含：一除以N之指標加法器，具有兩輸入端接收該 (N+1)準位量化器所產生之數位輸出碼及一前一時刻指標（delayed pointer，DPTR)，以及一輸出端輸出指標 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479416 A7 — _B7___ 五、發明說明（7 ) (請先閱讀背面之注意事項再填寫本頁) (pointer，PTR)，其計算該數位輸出碼與前一時刻指標之和A，SA<N，則指標値爲A ; gA>N，則指標値爲A 除以N後之餘數；一除以N之步進加法器，具有兩輸入端接收由除以N之指標加法器所傳來之指標（PTR)及由一步進控制信號產生器所傳來之步進個數S，以及一輸出端輸出已通過步進加法器之另一PTR，該另一PTR之獲得係計算PTR與S之和A’，若A’<N則另一 PTR爲A’ ；若A，>N，則另一 PTR爲A’除以N後之餘數；一第一累加暫存器與前述之步進加法器連接，其具有一輸入端接收該另一 PTR，及一輸出端輸出該前一時刻指標（DPTR)，該第一累加暫存器將該另一 PTR鎖閘（latching)—取樣週期；經濟部智慧財產局員工消費合作社印製一控制信號產生器其接收指標（PTR)及前一時刻指標（DPTR)並產生N個控制信號BG、B,、…、，其動作如下：PTR若大於DPTR，則BDPTR、B(DPTR + 1)、…、 B(PTR.l )爲 1 ’ 其餘皆爲0，若PTR小於DPTR，則BDPTR、 B(dptr + i)、···、Bn、B〇、Bi、爲 1 ’ 其餘皆爲〇 ’ 而若PTR等於DPTR，則所有N個控制信號BQ、Bi、…、 Β(Ν·!)皆爲 0 ; 一步進控制信號產生器其具有一預設的Sini， Sini爲1至N的整數，其接收來自於該控制信號產生器之 N個控制信號B。、Bi、…、Β(Ν_υ及一循環起始元件位址 SPTR，而產生Ν個步進式控制信號S。、Si、…、S(N、U及 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ^9416 A7 -----BZ__ 五、發明說明（8 ) (請先閱讀背面之注意事項再填寫本頁)Offset DWA (〇DWA) proposed by Systems II, pp.l 1 37-1 144 (Nov. 2000) uses the concept of "tone-shifting," which can maintain better signal / noise In the state of signal-to-distortion ratio, the above problems are solved. However, IDWA and ODWA still have the opportunity to be affected by the harmonics of the base band when the input signal contains a specific DC component. Summary of the Invention This invention proposes a "stepped data weighting" The averaging method, (Advanced DWA) technology, can reduce the use of data weighted averaging method t -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 479416 A7 B7____ 5. Description of the invention (3 ) (Please read the notes on the back before filling out this page) Multi-bit integral delta-sigma modulator baseband harmonics and intermodulation distortion without sacrificing the signal / noise distortion ratio 'and not easily affected by the DC component of the input signal Influence, according to this invention, the 'basic band harmonics can be shifted to the commercial frequency, and then filtered by the wave filter. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The (N + 1) level integral delta analog / digital converter of the present invention includes an integral delta modulator and a frequency reduction filter. The integrating delta modulator includes a loop filter, an (N + 1) level quantizer, a stepping element selection logic, and an internal (N + 1) level digit / analog converter, where N is greater than An integer of one. Among them, the internal (N + 1) quasi-bit / analog converter has N unit elements with mismatched components. Initially, the unit elements are selected in a circular manner (such as the traditional data weighted average method) to generate the corresponding (N + 1) ) The analog output signal of the digital output of the level quantizer. After completing one cycle, move the starting element of the next cycle forward by a fixed number S, and after each cycle is completed, the next cycle will be The starting element at the beginning is moved forward by a fixed number S, so that the harmonics of the multi-bit integral delta modulator can be moved out of the base frequency band, thereby obtaining a better signal / noise distortion ratio. Such a selection method is controlled by a signal generated by the stepwise component selection logic, and the control signal is based on the (N + 1) level quantizer output received by the stepwise component selection logic and the start of its internal loop Component address generated. The present invention can also be applied to (N + 1) quasi-integral delta-sigma digital / analog converters, including an upscaling filter, a (N + 1) quasi-digits delta-sigma delta modulator, a step-type element selection logic, An internal (N + 1) quasi-bit / analog converter and a post-stage analog filter, where N is an integer greater than one. Among them, there are N internal (N + 1) quasi-bit / analog converters with mismatched components. • 6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 479416 A7 B7_ V. Description of the Invention (4) (Please read the precautions on the .t side before filling out this page) Unit elements. Initially, the unit elements are selected in a circular manner (such as the traditional data weighted average method) to generate corresponding internal (N + 1) standards. The digital output of the bit quantizer is analog output signal. When one cycle is completed, the starting element at the beginning of the next cycle is moved forward by a fixed number S, and after each cycle is completed, the next cycle is started. The starting element is moved forward by a fixed number S, so that the harmonics of the multi-bit integral delta modulator can be shifted out of the base band, thereby obtaining a better signal / noise distortion ratio. Such a selection method is controlled by a signal generated by the stepwise component selection logic, and the control signal is based on the (N + 1) level quantizer output received by the stepwise component selection logic and the start of its internal loop Component address generated. In the above two applications, the preset number of forward components (step number) of S is an integer from 1 to N. The multi-bit integral triangle can be set by setting the default value of S. Modulators are suitable for applications with different performance requirements. Brief Description of the Drawings Figure 1 is a block diagram of a multi-bit integral delta analog / digital converter without the prior art using dynamic component matching technology. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 2 is a block diagram of the multi-bit integral delta analog / digital converter of the present invention. Figure 3 is a detailed functional block diagram of the step-by-step component selection logic in Figure 2. Figure 4 is a block diagram of a multi-bit integrating delta-sigma digital / analog converter without prior art techniques using dynamic component matching technology. Figure 5 shows the multi-point integral triangle digital / analog converter of the present invention. -7- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A7 B7 5. Description of the invention (5) Block diagram. Fig. 6 is a block diagram of an example of an integrated delta analog / digital converter of a third-order nine-level multipath feedback architecture according to the present invention. Figure 7 shows the output spectrum of the integral delta analog / digital converter of the third-order nine-level multipath feedback architecture using the traditional data weighted average method. The maximum component error is set to 0.5%, and the input frequency is 1/1024 of the sampling frequency. The input sizes are (a) -6dB (c) -45dB (e) -85dB, and (b) (d) ⑴ are the noise spectrum of the corresponding digital analog converter. Figure 8 shows the output spectrum of the integrated delta analog / digital converter of the third-order nine-level multi-path feedback architecture according to the present invention. The maximum component error is set to 0.5%, the input frequency is 1/1024 of the sampling frequency, and the input sizes are respectively It is U) -6dB (c) -45dB (e) -85dB, and (b) (d) ⑴ are the noise spectrum of the corresponding digital analog converter. Figure 9 is a signal / noise distortion ratio diagram of a delta analog / digital converter according to the integral of a third-order nine-level multipath feedback architecture according to the present invention. Figure 10 is a diagram showing the total harmonic energy of the baseband of a delta analog / digital converter according to the integral of the third-order nine-level multipath feedback architecture of the present invention. Figure 11 is a related histogram according to the present invention. Under the same conditions as in Figures 7 to 10, the input size is -45dB, U) is the improvement of the signal / noise distortion ratio. The histogram (b) is based on Improved histogram of total harmonic energy in the frequency band. Figure 12 compares the signal / noise distortion of the integrated delta analog / digital converter using the technology of the present invention and the third-order nine-level multi-path feedback architecture of IDWA and ODWA caused by comparing the input DC component (change from 0LSB to 1LSB). Comparison chart of degree of reduction. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----: ---------------- Order --------- (Please read the notes on the back before filling this page) 479416 A7 B7___ V. Description of the invention (6) Detailed description of the invention (please read the note on the back? Matters before filling out this page) This invention proposes a use for (N +1) Integral delta modulator of the level integral delta analog / digital converter, N is an integer greater than one, including: a loop filter for receiving (N + 1) level integral delta analog / digital converter An analog input signal is subtracted from an internal analog feedback signal and added to generate a filtered signal; an (N +1) level quantizer is used to quantize a filtered signal with a sampling frequency of fs to generate a digital output code; one step The progressive component selection logic is used to generate a set of stepwise control signals S (), S 1, ..., S (N · 1) corresponding to the digital output codes received by the (N + 1) level quantizer. And-the internal (N + 1) quasi-bit / analog converter contains N unit components, and there is a mismatch between the unit components, its function is The internal analog feedback signal is generated based on the control signals S (), Sj, ..., S (Nn) received from the progressive component selection logic. The employee's cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints this (N + 1) The level-integral delta analog / digital converter includes a frequency reduction filter to reduce the digital output code generated by the (N + 1) level quantizer back to the fundamental frequency digital signal, and this signal is the (N + 1) standard The digital output of the bit-integral delta analog / digital converter. The step-by-step component selection logic includes: an index adder divided by N, which has two inputs to receive the digital output generated by the (N + 1) level quantizer Code and a previous pointer (delayed pointer, DPTR), and an output terminal output indicator -9- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 479416 A7 — _B7___ 5. Description of the invention (7) (Please read the notes on the back before filling this page) (pointer, PTR), which calculates the sum of the digital output code and the index at the previous moment A, SA < N, then the index 値 is A; gA > N , Indicator 値 is the remainder after A divided by N; one divided by N The step adder has two input terminals receiving a pointer (PTR) transmitted by an index adder divided by N and a step number S transmitted by a step control signal generator, and an output terminal output has Through another PTR of the step adder, the acquisition of the other PTR is to calculate the sum A 'of PTR and S. If A' < N, the other PTR is A '; if A, > N, then another PTR is the remainder after dividing A ′ by N; a first accumulation register is connected to the aforementioned step adder, and has an input terminal to receive the other PTR, and an output terminal to output the previous time indicator (DPTR ), The first accumulation register latches the other PTR—the sampling period; the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a control signal generator whose reception index (PTR) and the previous time index ( DPTR) and generate N control signals BG, B, ..., and its actions are as follows: if PTR is greater than DPTR, then BDPTR, B (DPTR + 1), ..., B (PTR.l) are 1 ', and the rest are 0 If PTR is less than DPTR, then BDPTR, B (dptr + i), ..., Bn, B0, Bi, 1 ', the rest are 0', and if PTR, etc. DPTR, then all N control signals BQ, Bi, ..., B (N ·!) Are 0; a step control signal generator has a preset Sini, Sini is an integer from 1 to N, and its reception comes from The N control signals B of the control signal generator. , Bi, ..., B (N_υ and a cycle start element address SPTR, to generate N step control signals S., Si, ..., S (N, U, and -10-) This paper size applies Chinese national standards (CNS) A4 specifications (210 X 297 public love) ^ 9416 A7 ----- BZ__ 5. Description of the invention (8) (Please read the precautions on the back before filling this page)

一步進個數S，其動作如下：若循環起始元件位址SPTR 並不在B()、Br…、B(n.d爲1中的任一位址，則不對BQ、 Β!、…、B(NM)做任何步進動作，保持原狀輸出成步進 . 式控制信號SQ、Si、…、S(N.n及步進個數S輸出爲0; 若循環起始元件位址SPTR在B。、B,、…、B(N.U爲1中的任一位址，則對BQ、；^、…、B(N.n做步進動作，將大於等於SPTR且爲1之控制信號匕向前步進Sini個位址，也就是說步進式控制信號中S DPTR 、 S(DPTR+1> 、…、 S(SPTR- 1 ) ’ S(sptr + s)、S(SPTR+1+s)、…、S(PTR.1+s)成爲 1 ’ 其餘皆爲0，以及步進個數s輸出爲sini;及經濟部智慧財產局員工消費合作社印製一循環起始元件位址（SPTR)產生器，其具有一輸出端輸出該循環起始元件位址（SPTR)和一輸入端接收該步進控制信號產生器所送來的步進個數S，該SPTR 產生器內包含一除以N之加法器及一第二累加暫存器，其中除以N之加法器將接收到之步進個數S與從該第二累加暫存器輸出之SPTR相加產生一和A”，若 A”<N，則輸出A”；若A”>N，則輸出A”除以N後之餘數，而該第二累加暫存器將該除以N加法器之輸出鎖閘 (latching)—取樣週期。本發明亦提出一（N+ 1)準位積分三角數位/類比轉換器，N爲大於一之整數，包含：一升頻濾波器，其具有一個輸入端接收數個位元之數位字（digital word)，其取樣頻率爲Nyquist Rate，及一輸出端輸出一升頻後之數位字，其取樣頻率高於Nyquist Rate ; -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479416 A7 B7 1、發明說明（9 ) 一數位積分三角調變器，包含一數位迴路濾波器及一 (N+1)準位量化器，此調變器將已升頻後之數位字轉換成一 (N+1)準位量化數位字，該數位迴路濾波器接收該升頻後之數位字及負迴授之該（N+1)準位量化數位字，並產生一預處理信號，其再由該（N+1)準位量化器量化而輸出該（N+1)準位量化數位字；一步進式元件選擇邏輯用於產生一組對應於該（N+1) 準位量化數位字之步進式控制信號S。、Si、…、S(N.n ; 一（N + 1)準位數位/類比轉換器內含N個單位元件，而單位元件之間存有不匹配，其功能爲根據從步進式元件選擇邏輯所接收的控制信號S()、Si、…、S(N_n，來產生對應之類比信號給一後級類比濾波器；及一後級類比濾波器，將由（N+1)準位數位/類比轉換器所接收到類比信號之頻帶外雜訊是當濾除後輸出。該步進式元件選擇邏輯包含：一除以N之指標加法器，具有兩輸入端接收該 (N+1)準位量化器所產生之該（N+1)準位量化數位字及一前一時刻指標（delayed pointer，DPTR)，以及一輸出端輸出指標（pointer，PTR)，其計算該數位輸出碼與前一時刻指標之和A，若A<N，則指標値爲A ;若A>N，貝[J 指標値爲A除以N後之餘數；一除以N之步進加法器，具有兩輸入端接收由除以N之指標加法器所傳來之指標（PTR)及由一步進控制信號產生器所傳來之步進個數S，以及一輸出端輸出 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 裝One step number S, the action is as follows: If the loop start element address SPTR is not at any of B (), Br ..., B (nd is any of 1, then BQ, Β!, ..., B ( NM) do any stepping action and keep the original output as stepping. Type control signals SQ, Si, ..., S (Nn and step number S are output as 0; if the cycle start element address SPTR is at B., B ,, ..., B (NU is any address of 1, then BQ,; ^, ..., B (Nn will be stepped, and a control signal greater than or equal to SPTR and 1 will be stepped forward by Sini Address, that is, S DPTR, S (DPTR + 1 >, ..., S (SPTR-1) ', S (sptr + s), S (SPTR + 1 + s), ..., S in step control signals (PTR.1 + s) becomes 1 ', the rest are all 0, and the number of steps s is output as sini; and the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a cycle start element address (SPTR) generator, which An output terminal outputs the cycle start element address (SPTR) and an input terminal receives the number of steps S sent by the step control signal generator. The SPTR generator includes an adder divided by N. And a second accumulation register, where The adder that divides by N adds the received step number S and the SPTR output from the second accumulation register to generate a sum A ". If A" < N, then output A "; if A" > N, the remainder after dividing A "by N, and the second accumulation register divides this by the output of the N adder latching-sampling period. The present invention also proposes an (N + 1) Level-integral delta-sigma digital / analog converter, N is an integer greater than one, including: an up-converting filter, which has an input terminal to receive a number of digital words, and its sampling frequency is Nyquist Rate, And an output terminal outputs a digital digit after an upsampling, the sampling frequency is higher than the Nyquist Rate; -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 479416 A7 B7 1. Description of the invention (9) A digital integral delta modulator, including a digital loop filter and an (N + 1) level quantizer. This modulator converts the digital word after frequency upscaling to an (N + 1) level Quantized digital word, the digital loop filter receives the up-scale digital word and the (N + 1) level quantization of negative feedback And a pre-processed signal, which is quantized by the (N + 1) level quantizer to output the (N + 1) level quantized digital word; a stepwise element selection logic is used to generate a set of corresponding The stepped control signals S., Si, ..., S (Nn; one (N + 1) quasi-bit / analog converter) of the (N + 1) level quantized digital word contain N unit elements, and There is a mismatch between the unit elements, and its function is to generate corresponding analog signals to a subsequent analog filter according to the control signals S (), Si, ..., S (N_n) received from the step-type element selection logic. ; And a post-analog filter, the out-of-band noise of the analog signal received by the (N + 1) quasi-bit / analog converter is output after filtering. The stepwise component selection logic includes: an index adder divided by N, having two inputs receiving the (N + 1) level quantized digital word generated by the (N + 1) level quantizer and a previous A pointer at a time (delayed pointer, DPTR) and an output indicator (pointer, PTR), which calculates the sum A of the digital output code and the index at the previous time. If A < N, the indicator 値 is A; if A > N, P [J index 値 is the remainder after A divided by N; a stepwise adder divided by N, having two inputs receiving the index (PTR) transmitted by the index adder divided by N and The number of steps S transmitted by a step control signal generator, and an output terminal output -12- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the note on the back first ? Fill in this page again)

-n ·ϋ ·1 1 n n · ϋ n ϋ tKmm n n n I 經濟部智慧財產局員工消費合作社印製 479416 A7 B7__ 五、發明說明（10 ) 已通過步進加法器之另一 PTR，該另一 PTR之獲得係計算PTR與S之和A’，若A’<N則另一 PTR爲A’ ；若A’〉N，則另一PTR爲A’除以N後之餘數；一第一累加暫存器與前述之步進加法器連接，其具有一輸入端接收該另一 PTR，及一輸出端輸出該前一時刻指標（DPTR)，該第一累加暫存器將該另一PTR鎖閘（latching)—取樣週期；一控制信號產生器其接收指標（PTR)及前一時刻指標（DPTR)並產生N個控制信號B。、Βι、…、B(N.n，其動作如下：PTR若大於DPTR，則BDPTR、B(DPTR + 1)、…、 B(PTR.n爲1，其餘皆爲0，若PTR小於DPTR，則BDPTR、 B(DPTR + 1)、…、Bn、B()、Bi、B(PTR.n 爲 1，其餘皆爲〇，而若PTR等於DPTR，則所有N個控制信號BQ、Bi、...、 B ( n ·!)皆爲 Ο，一步進控制信號產生器其具有一預設的Sini，-n · ϋ · 1 1 nn · ϋ n ϋ tKmm nnn I Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A7 B7__ V. Description of the invention (10) Another PTR that has passed the step adder, the other PTR The acquisition is to calculate the sum A 'of PTR and S. If A' < N, the other PTR is A '; if A'> N, then the other PTR is the remainder of A 'divided by N; a first accumulation The register is connected to the aforementioned step adder, and has an input terminal to receive the other PTR and an output terminal to output the previous time index (DPTR). The first accumulation register locks the other PTR. Latching—sampling period; a control signal generator receives an index (PTR) and a previous index (DPTR) and generates N control signals B. , Bι, ..., B (Nn, its actions are as follows: if PTR is greater than DPTR, then BDPTR, B (DPTR + 1), ..., B (PTR.n is 1, the rest are 0, if PTR is less than DPTR, then BDPTR , B (DPTR + 1), ..., Bn, B (), Bi, B (PTR.n is 1, the rest are 0, and if PTR is equal to DPTR, all N control signals BQ, Bi, ... , B (n ·!) Are 0, a step control signal generator has a preset Sini,

Sini爲1至N的整數，其接收來自於該控制信號產生器之 N個控制信號BQ、Bi、…、B(N.U及一循環起始元件位址 SPTR，而產生N個步進式控制信號S。、S!、…、S(N.1}及一步進個數S，其動作如下：若循環起始元件位址SPTR 並不在BD、、…、B(N.n爲1中的任一位址，則不對B。、、…、Β(Ν.υ做任何步進動作，保持原狀輸出成步進式控制信號SG、、…、S(N.n及步進個數S輸出爲〇; 若循環起始元件位址SPTR在B〇、Bi、…、B(N.n爲1中的任一位址，則對B〇、Bi、…、Β(Ν.υ做步進動作，將大 -13 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）一 (請先閱讀背面之注意事項再填寫本頁) -Sini is an integer from 1 to N. It receives N control signals BQ, Bi, ..., B (NU and a cycle start element address SPTR from the control signal generator), and generates N step control signals. S., S!, ..., S (N.1} and a step number S, the actions are as follows: if the cycle start element address SPTR is not in BD, ..., B (Nn is any of 1 Address, do not perform any stepping action on B. ,, ..., B (N.υ, and keep the original output as stepping control signals SG ,, ..., S (Nn and step number S are output as 0; if the cycle The starting element address SPTR is at any of B0, Bi, ..., B (Nn is any address of 1, then stepping action is performed on B0, Bi, ..., B (N.υ, which will be greater than -13- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1 (Please read the precautions on the back before filling this page)-

T . βββ I am— an «ϋ I « ^ · 1 11 Bn 1·— n 11 n I 經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 479416 A7 B7 _ 五、發明說明（11 ) 於等於SPTR且爲1之控制信號1向前步進Sini個位址，也就是說步進式控制信號中sDPTR、s(DPTR+n、...、s(SPTR_n， S(sptr + s)、S(sptr + 1 + s)、…、S(PTR.1 + s)成爲1 ’ 其餘皆爲 Ο，以及步進個數S輸出爲sini;及一循環起始元件位址（SPTR)產生器，其具有一輸出朗輸出該循環起始兀件位址（S P T R)和一輸入端接收該步進控制信號產生器所送來的步進個數S，該SPTR 產生器內包含一除以N之加法器及一第二累加暫存器，其中除以N之加法器將接收到之步進個數S與從該第二累加暫存器輸出之SPTR相加產生一和A”，若 A”<N，則輸出A”；若A”>N，則輸出A”除以N後之餘數，而該第二累加暫存器將該除以N加法器之輸出鎖閘 (latching)—取樣週期。T. Βββ I am— an «ϋ I« ^ · 1 11 Bn 1 · — n 11 n I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A7 B7 _ V. Invention Explanation (11) The control signal 1 equal to SPTR and 1 steps forward Sini addresses, that is, sDPTR, s (DPTR + n, ..., s (SPTR_n, S ( sptr + s), S (sptr + 1 + s), ..., S (PTR.1 + s) becomes 1 'the rest are 0, and the number of steps S is output as sini; and the address of a cycle start element (SPTR) generator, which has an output output of the cycle start element address (SPTR) and an input terminal receiving the number of steps S sent by the step control signal generator. The SPTR generator contains Including an adder that divides by N and a second accumulation register, wherein the adder that divides by N adds the received step number S and the SPTR output from the second accumulation register to generate a sum A ", if A" < N, output A "; if A" > N, output the remainder after dividing A "by N, and the second accumulation register will divide the output by N adder lock Latching—The sampling period.

爲了能更淸楚地了解本發明實現電路的操作方式，在此以一採用本發明且設定步進個數S = 1之九準位/積分三角調變器爲實例來做說明。假設時刻η時，DPTR(n) = 2、量化器的數位輸出碼D(n) = 5、SPTR(n) = 5，則 PTR(n) = DPTR(n) + D(n) = 7，控制信號產生器輸出B = {00111110}，進入步進控制信號產生器後，因SPTR(n) = 5且 B5=l符合步進判斷準則，所以B5、B6向前步進一個單位元件，輸出步進控制信號S = {001 11011}及步進個數S = 1，如此形成 SPTR(n+l) = SPTR(n) + S二6、DPTR(n+l) = PTR(n) + S = 8 再除以8後之餘數DPTR(n+l) = 0 ;若時刻n+1時，D(n+1) = 4，則PTR(n+l) = DPTRU+l) + D(n+l) = 4，控制信號產生器輸出B -14- 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐）~ (請先閱讀背面之注意事項再填寫本頁) r--------訂----I----^91. 479416 A7 B7 五、發明說明（12 ) ={ 1 1 1 10000}，進入步進控制信號產生器後，因SPTR(n+l) = 6 而：86 = 0不符合步進判斷準則，所以沒有執行步進動作，輸出步進控制信號S = { 1 1 1 10000}及步進個數S = 0，如此形成 SPTR(n + 2) = SPTR(n+l) + S二6、DPTR(n + 2) = PTR(n+l) + S = 4;若時刻 n + 2時，D(n + 2) = 6，則 PTR(n + 2) = DPTR(n + 2) + D(n + 2)=10 再除以8後之餘數PTR(n + 2) = 2，控制信號產生器輸出B = {11001111}，進入步進控制信號產生器後，因SPTR(n + 2) = 6 且1=1符合步進判斷準則，所以B6、B7、BQ、：^向前步進一個單位元件，輸出步進控制信號S = {11101101}及步進個數 S=1，如此形成 SPTR(n + 3) = SPTR(n + 2) + S = 7、 DPTR(n + 3) = PTR(n + 2) + S = 3 ;以此類推。進一步說明本發明優點及效能之前先介紹示於圖一中的傳統（N+1)準位積分三角類比/數位轉換器10(N爲大於一之整數），此類比/數位轉換器10包含積分三角調變器11 及降頻濾波器16，而積分三角調變器11包含了：加法元件 12、迴路濾波器13、（N+1)準位量化器14、內部（N+1)準位數位/類比轉換器15。加法元件12接收類比輸入信號並減去內部（N+1)準位數位/類比轉換器15之類比迴授信號，而輸出到迴路濾波器13，再提供類比輸出給（N+1)準位量化器 14，此（N+1)準位量化器14以匕之頻率量化迴路濾波器13所提供之類比輸出，並產生（N+1)準位之數位輸出碼給內部 (N+1)準位數位/類比轉換器15及降頻濾波器16，此（N + 1)準位量化器14之數位輸出碼分布由0至N。其內部（N+1)準位數位/類比轉換器15內含N個具元件不匹配之單位元件，用來 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · 1 n n n n n 1 一口、I ϋ n n_i n n n I 0 經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 479416 A7 B7__ 五、發明說明（13 ) 提供對應於（N+1)準位量化器14之數位輸出碼之類比迴授信號，而降頻濾波器16以Nyquist Rate之頻率提供相對應之數位輸出字。多位元積分三角調變器之優點爲每多增加一位元，其相對應之量化雜訊功率就會減少6dB。然而其內部多位元迴授數位/類比轉換器必須擁有與整個轉換器相同之線性度。資料加權平均法經硏究可將由非理想數位/類比轉換器所造成的失真修整（shaping)至高頻而達成要求。不過，若將此法應用於多位元積分三角調變器之內部（N+1)準位數位/類比轉換器上時，會有基頻帶諧波及互調失真出現於調變器之輸出，進而影響整個積分三角轉換器之效能。圖二爲採用本發明技術之積分三角類比/數位轉換器 20，其包含積分三角調變器11’及降頻濾波器26，前者包含加法元件21、迴路濾波器22、（N+1)準位量化器23、步進式元件選擇邏輯24及內部（N+1)準位數位/類比轉換器25。而加法元件2 1接收類比輸入信號並減去內部（N+1)準位數位/ 類比轉換器25之類比迴授信號，而輸出到迴路濾波器22，再提供類比輸出給（N +1)準位量化器23，此（N+1)準位量化器23以匕之頻率量化迴路濾波器22所提供之類比輸出，並產生（N+1)準位之數位輸出碼給步進式元件選擇邏輯24及降頻濾波器26，此（N + 1)準位量化器23之數位輸出碼分布由〇至N。步進式元件選擇邏輯24會依據步進式資料加權平均法之準則來決定其輸出之控制信號，其內部（N+1)準位數位 /類比轉換器25內含N個具元件不匹配之單位元件，用來提 • 16- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·丨-丨-丨丨丨訂丨---丨ί· 479416 A7 B7_ 五、發明説明（14 ) (請先閲讀背面之注意事項再填寫本頁) 供對應於步進式元件選擇邏輯24之輸出控制信號之類比迴授信號，而降頻濾波器26以Nyquist Rate之頻率提供相對應之數位輸出字。圖三爲採用本發明之步進式元件選擇邏輯24詳細方塊圖，此元件選擇邏輯24包含一除以N之指標加法器30,具有兩輸入端接收其（N+ 1)準位量化器所產生之數位輸出碼及一前一時刻指標（delayed pointer，DPTR)，以及一輸出端輸出指標（pointer*，PTR)，其動作爲計算該數位輸出碼與前一時刻指標之和A。若A<N，則指標値爲A ;若A>N，則指標値爲A除以N後之餘數；一除以N之步進加法器31，具有兩輸入端接收由除以N之指標加法器30所傳來之指標（PTR) 及由步進控制信號產生器37所傳來之步進個數，以及一輸出端輸出已通過步進加法器3 1之PTR ; —累加暫存器32與前述之步進加法器31連接，其具有一輸入端接收已通過步進加法器3 1之指標（PTR)，及一輸出端輸出前一時刻指標 (DPTR)，該累加暫存器32將該已通過步進加法器31之PTR 鎖閘（latching)—取樣週期；一控制信號產生器33其接收指標（PTR)及前一時刻指標（DPTR)並產生N個控制信號B。、經濟部智慧財產局員工消費合作社印製In order to better understand the operation mode of the implementation circuit of the present invention, a nine-level / integral delta modulator adopting the present invention and setting the number of steps S = 1 will be described as an example. Suppose at time η, DPTR (n) = 2, the digital output code of the quantizer D (n) = 5, SPTR (n) = 5, then PTR (n) = DPTR (n) + D (n) = 7, Control signal generator output B = {00111110}. After entering the step control signal generator, because SPTR (n) = 5 and B5 = l meet the step judgment criteria, B5, B6 step forward one unit element, output Step control signal S = {001 11011} and the number of steps S = 1, so that SPTR (n + l) = SPTR (n) + S = 6, DPTR (n + l) = PTR (n) + S = 8 and the remainder after dividing by 8 DPTR (n + l) = 0; if at time n + 1, D (n + 1) = 4, then PTR (n + l) = DPTRU + l) + D (n + l) = 4, control signal generator output B -14- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ~ (Please read the precautions on the back before filling this page) r- ------- Order ---- I ---- ^ 91. 479416 A7 B7 V. Description of the invention (12) = {1 1 1 10000}. After entering the step control signal generator, the SPTR ( n + l) = 6 and: 86 = 0 does not meet the step judgment criteria, so no step action is performed, and a step control signal S = {1 1 1 10000} and the number of steps S = 0 are output, thus forming an SPTR (n + 2) = SPTR (n + l) + S = 6, DPTR (n + 2) = PTR (n + l) + S = 4; if at time n + 2, D (n + 2) = 6, then PTR (n + 2) = DPTR (n + 2) + D (n + 2) = 10 and the remainder after dividing by PTR (n + 2) = 2, the control signal generator output B = {11001111}, enter After the step control signal generator, because SPTR (n + 2) = 6 and 1 = 1 meet the step judgment criteria, B6, B7, BQ,: ^ step forward a unit element and output the step control signal S = {11101101} and the number of steps S = 1, so that SPTR (n + 3) = SPTR (n + 2) + S = 7, DPTR (n + 3) = PTR (n + 2) + S = 3 ; And so on. To further illustrate the advantages and performance of the present invention, the traditional (N + 1) level integral delta analog / digital converter 10 (N is an integer greater than one) shown in Figure 1 will be introduced first. Such ratio / digital converter 10 includes integrals. Triangular modulator 11 and down-frequency filter 16, and integral triangular modulator 11 includes: adding element 12, loop filter 13, (N + 1) level quantizer 14, internal (N + 1) level Digital / analog converter 15. The addition element 12 receives the analog input signal and subtracts the analog feedback signal from the internal (N + 1) quasi-bit / analog converter 15, and outputs it to the loop filter 13, and then provides the analog output to the (N + 1) quasi-level. Quantizer 14, This (N + 1) level quantizer 14 quantizes the analog output provided by the loop filter 13 at the frequency of the dagger, and generates the (N + 1) level digital output code to the internal (N + 1) The quasi-bit / analog converter 15 and the down-conversion filter 16, the digital output code distribution of the (N + 1) level quantizer 14 ranges from 0 to N. The internal (N + 1) quasi-digit / analog converter 15 contains N unit components with mismatched components for -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) (Please read the notes on the back before filling out this page) · 1 nnnnn 1 sip, I ϋ n n_i nnn I 0 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers ’Cooperatives of the Ministry of Economics and Intellectual Property Bureau 479416 A7 B7__ V. Description of the invention (13) An analog feedback signal corresponding to the digital output code of the (N + 1) level quantizer 14 is provided, and the down-conversion filter 16 provides a corresponding digital output word at a frequency of Nyquist Rate. The advantage of a multi-bit integral delta modulator is that for each additional bit, the corresponding quantized noise power is reduced by 6 dB. However, its internal multi-bit feedback digital / analog converter must have the same linearity as the entire converter. The data weighted averaging method has been researched to shape the distortion caused by non-ideal digital / analog converters to high frequencies to meet the requirements. However, if this method is applied to the internal (N + 1) quasi-bit / analog converter of a multi-bit integral delta modulator, the harmonics and intermodulation distortion of the base band will appear at the output of the modulator. , Which in turn affects the performance of the entire delta-sigma converter. FIG. 2 is an integrating delta analog / digital converter 20 using the technology of the present invention, which includes an integrating delta modulator 11 ′ and a frequency reducing filter 26. The former includes an adding element 21, a loop filter 22, and a (N + 1) standard. A bit quantizer 23, a step-by-step element selection logic 24, and an internal (N + 1) quasi-bit-bit / analog converter 25. The addition element 21 receives the analog input signal and subtracts the analog feedback signal of the internal (N + 1) quasi-bit / analog converter 25, and outputs it to the loop filter 22, and then provides the analog output to (N + 1) Level quantizer 23, the (N + 1) level quantizer 23 quantizes the analog output provided by the loop filter 22 at the frequency of the dagger, and generates a (N + 1) level digital output code to the stepping element Selection logic 24 and frequency reduction filter 26. The digital output code distribution of this (N + 1) level quantizer 23 ranges from 0 to N. The stepwise component selection logic 24 will determine the output control signal according to the stepwise data weighted average method. The internal (N + 1) quasi-bit / analog converter 25 contains N components with mismatched components. Unit components for the purpose of 16- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) · 丨-丨-丨丨 Order丨 --- 丨 479416 A7 B7_ V. Description of the invention (14) (Please read the notes on the back before filling out this page) For analog feedback signals corresponding to the output control signals corresponding to stepping element selection logic 24, The down-conversion filter 26 provides a corresponding digital output word at a frequency of Nyquist Rate. FIG. 3 is a detailed block diagram of the stepwise component selection logic 24 adopting the present invention. The component selection logic 24 includes an index adder 30 divided by N, which has two input terminals to receive the (N + 1) level quantizer. The digital output code and a previous pointer (delayed pointer, DPTR), and an output terminal output pointer (pointer *, PTR). Its action is to calculate the sum A of the digital output code and the previous pointer. If A < N, the index 値 is A; if A > N, the index 値 is the remainder after A divided by N; a stepwise adder 31 divided by N has two input terminals to receive the index divided by N The index (PTR) from the adder 30 and the number of steps from the step control signal generator 37, and an output terminal output has passed the PTR of the step adder 3 1;-accumulation register 32 is connected to the aforementioned step adder 31, which has an input terminal receiving the index (PTR) which has passed the step adder 31 and an output terminal outputting the previous time index (DPTR). The accumulation register 32 This has passed the PTR latching-sampling period of the step adder 31; a control signal generator 33 receives the index (PTR) and the previous time index (DPTR) and generates N control signals B. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Bl、…、Β(Ν_υ，其動作如下：PTR若大於DPTR，則BDPTR、 B(DPTR + 1)、…、B(PTR_U 爲 1 ’ 其餘皆爲〇 ’ 若 PTR 小於 DPTR，則 BDPTR、B(DPTR + n、…、BN、B。、Bi、Brtr])爲1，其餘皆爲0,而若PTR等於DPTR，則所有N個控制信號BQ、B,、…、 Bw.i)皆爲0 ; —步進控制信號產生器37接收來自於控制信號產生器33之N個控制信號BQ、Bi、…、B(N_n及循環起始 -17- 本紙張尺度適用中國国家標準（CNS )八4規格（210X297公釐1 ~ 479416 A7 ___B7__ 五、發明説明彳5 ) (請先閱讀背面之注意事項再填寫本頁) 元件位址SPTR，而產生N個步進式控制信號Sr Sj、…' S(N_n 及步進個數S，其動作如下：若循環起始元件位址SPTR並不在B。、Bi、…、B(N.1}爲1中的任一位址，則不對B。、Bi、…、 Β(Ν_ι)做任何步進動作，保持原狀輸出成步進式控制信號 S。、Si '…、S(N.n及步進個數輸出爲0，若循環起始元件位址SPTR在B()、、…、B(N.n爲1中的任一位址，則對B〇、、…、B(N.n做步進動作，將大於等於SPTR且爲1之控制信號1向前步進S個位址，也就是說步進式控制信號中 S D P T R 、 S (DPTR+ 1 ) 、 ... 、 S(SPTR. 1 ) ’ S ( S p T R + s ) 、 S(SPTR + i +S) 、 ···、 S(PTR.wS)成爲1，其餘皆爲0，以及步進個數輸出爲s; —循環起始元件位址（SPTR)產生器34，其具有一輸出端輸出循環起始元件位址（SPTR)和一輸入端接收步進控制信號產生器37所送來的步進個數S。該SPTR產生器內包含一除以N之加法器35及一累加暫存器36,其中除以N之加法器35將接收到之步進個數S與累加暫存器36輸出所拉回來之迴授SPTR 相加，而累加暫存器36將該已通過加法器之SPTR鎖閘 (latching)—取樣週期。經濟部智慧財產局員工消費合作社印製圖四中的傳統（N+1)準位積分三角數位/類比轉換器 40(N爲大於一之整數），此數位/類比轉換器40包含升頻濾波器41、數位積分三角調變器42、（N+1)準位數位/類比轉換器46及後級類比濾波器47，而數位積分三角調變器42包含了：加法元件43、迴路濾波器44、（N+1)準位量化器45。加法元件43接收升頻濾波器41輸出信號並減去（N+1)準位量化器45之迴授信號，而輸出到迴路濾波器44，再提供輸 -18- 本&張尺度適用中國國家標準（CNS ) A4祕（2獻297公麓) ~ " 479416 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明《6 ) 出給（N+1)準位量化器45，此（N+1)準位量化器45以fs之頻率量化迴路濾波器44所提供之輸出，並產生（N+1)準位之數位輸出碼給（N+1)準位數位/類比轉換器46，此（N+1)準位量化器45之數位輸出碼分布由0至N。該（N+1)準位數位/類比轉換器46內含N個具元件不匹配之單位元件，用來提供對應於（N+1)準位量化器45之數位輸出碼之迴授信號，而後級類比濾波器47將由(N+1)準位數位/類比轉換器46所接收到類比信號之頻帶外雜訊適當濾除後輸出。圖五爲採用本發明之（N+1)準位積分三角數位/類比轉換器50(NT爲大於一之整數），此數位/類比轉換器50包含升頻濾波器5 1、數位積分三角調變器52、步進式元件選擇邏輯56、（N+ 1)準位數位/類比轉換器57及後級類比濾波器58，而數位積分三角調變器52包含了：加法元件53、迴路濾波器54、（N+1)準位量化器55。加法元件53接收升頻濾波器51 輸出信號並減去（N+1)準位量化器55之迴授信號，而輸出到迴路濾波器54,再提供輸出給（N+1)準位量化器55，此（N+1) 準位量化器55以匕之頻率量化迴路濾波器54所提供之輸出，並產生（N+1)準位之數位輸出碼給步進式元件選擇邏輯 56,此（N + 1)準位量化器55之數位輸出碼分布由〇至N。如同圖二及圖三之步進式元件選擇邏輯24，此步進式元件選擇邏輯56將產生一組對應於由（N+ 1)準位量化器55之數位輸出碼之步進式控制信號S。、Si、…、S(N_n給^+1)準位數位/類比轉換器57，（N + 1)準位數位/類比轉換器57內含N個單位元件，而單位元件之間存有不匹配，其功能爲根據從步 -19- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2H)X297公釐） 479416 A7 ___B7__ 五、發明説明扣） (請先閱讀背面之注意事項再填寫本頁) 進式元件選擇邏輯56所接收的控制信號S()、S!、…、S(N.n，來產生對應之類比信號給後級類比濾波器58，而後級類比濾波器58將由（N+1)準位數位/類比轉換器57所接收到類比信號之頻帶外雜訊適當濾除後輸出。以下所示爲本發明之相關模擬結果，吾人在此以圖六之三階多路徑迴授積分三角調變器60爲例，此積分三角調變器60之超取樣比率（OSR)爲64，頻寬20kHz，取樣頻率 2.56MHz，並含三級離散時間積分器61，九準位量化器62，步進式元件選擇邏輯63及九準位數位/類比轉換器64。其調變器係數爲 ai = 1.21442, a2 = 1.46347, a3 = 1，gl = 0.395394, g2 = 0.570145, g3 = 1.36903, h 二 0.0023 15 15，並將九準位數位/類比轉換器64中之八個單位元件之元件誤差設爲e() zz -0.00484726, = 0.00246786, e2 = -0.00054904, e3 =- 經濟部智慧財產局員工消費合作社印製 0.00104965, e4 = 0.00431815, e5 = -0.00034006, e6 = 0.00209325, e7 = -0.00209325。九準位數位/類比轉換器64 之元件選擇將視量化器62輸出碼而決定，並由元件選擇邏輯63來控制。圖七是顯示採用傳統資料加權平均法之積分三角調變器所得到之模擬結果：當積分三角調變器輸入很大時，其內部九準位量化器在滿載刻度內具有較大之變動範圍；對-6dB大小之輸入而言，數位/類比轉換器輸入碼1 至 7之機率分別爲 3.5 %，16.6 %，21.7 %，16.5 %，21.3 %，17.0 %，3.3 %，如圖所示，基頻帶內並無明顯諧波。而當輸入中等大小之信號時（約爲-60dB〜-30dB )，在^及fs/2處分別有明顯之數位/類比轉換器諧波；例如輸入爲-45dB時， -20- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " 479416 A7 B7 五、發明説明彳8 ) 其數位/類比轉換器輸入碼3, 4, 5機率分別爲22 %，56 %，22 %，由圖可知數位/類比轉換器諧波已進入積分三角調變器之基頻帶，進而降低其信號/雜訊失真比。然而當輸入更小的信號時（-85dB)，基頻帶內並無出現明顯諧波。因此將針對中等大小輸入信號的狀況下來探討本發明之效能。當輸入信號大小爲-45dB時，輸入碼4是出現機率最高且連續出現的碼，以本發明採用起始元件前移個數S = 1爲例，九準位數位/類比轉換器會造成元件誤差量爲+ e〇 + e〇 , e〇 + e〇 + e〇 + e〇， e〇 + e〇 + e〇 + e〇 , e〇 + e〇 + e〇 + e。，·..，e。+ e。+ e。+ eQ，e。+ e。+ e。+ e〇，而將其諧波移往 (fs/16) · m處（m爲正整數），圖八爲此例之積分三角調變器輸出頻譜：輸入大小分別爲（a) -6dB (c) -45dB (e) -85dB，及其相對應之數位/類比轉換器雜訊頻譜（b)(d)(f)。相較於圖（c)(d)，圖（c)(d)的基頻帶內並無明顯諧波，此發明明顯改善了信號/雜訊失真比（SNDR)及基頻帶內諧波總能量，分別如圖九及圖十。更廣泛的討論，步進式資料加權平均技術可將數位/ 類比轉換器諧波移往： ft〇ne = (r/2N) · fs · m , m = 1,2, 3,... 其中r爲N及S之最大公因數。例如對一個九準位八單位元件數位類比轉換器而言，若分別採用起始元件前移個數S = 1 及S = 2，步進式資料加權平均技術可將數位/類比轉換器諧 -21 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) _~~ ---------衣-- (請先閱讀背面之注意事項再填寫本頁) -st> 經濟部智慧財產局員工消費合作社印製 479416 A7 _________ B7 五、發明説明彳9 ) (請先閲讀背面之注意事項再填寫本頁) 波移往（fs/l 6) · m及（fs/8) · m。爲了確保被移開的數位/類比轉換器諧波不會落入基頻帶內，以及考慮數位/類比轉換器諧波在輸入信號大時會擴散的特性，採用步進式資料加權平均技術的積分三角調變器之超取樣倍數（OSR)必須設計 & · 爲· OSR > 2(N/r) 如此便能確保基頻帶內無明顯諧波，進而獲得較佳之信號/ 雜訊失真比。使用蒙地卡羅（Monte Carlo)模擬對製程造成元件變化及採用本發明後之效能改善做分析，採用本發明後，均比採用傳統資料加權平均法獲得相當的改善：在最大元件誤差量爲0.5%，輸入大小-45dB，輸入頻率匕/1024及1000個試驗點的模擬狀況下，可得到信號/雜訊失真比（SNDR) 及基頻帶內諧波總能量改善支柱狀圖如圖十一（a)和（b)，平均分別有12dB及23dB的信號/雜訊失真比（SNDR)及基頻帶內諧波總能量之改善量。經濟部智慧財產局員工消費合作社印製圖十二對於發明之背景中所提到本發明較不受輸入信號之直流成份影響之特性做了模擬：將本發明及IDWA 和0DWA之輸入信號加上直流準位，由〇LSB(也就是最小量化器準位差異）變化到1LSB，很明顯可以發現本發明都能保有相當穩定的信號/雜訊失真比降低程度，但IDWA和0DWA 都在0.5LSB時遭受了較大程度的信號/雜訊失真比降低；如 -22- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 479416 A7 B7 五、發明説明如）此更擴大了本發明的應用範圍。對不同準位數位/類比轉換器及不同接數之積分三角調變器而言，採用本發明並遵守超取樣倍數（OSR)設計準則，均能有效將數位/類比轉換器諧波移出基頻帶外’而獲得較佳之信號/雜訊失真比。 (請先閱讀背面之注意事項再填寫本頁)Bl, ..., B (N_υ, its actions are as follows: if PTR is greater than DPTR, then BDPTR, B (DPTR + 1), ..., B (PTR_U is 1 ', the rest are 0') If PTR is less than DPTR, then BDPTR, B ( DPTR + n, ..., BN, B., Bi, Brtr]) is 1, the rest are 0, and if PTR is equal to DPTR, all N control signals BQ, B, ..., Bw.i) are 0 -Stepping control signal generator 37 receives N control signals BQ, Bi, ..., B (N_n and cycle start -17) from the control signal generator 33- This paper is in accordance with Chinese National Standard (CNS) 8-4 Specifications (210X297 mm 1 ~ 479416 A7 ___B7__ V. Description of the invention 彳 5) (Please read the precautions on the back before filling out this page) Component address SPTR, and generate N step control signals Sr Sj, ... 'S (N_n and the number of steps S, the action is as follows: if the loop start element address SPTR is not at B., Bi, ..., B (N.1) is any of 1, then B is not correct., Bi, ..., Β (Ν_ι) do any stepping action, and keep the original state output as stepping control signal S., Si '..., S (Nn and the number of steps are output as 0, if the cycle start element address SPTR In B ( ), ..., B (Nn is any address of 1, then stepping action on B0 ,, ..., B (Nn will step forward the control signal 1 which is greater than or equal to SPTR and 1 by S steps Address, that is, SDPTR, S (DPTR + 1), ..., S (SPTR. 1) 'S (Sp TR + s), S (SPTR + i + S), ··, S (PTR.wS) becomes 1, the rest are 0, and the number of steps is output as s;-cycle start element address (SPTR) generator 34, which has an output terminal to output the cycle start element The address (SPTR) and an input end receive the number of steps S from the step control signal generator 37. The SPTR generator includes an adder 35 divided by N and an accumulation register 36, where The adder 35, which divides by N, adds the received step number S to the feedback SPTR pulled back by the output of the accumulation register 36, and the accumulation register 36 locks the SPTR that has passed the adder ( latching) —sampling cycle. The traditional (N + 1) level integral triangle digital / analog converter 40 (N is an integer greater than one) printed in Figure 4 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this digital / analog conversion The converter 40 includes an up-scaling filter 41, a digital integral delta modulator 42, an (N + 1) quasi-bit / analog converter 46, and a post-stage analog filter 47. The digital integral delta modulator 42 includes: The addition element 43, the loop filter 44, and the (N + 1) level quantizer 45. The addition element 43 receives the output signal of the up-scaling filter 41 and subtracts the feedback signal of the (N + 1) level quantizer 45, and outputs it to the loop filter 44 to provide an output of -18. This & Zhang scale is applicable to China National Standard (CNS) A4 Secret (2 offering 297 feet) ~ " 479416 Printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description "6) For (N + 1) level quantizer 45, The (N + 1) level quantizer 45 quantizes the output provided by the loop filter 44 at the frequency of fs, and generates a (N + 1) level digital output code for the (N + 1) level digit / analog conversion. The digital output code of the (N + 1) level quantizer 45 ranges from 0 to N. The (N + 1) quasi-bit / analog converter 46 contains N unit elements with mismatched components, and is used to provide a feedback signal corresponding to the digital output code of the (N + 1) quantizer 45. Then, the subsequent-stage analog filter 47 appropriately filters out-of-band noise of the analog signal received by the (N + 1) quasi-bit / analog converter 46 and outputs it. Figure 5 shows the (N + 1) level integral delta digital / analog converter 50 (NT is an integer greater than one) using the present invention. The digital / analog converter 50 includes an up-conversion filter 5 1. Digital integral delta tuning Transformer 52, stepping element selection logic 56, (N + 1) quasi-bit / analog converter 57 and post-stage analog filter 58, and the digital integral delta modulator 52 includes: an adding element 53, a loop filter 54. (N + 1) level quantizer 55. The adding element 53 receives the output signal of the up-conversion filter 51 and subtracts the feedback signal of the (N + 1) level quantizer 55, outputs it to the loop filter 54, and provides the output to the (N + 1) level quantizer. 55. This (N + 1) level quantizer 55 quantizes the output provided by the loop filter 54 with the frequency of the dagger, and generates a (N + 1) level digital output code to the stepping element selection logic 56, this The (N + 1) digital output code distribution of the level quantizer 55 ranges from 0 to N. As in the stepwise component selection logic 24 of FIGS. 2 and 3, the stepwise component selection logic 56 will generate a set of stepwise control signals S corresponding to the digital output codes of the (N + 1) level quantizer 55 . , Si, ..., S (N + 1 to ^ + 1) quasi-bit / analog converter 57, (N + 1) quasi-bit / analog converter 57 contains N unit elements, and there are Matching, its function is based on the steps from -19- (Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standard (CNS) A4 size (2H) X297 mm) 479416 A7 ___B7__ V. Description of the invention (Please read the notes on the back before filling this page) The control signals S (), S!, ..., S (Nn) received by the progressive component selection logic 56 to generate the corresponding analog signals for the analog filtering of the subsequent stage Filter 58 and the subsequent analog filter 58 will appropriately filter out the out-of-band noise of the analog signal received by the (N + 1) quasi-bit / analog converter 57 and output it. The following shows the relevant simulation results of the present invention. I take the third-order multipath feedback integral delta modulator 60 in Figure 6 as an example. The oversampling ratio (OSR) of this integral delta modulator 60 is 64, the bandwidth is 20kHz, and the sampling frequency is 2.56MHz. Three-stage discrete-time integrator 61, nine-level quantizer 62, step-wise element selection logic 63 and ninth digit / analog converter 64. Its modulator coefficients are ai = 1.21442, a2 = 1.46347, a3 = 1, gl = 0.395394, g2 = 0.570145, g3 = 1.36903, h = 0.0023 15 15 and The component error of the eight unit components in the ninth digit / analog converter 64 is set to e () zz -0.00484726, = 0.00246786, e2 = -0.00054904, e3 =-printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 0.00104965, e4 = 0.00431815, e5 = -0.00034006, e6 = 0.00209325, e7 = -0.00209325. The component selection of the 9th digit / analog converter 64 will be determined by the output code of the quantizer 62 and controlled by the component selection logic 63. Figure The seventh is to show the simulation results obtained by the integrating delta modulator using the traditional data weighted average method: When the input of the integrating delta modulator is large, its internal nine-level quantizer has a large range of variation within the full-load scale; For -6dB input, the probability of digital to analog converter input codes 1 to 7 is 3.5%, 16.6%, 21.7%, 16.5%, 21.3%, 17.0%, 3.3%, as shown in the figure. There are no obvious harmonics in the frequency band. When the input For signals of equal size (approximately -60dB ~ -30dB), there are obvious digital / analog converter harmonics at ^ and fs / 2; for example, when the input is -45dB, -20- This paper scale is applicable to China Standard (CNS) A4 specification (210X297 mm) " 479416 A7 B7 V. Description of invention 彳 8) The digital / analog converter input codes 3, 4, 5 are 22%, 56%, 22%, respectively. It can be seen that the harmonics of the digital / analog converter have entered the base band of the integrating delta modulator, thereby reducing its signal / noise distortion ratio. However, when a smaller signal is input (-85dB), no significant harmonics appear in the base band. Therefore, the effectiveness of the present invention will be discussed in the context of a medium-sized input signal. When the input signal size is -45dB, the input code 4 is the code that has the highest probability of occurrence and appears continuously. Taking the present invention to advance the number of starting components S = 1 as an example, a nine-bit digit / analog converter will cause components. The amount of error is + e〇 + e 0, e 0 + e 0 + e 0 + e 0, e 0 + e 0 + e 0 + e 0, e 0 + e 0 + e 0 + e. , .., e. + e. + e. + eQ, e. + e. + e. + e〇, and move its harmonics to (fs / 16) · m (m is a positive integer), Figure 8 shows the output spectrum of the integral delta modulator for this example: the input sizes are (a) -6dB ( c) -45dB (e) -85dB, and the corresponding digital / analog converter noise spectrum (b) (d) (f). Compared to Figures (c) (d), there are no significant harmonics in the base band of Figure (c) (d). This invention significantly improves the signal / noise distortion ratio (SNDR) and the total harmonic energy in the base band. , As shown in Figure 9 and Figure 10. For a broader discussion, the stepped data weighted average technique can shift the digital / analog converter harmonics to: ft〇ne = (r / 2N) · fs · m, m = 1,2, 3, ... where r is the greatest common factor of N and S. For example, for a nine-level, eight-unit digital analog converter, if the starting components are shifted forward by S = 1 and S = 2, respectively, the stepwise data weighted average technology can harmonize the digital / analog converter- 21-This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) _ ~~ --------- Cloth-(Please read the precautions on the back before filling this page) -st > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A7 _________ B7 V. Description of Invention 彳 9) (Please read the notes on the back before filling this page) Wave moves to (fs / l 6) · m and (fs / 8 ) · M. In order to ensure that the removed digital / analog converter harmonics do not fall into the base band, and consider the characteristics of digital / analog converter harmonics that will diffuse when the input signal is large, the integration is performed using stepwise data weighted average The oversampling multiple (OSR) of the triangle modulator must be designed & · · · OSR > 2 (N / r) This will ensure that there are no significant harmonics in the base band, and then a better signal / noise distortion ratio is obtained. Monte Carlo simulation is used to analyze the component changes caused by the process and the performance improvement after using the present invention. After adopting the present invention, it is significantly improved than using the traditional data weighted average method: the maximum component error is 0.5%, input size -45dB, input frequency dagger / 1024 and 1000 test points under simulated conditions, the signal / noise distortion ratio (SNDR) and the total harmonic energy improvement in the base band can be obtained. (A) and (b), on average, there are 12dB and 23dB signal / noise distortion ratio (SNDR) and the improvement of the total harmonic energy in the base band, respectively. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 12 simulates the characteristics of the invention that are less affected by the DC component of the input signal mentioned in the background of the invention: adding the invention and the input signals of IDWA and 0DWA The DC level is changed from 0LSB (that is, the minimum quantizer level difference) to 1LSB. It is obvious that the present invention can maintain a relatively stable reduction of the signal / noise distortion ratio, but both IDWA and 0DWA are at 0.5LSB. Suffered a relatively large reduction in the signal / noise distortion ratio; such as -22- this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 479416 A7 B7 5. The invention description such as) The scope of application of the invention. For different quasi-bit / analog converters and integrating delta-sigma modulators with different connections, the invention can effectively remove the digital / analog converter harmonics from the base frequency band and comply with the oversampling multiple (OSR) design guidelines. External 'to get better signal / noise distortion ratio. (Please read the notes on the back before filling this page)

T 經濟部智慧財產局員工消費合作社印製 -23- 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐）T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -23- This paper size applies to China National Standard (CNS) A4 (210x297 mm)

Claims

479416 A8 B8 C8 D8 6. Application for patent application 1. A integral delta modulator for (N + 1) quasi-integral delta analog / digital converter, where N is an integer greater than one, including: for a loop filter After receiving its (N + 1) level-integral delta analog / digital converter analog input signal, subtracting a sum signal of an internal analog feedback signal to generate a filtered signal; an (N + 1) level quantizer is used A digital output code is generated when quantizing a sampling signal with a sampling affinity of fs; a stepwise component selection logic is used to generate a set of steps corresponding to the digital output code received by the (N + 1) level quantizer The control signals S0, S 丨, ..., S (N. " and an internal (N + 1) quasi-bit / analog converter contain N unit elements, and there is a mismatch between the unit elements. Its function is to generate the internal analog feedback signal according to the control signals S., Si, ..., S (N_n) received from the step-type component selection logic; wherein the step-type component selection logic includes: one divided by N Index adder with two inputs to receive the (N + 1) standard The digital output code and a previous pointer (DPTR) generated by the quantizer, and an output pointer (PTR), which calculates the sum A of the digital output code and the previous pointer, if A < N, the index 値 is A; if A > N, the index 値 is the remainder after A divided by N; a stepwise adder divided by N, which has two inputs to receive by the index adder divided by N Incoming indicator (PTR) and the number of steps S transmitted by a step control signal generator, and an output terminal output -24-This i-scale applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ） ~ &Quot; --------— (Please read the notes on the back before filling out this page), 1T i · Printed by the Intellectual Property Bureau Employee Consumer Cooperatives 479416 A8 B8 C8 D8 范围, Patent Application Scope (Please read the precautions on the back before filling this page) Another PTR of the step adder has been obtained. The other PTR is obtained by calculating the sum of PTR and S A '. If A' < N is another PTR Is A '; if A'> N, then another PTR is the remainder after A 'divided by N; a first The adding register is connected to the aforementioned step adder, and has an input terminal receiving the other PTR and an output terminal outputting the previous time index (DPTR). The first accumulation register stores the other PTR. Latching—sampling period; a control signal generator receives the index (PTR) and the previous time index (DPTR) and generates N control signals B (), Bi, ..., B (N_n, its actions are as follows · · If PTR is greater than DPTR, then BDPTR, B (DPTR + n,…, B (PTR.u is 1; the rest are 0) If PTR is less than DPTR, then BDPTR, B (dptr + i) '…, Bn, B 〇, Bi, are 1 'and the rest are 0'. If PTR is equal to DPTR, then all N control signals B. , B!, ..., B (N " are all 0. A step control signal generator has a preset Sini. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed Sini as an integer from 1 to N, and its reception comes from The control signal generator includes N control signals B., ..., B (N.Π and a cycle start element address SPTR, and generates N step control signals SQ, Si, ..., and a step one. The number S, its action is as follows: if the loop start element address SPTR is not at B0, B !, ..., B (Nn is any address of 1 ', then B0,, ..., B (NU Do any stepping action, and keep the original output as stepping control signals S., S!, ..., and the number of steps S is output as 0; if the cycle start element address SPTR is at B., Bi, ..., B (n.1) is any address in 1, then stepping on Bo, Bi, ..., B (Nn, will be larger -25- This paper size applies to China National Standard (CNS) A4 size (210x297 mm) ®) 479416 A8 B8 C8 D8 6. Scope of patent application (please read the precautions on the back before filling this page) The control signal equal to SPTR and 1 1 Step forward Sini Address, that is, sDPTR, s (DPTR + 1), ..., s (SPTR.n, S (SPTR + S), ..., S (pTR.1 + s) in step control signals become 1 'The rest are 0' and the number of steps S is output as sini; and a cycle start element address (SPTR) generator, which has an output terminal outputting the cycle start element address (SPTR) and an input terminal After receiving the step number S sent by the step control signal generator, the SPTR generator includes an adder divided by N and a second accumulation register, and the adder divided by N will receive the The step number S is added to the SPTR output from the second accumulation register to generate a sum A ", if A" < N, then A "is output; if A" > N, then A "is divided The remainder after N, and the second accumulation register divides the output latching of the N adder—sampling period. 2. For example, the integral triangle modulator of the first item of the patent application, where Sini is 丨 or 2. Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs. 3. If the integral triangle modulator of item 1 of the patent scope is applied, the loop filtering is connected in series by analogy. Divider implementation. 4. If the integrating delta modulator of item 1 in the scope of patent application, the series analog integrator can be implemented by discrete-time or continuous-time circuits. -26- This paper size is applicable to national standards (CNS) A4 inspection (210X297 public director) "-479416 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs N + 1) The level-integral delta analog / digital converter includes a frequency reduction filter to reduce the digital output code generated by the (N + 1) level quantizer back to the fundamental frequency digital signal, and this signal is (N + 1) Digital output of level-integral delta analog / digital converter. 6. —A kind of (N + 1) quasi-integral delta digital / analog converter, where N is an integer greater than one, which includes: an up-conversion filter, which has an input terminal to receive a number of digital words (digital word), whose sampling frequency is Nyquist Rate, and an output terminal outputs a digital word after an upsampling, whose sampling frequency is higher than Nyquist Rate; a digital integral delta modulator, which includes a digital loop filter and an (N + 1 ) Level quantizer. This modulator converts the digital word that has been up-converted into an (N + 1) quantized digital word. The digital loop filter receives the digital word after up-conversion and negative feedback. The (N + 1) level quantized digital word and generates a pre-processed signal, which is quantized by the (N + 1) level quantizer to output the (N + 1) level quantized digital word; a stepping element The selection logic is used to generate a set of stepwise control signals S corresponding to the (N + 1) level quantized digital words. , S!, ..., S (N_}); One (N + 1) quasi-bit / analog converter contains N unit elements, and there is a mismatch between unit elements. Its function is based on the step-by-step Control signal S received by the component selection logic. , Si, ..., S (N, n) to generate corresponding analog signals to a post-stage analog filter; and a post-stage analog filter, which will be received by the (N + 1) quasi-bit / analog converter. Signal out-of-band noise filtered out; 27- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 479416 A8 B8 C8 D8 6 Scope of patent application The step-by-step component selection logic includes: an index adder divided by N, having a rain input terminal to receive the (N + 1) level quantized digits generated by the (N + 1) level quantizer Word and a previous pointer (delayed pointer, DPTR), and an output terminal pointer (pointer, PTR), which calculates the sum A of the digital output code and the pointer at the previous time, if A < N, the indicator 値 is A; if A > N, the index 値 is the remainder after A divided by N; a stepwise adder that divides by N has two inputs to receive the index (PTR) transmitted by the index adder divided by N And the number of steps S transmitted by a step control signal generator, and The output end has passed through another PTR of the step adder. The acquisition of the other PTR is to calculate the sum A 'of PTR and S. If A' < N, the other PTR is A '; if A' > N , The other PTR is the remainder after A ′ divided by N; a first accumulation register is connected to the aforementioned step adder, and has an input end receiving the other PTR, and an output end outputting the previous one. Time index (DPTR), the first accumulation register latches another PTR—sampling period; a control signal generator receives the index (PTR) and the previous time index (DPTR) and generates N The control signals, Bi, ..., B (Nn, their actions are as follows: if PTR is greater than DPTR, then BDPTR, B (Ι) ΡΤΚ, υ, ..., Β (ΡΙΙ ^) are 1, and the rest are 0 'if PTR is less than DPTR , Then BDPTR, B (dptr + ", ..., Bν, B〇, B !, B (PTR_n is 1 'and the rest are 0, and if PTR is equal to DPTR, then all N control signals B (), B, , ..., B (N _ 丨) are 0, -28- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ---------- (Please read the back first Please note this page, please fill in this page) Order 4 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A8 B8 C8 D8 VI. Application for a patent scope A step control signal generator with a preset slni, Sini is 1 to N An integer that receives N control signal cores, B!, ..., B (N, υ, and a cycle start element address SPTR from the control signal generator, and generates N step control signals S. , Si, ..., S (Nn and a step number S, the actions are as follows: if the cycle start element address SPTR is not at B., Bi, ..., Βπο is any of 1, it is not correct, Β !, ..., B (N.η do any stepping action, and output the original state as stepping control signals SQ, S!, ..., and the number of step s is output as 0; if the cycle start element address SPTR is in B., ..., B (N.1) is any address of 1, then stepping on B0, B!, ..., will move the control signal of SPTR greater than or equal to 1 forward Enter Sini addresses, that is, SDPTR, S (DPTR + U, ..., S (SPTR.n, S (SPTR + S), S (sptr + 1 + s), ... , S (pTR.1 + s) becomes 1, the rest are 0 'and the number of steps S is output as sini: and a cycle start element address (SPTR) generator, which has an output_output for this cycle. The start address (SPTR) and an * input end receive the number of steps S sent by the step control signal generator. The SPTR generator includes an adder divided by N and a second accumulator. Register where the divider divided by N will receive the step The number S is added to the SPTR output from the second accumulation register to generate a sum A ", if A" < N, then A "is output; if A" > N, then A "is divided by N The remainder, and the second accumulation register divides by the output latching of the N adder—sampling period. -29- The “Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ) '' 'II (please read the precautions on the back before filling this page), I # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479416 A8 B8 C8 D8, apply for patents 7. If you apply for a patent scope The (N + 1) quasi-integral delta-sigma digital / analog converter of the sixth item, where Sini is 1 or 2. 8. —An oversampling converter applies for the integral delta modulator of the first scope of the patent application. Right age. (Please read the notes on the back before filling out this page) Printed on the paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to the Chinese National Standard (CNS) Α4 specification (210 X 297 mm)