WO2020155447A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2020155447A1
WO2020155447A1 PCT/CN2019/085131 CN2019085131W WO2020155447A1 WO 2020155447 A1 WO2020155447 A1 WO 2020155447A1 CN 2019085131 W CN2019085131 W CN 2019085131W WO 2020155447 A1 WO2020155447 A1 WO 2020155447A1
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WO
WIPO (PCT)
Prior art keywords
layer
display panel
substrate
disposed
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/085131
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English (en)
French (fr)
Inventor
宋利旺
王�琦
焦蒙蒙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020155447A1 publication Critical patent/WO2020155447A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers

Definitions

  • This application relates to the field of display technology, and in particular to a display panel.
  • AMLCD Active Matrix Liquid Crystal Display
  • AMLCD Active Matrix Liquid Crystal Display
  • MCD Active Matrix Liquid Crystal Display
  • PFA Film on Array
  • the organic material has a flattening effect, it can also improve liquid crystal efficiency and reduce parasitic capacitance.
  • PFA Planarization layer
  • the gap between the color filter substrate and the array substrate constituting the active matrix liquid crystal display will change, which will cause light to pass through the color filter substrate and the array substrate. The distance between them changes, which will affect the display effect of the active matrix liquid crystal display.
  • the purpose of the present application is to provide a display panel to solve the problem that the flattening layer of the display panel is easy to deform, which leads to poor compression resistance of the display panel.
  • a display panel comprising:
  • a passivation layer, the passivation layer is disposed on the array substrate;
  • a planarization layer, the planarization layer is disposed on the passivation layer;
  • a pressure resistant layer, the pressure resistant layer is disposed on the planarization layer;
  • a first substrate, the first substrate is arranged opposite to the surface of the array substrate provided with the passivation layer;
  • a spacer the spacer is located between the array substrate and the first substrate and is in contact with the pressure-resistant layer;
  • the preparation material of the passivation layer is an inorganic insulating material.
  • the pressure resistant layer is an inorganic insulating layer.
  • the preparation material of the inorganic insulating layer is any one of silicon nitride, silicon oxide or silicon oxynitride.
  • the pressure resistant layer is a patterned indium tin oxide layer.
  • the display panel further includes a pixel electrode disposed on the planarization layer and penetrates the planarization layer and the passivation layer to contact the array substrate.
  • the patterned indium tin oxide layer and the pixel electrode are manufactured through the same manufacturing process.
  • the pressure resistant layer includes an inorganic insulating layer and a patterned indium tin oxide layer sequentially disposed on the planarization layer.
  • the display panel further includes a common electrode, and the common electrode is disposed on a surface of the first substrate opposite to the array substrate.
  • the display panel further includes a black matrix, and the black matrix is disposed between the common electrode and the first substrate.
  • the display panel further includes a color film layer, and the color film layer is disposed between the passivation layer and the planarization layer.
  • a display panel comprising:
  • a passivation layer, the passivation layer is disposed on the array substrate;
  • a planarization layer, the planarization layer is disposed on the passivation layer;
  • a pressure resistant layer, the pressure resistant layer is disposed on the planarization layer;
  • a first substrate, the first substrate is arranged opposite to the surface of the array substrate provided with the passivation layer;
  • the spacer is located between the array substrate and the first substrate and is in contact with the pressure-resistant layer.
  • the pressure resistant layer is an inorganic insulating layer.
  • the preparation material of the inorganic insulating layer is any one of silicon nitride, silicon oxide or silicon oxynitride.
  • the pressure resistant layer is a patterned indium tin oxide layer.
  • the display panel further includes a pixel electrode disposed on the planarization layer and penetrates the planarization layer and the passivation layer to contact the array substrate.
  • the patterned indium tin oxide layer and the pixel electrode are manufactured through the same manufacturing process.
  • the pressure resistant layer includes an inorganic insulating layer and a patterned indium tin oxide layer sequentially disposed on the planarization layer.
  • the display panel further includes a common electrode, and the common electrode is disposed on a surface of the first substrate opposite to the array substrate.
  • the display panel further includes a black matrix, and the black matrix is disposed between the common electrode and the first substrate.
  • the display panel further includes a color film layer, and the color film layer is disposed between the passivation layer and the planarization layer.
  • the present application provides a display panel.
  • a pressure-resistant layer in contact with spacers is provided on a planarization layer to improve the pressure resistance of the display panel so as to avoid poor pressure resistance of the display panel, resulting in an array substrate and a first substrate constituting the display panel The distance between them changes to affect the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to the first embodiment of the application
  • FIG. 2 is a schematic structural diagram of a display panel according to a second embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a display panel according to a third embodiment of the application.
  • 10 display panel 100 array substrate; 110 passivation layer; 120, 220, 320 planarization layer; 130, 230, 330 compression layer; 331 inorganic insulating layer; 332 patterned indium tin oxide layer; 140 first substrate; 150, 250 spacers; 160, 260 pixel electrodes; 170 common electrodes; 180 color film layers; 190 black matrix; 101 substrates; 1021 first gate patterns; 1022 second gate patterns; 103 first insulating layers; 104 Channel layer; 1051 source electrode; 1052 drain electrode.
  • FIG. 1 is a schematic diagram of the structure of the display panel 10 according to the first embodiment of the application.
  • the display panel 10 includes an array substrate 100, a passivation layer 110, a planarization layer 120, a pressure resistant layer 130, a first substrate 140 and spacers 150.
  • the passivation layer 110 is disposed on the array substrate 100
  • the planarization layer 120 is disposed on the passivation layer 110
  • the pressure resistant layer 130 is disposed on the planarization layer 120
  • the first substrate 140 and the array substrate 100 are provided with the passivation layer 110.
  • the surfaces are arranged oppositely, and the spacer 150 is located between the array substrate 110 and the first substrate 140 and is in contact with the pressure-resistant layer 130.
  • the array substrate 100 includes:
  • a patterned first conductive layer formed on the substrate 101, the patterned first conductive layer includes a first gate pattern 1021 and a second gate pattern 1022;
  • a patterned second conductive layer is formed on the channel layer 104.
  • the patterned second conductive layer includes a source electrode 1051 and a drain electrode 1052.
  • the source electrode 1051 and the drain electrode 1052 are formed on the patterned second conductive layer. Separated by grooves.
  • the substrate 101 is a glass substrate, a flexible substrate, or a flexible substrate.
  • the patterned first conductive layer includes a first gate pattern 1021 and a second gate pattern 1022.
  • the first gate pattern 1021 and the film layer above it constitute a thin film transistor
  • the second gate pattern 1022 and the second conductive layer patterned thereon constitute a storage capacitor.
  • the material for preparing the patterned first conductive layer is at least one of molybdenum, aluminum, copper, and titanium, with a thickness of 2000 angstroms to 8000 angstroms.
  • the first insulating layer 103 is a gate insulating layer (Gate Insulation Layer, GI).
  • the material of the first insulating layer 103 includes, but is not limited to, silicon nitride, silicon oxide, and silicon oxynitride, with a thickness of 1000 angstroms to 3000 angstroms.
  • the channel layer 104 includes a polysilicon layer ( ⁇ -Si) and a phosphorus-doped amorphous silicon layer (n + -Si) sequentially arranged on the first insulating layer 103; the patterned second conductive layer is provided with trenches to The source electrode 1051 and the drain electrode 1052 are formed.
  • the passivation layer (Passivation Layer) 110 is used to block spacers from entering the thin film transistor on the array substrate 100 to prevent ions from affecting the electrical performance of the thin film transistor.
  • the passivation layer 110 is made of inorganic insulating materials, and the inorganic insulating materials include but are not limited to silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide.
  • the preparation method of the passivation layer 110 includes, but is not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and thermal chemical vapor deposition (Thermal Chemical Vapor Deposition, TCVD) , Atom Layer Depositon (ALD), etc.
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • TCVD Thermal chemical vapor deposition
  • ALD Atom Layer Depositon
  • the planarization layer (PLN) 120 is used to planarize the surface of the array substrate 100 to improve the display effect of the display panel.
  • the preparation material of the planarization layer 120 is an organic material, which can be obtained by spin coating or evaporation (Evaporation). ), the thickness is 20000 angstroms-35000 angstroms.
  • the compressive layer 130 is an inorganic insulating layer, which covers the entire surface of the planarization layer 120.
  • the spacer 150 transmits the external force to the compressive layer 130 without causing deformation of the compressive layer 130, thereby improving the display panel.
  • the compression resistance of 10 prevents the spacer 150 from directly applying an external force to the planarization layer 120 to cause the planarization layer 120 to deform and affect the display effect of the display panel.
  • the pressure-resistant layer 130 may also be provided only on the corresponding planarization layer 120 under the spacer 150.
  • the preparation method of the inorganic insulating layer includes but is not limited to CVD, PECVD, TCVD, and ALD.
  • the preparation material of the inorganic insulating layer is any one of a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer.
  • the pressure-resistant layer 130, the passivation layer 110, and the planarization layer 120 between the two constitute a sandwich structure in which two inorganic layers sandwich an organic layer to synergistically improve the pressure resistance of the display panel 10.
  • the first substrate 140 is a transparent substrate, which may be a glass substrate.
  • the spacer 150 is used to support the first substrate 140 and the array substrate 100 so that a proper distance is maintained between the first substrate 140 and the array substrate 100.
  • the spacer 150 is columnar with a height of 3 micrometers to 4 micrometers.
  • the display panel 10 further includes a pixel electrode 160, which is disposed on the anti-stress layer 130 and penetrates the anti-stress layer 130, the planarization layer 120 and the passivation layer 110 to contact the array substrate 100. Specifically, the pixel electrode 160 penetrates through the compression layer 130, the planarization layer 120, the color film layer 180, and the passivation layer 110 to contact the drain electrode 1052 of the thin film transistor.
  • the pixel electrode 160 is made of indium tin oxide (Indium Tin Oxide) Oxide, ITO), the pixel electrode 160 is formed on the planarization layer 120 by sputtering deposition and wet etching.
  • the display panel 10 further includes a common electrode 170, and the common electrode 170 is disposed on the surface of the first substrate 140 opposite to the array substrate 100. After the pixel electrode 160 and the common electrode 170 are energized, a vertical electric field is formed to deflect the liquid crystal (not shown) in the display panel 10 to control the display state of the display panel 10.
  • the material of the common electrode 170 is indium tin oxide.
  • the thickness of the common electrode 170 is 0.1 ⁇ m-0.16 ⁇ m.
  • the display panel 10 further includes a color film layer 180 and a black matrix 190.
  • the color film layer 180 is disposed between the passivation layer 110 and the planarization layer 120, and the black matrix 190 is disposed on the first substrate and located on the first substrate 140 and the common electrode 170.
  • the color film layer 180 and the black matrix 190 may be located on the array substrate 100 or the first substrate 140 at the same time.
  • the color film layer 180 is disposed on the array substrate 100 so that the display panel 10 has a higher aperture ratio; compared to disposing the black matrix 190 on the array substrate 100
  • disposing the black matrix 190 on the first substrate 140 can simplify the manufacturing process.
  • the color film layer 180 is used to transmit light of different colors, including red photoresist, green photoresist and blue photoresist.
  • the thickness of the color film layer 180 is 2 microns to 5 microns; the black matrix 190 is used to prevent light from entering the film
  • the channel layer of the transistor causes current leakage.
  • the black matrix 190 is made of a mixture of black metal (such as chromium), organic materials and black pigments.
  • the thickness of the black matrix 190 is 1 ⁇ m-2 ⁇ m.
  • FIG. 2 is the display panel 20 according to the second embodiment of the application.
  • the display panel 20 of the second embodiment is basically similar to the display panel 10 of the first embodiment, except that the pressure-resistant layer 230 is a patterned indium tin oxide layer, and the patterned indium tin oxide layer passes through the pixel electrode 260 Manufactured by the same process, the patterned indium tin oxide layer and the pixel electrode 260 are not electrically connected, that is, the patterned indium tin oxide cannot input electrical signals.
  • the pressure resistant layer 230 is disposed on the planarization layer 220 directly under the spacer 250. Compared with the display panel 10 of the first embodiment, by preparing the pixel electrode 260 and preparing the pressure-resistant layer 230 at the same time, the pressure resistance of the display panel 20 can be improved, and the manufacturing process of the display panel can be reduced.
  • FIG. 3 is a display panel 30 according to the third embodiment of the application.
  • the display panel 30 of the third embodiment is basically similar to the display panel 10 of the first embodiment, except that the pressure-resistant layer 330 includes an inorganic insulating layer 331 and patterned indium tin oxide that are sequentially disposed on the planarization layer 320. ⁇ 332.
  • the pressure resistant layer 330 of this embodiment further improves the pressure resistance of the display panel.
  • a pressure resistant layer in contact with the spacer is provided on the planarization layer to improve the pressure resistance of the display panel, thereby avoiding the poor pressure resistance of the display panel from causing the distance between the array substrate and the first substrate constituting the display panel to change Thereby affecting the display effect of the display panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（10），通过在平坦化层（120）上设置与隔垫物（150）接触的抗压层（130）以提高显示面板（10）的抗压性从而避免显示面板（10）抗压性差导致组成显示面板（10）的阵列基板（100）和第一基板（140）之间的距离发生变化从而影响显示面板（10）的显示效果。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
主动式矩阵液晶显示器(Active Matrix Liquid Crystal Display, AMLCD)的生产业者为了制造更高阶的显示器，通常会在主动式矩阵液晶显示器的像素电极和薄膜晶体管之间形成有机材料（Polymer film on Array，PFA）作为平坦层，该有机材料起到平坦化作用的同时，也能提升液晶效率并降低寄生电容。然而，在采用PFA作为平坦化层之后，PFA由于存在抗压性差的问题会使得组成主动式矩阵液晶显示器的彩膜基板和阵列基板之间的间距发生变化继而导致光线通过彩膜基板和阵列基板之间的距离发生变化，从而会影响主动式矩阵液晶显示器的显示效果。
 技术问题
本申请的目的在于提供一种显示面板，以解决显示面板的平坦化层易变形导致显示面板的抗压性较差的问题。
 技术解决方案
一种显示面板，所述显示面板包括：
一阵列基板；
一钝化层，所述钝化层设置于所述阵列基板上；
一平坦化层，所述平坦化层设置于所述钝化层上；
一抗压层，所述抗压层设置于所述平坦化层上；
一第一基板，所述第一基板与所述阵列基板设置有所述钝化层的表面相对设置；
隔垫物，所述隔垫物位于所述阵列基板和所述第一基板之间且与所述抗压层接触；
所述钝化层的制备材料为无机绝缘材料。
在上述显示面板中，所述抗压层为无机绝缘层。
在上述显示面板中，所述无机绝缘层的制备材料为氮化硅、氧化硅或者氮氧化硅中的任意一种。
在上述显示面板中，所述抗压层为图案化的氧化铟锡层。
在上述显示面板中，所述显示面板还包括像素电极，所述像素电极设置于平坦化层上且贯穿所述平坦化层以及所述钝化层以与所述阵列基板接触。
在上述显示面板中，所述图案化的氧化铟锡层与所述像素电极通过同一制程制得。
在上述显示面板中，所述抗压层包括依次设置于所述平坦化层上的无机绝缘层和图案化的氧化铟锡层。
在上述显示面板中，所述显示面板还包括公共电极，所述公共电极设置于所述第一基板与所述阵列基板相对的表面上。
在上述显示面板中，所述显示面板还包括黑色矩阵，所述黑色矩阵设置于所述公共电极和所述第一基板之间。
在上述显示面板中，所述显示面板还包括彩色膜层，所述彩色膜层设置于所述钝化层与所述平坦化层之间。
一种显示面板，所述显示面板包括：
一阵列基板；
一钝化层，所述钝化层设置于所述阵列基板上；
一平坦化层，所述平坦化层设置于所述钝化层上；
一抗压层，所述抗压层设置于所述平坦化层上；
一第一基板，所述第一基板与所述阵列基板设置有所述钝化层的表面相对设置；
隔垫物，所述隔垫物位于所述阵列基板和所述第一基板之间且与所述抗压层接触。
在上述显示面板中，所述抗压层为无机绝缘层。
在上述显示面板中，所述无机绝缘层的制备材料为氮化硅、氧化硅或者氮氧化硅中的任意一种。
在上述显示面板中，所述抗压层为图案化的氧化铟锡层。
在上述显示面板中，所述显示面板还包括像素电极，所述像素电极设置于平坦化层上且贯穿所述平坦化层以及所述钝化层以与所述阵列基板接触。
在上述显示面板中，所述图案化的氧化铟锡层与所述像素电极通过同一制程制得。
在上述显示面板中，所述抗压层包括依次设置于所述平坦化层上的无机绝缘层和图案化的氧化铟锡层。
在上述显示面板中，所述显示面板还包括公共电极，所述公共电极设置于所述第一基板与所述阵列基板相对的表面上。
在上述显示面板中，所述显示面板还包括黑色矩阵，所述黑色矩阵设置于所述公共电极和所述第一基板之间。
在上述显示面板中，所述显示面板还包括彩色膜层，所述彩色膜层设置于所述钝化层与所述平坦化层之间。
 有益效果
本申请提供一种显示面板，通过在平坦化层上设置与隔垫物接触的抗压层以提高显示面板的抗压性从而避免显示面板抗压性差导致组成显示面板的阵列基板和第一基板之间的距离发生变化从而影响显示面板的显示效果。
 附图说明
图1为本申请第一实施例显示面板的结构示意图；
图2为本申请第二实施例显示面板的结构示意图；
图3为本申请第三实施例显示面板的结构示意图。
附图标注：
10显示面板；100阵列基板； 110钝化层； 120、220、320平坦化层； 130 、230、330抗压层； 331 无机绝缘层； 332 图案化的氧化铟锡层；140第一基板； 150、250隔垫物；  160、260像素电极； 170公共电极； 180 彩色膜层； 190黑色矩阵； 101基板； 1021 第一栅极图案； 1022第二栅极图案；  103第一绝缘层； 104沟道层； 1051 源电极； 1052漏电极。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请第一实施例显示面板10的结构示意图。显示面板10包括阵列基板100、钝化层110、平坦化层120、抗压层130、第一基板140以及隔垫物150。钝化层110设置于阵列基板100上，平坦化层120设置于钝化层110上，抗压层130设置于平坦化层120上，第一基板140与阵列基板100设置有钝化层110的表面相对设置，隔垫物150位于阵列基板110和第一基板140之间且与抗压层130接触。
在本实施例中，阵列基板100包括：
基板101；
于基板101上形成的图案化的第一导电层，图案化的第一导电层包括第一栅极图案1021和第二栅极图案1022；
覆盖基板101和图案化的第一导电层的第一绝缘层103；
于第一绝缘层103上形成的沟道层104；
于沟道层104上形成图案化的第二导电层，图案化的第二导电层包括源电极1051和漏电极1052，源电极1051和漏电极1052通过设置于图案化的第二导电层上的沟槽隔开。
组成阵列基板100的各膜层分别形成薄膜晶体管和存储电容。基板101为玻璃基板、柔性基板或者可挠性基板。图案化的第一导电层包括第一栅极图案1021和第二栅极图案1022，第一栅极图案1021与其上方的膜层（第一绝缘层、沟道层以及源漏电极）构成薄膜晶体管，第二栅极图案1022与其上方图案化的第二导电层构成存储电容。图案化的第一导电层的制备材料为钼、铝、铜、钛中的至少一种，其厚度为2000埃-8000埃。第一绝缘层103为栅极绝缘层（Gate Insulation Layer, GI），第一绝缘层103的制备材料包括但不限于氮化硅、氧化硅以及氮氧化硅，其厚度为1000埃-3000埃。沟道层104包括依次设置于第一绝缘层103上的多晶硅层（α-Si）和磷掺杂非晶硅层（n +-Si）；图案化的第二导电层上设置有沟槽以形成源电极1051和漏电极1052。
在本实施例中，钝化层（Passivation Layer）110用于阻隔离子进入阵列基板100上的薄膜晶体管中，避免离子影响薄膜晶体管的电学性能。钝化层110的制备材料为无机绝缘材料，无机绝缘材料包括但不限于氮化硅、氧化硅、氮氧化硅以及氧化铝。钝化层110的制备方法包括但不限于化学气相沉积(Chemical Vapor Deposition, CVD)、等离子体增强化学气相沉积（Plasma Enhanced Chemical Vapor Deposition, PECVD）、热化学气相沉积（Thermal Chemical Vapor Deposition, TCVD）、原子层沉积（Atom Layer Depositon, ALD ）等。
平坦化层（Planarizationlayer, PLN）120用于平坦化阵列基板100的表面以改善显示面板的显示效果，平坦化层120的制备材料为有机材料，通过旋转涂布（Spin Coating）或蒸镀(Evaporation)的方式形成，其厚度为20000埃-35000埃。
抗压层130为无机绝缘层，其覆盖平坦化层120的整个表面，外力作用于显示面板10时，隔垫物150传递外力至抗压层130不会导致抗压层130变形从而提高显示面板10的抗压性，避免隔垫物150直接将外力施加至平坦化层120导致平坦化层120发生变形而影响显示面板的显示效果。在其他实施例中，抗压层130也可以只设置于隔垫物150下方对应的平坦化层120上。无机绝缘层的制备方法包括但不限于CVD、PECVD、TCVD以及ALD，无机绝缘层的制备材料为氮化硅层、氧化硅层或者氮氧化硅中的任意一种。抗压层130、钝化层110以及位于两者之间的平坦化层120构成两无机层夹住一有机层的夹层结构以协同提高显示面板10的抗压性。
第一基板140为透明基板，其可以为玻璃基板。
隔垫物150用于支撑第一基板140和阵列基板100使得第一基板140和阵列基板100之间保持合适的间距。隔垫物150为柱状，其高度为3微米-4微米。
显示面板10还包括像素电极160，像素电极160设置于抗压层130上且贯穿抗压层130、平坦化层120以及钝化层110以与阵列基板100接触。具体地，像素电极160贯穿抗压层130、平坦化层120彩色膜层180以及钝化层110以与薄膜晶体管的漏电极1052接触。像素电极160的制备材料为氧化铟锡（Indium Tin Oxide, ITO），像素电极160是通过溅射沉积和湿法刻蚀形成于平坦化层120上。
进一步地，显示面板10还包括公共电极170，公共电极170设置于第一基板140与阵列基板100相对的表面上。像素电极160和公共电极170通电后形成垂直电场使显示面板10中的液晶（未示出）发生偏转以控制显示面板10的显示状态。公共电极170的制备材料为氧化铟锡。公共电极170厚度为0.1微米-0.16微米。
进一步地，显示面板10还包括彩色膜层180和黑色矩阵190。彩色膜层180设置于钝化层110和平坦化层120之间，黑色矩阵190设置于第一基板上且位于第一基板140和公共电极170。在其他实施中，彩色膜层180和黑色矩阵190可以同时位于阵列基板100或者第一基板140上。相对于彩色膜层180设置于第一基板140上，本实施例将彩色膜层180设置在阵列基板100使得显示面板10具有更高的开口率；相对于将黑色矩阵190设置在阵列基板100上，本实施例将黑色矩阵190设置在第一基板140上能简化制造工艺。彩色膜层180用于透过不同颜色的光，其包括红色光阻、绿色光阻以及蓝色光阻，彩色膜层180的厚度为2微米-5微米；黑色矩阵190用于防止光线入射至薄膜晶体管的沟道层而产生漏电，黑色矩阵190的制备材料包括为黑色金属（例如铬）、有机材料与黑色颜料的混合物，黑色矩阵190的厚度为1微米-2微米。
请参阅图2，其为本申请第二实施例的显示面板20。第二实施例的显示面板20与第一实施例的显示面板10基本相似，不同之处在于，抗压层230为图案化的氧化铟锡层，图案化的氧化铟锡层与像素电极260通过同一制程制得，图案化的氧化铟锡层与像素电极260之间是不电性连接的，即图案化的氧化铟锡不能输入电信号。抗压层230设置于隔垫物250正下方的平坦化层220上。相对于第一实施例的显示面板10，通过制备像素电极260的同时制备抗压层230能提高显示面板20抗压性的同时，能够减少显示面板的制造制程。
请参阅图3，其为本申请第三实施例的显示面板30。第三实施例的显示面板30与第一实施例的显示面板10基本相似，不同之处在于，抗压层330包括依次设置于平坦化层320上的无机绝缘层331和图案化的氧化铟锡层332。相对于第一实施例的显示面板10和第二实施例的显示面板20，本实施例的抗压层330进一步地提高显示面板的抗压性。
本申请通过在平坦化层上设置与隔垫物接触的抗压层以提高显示面板的抗压性从而避免显示面板抗压性差导致组成显示面板的阵列基板和第一基板之间的距离发生变化从而影响显示面板的显示效果。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    一阵列基板；
    一钝化层，所述钝化层设置于所述阵列基板上；
    一平坦化层，所述平坦化层设置于所述钝化层上；
    一抗压层，所述抗压层设置于所述平坦化层上；
    一第一基板，所述第一基板与所述阵列基板设置有所述钝化层的表面相对设置；
    隔垫物，所述隔垫物位于所述阵列基板和所述第一基板之间且与所述抗压层接触；
    所述钝化层的制备材料为无机绝缘材料。
  2. 根据权利要求1所述的显示面板，其中，所述抗压层为无机绝缘层。
  3. 根据权利要求2所述的显示面板，其中，所述无机绝缘层的制备材料为氮化硅、氧化硅或者氮氧化硅中的任意一种。
  4. 根据权利要求1所述的显示面板，其中，所述抗压层为图案化的氧化铟锡层。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括像素电极，所述像素电极设置于平坦化层上且贯穿所述平坦化层以及所述钝化层以与所述阵列基板接触。
  6. 根据权利要求5所述的显示面板，其中，所述图案化的氧化铟锡层与所述像素电极通过同一制程制得。
  7. 根据权利要求1所述的显示面板，其中，所述抗压层包括依次设置于所述平坦化层上的无机绝缘层和图案化的氧化铟锡层。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括公共电极，所述公共电极设置于所述第一基板与所述阵列基板相对的表面上。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括黑色矩阵，所述黑色矩阵设置于所述公共电极和所述第一基板之间。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括彩色膜层，所述彩色膜层设置于所述钝化层与所述平坦化层之间。
  11. 一种显示面板，其中，所述显示面板包括：
    一阵列基板；
    一钝化层，所述钝化层设置于所述阵列基板上；
    一平坦化层，所述平坦化层设置于所述钝化层上；
    一抗压层，所述抗压层设置于所述平坦化层上；
    一第一基板，所述第一基板与所述阵列基板设置有所述钝化层的表面相对设置；
    隔垫物，所述隔垫物位于所述阵列基板和所述第一基板之间且与所述抗压层接触。
  12. 根据权利要求11所述的显示面板，其中，所述抗压层为无机绝缘层。
  13. 根据权利要求12所述的显示面板，其中，所述无机绝缘层的制备材料为氮化硅、氧化硅或者氮氧化硅中的任意一种。
  14. 根据权利要求11所述的显示面板，其中，所述抗压层为图案化的氧化铟锡层。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括像素电极，所述像素电极设置于平坦化层上且贯穿所述平坦化层以及所述钝化层以与所述阵列基板接触。
  16. 根据权利要求15所述的显示面板，其中，所述图案化的氧化铟锡层与所述像素电极通过同一制程制得。
  17. 根据权利要求11所述的显示面板，其中，所述抗压层包括依次设置于所述平坦化层上的无机绝缘层和图案化的氧化铟锡层。
  18. 根据权利要求11所述的显示面板，其中，所述显示面板还包括公共电极，所述公共电极设置于所述第一基板与所述阵列基板相对的表面上。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括黑色矩阵，所述黑色矩阵设置于所述公共电极和所述第一基板之间。
  20. 根据权利要求11所述的显示面板，其中，所述显示面板还包括彩色膜层，所述彩色膜层设置于所述钝化层与所述平坦化层之间。
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