WO2013044836A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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WO2013044836A1
WO2013044836A1 PCT/CN2012/082245 CN2012082245W WO2013044836A1 WO 2013044836 A1 WO2013044836 A1 WO 2013044836A1 CN 2012082245 W CN2012082245 W CN 2012082245W WO 2013044836 A1 WO2013044836 A1 WO 2013044836A1
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Prior art keywords
layer
gate
graphene
array substrate
semiconductor active
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PCT/CN2012/082245
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English (en)
French (fr)
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戴天明
薛建设
姚琪
张锋
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京东方科技集团股份有限公司
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Priority to US13/704,704 priority Critical patent/US9159805B2/en
Publication of WO2013044836A1 publication Critical patent/WO2013044836A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Embodiments of the present invention relate to a TFT array substrate, a method of fabricating the same, and a display device. Background technique
  • a Thin Film Transistor-Liquid Crystal Display displays an image by changing the intensity of the electric field applied to the liquid crystal layer to change the degree of rotation of the liquid crystal molecules, thereby controlling the intensity of the light transmission.
  • a liquid crystal display panel includes a backlight module group, a polarizer, an upper substrate (usually a color filter substrate), a lower substrate (usually an array substrate), and a liquid crystal filled in a liquid crystal cell composed of the two substrates.
  • Molecular layer Data lines and gate lines are formed on the array substrate, and the data lines and the gate lines are arranged to form pixel units arranged in a matrix form. Each pixel unit includes a TFT switch and a pixel electrode.
  • the TFT switch includes a gate electrode, a source electrode, a drain electrode, and an active layer; a gate electrode is connected to the gate line, a source electrode is connected to the data line, a drain electrode is connected to the pixel electrode, and an active layer is formed between the source and drain electrodes and the gate electrode.
  • a common electrode may be formed on the substrate for forming an electric field with the pixel electrode, and a change in electric field intensity between the common electrode and the pixel electrode controls the degree of rotation of the liquid crystal molecules.
  • a storage capacitor may also be formed between the storage bottom capacitance line and the pixel electrode of the TFT array substrate parallel to the gate line and in the same layer to maintain the state of the liquid crystal molecules before the next signal.
  • Advanced Super Dimension Switch forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that the slit in the liquid crystal cell All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • Embodiments of the present invention provide a TFT array substrate, a manufacturing method thereof, and a display device, which improve the structure of the TFT array substrate, make the thickness of the substrate thin, and simplify the process flow.
  • a method of fabricating a thin film transistor (TFT) array substrate comprising:
  • a protective layer is formed over the data line, the source, the semiconductor active layer, the drain, and the pixel electrode.
  • a common electrode is formed over the pixel electrode.
  • a TFT array substrate including:
  • a data line a source, a semiconductor active layer, a drain, and a pixel electrode composed of graphene; wherein the source is in contact with the semiconductor active layer, the drain a pole is in contact with the semiconductor active layer, defining a TFT channel, the pixel electrode is in contact with the drain; and forming on the data line, the source, the semiconductor active layer, the drain, and the pixel electrode
  • the protective layer In one example, on the protective layer, a common electrode layer is formed over the pixel electrode.
  • a display device including the above TFT array substrate.
  • the TFT array substrate provided by the embodiment of the invention, the manufacturing method thereof and the display device, the data line, the source, the drain, the active layer and the pixel electrode layer of the TFT substrate are prepared in the same layer on the gate insulating layer by using the graphene material.
  • the thickness of the TFT array substrate can be thinned, and the process flow can be simplified.
  • FIG. 1 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a substrate in a process of manufacturing a TFT array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view of a substrate structure in a method of manufacturing a TFT array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a substrate in a process of manufacturing a TFT array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram 5 of a substrate during a method for fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram 7 of a substrate structure in a method for fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a substrate structure during a method of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a substrate structure during a method of fabricating a TFT array substrate according to an embodiment of the present invention. detailed description
  • the array substrate of the embodiment of the invention includes a plurality of gate lines and a plurality of data lines, and the gate lines and the numbers
  • the data lines intersect each other thereby defining pixel units arranged in a matrix, each of which includes a thin film transistor and a pixel electrode as switching elements.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • a method for fabricating a TFT array substrate according to an embodiment of the invention includes the following steps.
  • a metal thin film layer having a thickness of, for example, 1000 A to 7000 A can be formed on the base substrate 201 by a magnetron sputtering method.
  • the material of the metal thin film layer may be usually a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a laminated structure of a film of the above materials.
  • a plurality of lateral gate lines (not shown in FIG. 1) and connected to the gate lines are formed on a certain area of the glass substrate 201 by a first patterning process such as exposure, development, etching, and peeling using a mask plate.
  • Gate 202 is a first patterning process such as exposure, development, etching, and peeling using a mask plate.
  • a gate insulating layer 203 can be deposited on the gate line and the gate electrode 202 by a plasma enhanced chemical vapor deposition (PEC VD), for example, a gate insulating layer 203 having a thickness of, for example, 1000 A to 6000 A.
  • the material of 203 is usually silicon nitride, and an insulating material such as silicon oxide or silicon oxynitride may also be used.
  • a graphene layer 204 is formed by, for example, depositing a layer of a graphene material on the gate insulating layer 203 by PECVD or spin-coating a water-soluble single layer or a plurality of graphene materials.
  • a layer of photoresist 211 is coated on the graphene layer 204.
  • the channel region graphene 207 is exposed, as shown in FIG.
  • the channel region graphene 207 is subjected to hydrogenation treatment by a mixed gas of 3 ⁇ 4, or 3 ⁇ 4 and Ar gas, and a semiconductor active layer 207 is obtained over the gate electrode 202.
  • graphene has a zero bandgap property, and the average free path and coherence length of the downloaded stream in graphene can reach micron level even at room temperature. Meanwhile, graphene is also It has a much higher carrier mobility than silicon, so it is a semiconductor material with excellent performance. Finally, the remaining photoresist is stripped off as shown in FIG.
  • the data line, the source, the drain, and the pixel electrode composed of graphene are obtained by a third patterning process on the graphene layer; the source is in contact with the semiconductor active layer, and the drain and the semiconductor active layer are Contact, defining the TFT channel, the pixel electrode is in contact with the drain.
  • a photoresist is coated on the graphene layer 204, and after exposure, development, etching, and stripping, a data line (not shown in FIG. 7) composed of graphene, a source 208, The drain 206 and the pixel electrode 205.
  • the source 208 is in contact with the semiconductor active layer 207
  • the drain 206 is in contact with the semiconductor active layer 207
  • the TFT channel is defined
  • the pixel electrode 205 is in contact with the drain 206.
  • the width of the semiconductor active layer 207 is required to be smaller than the width of the gate electrode 202 such that a region defining the source 208 of the TFT channel is in contact with the semiconductor active layer 207, and the drain 206 is in contact with the semiconductor active layer 207.
  • the regions are all located above the gate 202.
  • the data line, the source, the semiconductor active layer, the drain, and the pixel electrode in the embodiment of the present invention are located on the same layer, which can make the thickness of the array substrate thin, and reduce the process compared with the existing layer preparation. .
  • graphene Since graphene is a two-dimensional material, its properties are between the semiconductor and the conductor. In the eigenstate, the electrical conductivity of graphene has metal characteristics due to the band gap, and the electrical conductivity can reach 20,000 cm 2 /VS, which can be used as the source and drain material of the TFT; when hydrogen or argon is used, or a mixture of the two After the gas treatment, hydrogenated graphene is produced, which has an increased relative band gap and can be used as a semiconductor material. And it has a higher carrier mobility than a general semiconductor material.
  • a protective layer 209 having a thickness of, for example, 1000A to 6000A is applied over the data line, the source 208, the semiconductor active layer 207, the drain 206, and the pixel electrode 205, and the material thereof is usually dioxide.
  • An oxide such as silicon or a transparent organic resin material.
  • the above pixel electrode is controlled for display by a thin film transistor as a switching element.
  • the TFT array substrate is, for example, an array substrate for an ADS type liquid crystal display device, whereby a common electrode is further formed on the protective layer.
  • a common electrode is formed above the pixel electrode.
  • a layer of ITO (Indium Tin Oxides) or graphene is deposited on the protective layer 209 to a thickness of between 100 and 1,000.
  • a layer of photoresist is coated on the deposited ITO or graphene, and then subjected to a patterning process such as exposure, development, etching, and stripping to obtain a common electrode 210 on the pixel electrode 205.
  • the common electrode 210 may include a plurality of slits (not shown) for cooperating with the pixel electrode 205 to generate a horizontal electric field after applying a voltage difference between each other, thereby driving the liquid crystal to rotate.
  • the TFT array substrate is, for example, an array substrate for a vertical alignment (VA) type liquid crystal display device.
  • VA vertical alignment
  • the pixel electrodes on the array substrate are used to cooperate with the common electrodes on the opposite substrate opposite to the array substrate to generate a vertical electric field for driving the liquid crystal to rotate.
  • the data line, the source, the drain, the active layer and the pixel electrode layer of the TFT substrate are prepared in the same layer on the gate insulating layer by using the graphene material.
  • the thickness of the TFT array substrate is thinned, and the process flow is simplified.
  • the TFT array substrate provided by the embodiment of the present invention, as shown in FIG. 9, includes: a base substrate 201; a gate line (not shown) and a gate 202 are formed on the substrate 201; and formed on the gate line and the gate 202 A gate insulating layer 203 is formed; a data line (not shown) made of graphene, a source electrode 208, a semiconductor active layer 207, a drain electrode 206, and a pixel electrode 205 are formed on the gate insulating layer 203.
  • the source 208 is in contact with the semiconductor active layer 207, the drain 206 is in contact with the semiconductor active layer 207, the TFT channel is defined, and the pixel electrode 205 is in contact with the drain 206; the data line, the source 208, and the semiconductor are active.
  • a protective layer 209 is formed on the layer 207, the drain 206, and the pixel electrode 205.
  • the TFT array substrate is, for example, an array substrate for an ADS type liquid crystal display device, whereby a common electrode is further formed on the protective layer.
  • a common electrode 210 is formed on the protective layer 209, above the pixel electrode 205.
  • the common electrode 210 may include a plurality of slits (not shown) for cooperating with the pixel electrode 205 to generate a horizontal electric field after applying a voltage difference between each other, thereby driving the liquid crystal to rotate.
  • the TFT array substrate is, for example, an array substrate for a vertical alignment (VA) type liquid crystal display device.
  • VA vertical alignment
  • the pixel electrodes on the array substrate are used to cooperate with the common electrodes on the opposite substrate opposite to the array substrate to generate a vertical electric field for driving the liquid crystal to rotate.
  • the graphene of the semiconductor active layer 207 is a hydrogenated graphene layer. Since graphene is a two-dimensional material, its properties are between the semiconductor and the conductor. When in eigenstate, by The energy band has overlap, the conductivity has metal characteristics, the electrical conductivity can reach 20,000 cm 2 / VS, and can be used as a source and drain material of the TFT; when hydrogen or argon gas or a mixture of the two gases is used, hydrogenated graphene is produced, The band gap is relatively increased and can be used as a semiconductor material. It has a higher carrier mobility than a general semiconductor material.
  • the width of the semiconductor active layer 207 may be smaller than the width of the gate 202 such that a region defining the source 208 of the TFT channel in contact with the semiconductor active layer 207, and the drain 206 and the semiconductor active layer The regions in contact with 207 are all located above the gate 202.
  • the common electrode 210 in this embodiment may be composed of indium tin oxide or graphene.
  • the data line, the source, the semiconductor active layer, the drain, and the pixel electrode are on the same layer, so that the thickness of the TFT array substrate is thinned, which simplifies the preparation process compared with the existing layered preparation. .
  • the embodiment of the invention further provides a display device using the above TFT array substrate.
  • An example of the display device is a liquid crystal display device in which a TFT array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • the liquid crystal display device is, for example, a vertical alignment (VA) type or an ADS type liquid crystal display device.
  • Another example of the display device is an organic electroluminescence display device in which a pixel electrode of each pixel unit of the TFT array substrate serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • Still another example of the display device is an electronic paper display device in which the pixel electrode of each pixel unit of the TFT array substrate is used to control the movement of charged particles contained in the ink, thereby being used for displaying an image.
  • the display device of the embodiment of the present invention can be used, for example, for a television, a mobile phone, a tablet, a navigator or the like.
  • the data line, the source, the semiconductor active layer, the drain, and the pixel electrode in the TFT array substrate are located on the same layer, so that the thickness of the TFT array substrate is thinned, resulting in a display device. It is also thinned accordingly and simplifies the preparation process compared to existing layered preparations.

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Abstract

提供一种薄膜晶体管阵列基板及其制造方法和显示装置。该薄膜晶体管阵列基板制造方法包括：在基底基板（201）上通过第一次构图工艺处理得到栅线和栅极（202）；在栅线和栅极（202）上形成栅绝缘层（203）；在栅绝缘层（203）上形成石墨烯层（204），通过第二次构图工艺处理及氢化处理，在栅极（202）的上方得到半导体有源层（207）；再通过第三次构图工艺处理得到位于同一层的数据线、源极（208）、漏极（206）和像素电极（205）；在数据线、源极（208）、半导体有源层（207）、漏极（206）、像素电极（205）之上形成保护层（209）。该薄膜晶体管阵列基板改进了薄膜晶体管阵列基板的结构，厚度变薄，并简化了工艺流程。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种 TFT阵列基板及其制造方法和显示装置。 背景技术
薄膜场晶体管液晶显示器 ( Thin Film Transistor-Liquid Crystal Display, TFT-LCD )是利用施加在液晶层的电场强度的变化， 来改变液晶分子的旋转 程度， 从而控制透光的强弱来显示图像。 一般来讲， 液晶显示面板包括背光 模块组、 偏光片、 上基板（通常是彩膜基板） 、 下基板（通常是阵列基板） 以及在这两块基板组成的液晶盒（cell )中填充的液晶分子层。 阵列基板上形 成有横纵交叉的数据线和栅线， 数据线和栅线围设形成矩阵形式排列的像素 单元。 每个像素单元包括 TFT开关和像素电极。 TFT开关包括栅电极、 源电 极、 漏电极和有源层； 栅电极连接栅线， 源电极连接数据线， 漏电极连接像 素电极， 有源层形成在源、 漏电极与栅电极之间。 基板上还可以形成有公共 电极， 用于和像素电极形成电场， 公共电极与像素电极之间的电场强度变化 控制着液晶分子的旋转的程度。 TFT阵列基板上与栅线平行并处于同一层的 存储底电容线和像素电极之间还可以形成存储电容， 用来维持下一个信号来 临前液晶分子的状态。
高级超维场转换技术（ Advanced Super Dimension Switch, ADS )通过同 一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的 电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子 都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场 转换技术可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋（push Mura )等优点。
在 ADS模式的 TFT阵列基板的制备过程中， 像素电极层、 源极、 漏极 以及有源层的制备通常分层制备， 不仅基板厚度增加， 且工艺流程繁瑣。 发明内容 本发明的实施例提供了一种 TFT阵列基板及其制造方法和显示设备，改 进了 TFT阵列基板结构， 使基板厚度变薄， 并简化了工艺流程。
根据本发明的一方面， 提供了一种薄膜晶体管 （TFT ) 阵列基板制造方 法， 包括：
在基底基板上通过第一次构图工艺处理得到栅线和栅极；
在所述栅线和栅极上形成栅绝缘层；
在所述栅绝缘层上形成石墨烯层， 在所述栅极的上方， 通过第二次构图 工艺处理及氢化处理得到由石墨烯构成的半导体有源层；
在所述石墨烯层上， 通过第三次构图工艺处理得到由石墨烯构成的数据 线、 源极、 漏极和像素电极； 其中， 所述源极与所述半导体有源层相接触， 所述漏极与所述半导体有源层相接触， 定义 TFT沟道， 所述像素电极与所述 漏极相接触；
在所述数据线、 源极、 半导体有源层、 漏极、像素电极之上形成保护层。 在一个示例中，在所述保护层上， 在所述像素电极上方， 形成公共电极。 根据本发明的另一方面， 提供了一种 TFT阵列基板， 包括：
基底基板；
所述基底基板上形成有栅线和栅极；
所述栅线和栅极上形成有栅绝缘层；
在所述栅绝缘层上形成有由石墨烯构成的数据线、源极、半导体有源层、 漏极和像素电极； 其中， 所述源极与所述半导体有源层相接触， 所述漏极与 所述半导体有源层相接触，定义 TFT沟道，所述像素电极与所述漏极相接触； 在所述数据线、 源极、半导体有源层、 漏极和像素电极上形成有保护层。 在一个示例中， 在所述保护层上， 在所述像素电极上方， 形成有公共电 极层。
根据本发明的再一方面，提供了一种显示装置，包括上述 TFT阵列基板。 本发明实施例提供的 TFT阵列基板及其制造方法和显示装置，釆用石墨 烯材料在栅绝缘层上同层制备了 TFT基板的数据线、 源极、 漏极、 有源层和 像素电极层， 相比在不同层制备的方法而言， 可以使 TFT阵列基板的厚度变 薄， 并简化了工艺流程。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图一；
图 2为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图二；
图 3为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图三；
图 4为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图四；
图 5为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图五；
图 6为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图六；
图 7为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图七；
图 8为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图八；
图 9为本发明实施例提供的 TFT阵列基板制造方法过程中的基板结构示 意图九。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的 前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数 据线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为 开关元件的薄膜晶体管和像素电极。 例如， 每个像素的薄膜晶体管的栅极 与相应的栅线电连接或一体形成，源极与相应的数据线电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述主要针对单个或多 个像素单元进行， 但是其他像素单元可以相同地形成。
本发明实施例提供的 TFT阵列基板制造方法， 包括如下步骤。
5101、 在基底基板上沉积金属层， 通过第一次构图工艺处理得到栅线 和栅极。
如图 1所示， 例如可以使用磁控溅射方法， 在基底基板 201上制备一 层厚度例如在 1000A至 7000A的金属薄膜层。该金属薄膜层的材料通常可 以釆用钼、 铝、 铝镍合金、 钼钨合金、 铬、 或铜等金属， 也可以使用上述 几种材料薄膜的叠层结构。 然后， 用掩模版通过曝光、 显影、 刻蚀、 剥离 等第一次构图工艺处理， 在玻璃基板 201的一定区域上形成多条横向的栅 线（图 1中未表示）和与栅线相连的栅极 202。
5102、 在栅线和栅极上形成栅绝缘层。
如图 2 所示， 例如可以利用等离子增强化学汽相沉积法 （Plasma Enhanced Chemical Vapor Deposition, PEC VD )在栅线、 栅极 202上沉积 厚度例如为 1000A至 6000A的栅绝缘层 203 , 栅绝缘层 203的材料通常是 氮化硅， 也可以使用氧化硅和氮氧化硅等绝缘材料。
5103、 在栅绝缘层上形成石墨烯层， 通过第二次构图工艺处理及氢化 处理， 在栅极的上方得到由石墨烯构成的半导体有源层。
首先， 如图 3所示， 例如在栅绝缘层 203上利用 PECVD沉积一层石 墨烯材料， 或者旋涂一层水溶性单层或多层石墨烯材料， 形成石墨烯层 204。
接着， 如图 4所示， 在石墨烯层 204上涂覆一层光刻胶 211。
之后， 经过曝光、 显影后露出沟道区石墨烯 207, 如图 5所示。 例如， 再通过 ¾, 或 ¾和 Ar气的混合气体对沟道区石墨烯 207进行氢化处理， 在栅极 202的上方得到半导体有源层 207。
在这里需要说明的是， 石墨烯具有零禁带特性， 即使在室温下载流子 在石墨烯中的平均自由程和相干长度也可以达到微米级， 同时， 石墨烯还 具有远比硅高的载流子迁移率， 因此它是一种性能优异的半导体材料。 最后， 剥离掉其余的光刻胶， 如图 6所示。
5104、 在石墨烯层上通过第三次构图工艺处理得到由石墨烯构成的数 据线、 源极、 漏极和像素电极； 源极与半导体有源层相接触， 漏极与半导 体有源层相接触， 定义 TFT沟道， 像素电极与漏极相接触。
如图 7所示， 再在石墨烯层 204上涂覆光刻胶， 经过曝光、 显影、 刻 蚀、 剥离之后， 得到由石墨烯构成的数据线（图 7中未表示） 、 源极 208、 漏极 206和像素电极 205。 源极 208与半导体有源层 207相接触， 漏极 206 与半导体有源层 207相接触， 定义 TFT沟道， 像素电极 205与漏极 206相 接触。 在此， 要求半导体有源层 207的宽度小于栅极 202的宽度， 使得定 义 TFT沟道的源极 208与半导体有源层 207相接触的区域， 以及漏极 206 与半导体有源层 207相接触的区域均位于栅极 202的上方。
至此， 本发明实施例中的数据线、 源极、 半导体有源层、 漏极、 像素 电极位于同一层上， 可使得阵列基板的厚度变薄， 且与现有分层制备而言 减少了工艺。
由于石墨烯是一种二维材料， 其特性介于半导体与导体之间。 处于本 征态时， 由于能带交叠， 石墨烯的导电性具有金属特性， 电导率能达到 20000cm2/V.S, 可以作为 TFT的源漏极材料； 当用氢气或氩气， 或者两者 混合气体处理之后， 产生氢化石墨烯， 其相对带隙增加， 可以作为半导体 材料。 且相对于一般的半导体材料而言， 其具有更高的载流子迁移率。
5105、 在数据线、 源极、 半导体有源层、 漏极、 像素电极之上形成保 护层。
如图 8所示， 在数据线、 源极 208、 半导体有源层 207、 漏极 206、 像 素电极 205之上涂覆一层厚度例如在 1000A到 6000A的保护层 209, 其材 料通常是二氧化硅或透明的有机树脂材料等氧化物。
由此， 得到 TFT阵列基板。 上述像素电极受作为开关元件的薄膜晶体 管的控制用于显示。
在一个示例中， TFT阵列基板例如是用于 ADS型液晶显示装置的阵 列基板， 由此在保护层上还继续形成公共电极。
5106、 在保护层上， 在像素电极的上方， 形成公共电极。 如图 9所示， 在保护层 209沉积一层 ITO ( Indium Tin Oxides, 铟锡氧 化物）或石墨烯， 厚度在 100人至 1000人之间。 然后在沉积的 ITO或石墨 烯上涂覆一层光刻胶， 然后进过曝光、 显影、 刻蚀、 剥离等构图工艺得到 位于像素电极 205之上的公共电极 210。
该公共电极 210可包括多个狭缝（未示出） ， 用于和像素电极 205协 作在彼此间施加电压差之后产生水平电场， 从而用于驱动液晶转动。
在另一个示例中， 该 TFT阵列基板例如是用于垂直配向 （VA )型液 晶显示装置的阵列基板。 由此， 阵列基板上的像素电极用于和与阵列基板 相对的对置基板上的公共电极配合产生垂直电场，从而用于驱动液晶转动。
本发明实施例提供的 TFT阵列基板及其制造方法，釆用石墨烯材料在 栅绝缘层上于同一层中制备了 TFT基板的数据线、 源极、 漏极、 有源层和 像素电极层， 相比现有技术的在不同层制备的方法而言， 使 TFT阵列基板 的厚度变薄， 并简化了工艺流程。
本发明实施例提供的 TFT阵列基板， 如图 9所示， 包括： 基底基板 201 ; 在基板 201上形成有栅线（图中未表示）和栅极 202; 在栅线和栅极 202上形成有栅绝缘层 203;在栅绝缘层 203上形成有由石墨烯构成的数据 线（图中未表示） 、 源极 208、 半导体有源层 207、 漏极 206和像素电极 205。 源极 208与半导体有源层 207相接触， 漏极 206与半导体有源层 207 相接触， 定义 TFT沟道， 像素电极 205与漏极 206相接触； 在数据线、 源 极 208、半导体有源层 207、漏极 206和像素电极 205上形成有保护层 209。
在一个示例中， TFT阵列基板例如是用于 ADS型液晶显示装置的阵 列基板， 由此在保护层上还继续形成公共电极。 在保护层 209上， 在像素 电极 205上方，形成有公共电极 210。该公共电极 210可包括多个狭缝（未 示出），用于和像素电极 205协作在彼此间施加电压差之后产生水平电场， 从而用于驱动液晶转动。
在另一个示例中， 该 TFT阵列基板例如是用于垂直配向 （VA )型液 晶显示装置的阵列基板。 由此， 阵列基板上的像素电极用于和与阵列基板 相对的对置基板上的公共电极配合产生垂直电场，从而用于驱动液晶转动。
半导体有源层 207的石墨烯为经过氢化处理后的石墨烯层。 由于石墨 烯是一种二维材料， 其特性介于半导体与导体之间。 当处于本征态时， 由 于能带交叠， 其导电性具有金属特性， 电导率能达到 20000cm2/V.S, 可以 作为 TFT的源漏极材料； 当用氢气或氩气， 或者两者混合气体处理之后， 产生氢化石墨烯， 带隙相对增加， 可以作为半导体材料。 相对于一般的半 导体材料而言， 其具有更高的载流子迁移率。
在本实施例中， 半导体有源层 207的宽度可以小于栅极 202的宽度， 使得定义 TFT沟道的源极 208与半导体有源层 207相接触的区域， 以及漏 极 206与半导体有源层 207相接触的区域均位于栅极 202的上方。
另外， 本实施例中的公共电极 210可以由氧化铟锡或石墨烯构成。 在本实施例中， 数据线、 源极、 半导体有源层、 漏极、 像素电极位于 同一层上， 使得 TFT阵列基板的厚度变薄， 与现有的分层制备相比， 简化 了制备工艺。
本发明实施例还提供了一种显示装置， 使用了上述 TFT阵列基板。 该显示装置的一个示例为液晶显示装置， 其中， TFT 阵列基板与对 置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板 例如为彩膜基板。 TFT阵列基板的每个像素单元的像素电极用于施加电场 对液晶材料的旋转的程度进行控制从而进行显示操作。在一些示例中，该 液晶显示装置还包括为阵列基板提供背光的背光源。该液晶显示装置例如 是比如垂直配向 （VA )型或者比如 ADS型液晶显示装置。
该显示装置的另一个示例为有机电致发光显示装置， 其中， TFT 阵 列基板的每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材 料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置， 其中， TFT 阵列基板 的每个像素单元的像素电极用于控制包含在墨水之中的带电颗粒的移动， 从而用于显示图像。
本发明实施例的显示装置例如可以用于电视、 手机、 平板电脑、 导航 仪等。
本实施例中的显示装置， 由于其使用的 TFT阵列基板中的数据线、 源极、 半导体有源层、 漏极、 像素电极位于同一层上， 使得 TFT阵列基板 的厚度变薄， 导致显示装置也相应变薄， 且与现有的分层制备相比， 简化 了制备工艺。 以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种薄膜晶体管 （TFT ) 阵列基板制造方法， 包括：
在基底基板上形成金属层， 通过第一次构图工艺处理得到栅线和栅 极；
在所述栅线和栅极上形成栅绝缘层；
在所述栅绝缘层上形成石墨烯层，通过第二次构图工艺处理及氢化处 理， 在所述栅极的上方得到由石墨烯构成的半导体有源层；
在所述石墨烯层上通过第三次构图工艺处理得到由石墨烯构成的数 据线、 源极、 漏极和像素电极； 其中， 所述源极与所述半导体有源层相接 触， 所述漏极与所述半导体有源层相接触， 定义 TFT沟道， 所述像素电 极与所述漏极相接触；
在所述数据线、 源极、 半导体有源层、 漏极、 像素电极之上形成保护 层。
2、 根据权利要求 1所述的 TFT阵列基板制造方法， 其中， 在所述保 护层上， 在所述像素电极上方， 形成公共电极。
3、 根据权利要求 1所述的 TFT阵列基板制造方法， 其中， 在所述栅 绝缘层上形成石墨烯层， 通过第二次构图工艺处理及氢化处理， 在所述 栅极的上方得到由石墨烯构成的半导体有源层包括：
在所述栅绝缘层上，利用等离子体增强化学气相沉积法沉积一层石墨 烯材料， 或者旋涂一层水溶性单层或多层石墨烯材料， 形成石墨烯层； 在所述石墨烯层上涂覆光刻胶，经过曝光、显影后露出沟道区的石墨 对所述沟道区的石墨烯进行氢化处理；
剥离掉剩余的光刻胶，在所述栅极的上方得到由石墨烯构成的半导体 有源层。
4、 根据权利要求 2所述的 TFT阵列基板制造方法， 其中， 所述公共 电极由氧化铟锡或石墨烯构成。
5、 根据权利要求 1所述的 TFT阵列基板制造方法， 其中， 所述半导体有源层的宽度小于所述栅极的宽度， 使得定义 TFT沟道 的所述源极与所述半导体有源层相接触的区域， 以及所述漏极与所述半导 体有源层相接触的区域均位于所述栅极的上方。
6、 一种薄膜晶体管 （TFT ) 阵列基板， 包括：
基底基板；
在所述基底基板上形成有栅线和栅极；
在所述栅线和栅极上形成有栅绝缘层；
在所述栅绝缘层上形成有由石墨烯构成的数据线、源极、半导体有源 层、 漏极和像素电极； 其中， 所述源极与所述半导体有源层相接触， 所述 漏极与所述半导体有源层相接触， 定义 TFT沟道， 所述像素电极与所述 漏极相接触；
在所述数据线、 源极、 半导体有源层、 漏极和像素电极上形成有保护 层。
7、 根据权利要求 6所述的 TFT阵列基板， 其中， 在所述保护层上， 在所述像素电极上方， 形成有公共电极。
8、 根据权利要求 6所述的 TFT阵列基板， 其中， 所述半导体有源层 的石墨烯为经过氢化处理后的石墨烯层。
9、 根据权利要求 7所述的 TFT阵列基板， 其中， 所述公共电极层 由氧化铟锡或石墨烯构成。
10、 一种显示装置， 包括权利要求 6所述的 TFT阵列基板。
11、 根据权利要求 10所述的显示装置， 其中， 所述显示装置是液晶 显示装置、 有机发光二极管显示装置或电子纸显示装置。
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