WO2022222404A1 - 阵列基板及其制备方法、显示面板、显示装置 - Google Patents

阵列基板及其制备方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2022222404A1
WO2022222404A1 PCT/CN2021/127111 CN2021127111W WO2022222404A1 WO 2022222404 A1 WO2022222404 A1 WO 2022222404A1 CN 2021127111 W CN2021127111 W CN 2021127111W WO 2022222404 A1 WO2022222404 A1 WO 2022222404A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
metal oxide
thin film
pattern
array substrate
Prior art date
Application number
PCT/CN2021/127111
Other languages
English (en)
French (fr)
Inventor
张震
李付强
张振宇
王利忠
邸云萍
宁策
方正
张晨阳
王亚薇
王玮
王洪润
童彬彬
姚念琦
韩佳慧
徐成福
梁蓬霞
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2022222404A1 publication Critical patent/WO2022222404A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof, a display panel and a display device.
  • the application provides an array substrate and a preparation method thereof, a display panel, and a display device, and the technical solutions are as follows:
  • an array substrate comprising:
  • the base substrate has a display area
  • each of the oxide thin film transistors including a metal oxide pattern having a first portion, a channel portion, and a second portion connected in sequence , the first part is used to receive a data signal;
  • the color filter layer located in the display area, the color filter layer is located between the metal oxide pattern and the base substrate, and the color filter layer includes a one-to-one relationship with the plurality of oxide thin film transistors A plurality of corresponding color resist blocks of different colors, the orthographic projection of each color resist block on the base substrate corresponds to the second portion of the oxide thin film transistor on the base substrate The orthographic projections of , at least partially overlap.
  • both the conductivity of the first portion and the conductivity of the second portion are greater than the conductivity of the channel portion.
  • the array substrate further includes: a plurality of data lines and a first insulating layer;
  • the plurality of data lines are located between the metal oxide patterns and the base substrate, the first insulating layer is located between the plurality of data lines and the metal oxide patterns, and the first The insulating layer has a plurality of first vias;
  • each of the data lines is electrically connected to the first portion of at least one of the oxide thin film transistors through at least one of the first via holes.
  • the first insulating layer is a first passivation layer located between the plurality of data lines and the color filter layer;
  • the distance between the surface of the target part of the second part close to the base substrate and the base substrate is greater than the distance between the surface of the first part close to the base substrate and the base substrate distance, and is greater than the distance between the side of the channel portion close to the base substrate and the base substrate, and the target portion is the orthographic projection of the second portion on the base substrate The portion overlapping with the orthographic projection of the color resist block on the base substrate.
  • the first insulating layer includes: a first passivation layer located between the plurality of data lines and the color filter layer, and a first passivation layer located between the color filter layer and the metal oxide pattern. a planarization layer, and a second passivation layer on the planarization layer and the metal oxide pattern.
  • the array substrate further includes: a second insulating layer located on a side of the second portion away from the base substrate, and a second insulating layer located on a side of the second insulating layer away from the base substrate common electrode;
  • the orthographic projection of the common electrode on the base substrate at least partially overlaps with the orthographic projection of the second portion on the base substrate, and the second portion is used as a pixel electrode to interact with the
  • the common electrode drives the liquid crystal to deflect together.
  • the array substrate further comprises: a third insulating layer on a side of the metal oxide pattern away from the base substrate and stacked in sequence along a direction away from the base substrate, a pixel electrode, a fourth insulating layer an insulating layer and a common electrode, the orthographic projection of the pixel electrode on the base substrate at least partially overlaps with the orthographic projection of the common electrode on the base substrate;
  • the third insulating layer has a plurality of second via holes, each of the second via holes is used for exposing at least part of the second part of one of the oxide thin film transistors, and the pixel electrode passes through all the second via holes.
  • the second via hole is electrically connected to the second portion.
  • each of the oxide thin film transistors further includes: a first gate pattern located in the display area; the array substrate further includes: a fifth insulating layer; the first gate pattern is located in the metal between the oxide pattern and the base substrate, the fifth insulating layer is located between the first gate pattern and the metal oxide pattern;
  • the orthographic projection of the first gate pattern on the base substrate covers an orthographic projection of the channel portion of the metal oxide pattern on the base substrate. Orthographic projection.
  • the array substrate further includes: a plurality of scan lines extending along the pixel row direction;
  • the plurality of scan lines are located on a side of the first gate pattern close to the base substrate, and each of the scan lines is at least partially associated with the first gate pattern of at least one of the oxide thin film transistors contact, the length of the orthographic projection of the first gate pattern on the base substrate along the pixel column direction is greater than the length of the orthographic projection of the scan line on the base substrate along the pixel column direction.
  • the base substrate further has a peripheral area located on one side of the display area;
  • the array substrate further includes: a drive circuit located in the peripheral area;
  • the drive circuit includes at least one polysilicon thin film transistor; each Each of the polysilicon thin film transistors includes: a second gate pattern and a source and drain pattern;
  • the second gate pattern and the plurality of scan lines are located on the same layer, and the source and drain patterns are located on the same layer as the multiple data lines of the array substrate.
  • each of the polysilicon thin film transistors further includes: an active pattern;
  • the array substrate further includes: a sixth insulating layer; the active pattern is located between the second gate pattern and the base substrate in between, the sixth insulating layer is located between the active pattern and the second gate pattern;
  • the source-drain pattern is electrically connected with the active pattern.
  • a method for preparing an array substrate comprising:
  • a base substrate is provided, the base substrate has a display area
  • each of the oxide thin film transistors includes a metal oxide pattern, the metal oxide pattern has a first part, a channel part, and a second part connected in sequence, and the first part is used for receiving a data signal;
  • the The color filter layer is located between the metal oxide pattern and the base substrate, and the color filter layer includes a plurality of color resist blocks of different colors corresponding to the plurality of oxide thin film transistors one-to-one.
  • the orthographic projection of the color blocking block on the base substrate at least partially overlaps with the orthographic projection of the corresponding second portion of the oxide thin film transistor on the base substrate.
  • forming the metal oxide pattern of the oxide thin film transistor includes:
  • a photoresist is coated on a first area of the metal oxide structure on the side away from the base substrate, and the side of the metal oxide structure away from the base substrate further includes a second area and a third area , the second area and the third area are located on both sides of the first area;
  • the photoresist is removed to obtain a channel portion of the metal oxide pattern.
  • a display panel in yet another aspect, includes: a cover plate, a liquid crystal layer, and the array substrate according to the above aspect;
  • the liquid crystal layer is located between the cover plate and the array substrate.
  • a display device comprising: a power supply assembly and the display panel according to the above aspect;
  • the power supply assembly is used for supplying power to the display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a top view of a base substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the positions of a color filter layer and a light source provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of the positions of a color filter layer and a light source in the related art
  • FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 8 is a flowchart of a method for preparing an array substrate provided by an embodiment of the present application.
  • FIG. 9 is a flowchart of another method for fabricating an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a cross-sectional view of forming a second gate pattern and a scan line provided by an embodiment of the present application
  • FIG. 11 is a top view of a scan line provided by an embodiment of the present application.
  • FIG. 12 is a top view of a first gate pattern formed according to an embodiment of the present application.
  • FIG. 13 is a cross-sectional view of forming a source-drain pattern and a data line according to an embodiment of the present application
  • FIG. 14 is a top view of a data line formed according to an embodiment of the present application.
  • FIG. 15 is a top view of a color blocking block formed according to an embodiment of the present application.
  • 16 is a cross-sectional view of forming a first via hole provided by an embodiment of the present application.
  • FIG. 17 is a top view of forming a first via hole provided by an embodiment of the present application.
  • FIG. 18 is a top view of a metal oxide structure formed according to an embodiment of the present application.
  • 19 is a top view of a photoresist coating on the first region provided by an embodiment of the present application.
  • 20 is a cross-sectional view of a photoresist coating on the first region provided by an embodiment of the present application
  • 21 is a cross-sectional view of conducting conductorization of the second region and the third region provided by an embodiment of the present application;
  • 22 is a schematic diagram of a high-resistance region provided by an embodiment of the present application.
  • FIG. 23 is a top view of a metal oxide pattern formed according to an embodiment of the present application.
  • FIG. 24 is a top view of forming a common electrode provided by an embodiment of the present application.
  • FIG. 25 is a flowchart of another method for fabricating an array substrate provided by an embodiment of the present application.
  • FIG. 26 is a top view of another metal oxide structure formed according to an embodiment of the present application.
  • 27 is another top view of coating photoresist on the first region provided by the embodiment of the present application.
  • FIG. 28 is a top view of another metal oxide pattern formed according to an embodiment of the present application.
  • FIG. 29 is a cross-sectional view of forming a second via hole provided by an embodiment of the present application.
  • FIG. 30 is a top view of forming a second via hole provided by an embodiment of the present application.
  • FIG. 31 is a top view of forming a pixel electrode according to an embodiment of the present application.
  • Fig. 32 is another top view of forming a common electrode provided by an embodiment of the present application.
  • FIG. 33 is a flowchart of still another method for fabricating an array substrate provided by an embodiment of the present application.
  • 34 is another cross-sectional view of forming a first via hole provided by an embodiment of the present application.
  • FIG. 35 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 36 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • a display panel includes a driving circuit and a plurality of sub-pixels of different colors, and each sub-pixel can emit light under the driving of the driving circuit, so as to realize the color display of the display panel.
  • VR virtual reality
  • the thin film transistor (TFT) in the sub-pixel of the display area of the array substrate is usually a low temperature poly-silicon (LTPS) thin film transistor.
  • LTPS low temperature poly-silicon
  • the magnitude of the leakage current of the polysilicon thin film transistor (10 -11 ) is relatively high, that is, the leakage current is relatively large, and the voltage of the sub-pixel cannot be kept stable during the display process of the sub-pixel, resulting in a high PPI display panel (for example, a display panel above 1000 PPI). display panel) cannot be displayed properly.
  • Words like “include” or “include” mean that the elements or items appearing before “including” or “including” cover the elements or items listed after “including” or “including” and their equivalents, and do not exclude other component or object.
  • Words like “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate 10 may include: a base substrate 101 , a plurality of oxide thin film transistors 102 spaced apart, and a color filter layer 103 .
  • FIG. 2 is a top view of a base substrate provided by an embodiment of the present application.
  • the base substrate 101 may have a display area 101a.
  • the plurality of oxide thin film transistors 102 and the color filter layer 103 included in the array substrate 10 may all be located in the display area 101 a of the base substrate 101 .
  • the display area 101a may also be referred to as an active display area (AA) area.
  • the voltage stability of the display area 101a during image display can be improved to ensure that the display panel can display normally.
  • each oxide thin film transistor 102 includes a metal oxide pattern 1021 .
  • the metal oxide pattern 1021 has a first part 10211, a channel part 10212 and a second part 10213 connected in sequence, and the first part 10211 can be used for receiving a data signal.
  • the color filter layer 103 is located between the metal oxide pattern 1021 and the base substrate 101 . That is, the metal oxide pattern 1021 is located on the side of the color filter layer 103 away from the base substrate 101 .
  • the color filter layer 103 may include a plurality of color resist blocks 1031 of different colors corresponding to the plurality of oxide thin film transistors 102 one-to-one.
  • FIG. 1 shows three oxide thin film transistors 102 and three color resist blocks 1031 , and different filling patterns indicate that the colors of the color resist blocks 1031 are different.
  • each color resist block 1031 on the base substrate 101 at least partially overlaps with the orthographic projection of the second portion 10213 of the corresponding oxide thin film transistor 102 on the base substrate 101 . Furthermore, since the color resist blocks 1031 and the second portion 10213 of the metal oxide pattern 1021 at least partially overlap, the overall space occupied by the metal oxide patterns 1021 and the color resist blocks 1031 on the base substrate 101 can be reduced, facilitating high PPI Implementation of the display panel.
  • the colors of any two adjacent color resist blocks 1031 among the plurality of color resist blocks 1031 included in the color filter layer 103 may be different.
  • the color filter layer 103 since the color filter layer 103 is disposed on one side of the array substrate 10 , that is, the array substrate 10 may be a (color film on array, COA) array substrate, it is located far from the base substrate 101 The distance between the light source on one side of the color filter layer 103 and the color filter layer 103 can be relatively close, which can prevent the light in the area of each color blocking block 1031 in the color filter layer 103 from being emitted from the adjacent color blocking blocks 1031, thereby preventing The display panel appears cross-color phenomenon to ensure the display effect of the display panel.
  • the embodiments of the present application provide an array substrate, the array substrate includes a color filter layer, so the distance between the light source and the color filter layer on the side of the base substrate away from the color filter layer can be relatively close , the light in the area where each color blocking block is located can be prevented from being emitted from the adjacent color blocking blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • the material of the metal oxide pattern 1021 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • Both the conductivity of the first portion 10211 and the conductivity of the second portion 10213 may be greater than the conductivity of the channel portion 10212 .
  • the first portion 10211 and the second portion 10213 may be conductive, and the channel portion 10212 may not be conductive.
  • the color filter layer 103 may include multiple red color resist blocks 1031 , multiple green color resist blocks 1031 and multiple blue color resist blocks 1031 .
  • the red color blocking block 1031 can be used to transmit red light
  • the green color blocking block 1031 can be used to transmit green light
  • the blue color blocking block 1031 can be used to transmit blue light.
  • the thickness of the plurality of color blocking blocks 1031 in the color filter layer 103 ranges from 1 micrometer to 2 micrometers.
  • the color filter layer 103 is arranged on one side of the array substrate 10 in this embodiment of the present application, and the distance between the color filter layer 103 and the light source is greatly reduced. The light in the area where the green color blocking block 1031 is located will not be emitted from the adjacent red color blocking block or blue color blocking block, thereby reducing the cross-color phenomenon.
  • FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • the array substrate 10 may further include: a plurality of data lines 104 and a first insulating layer 105 .
  • the plurality of data lines 104 may be located between the metal oxide patterns 1021 and the base substrate 101, and the first insulating layer 105 may be located between the plurality of data lines 104 and the metal oxide patterns 1021, and the first insulating layer 105 is used for
  • the metal oxide pattern 1021 and the plurality of data lines 104 are insulated from each other.
  • the first insulating layer 105 may have a plurality of first via holes, and each of the first via holes may be used to expose at least part of one data line 104 .
  • the orthographic projection of the first portion 10211 of each metal oxide pattern 1021 on the base substrate 101 at least partially overlaps the orthographic projection of one first via hole on the base substrate 101 .
  • at least a portion of the first portion 10211 of each metal oxide pattern 1021 may be located in a first via hole and electrically connected to a data line 104 exposed by the first via hole.
  • each data line 104 can be electrically connected to the first part 10211 of the at least one oxide thin film transistor 102 through at least one first via hole, so that the data line 104 is the first part of the at least one oxide thin film transistor 102 10211 provides data signals.
  • the plurality of data lines 104 may all extend along the pixel column direction
  • the first insulating layer 105 may include a plurality of target first via holes arranged along the pixel column direction
  • the array substrate 10 may include a plurality of first via holes arranged along the pixel column direction
  • the plurality of first target oxide thin film transistors arranged along the pixel column direction correspond to the plurality of target first via holes arranged along the pixel column direction in one-to-one correspondence.
  • Each data line 104 is electrically connected to the first portion 10211 of the first target oxide thin film transistor located in a column through a corresponding target first via hole.
  • the first insulating layer 105 is a first passivation layer (passivation, PVX) located between the plurality of data lines 104 and the color filter layer 103 . Since the thickness of the color blocking block 1031 in the color filter layer 103 is relatively thick, and the first insulating layer 105 does not include a planarization layer (PLN) located on the side of the color filter layer 103 away from the base substrate 101, the metal oxide The portion of the pattern 1021 that overlaps with the color blocking blocks 1031 may have a larger distance from the base substrate 101, and the portion of the metal oxide pattern 1021 that does not overlap with the color blocking blocks 1031 in the color filter layer 103 may be separated from the substrate 101.
  • passivation PVX
  • the distance between the base substrates 101 is small.
  • the portion of the metal oxide pattern 1021 that overlaps with the color resist blocks 1031 refers to the portion where the orthographic projection of the metal oxide pattern 1021 on the base substrate 101 and the orthographic projection of the color resist blocks 1031 on the base substrate 101 overlap.
  • the portion of the metal oxide pattern 1021 that does not overlap with the color resist blocks 1031 refers to the portion where the orthographic projection of the metal oxide pattern 1021 on the base substrate 101 and the orthographic projection of the color resist blocks 1031 on the base substrate 101 do not overlap. .
  • the distance h1 between the target portion of the second portion 10213 of the metal oxide pattern 1021 close to the base substrate 101 and the base substrate 101 is greater than the distance h1 between the side of the first portion 10211 close to the base substrate 101 and the base substrate.
  • the distance h2 between 101 is greater than the distance h3 between the side of the channel portion 10212 close to the base substrate 101 and the base substrate 101 .
  • the target portion is the portion overlapping the orthographic projection of the color resist block 1031 on the base substrate 101 in the orthographic projection of the second portion 10213 on the base substrate 101 .
  • the target portion of the second portion 10213 of the metal oxide pattern 1021 is close to the side of the base substrate 101 , and is different from the side of the first portion 10211 close to the base substrate 101 and the side of the channel portion 10212 close to the base substrate 101 . coplanar.
  • the first insulating layer 105 may include: a first passivation layer 1051 located between the plurality of data lines 104 and the color filter layer 103 , and located between the color filter layers 103 and the color filter layer 103 .
  • the thickness of the color blocking blocks 1031 in the color filter layer 103 is relatively thick, since the first insulating layer 105 includes the flat layer 1052 located between the metal oxide pattern 1021 and the color filter layer 103 , the flat layer 1052 can be kept away from the color filter layer 103 .
  • the side of the film layer on one side of the base substrate 101 close to the base substrate 101 is flat.
  • the surface of the flat layer 1052 away from the base substrate 101 is a plane surface and is substantially parallel to the bearing surface of the base substrate 101 . That is, the area around the color resist blocks 1031 in the array substrate 10 can be flattened by arranging the planarization layer 1052 , that is, the area with the color resist blocks 1031 and the area without the color resist blocks 1031 can be planarized.
  • the side of the first insulating layer 105 located on the flat layer 1052 away from the base substrate 101 is the second passivation layer 1053 , the side of the second passivation layer 1053 close to the base substrate 101 is flat.
  • the second passivation layer 1053 covers the entire layer, the flatness of the array substrate 10 will not be affected, that is, the metal oxide pattern 1021 located on the side of the second passivation layer 1053 away from the base substrate 101 is close to the substrate One surface of the base substrate 101 is also flat.
  • the distance between the side of the second portion 10213 of the metal oxide pattern 1021 close to the base substrate 101 and the base substrate 101, the distance between the side of the first portion 10211 of the metal oxide pattern 1021 close to the base substrate 101 and the base substrate 101 The distance between the substrates 101 and the distance between the side of the channel portion 10212 of the metal oxide pattern 1021 close to the base substrate 101 and the base substrate 101 are all equal.
  • the second portion 10213 of the metal oxide pattern 1021 is close to the side of the base substrate 101
  • the first portion 10211 of the metal oxide pattern 1021 is close to the side of the base substrate 101
  • the channel portion 10212 of the metal oxide pattern 1021 One side close to the base substrate 101 is coplanar.
  • the pixel electrode in the array substrate (for example, the second part 10213 of the metal oxide pattern 1021 in FIG. 5 and FIG. 6 , or the pixel electrode 107 in FIG. 7 ) is located far from the color filter layer 103
  • the array substrate 10 further includes: a second insulating layer 106 located on a side of the second portion 10213 away from the base substrate 101 , and a second insulating layer 106 located away from the substrate
  • the common electrode 107 on one side of the substrate 101 .
  • the orthographic projection of the common electrode 107 on the base substrate 101 at least partially overlaps with the orthographic projection of the second portion 10213 on the base substrate 101 .
  • the second portion 10213 can be used as a pixel electrode to form an electric field with the common electrode 107 to jointly drive the liquid crystal to deflect.
  • the structure of the array substrate 10 can be simplified, and the manufacturing cost of preparing the array substrate 10 can be reduced.
  • the first insulating layer 105 in the array substrate 10 does not include a flat layer. Therefore, in order to ensure the flatness of the array substrate 10 , the second insulating layer 106 may include:
  • the pattern 1021 has a second passivation layer 1061 on a side away from the base substrate 101 , and a flat layer 1062 at a side away from the base substrate 101 of the second passivation layer 1061 .
  • the surface of the flat layer 1062 away from the base substrate 101 is flat and substantially parallel to the bearing surface of the base substrate 101 . That is, the area around the color resist blocks 1031 in the array substrate 10 can be flattened by arranging the planarization layer 1062 , that is, the area with the color resist blocks 1031 and the area without the color resist blocks 1031 can be planarized.
  • the first insulating layer 105 in the array substrate 10 includes a flat layer 1052 , so the flatness of the array substrate 10 is already good, and the second insulating layer 106 can be located in a metal oxide pattern.
  • 1021 is the third passivation layer on the side away from the base substrate 101 .
  • the second insulating layer 106 of the array substrate 10 shown in FIG. 6 may include, in addition to the third passivation layer located on the side of the metal oxide pattern 1021 away from the base substrate 101 , may also include a third passivation layer located on the side of the metal oxide pattern 1021 away from the base substrate 101 .
  • the common electrode 107 may be located on the side of the other flat layer away from the base substrate 101 . That is, the array substrate 10 in this solution may include two flat layers.
  • the array substrate 10 may further include: a third insulating layer 108 that is located on a side of the metal oxide pattern 1021 away from the base substrate 101 and sequentially stacked along a direction away from the base substrate 101 , the pixel electrode 109 , the fourth insulating layer 110 and the common electrode 107 .
  • the orthographic projection of the pixel electrode 109 on the base substrate 101 may at least partially overlap with the orthographic projection of the common electrode 107 on the base substrate 101 .
  • the pixel electrode 109 and the common electrode 107 can form an electric field to jointly drive the liquid crystal to deflect.
  • the third insulating layer 108 may have a plurality of second via holes, and each of the second via holes may be used to expose at least part of the second portion 10213 of one oxide thin film transistor 102 .
  • the pixel electrode 109 may be electrically connected to the second portion 10213 through the second via hole, so that the second portion 10213 provides a driving signal for the pixel electrode 109 .
  • each oxide thin film transistor 102 in the plurality of oxide thin film transistors 102 in the embodiment of the present application may correspond to one pixel electrode 109 .
  • the pixel electrode 109 is electrically connected to the corresponding second portion 10213 of the oxide thin film transistor 102 through the second via hole.
  • the first insulating layer 105 in the array substrate 10 includes a first passivation layer and does not include a flat layer. Therefore, in order to ensure the flatness of the array substrate 10 , the fourth insulating layer 110 may include: a second passivation layer 1101 located on the side of the pixel electrode 109 away from the base substrate 101 , and a second passivation layer 1101 located away from the second passivation layer 1101 The flat layer 1102 on one side of the base substrate 101 .
  • the surface of the flat layer 1102 away from the base substrate 101 is flat and substantially parallel to the bearing surface of the base substrate 101 . That is, by disposing the flattening layer 1102 , the area with the color resist blocks 1031 and the area without the color resist blocks 1031 in the array substrate 10 are planarized.
  • each oxide thin film transistor 102 may further include: a first gate pattern 1022 located in the display area 101a.
  • the array substrate 10 may further include: a fifth insulating layer 111 .
  • the first gate pattern 1022 may be located between the metal oxide pattern 1021 and the base substrate 101
  • the fifth insulating layer 111 may be located between the first gate pattern 1022 and the metal oxide pattern 1021 .
  • the orthographic projection of the first gate pattern 1022 on the base substrate 101 may cover the orthographic projection of the channel portion 10212 in the metal oxide pattern 1021 on the base substrate 101 . That is, the orthographic projection of the channel portion 10212 on the base substrate 101 is located within the orthographic projection of the first gate pattern 1022 on the base substrate 101 .
  • the material of the first gate pattern 1022 may be indium tin oxide (Indium tin oxide, ITO).
  • the array substrate 10 may further include: a plurality of scan lines 112 .
  • the plurality of scan lines 112 extend along the pixel row direction.
  • the plurality of scan lines 112 are located on a side of the first gate pattern 1022 close to the base substrate 101 , and each scan line 112 is in contact with at least part of the first gate pattern 1022 of at least one oxide thin film transistor 102 .
  • Each scan line 112 may be used to provide a scan signal for the oxide thin film transistor 102 to which the contacted first gate pattern 1022 belongs.
  • the pixel column direction is perpendicular to the pixel row direction.
  • the array substrate 10 may include a plurality of second target oxide thin film transistors arranged along the pixel row direction, each scan line 112 and the first gate pattern 1022 located in the plurality of second target oxide thin film transistors in one row touch.
  • the length of the orthographic projection of the first gate pattern 1022 on the base substrate 101 along the pixel column direction is greater than the length of the orthographic projection of the scan lines 112 on the base substrate 101 along the pixel column direction. So that the orthographic projection of the first gate pattern 1022 on the base substrate 101 covers the orthographic projection of the channel portion 10212 in the metal oxide pattern 1021 on the base substrate 101 .
  • the scan line 112 can be made of an opaque material.
  • the scan line can also be used as a light shielding layer of the oxide thin film transistor to ensure backlighting. Under the influence of , the characteristics of the oxide thin film transistor 102 are normal.
  • the base substrate 101 may also have a peripheral region 101b located on one side of the display region 101a.
  • the peripheral area 101b shown in FIG. 2 is located on the left side of the display area 101a.
  • the peripheral area 101b may also be located on the right side of the display area 101a, which is not limited in this embodiment of the present application.
  • the display area 101a may be provided with a plurality of sub-pixels, and each sub-pixel includes: a light-emitting unit and a pixel circuit.
  • the oxide thin film transistor 102 located in the display area 101a in the array substrate 10 can be used as a transistor in a pixel circuit of a sub-pixel.
  • the array substrate 10 may include: a driving circuit 113 .
  • the driving circuit may be located in the peripheral region 101b, and may be connected to a plurality of sub-pixels to provide driving signals for the plurality of sub-pixels.
  • the driving circuit may be connected to the oxide thin film transistor 102 in the pixel circuit of the sub-pixel, and the driving circuit may be a gate driver on array (GOA).
  • GOA gate driver on array
  • the driving circuit 113 located in the peripheral area 101b may be connected to a plurality of scan lines 112, and the multiple scan lines 112 may be connected to the oxide thin film transistors 102 located in the display area 101a.
  • the driving circuit 113 can provide scan signals to the oxide thin film transistor 102 through the plurality of scan lines 112 .
  • the driving circuit 113 may include at least one polysilicon thin film transistor 1131 .
  • a polysilicon thin film transistor 1131 is shown in each of FIGS. 5 to 7 .
  • the transistor in the driving circuit 113 is designed as the polysilicon thin film transistor 1131, which can ensure the driving ability of the driving circuit 113 to the display area 101a.
  • the driving circuit 113 located in the peripheral region 101b may further include an oxide thin film transistor 102 in addition to at least one polysilicon thin film transistor.
  • the driving circuit located in the peripheral region 101b may not include polysilicon thin film transistors, but only include oxide thin film transistors 102 .
  • the embodiments of the present application do not limit the types of transistors included in the driving circuit.
  • each polysilicon thin film transistor 1131 may include: a second gate pattern 11311 and a source and drain pattern 11312 .
  • the second gate pattern 11311 may be located on the same layer as the plurality of scan lines 112 .
  • the second gate pattern 11311 and the plurality of scan lines 112 can be prepared based on the same material and using the same patterning process.
  • the source and drain patterns 11312 may be located on the same layer as the plurality of data lines 104.
  • the source-drain pattern 11312 and the plurality of data lines 104 can be prepared based on the same material and using the same patterning process.
  • each polysilicon thin film transistor may further include: an active pattern 11313 .
  • the array substrate 10 may further include: a sixth insulating layer 114 .
  • the active pattern 11313 may be located between the second gate pattern 11311 and the base substrate 101
  • the sixth insulating layer 114 may be located between the active pattern 11313 and the second gate pattern 11311 .
  • the source-drain pattern 11312 may be electrically connected to the active pattern 11313 .
  • the source-drain pattern 11312 may include a source (source, S) a1 and a drain (drain, D) a2 arranged at intervals.
  • the source-drain pattern 11312 is electrically connected to the active pattern 11313 may refer to: the source a1 is electrically connected to the active pattern 11313 , and the drain a2 is electrically connected to the active pattern 11313 .
  • the array substrate 10 may further include: a buffer layer (buffer) 115 .
  • the buffer layer 115 may be located between the base substrate 101 and the oxide thin film transistor 102 , and one side of the buffer layer 115 may be in contact with one side of the base substrate 101 .
  • the embodiments of the present application provide an array substrate, the array substrate includes a color filter layer, so the distance between the light source and the color filter layer on the side of the base substrate away from the color filter layer can be relatively close , the light in the area where each color blocking block is located can be prevented from being emitted from the adjacent color blocking blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • FIG. 8 is a flowchart of a method for fabricating an array substrate provided by an embodiment of the present application. As can be seen with reference to Figure 8, the method may include:
  • Step 201 providing a base substrate.
  • the material of the base substrate 101 can be glass or polyimide. Referring to FIG. 2, the base substrate 101 may have a display area 101a.
  • Step 202 forming a plurality of spaced oxide thin film transistors and a color filter layer in the display area.
  • each oxide thin film transistor 102 may include a metal oxide pattern 1021 .
  • the metal oxide pattern 1021 has a first portion 10211, a channel portion 10212 and a second portion 10213 connected in sequence. The first part 10211 is used to receive signals.
  • the color filter layer 103 is located between the metal oxide pattern 1021 and the base substrate 101 .
  • the color filter layer 103 includes a plurality of color resist blocks 1031 of different colors corresponding to the plurality of oxide thin film transistors 102 one-to-one.
  • the orthographic projection of each color resist block 1031 on the base substrate 101 at least partially overlaps the orthographic projection of the second portion 10213 of the corresponding oxide thin film transistor 102 on the base substrate 101 .
  • the color resist block 1031 and the second portion 10213 of the metal oxide pattern 1021 at least partially overlap, the overall space occupied by the metal oxide pattern 1021 and the color resist block 1031 on the base substrate 101 can be reduced, which is convenient for a high PPI display panel realization.
  • colors of two adjacent color resist blocks 1031 among the multiple color resist blocks 1031 included in the color filter layer 103 may be different.
  • the distance between the light source located on the side of the base substrate 101 away from the color filter layer 103 and the color filter layer 103 can be relatively close, which can avoid In the color filter layer 103 , the light in the area where each color resist block 1031 is located is emitted from the adjacent color resist blocks 1031 , so as to avoid the phenomenon of cross color on the display panel and ensure the display effect of the display panel.
  • the embodiments of the present application provide a method for preparing an array substrate.
  • the array substrate prepared by the method includes a color filter layer, so the light source and the color filter layer are located on the side of the base substrate away from the color filter layer. The distance between them is relatively short, so that the light in the area where each color resist block is located can be prevented from being emitted from the adjacent color resist blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • FIG. 9 is a flowchart of another method for fabricating an array substrate provided by an embodiment of the present application. This method can be used to prepare the array substrate provided in the above embodiments, for example, the preparation of the array substrate shown in FIG. 5 is taken as an example. Referring to Figure 9, the method may include:
  • Step 301 providing a base substrate.
  • the material of the base substrate 101 can be glass or polyimide.
  • the base substrate 101 may have a display area 101a and a peripheral area 101b on one side of the display area 101a.
  • the peripheral area 101b shown in FIG. 2 is located on the left side of the display area 101a.
  • the peripheral area 101b may also be located on the right side of the display area 101a, which is not limited in this embodiment of the present application.
  • Step 302 forming a buffer layer on one side of the base substrate.
  • a buffer layer 115 may be formed on one side of the base substrate 101 .
  • the function of the buffer layer 115 is to reduce the impact force of the base substrate 101 on other films to be formed subsequently, so as to facilitate the formation of other films subsequently.
  • Step 303 forming a plurality of active patterns of polysilicon thin film transistors on the side of the buffer layer away from the base substrate.
  • an active thin film may be formed on the side of the buffer layer away from the base substrate 101 , and then the active thin film may be crystallized. After that, a patterned mask is set on the side of the crystallized active thin film away from the base substrate 101, and the crystallized active thin film is patterned to obtain a plurality of polysilicon thin film transistors. Active pattern 11313.
  • the patterning process may include photoresist coating, exposure, development, etching, and photoresist removal.
  • the material of the active thin film may be amorphous silicon (a silicon), and the material of the active thin film after the crystallization process may be low temperature polysilicon (low temperature polysilicon, LTPS).
  • low temperature polysilicon low temperature polysilicon, LTPS
  • the low-temperature polysilicon may also be referred to as p-silicon.
  • the plurality of polysilicon thin film transistors may be used as transistors in the driving circuit, that is, the driving circuit may include a plurality of polysilicon thin film transistors, and the plurality of polysilicon thin film transistors may be located in the peripheral region 101b.
  • the driving circuit located in the peripheral region 101b may include the oxide thin film transistor 102 in addition to the polysilicon thin film transistor.
  • the driving circuit located in the peripheral region 101b may only include the oxide thin film transistor 102, which is not limited in this embodiment of the present application.
  • the method for fabricating the array substrate is described by taking the transistors in the driving circuit as polysilicon thin film transistors and the transistors in the display area 101a as oxide thin film transistors 102 as examples.
  • Step 304 forming a sixth insulating layer on the side of the active patterns of the plurality of polysilicon thin film transistors away from the base substrate.
  • a sixth insulating layer 114 may be formed on the side of the active patterns 11313 of the plurality of polysilicon thin film transistors away from the base substrate 101 .
  • the sixth insulating layer 114 may also be referred to as a gate insulating layer.
  • Step 305 forming a plurality of scan lines and a plurality of second gate patterns of polysilicon thin film transistors on the side of the sixth insulating layer away from the base substrate.
  • a plurality of scan lines 112 and a plurality of polysilicon thin film transistors may be formed on the side of the sixth insulating layer 114 away from the base substrate 101 .
  • the materials of the plurality of scan lines 112 and the second gate patterns 11311 of the plurality of polysilicon thin film transistors include conductive materials, such as metal materials.
  • a first conductive film may be formed on the side of the sixth insulating layer 114 away from the base substrate 101 first, and a first conductive film may be formed on the side of the sixth insulating layer 114 away from the base substrate 101.
  • a patterned mask is disposed on a side of a conductive film away from the base substrate 101, and the first conductive film is patterned to obtain a plurality of scan lines 112 and a second gate pattern 11311 of the polysilicon thin film transistor.
  • the patterning mask used for patterning the first conductive film is different from the patterning mask used for patterning the crystallized active film.
  • the plurality of scan lines 112 and the second gate patterns 11311 of the plurality of polysilicon thin film transistors are prepared by one patterning process, only one patterned mask can be used to simultaneously prepare the plurality of scan lines 112 and the plurality of polysilicon
  • the second gate pattern 11311 of the thin film transistor can reduce the number of masks required for preparing the array substrate and reduce the manufacturing cost.
  • FIG. 11 is a schematic diagram of a scan line provided by an embodiment of the present application.
  • the plurality of scan lines 112 may be located in the display area 101 a of the base substrate 101 and extend along the pixel row direction X. Referring to FIG. Two scan lines 112 are shown in FIG. 11 .
  • the plurality of scan lines 112 can be used to provide scan signals for the oxide thin film transistors 102 formed in the display area 101a subsequently.
  • the driving circuit located in the peripheral region 101b may be connected to a plurality of scan lines 112 , and the driving circuit may provide scan signals for the oxide thin film transistor 102 to be formed subsequently through the plurality of scan lines 112 .
  • the length of the scan line 112 along the pixel column direction Y (ie, the width of the scan line 112 ) ranges from 1.5 ⁇ m to 2.5 ⁇ m, for example, 1.8 ⁇ m.
  • Step 306 forming first gate patterns of a plurality of oxide thin film transistors on a side of the plurality of scan lines away from the base substrate.
  • the material of the first gate patterns 1022 of the plurality of oxide thin film transistors 102 may include a conductive material, for example, a metal material.
  • a first gate film may be formed on the side of the plurality of scan lines 112 away from the base substrate 101 , and then a gate film may be provided on the side of the first gate film away from the base substrate 101 .
  • the mask is patterned, and the first gate thin film is patterned to obtain the first gate patterns 1022 of the plurality of oxide thin film transistors 102 .
  • the patterning masks used for patterning different thin films are different. For example, a patterned mask used for patterning the first gate film, a patterned mask used for patterning the first conductive film, and a patterned mask used for the crystallized active film The patterned masks used in the patterning process are all different masks.
  • FIG. 12 is a schematic diagram of forming a first gate pattern according to an embodiment of the present application.
  • the length of the orthographic projection of the first gate pattern 1022 on the base substrate 101 along the pixel column direction Y may be greater than the length of the orthographic projection of the scan line 112 on the base substrate 101 along the pixel column direction Y, So that the orthographic projection of the first gate pattern 1022 on the base substrate 101 covers the orthographic projection of the channel portion 10212 in the subsequently formed metal oxide pattern 1021 on the base substrate 101 .
  • the pixel column direction Y is perpendicular to the pixel row direction X.
  • Step 307 forming a fifth insulating layer on the side of the first gate pattern and the second gate pattern away from the base substrate.
  • the fifth insulating layer 111 may be formed on the side of the first gate pattern 1022 and the second gate pattern 11311 away from the base substrate 101 .
  • the orthographic projection of the fifth insulating layer 111 on the base substrate 101 may cover the orthographic projection of the first gate patterns 1022 of the plurality of oxide thin film transistors 102 on the base substrate 101 , and cover the orthographic projections of the plurality of polysilicon thin film transistors 1131 An orthographic projection of the second gate pattern 11311 on the base substrate 101 .
  • the fifth insulating layer 111 may be referred to as an interlayer dielectric (inter layer dielectric, ILD).
  • the material of the fifth insulating layer 111 may include at least one of silicon dioxide and silicon nitride. Wherein, since the fifth insulating layer 111 completely covers the base substrate 101, it is not shown in a top view.
  • Step 308 forming a plurality of data lines and a plurality of source and drain patterns of polysilicon thin film transistors on the side of the fifth insulating layer away from the base substrate.
  • a plurality of data lines 104 and a plurality of polysilicon thin film transistors 1131 may be formed on the side of the fifth insulating layer 111 away from the base substrate 101
  • the materials of the plurality of data lines 104 and the source and drain patterns 11312 of the plurality of polysilicon thin film transistors 1131 include conductive materials, such as metal materials.
  • a second conductive film can be formed on the side of the first insulating layer 105 away from the base substrate 101 first, and a second conductive film can be formed on the first insulating layer 105.
  • a patterned mask is disposed on the side of the second conductive film away from the base substrate 101 , and the second conductive film is patterned to obtain a plurality of data lines 104 and source and drain patterns 11312 of the polysilicon thin film transistor 1131 .
  • the source and drain patterns 11312 of the plurality of data lines 104 and the plurality of polysilicon thin film transistors 1131 are prepared by one patterning process, only one patterned mask can be used to simultaneously prepare the plurality of data lines 104 and the plurality of polysilicon
  • the source and drain patterns 11312 of the thin film transistor can reduce the number of masks required for preparing the array substrate and reduce the manufacturing cost.
  • FIG. 14 is a schematic diagram of forming a data line according to an embodiment of the present application.
  • the plurality of data lines 104 may be located in the display area 101a of the base substrate 101 and extend along the pixel column direction Y, and are used for the subsequent formation of the metal oxide pattern 1021 of the oxide thin film transistor 102 in the display area 101a.
  • the first part 10211 provides data signals.
  • the source and drain patterns 11312 of the polysilicon thin film transistor 1131 may be electrically connected to the active pattern 11313 .
  • the source and drain patterns 11312 of the polysilicon thin film transistor 1131 may include a source electrode a1 and a drain electrode a2 arranged at intervals, and the fifth insulating layer 111 and the sixth insulating layer 114 each have a third via hole and a fourth via hole.
  • the source electrode a1 may be electrically connected to the active pattern 11313 through a third via hole
  • the drain electrode a2 may be electrically connected to the active pattern 11313 through a fourth via hole.
  • Step 309 forming an insulating material layer on the side of the plurality of data lines and the source and drain patterns away from the base substrate.
  • an insulating material layer c may be formed on the side of the plurality of data lines 104 and the source and drain patterns 11312 away from the base substrate 101 .
  • the material of the insulating material layer may include silicon dioxide (SiO 2 ). Wherein, since the insulating material layer covers the base substrate 101 as a whole, the insulating material layer is not shown in a top view.
  • Step 310 forming a color filter layer on the side of the insulating material layer away from the base substrate.
  • a color filter layer 103 may be formed on the side of the insulating material layer away from the base substrate 101 .
  • the color filter layer 103 includes a plurality of color resist blocks 1031 of different colors corresponding to the plurality of oxide thin film transistors 102 one-to-one. Each color blocking block 1031 can be used to transmit light of a corresponding color.
  • the color filter layer 103 may include a plurality of red color blocking blocks, a plurality of green color blocking blocks and a plurality of blue color blocking blocks.
  • the red color blocking block can be used to transmit red light
  • the green color blocking block can be used to transmit green light
  • the blue color blocking block can be used to transmit blue light.
  • the plurality of red color resist blocks included in the color filter layer 103 may be prepared by the same patterning process.
  • the multiple green color resist blocks included in the color filter layer 103 can be prepared by the same patterning process.
  • the plurality of blue color resists included in the color filter layer 103 can be prepared by the same patterning process.
  • the color resist blocks of different colors are prepared by different patterning processes. That is, the plurality of red color resistance blocks 1031 , the plurality of green color resistance blocks, and the plurality of blue color resistance blocks are respectively prepared by three patterning processes.
  • the color resist film of the color is firstly coated on the whole layer, and then a patterned mask is set on the side of the color resist film away from the base substrate 101, The color resist film is patterned to obtain a plurality of color resist blocks 1031 of the color.
  • the patterned masks used for preparing the color resist blocks 1031 of different colors are different.
  • the thicknesses of the color resists 1031 of the three colors may be different, which may lead to certain differences in the display of sub-pixels of different colors in the display panel. Therefore, after the subsequent array substrate preparation is completed, the brightness of the sub-pixels can be adjusted by adjusting the driving voltages provided to the sub-pixels of different colors during the product debugging process, and then display correction can be performed through optical calibration.
  • each sub-pixel in the display panel includes: a pixel circuit.
  • the oxide thin film transistor 102 included in the array substrate 10 can be used as a transistor in a pixel circuit of a sub-pixel. That is, the oxide thin film transistor 102 included in the array substrate 10 may be located in the display area 101 a of the base substrate 101 .
  • each sub-pixel includes a color blocking block 1031 for emitting light of a color corresponding to the color blocking block 1031 .
  • Step 311 etching the insulating material layer to obtain a first insulating layer formed with a plurality of first via holes.
  • the insulating material layer can be etched to obtain a first insulating layer with a plurality of first via holes 105a formed thereon 105.
  • the etching process for etching the insulating material layer may be dry etching or wet etching.
  • Each of the first vias 105a in the first insulating layer 105 may be used to expose at least a portion of a data line 104 .
  • a filling pattern is used to represent the first via hole 105a in FIG. 17 .
  • Other regions where no filling pattern is drawn are used to represent regions where the first insulating layer 105 has a solid material.
  • Step 312 forming a metal oxide film on the side of the first insulating layer away from the base substrate.
  • a metal oxide material may be used to form a metal oxide film on the side of the first insulating layer 105 away from the base substrate 101 .
  • the material of the metal oxide thin film includes metal oxide.
  • Step 313 patterning the metal oxide film to obtain a metal oxide structure.
  • a patterned mask may be set on the side of the metal oxide film away from the base substrate 101, and the metal oxide film is patterned to obtain Metal oxide structures, for example, referring to FIG. 18, a plurality of metal oxide structures b can be obtained.
  • the patterning masks used for patterning different thin films in the embodiments of the present application are different.
  • the distance d1 between two adjacent metal oxide structures b along the pixel column direction Y may be 2.5 ⁇ m.
  • the distance d4 between the first region b1 of the metal oxide structure and the scan line 112 along the pixel column direction Y may be 0.9 ⁇ m.
  • the third region b3 of the metal oxide structure has a first sub-region and a second sub-region, and the length of the first sub-region along the pixel row direction X is greater than the length of the second sub-region along the pixel row direction X.
  • the length of the first sub-region along the pixel column direction Y may be 9.6 microns.
  • the distance d3 between the second sub-region and the scan line 112 along the pixel column direction Y may be 0.9 ⁇ m. That is, the distance d3 may be equal to the distance d4, and of course, the distance d3 and the distance d4 may also be unequal, which is not limited in this embodiment of the present application.
  • Step 314 Coat a photoresist on the first region of the metal oxide structure on the side away from the base substrate.
  • the orthographic projection of the coated photoresist on the base substrate 101 is located within the orthographic projection of the first gate pattern 1022 on the base substrate 101 .
  • the side of the metal oxide structure b away from the base substrate 101 further includes a second region b2 and a third region b3.
  • the second area b2 and the third area b3 are located on both sides of the first area b1, respectively.
  • Step 315 conducting conductorization processing on the second region and the third region on the side of the metal oxide structure away from the base substrate to obtain the first part and the second part of the metal oxide pattern.
  • ions are implanted into the metal oxide structure b (ie, ion doping), so that the second region without photoresist is coated Conducting conductive treatment on b2 and the third region b3 to obtain the first part 10211 and the second part 10213 of the metal oxide pattern 1021 .
  • the implanted ions may be boron ions or phosphorus ions.
  • the area of the orthographic projection of the photoresist coated in the above step 314 on the base substrate 101 is larger than the area of the orthographic projection of the first gate pattern 1022 on the base substrate 101, referring to FIG. 22 , in the second area After the conductorization of the b2 and the third region b3, there are some regions that are not conductorized except for the channel portion. In this case, a high-resistance region is formed when the oxide thin film transistor 102 is operating, which affects the characteristics of the oxide thin film transistor.
  • the area of the orthographic projection of the coated photoresist on the base substrate 101 is located within the area of the orthographic projection of the first gate pattern 1022 on the base substrate 101, which can ensure that the oxide thin film transistor The normal operation, that is, to ensure the characteristics of the oxide thin film transistor.
  • Step 316 removing the photoresist to obtain the channel portion of the metal oxide pattern.
  • the metal oxide structure b may be kept away from the The photoresist of the first region on one side of the base substrate 101 is removed to obtain the channel portion 10212 of the metal oxide pattern 1021 . That is, the metal oxide pattern 1021 of the oxide thin film transistor 10 is obtained.
  • Step 317 forming a second insulating layer on the side of the metal oxide structure away from the base substrate.
  • the second insulating layer 106 may be formed on the side of the metal oxide pattern 1021 away from the base substrate 101 .
  • the second insulating layer 106 may include a second passivation layer 1061 and a planarization layer 1062 stacked in a direction away from the base substrate 101 .
  • the part of the second passivation layer 1061 covering the color resist block 1031 and the side away from the base substrate 101 may be coplanar with the side of the flat layer 1062 away from the base substrate 101 .
  • the side of the second passivation layer 1061 covering the color resist block 1031 away from the base substrate 101 may not be coplanar with the side of the flat layer 1062 away from the base substrate 101 .
  • the distance between the side of the flat layer 1062 away from the base substrate 101 and the base substrate 101 may be greater than the distance between the side of the second passivation layer 1061 covering the color resist blocks 1031 away from the base substrate 101 and the base substrate 101 The distance between them is not limited in this embodiment of the present application.
  • the second passivation layer 1061 and the flat layer 1062 may cover the entire layer, so the top view of the second passivation layer 1061 and the flat layer 1062 is not shown.
  • the thickness of the planarization layer 1062 ranges from 1 micrometer to 2 micrometers.
  • Step 318 forming a common electrode on the side of the second insulating layer away from the base substrate.
  • a common electrode 107 may be formed on the side of the second insulating layer 106 away from the base substrate 101 .
  • the orthographic projection of the common electrode 107 on the base substrate 101 at least partially overlaps the orthographic projection of the third portion 10213 in the metal oxide pattern 1021 on the base substrate 101 .
  • the third part 10313 is used as a pixel electrode to drive the liquid crystal deflection together with the common electrode 107 .
  • steps 302 to 309 , step 311 , and steps 317 to 318 may be deleted according to circumstances, and step 311 may be performed before step 310 .
  • Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of any variation of the method, which should be covered by the protection scope of the present application, and thus will not be repeated here.
  • the embodiments of the present application provide a method for preparing an array substrate.
  • the array substrate prepared by the method includes a color filter layer, so the light source and the color filter layer are located on the side of the base substrate away from the color filter layer. The distance between them is relatively short, so that the light in the area where each color resist block is located can be prevented from being emitted from the adjacent color resist blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • FIG. 25 is a flowchart of another method for fabricating an array substrate provided by an embodiment of the present application. This method can be used to prepare the array substrate provided in the above embodiments, for example, the preparation of the array substrate shown in FIG. 7 is taken as an example. Referring to Figure 25, the method may include:
  • Step 401 providing a base substrate.
  • step 401 for the detailed content of step 401, reference may be made to the content of the foregoing step 301, which is not repeated in this embodiment of the present application.
  • Step 402 forming a buffer layer on one side of the base substrate.
  • step 402 for the detailed content of step 402, reference may be made to the content of the foregoing step 302, which is not repeated in this embodiment of the present application.
  • Step 403 forming a plurality of active patterns of polysilicon thin film transistors on the side of the buffer layer away from the base substrate.
  • step 403 for the detailed content of step 403, reference may be made to the content of the foregoing step 303, which is not repeated in this embodiment of the present application.
  • Step 404 forming a sixth insulating layer on the side of the active patterns of the plurality of polysilicon thin film transistors away from the base substrate.
  • step 404 for the detailed content of step 404, reference may be made to the content of the foregoing step 304, which is not repeated in this embodiment of the present application.
  • Step 405 forming a plurality of scan lines and a plurality of second gate patterns of polysilicon thin film transistors on the side of the sixth insulating layer away from the base substrate.
  • step 405 for the detailed content of step 405, reference may be made to the content of the foregoing step 305, which is not repeated in this embodiment of the present application.
  • Step 406 forming first gate patterns of a plurality of oxide thin film transistors on a side of the plurality of scan lines away from the base substrate.
  • step 406 for the detailed content of step 406, reference may be made to the content of the foregoing step 306, which is not repeated in this embodiment of the present application.
  • Step 407 forming a fifth insulating layer on the side of the first gate pattern and the second gate pattern away from the base substrate.
  • step 407 for the detailed content of step 407, reference may be made to the content of the foregoing step 307, which is not repeated in this embodiment of the present application.
  • Step 408 forming a plurality of data lines and a plurality of source and drain patterns of polysilicon thin film transistors on the side of the fifth insulating layer away from the base substrate.
  • step 408 for the detailed content of step 408, reference may be made to the content of the foregoing step 308, which is not repeated in this embodiment of the present application.
  • Step 409 forming an insulating material layer on the side of the plurality of data lines and the source and drain patterns away from the base substrate.
  • step 409 for the detailed content of step 409, reference may be made to the content of the foregoing step 309, which is not repeated in this embodiment of the present application.
  • Step 410 forming a color filter layer on the side of the insulating material layer away from the base substrate.
  • step 410 for the detailed content of step 410, reference may be made to the content of the foregoing step 310, and details are not described herein again in this embodiment of the present application.
  • Step 411 etching the insulating material layer to obtain a first insulating layer formed with a plurality of first via holes.
  • step 411 for the detailed content of step 411, reference may be made to the content of the foregoing step 311, and details are not described herein again in this embodiment of the present application.
  • Step 412 forming a metal oxide film on the side of the first insulating layer away from the base substrate.
  • step 412 for the detailed content of step 412, reference may be made to the content of the foregoing step 312, and details are not described herein again in this embodiment of the present application.
  • Step 413 patterning the metal oxide film to obtain a metal oxide structure.
  • step 413 for the detailed content of step 413, reference may be made to the content of the foregoing step 313, and details are not described herein again in this embodiment of the present application.
  • the orthographic projection of the metal oxide structure for preparing the metal oxide pattern obtained in step 413 on the base substrate 101 The area may be smaller than the area of the orthographic projection of the metal oxide structure obtained in step 313 for preparing the metal oxide pattern on the base substrate 101 .
  • the length of the metal oxide structure b along the pixel column direction Y may be small, as long as the pixel electrode formed subsequently can be electrically connected to the second part of the metal oxide pattern.
  • Step 414 Coat photoresist on the first region of the metal oxide structure on the side away from the base substrate.
  • the orthographic projection of the coated photoresist on the base substrate 101 is located within the orthographic projection of the first gate pattern 1022 on the base substrate 101 .
  • the side of the metal oxide structure b away from the base substrate 101 further includes a second region b2 and a third region b3.
  • the second area b2 and the third area b3 are located on both sides of the first area b1, respectively.
  • Step 415 conducting conductorization processing on the second region and the third region on the side of the metal oxide structure away from the base substrate, to obtain the first part and the second part of the metal oxide pattern.
  • step 415 For the detailed content of step 415, reference may be made to the content of the foregoing step 315, and details are not described herein again in this embodiment of the present application.
  • Step 416 removing the photoresist to obtain the channel portion of the metal oxide pattern.
  • FIG. 28 is another schematic diagram of obtaining a metal oxide pattern provided by the embodiment of the present application.
  • step 416 reference may be made to the content of the foregoing step 316, which is not repeated in this embodiment of the present application.
  • Step 417 forming a third insulating layer on the side of the metal oxide structure away from the base substrate.
  • a third insulating layer 108 may be formed on the side of the metal oxide pattern 1021 away from the base substrate 101 .
  • the third insulating layer 108 may be a passivation layer (passivation, PVX).
  • the material of the second insulating layer 106 may include silicon dioxide.
  • the third insulating layer 108 may be in contact with the second portion 10213, and the third insulating layer 108 may have a plurality of second vias 108a, each of which may be used to expose an oxide film At least part of the second portion 10213 of the transistor 102 .
  • a filling pattern is used to represent the second via hole 108a in FIG. 28 .
  • Other regions where the filling pattern is not drawn are used to represent regions where the third insulating layer 108 has a solid material.
  • Step 418 forming a pixel electrode on the side of the third insulating layer away from the base substrate.
  • a pixel electrode 109 may be formed on the side of the third insulating layer 108 away from the base substrate 101 .
  • the orthographic projection of the pixel electrode 109 on the base substrate 101 at least partially overlaps with the orthographic projection of the second via hole 108 a on the base substrate 101 .
  • the two parts 10213 are electrically connected.
  • Step 419 forming a fourth insulating layer on the side of the pixel electrode away from the base substrate.
  • a fourth insulating layer 110 may be formed on the side of the pixel electrode 109 away from the base substrate 101 .
  • the fourth insulating layer 110 may be a planarization layer (PLN).
  • the flat layer can be used to flatten the side of the base substrate 101 on which the film layer is provided.
  • Step 420 forming a common electrode on the side of the fourth insulating layer away from the base substrate.
  • the common electrode 107 may be formed on the side of the fourth insulating layer 110 away from the base substrate 101 .
  • the orthographic projection of the common electrode 107 on the base substrate 101 at least partially overlaps the orthographic projection of the pixel electrode 109 on the base substrate 101 .
  • the lead pixel electrode 109 and the common electrode 107 together drive the liquid crystal to deflect.
  • steps 402 to 409 , step 411 , and steps 417 to 418 may be deleted according to the situation, and step 411 may be performed before step 410 .
  • Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of any variation of the method, which should be covered by the protection scope of the present application, and thus will not be repeated here.
  • the embodiments of the present application provide a method for preparing an array substrate.
  • the array substrate prepared by the method includes a color filter layer, so the light source and the color filter layer are located on the side of the base substrate away from the color filter layer. The distance between them is relatively short, so that the light in the area where each color resist block is located can be prevented from being emitted from the adjacent color resist blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • FIG. 33 is a flowchart of still another method for fabricating an array substrate provided by an embodiment of the present application. This method can be used to prepare the array substrate provided in the above embodiments, for example, the preparation of the array substrate shown in FIG. 6 is taken as an example. Referring to Figure 33, the method may include:
  • Step 501 providing a base substrate.
  • step 501 for the detailed content of step 501, reference may be made to the content of the foregoing step 301, and details are not described herein again in this embodiment of the present application.
  • Step 502 forming a buffer layer on one side of the base substrate.
  • step 502 for the detailed content of step 502, reference may be made to the content of the foregoing step 302, which is not repeated in this embodiment of the present application.
  • Step 503 forming a plurality of active patterns of polysilicon thin film transistors on the side of the buffer layer away from the base substrate.
  • step 503 for the detailed content of step 503, reference may be made to the content of the foregoing step 303, which is not repeated in this embodiment of the present application.
  • Step 504 forming a sixth insulating layer on the side of the active patterns of the plurality of polysilicon thin film transistors away from the base substrate.
  • step 504 for the detailed content of step 504, reference may be made to the content of the foregoing step 304, which is not repeated in this embodiment of the present application.
  • Step 505 forming a plurality of scan lines and a plurality of second gate patterns of polysilicon thin film transistors on the side of the sixth insulating layer away from the base substrate.
  • step 505 for the detailed content of step 505, reference may be made to the content of the foregoing step 305, which is not repeated in this embodiment of the present application.
  • Step 506 forming first gate patterns of a plurality of oxide thin film transistors on a side of the plurality of scan lines away from the base substrate.
  • step 506 for the detailed content of step 506, reference may be made to the content of the foregoing step 306, which is not repeated in this embodiment of the present application.
  • Step 507 forming a fifth insulating layer on the side of the first gate pattern and the second gate pattern away from the base substrate.
  • step 507 for the detailed content of step 507, reference may be made to the content of the foregoing step 307, which is not repeated in this embodiment of the present application.
  • Step 508 forming a plurality of data lines and a plurality of source and drain patterns of polysilicon thin film transistors on the side of the fifth insulating layer away from the base substrate.
  • step 508 for the detailed content of step 508, reference may be made to the content of the foregoing step 308, which is not repeated in this embodiment of the present application.
  • Step 509 forming a first passivation layer in the first insulating layer on the side of the plurality of data lines and the source and drain patterns away from the base substrate.
  • a first passivation of the first insulating layer 105 may be formed on the side of the plurality of data lines and source-drain patterns away from the base substrate Layer 1051.
  • Step 510 forming a color filter layer on the side of the first passivation layer in the first insulating layer away from the base substrate.
  • step 510 for the detailed content of step 510, reference may be made to the content of the foregoing step 310, and details are not described herein again in this embodiment of the present application.
  • Step 511 forming a flat layer in the first insulating layer on the side of the color filter layer away from the base substrate.
  • a planarization layer 1052 in the first insulating layer 105 may be formed on the side of the color filter layer away from the base substrate 101 .
  • Step 512 forming a second passivation layer in the first insulating layer on a side of the flat layer in the first insulating layer away from the base substrate.
  • a second passivation layer 1053 in the first insulating layer 105 may be formed on the side of the planarization layer 1052 away from the base substrate 101 .
  • the second passivation layer 1053 does not contain hydrogen element, and does not affect the channel portion of the metal oxide pattern.
  • the first insulating layer 105 has a plurality of first vias 105a, and each of the first vias 105a can be used to expose at least part of a data line 104 so as to facilitate the subsequent formation of the first part of the metal oxide pattern 1021 10211 is electrically connected to the data line 104 through the first via hole 105a. Since the first insulating layer 105 includes a first passivation layer 1051 , a planarization layer 1052 and a second planarization layer 1053 , the first passivation layer 1051 , the planarization layer 1052 and the second planarization layer 1053 all have a plurality of first Via 105a.
  • Step 513 forming a metal oxide film on the side of the second passivation layer in the first insulating layer away from the base substrate.
  • a metal oxide film may be formed on the side of the second passivation layer away from the base substrate 101 .
  • the material of the metal oxide thin film includes metal oxide.
  • Step 514 patterning the metal oxide film to obtain a metal oxide structure.
  • step 514 for the detailed content of step 514, reference may be made to the content of the foregoing step 313, and details are not described herein again in this embodiment of the present application.
  • Step 515 Coat a photoresist on the first region of the metal oxide structure on the side away from the base substrate.
  • step 515 for the detailed content of step 515, reference may be made to the content of the foregoing step 314, which is not repeated in this embodiment of the present application.
  • Step 516 conducting conductorization processing on the second region and the third region on the side of the metal oxide structure away from the base substrate, to obtain the first part and the second part of the metal oxide pattern.
  • step 516 for the detailed content of step 516, reference may be made to the content of the foregoing step 315, which is not repeated in this embodiment of the present application.
  • Step 517 removing the photoresist to obtain the channel portion of the metal oxide pattern.
  • step 517 for the detailed content of step 517, reference may be made to the content of the foregoing step 316, which is not repeated in this embodiment of the present application.
  • Step 518 forming a second insulating layer on the side of the metal oxide structure away from the base substrate.
  • the first insulating layer 105 formed includes the flat layer 1052 located between the metal oxide pattern 1021 and the color filter layer 103, the array substrate 10 has good flatness, and the second insulating layer 106 can be is a third passivation layer located on the side of the metal oxide pattern 1021 away from the base substrate 101 .
  • the second insulating layer 106 may include a third passivation layer located on the side of the metal oxide pattern 1021 away from the base substrate 101 , and may also include a third passivation layer located at the side of the third passivation layer away from the base substrate 101 . another flat layer. That is, the array substrate 10 in this solution may include two flat layers.
  • Step 519 forming a common electrode on the side of the second insulating layer away from the base substrate.
  • step 519 for the detailed content of step 519, reference may be made to the content of the foregoing step 318, and details are not described herein again in this embodiment of the present application.
  • steps 302 to 409 , step 411 , and steps 417 to 418 may be deleted according to the situation, and step 411 may be performed before step 410 .
  • Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of any variation of the method, which should be covered by the protection scope of the present application, and thus will not be repeated here.
  • the embodiments of the present application provide a method for preparing an array substrate.
  • the array substrate prepared by the method includes a color filter layer, so the light source and the color filter layer are located on the side of the base substrate away from the color filter layer. The distance between them is relatively short, so that the light in the area where each color resist block is located can be prevented from being emitted from the adjacent color resist blocks, thereby avoiding the phenomenon of cross-coloring of the display panel, and the display effect of the display panel is better.
  • the color blocking block at least partially overlaps with the second part of the metal oxide pattern in the oxide thin film transistor, which can reduce the space occupied by the oxide thin film transistor and the color filter layer, and facilitate the realization of a high pixel density display panel.
  • FIG. 35 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 00 may include: a cover plate 60 , a liquid crystal layer 70 , and the array substrate 10 provided in the above-mentioned embodiments.
  • the array substrate 10 in the display panel 00 may be the array substrate shown in any one of FIGS. 5 to 7 .
  • the liquid crystal layer 70 may be located between the cover plate 60 and the array substrate 10 .
  • the second portion 10213 of the metal oxide structure 1021 in the array substrate 10 and the common electrode 107 together drive the liquid crystal deflection in the liquid crystal layer 70 .
  • the pixel electrode 109 and the common electrode 107 in the array substrate 10 jointly drive the liquid crystal deflection in the liquid crystal layer 70 .
  • the liquid crystal arrangement and electric field in each area of the array substrate 10 will be abnormal, which will lead to abnormal display in the corresponding area of the display panel. Therefore, in order to ensure the display effect of the display panel, a large-sized black matrix needs to be arranged on one side of the cover plate, and the orthographic projection of the black matrix on the array substrate covers the area with poor flatness (for example, the over-surface covering the flat layer). hole). Such a solution will result in a lower effective aperture ratio of the pixel.
  • the flatness of the array substrate 10 is good, which can ensure the flatness of the liquid crystal layer 70 located on one side of the array substrate 10 , thereby ensuring that each area of the array substrate 10 is flat.
  • the consistency of the liquid crystal arrangement and the electric field is not necessary to design a larger-sized black matrix, and the display effect of the display panel can be guaranteed on the premise of avoiding reducing the aperture ratio of the pixel.
  • FIG. 36 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: a power supply assembly 002 and the display panel 001 provided in the above-mentioned embodiment.
  • the power supply assembly 002 is used to supply power to the display panel 001 .
  • the display device may be a virtual reality (VR) device or an augmented reality (AR) device.
  • the display device can also be any product or component with display function and fingerprint recognition function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种阵列基板及其制备方法、显示面板、显示装置，涉及显示技术领域。该阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离可以较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。

Description

阵列基板及其制备方法、显示面板、显示装置
本公开要求于2021年4月19日提交的申请号为202110417335.3、发明名称为“阵列基板及其制备方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
随着显示技术的不断发展，市场对显示面板的高像素密度(pixels per inch，PPI)的需求越来越高。
发明内容
本申请提供了一种阵列基板及其制备方法、显示面板、显示装置，所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：
衬底基板，所述衬底基板具有显示区域；
位于所述显示区域的间隔的多个氧化物薄膜晶体管，每个所述氧化物薄膜晶体管包括金属氧化物图案，所述金属氧化物图案具有依次连接的第一部分，沟道部分，以及第二部分，所述第一部分用于接收数据信号；
以及，位于所述显示区域的彩膜层，所述彩膜层位于所述金属氧化物图案与所述衬底基板之间，所述彩膜层包括与所述多个氧化物薄膜晶体管一一对应的不同颜色的多个色阻块，每个所述色阻块在所述衬底基板上的正投影与对应的所述氧化物薄膜晶体管中所述第二部分在所述衬底基板上的正投影至少部分重叠。
可选的，所述第一部分的导电性和所述第二部分的导电性均大于所述沟道部分的导电性。
可选的，所述阵列基板还包括：多个数据线以及第一绝缘层；
所述多个数据线位于所述金属氧化物图案与所述衬底基板之间，所述第一绝缘层位于所述多个数据线与所述金属氧化物图案之间，且所述第一绝缘层具有多个第一过孔；
其中，每个所述数据线通过至少一个所述第一过孔与至少一个所述氧化物薄膜晶体管的所述第一部分电连接。
可选的，所述第一绝缘层为位于所述多个数据线和所述彩膜层之间的第一钝化层；
其中，所述第二部分的目标部分靠近所述衬底基板的一面与所述衬底基板之间的距离，大于所述第一部分靠近所述衬底基板的一面与所述衬底基板之间的距离，且大于所述沟道部分靠近所述衬底基板的一面与所述衬底基板之间的距离，所述目标部分为所述第二部分在所述衬底基板上的正投影中与所述色阻块在所述衬底基板上的正投影重叠的部分。
可选的，所述第一绝缘层包括：位于所述多个数据线和所述彩膜层之间的第一钝化层，位于所述彩膜层和所述金属氧化物图案之间的平坦层，以及位于所述平坦层和所述金属氧化物图案的第二钝化层。
可选的，所述阵列基板还包括：位于所述第二部分远离所述衬底基板的一侧的第二绝缘层，以及位于所述第二绝缘层远离所述衬底基板的一侧的公共电极；
其中，所述公共电极在所述衬底基板上的正投影，与所述第二部分在所述衬底基板上的正投影至少部分重叠，所述第二部分用于作为像素电极与所述公共电极共同驱动液晶偏转。
可选的，所述阵列基板还包括：位于所述金属氧化物图案远离所述衬底基板的一侧且沿远离所述衬底基板的方向依次层叠的第三绝缘层，像素电极，第四绝缘层以及公共电极，所述像素电极在所述衬底基板上的正投影，与所述公共电极在所述衬底基板上的正投影至少部分重叠；
其中，所述第三绝缘层具有多个第二过孔，每个所述第二过孔用于露出一个所述氧化物薄膜晶体管的所述第二部分的至少部分，所述像素电极通过所述第二过孔与所述第二部分电连接。
可选的，每个所述氧化物薄膜晶体管还包括：位于所述显示区域的第一栅极图案；所述阵列基板还包括：第五绝缘层；所述第一栅极图案位于所述金属氧化物图案与所述衬底基板之间，所述第五绝缘层位于所述第一栅极图案与所 述金属氧化物图案之间；
其中，每个所述氧化物薄膜晶体管中，所述第一栅极图案在所述衬底基板上的正投影覆盖所述金属氧化物图案中所述沟道部分在所述衬底基板上的正投影。
可选的，所述阵列基板还包括：沿像素行方向延伸的多个扫描线；
所述多个扫描线位于所述第一栅极图案靠近所述衬底基板的一侧，且每个所述扫描线与至少一个所述氧化物薄膜晶体管的所述第一栅极图案至少部分接触，所述第一栅极图案在所述衬底基板上的正投影沿像素列方向的长度，大于所述扫描线在所述衬底基板上的正投影沿所述像素列方向的长度。
可选的，所述衬底基板还具有位于所述显示区域一侧的周边区域；所述阵列基板还包括：位于所述周边区域的驱动电路；所述驱动电路包括至少一个多晶硅薄膜晶体管；每个所述多晶硅薄膜晶体管包括：第二栅极图案和源漏极图案；
其中，所述第二栅极图案与所述多个扫描线位于同层，所述源漏极图案与所述阵列基板的多个数据线位于同层。
可选的，每个所述多晶硅薄膜晶体管还包括：有源图案；所述阵列基板还包括：第六绝缘层；所述有源图案位于所述第二栅极图案与所述衬底基板之间，所述第六绝缘层位于所述有源图案与所述第二栅极图案之间；
其中，所述源漏极图案与所述有源图案电连接。
另一方面，提供了一种阵列基板的制备方法，所述方法包括：
提供一衬底基板，所述衬底基板具有显示区域；
在所述显示区域形成间隔的多个氧化物薄膜晶体管以及彩膜层；
其中，每个所述氧化物薄膜晶体管包括金属氧化物图案，所述金属氧化物图案具有依次连接的第一部分，沟道部分，以及第二部分，所述第一部分用于接收数据信号；所述彩膜层位于所述金属氧化物图案与所述衬底基板之间，所述彩膜层包括与所述多个氧化物薄膜晶体管一一对应的不同颜色的多个色阻块，每个所述色阻块在所述衬底基板上的正投影与对应的所述氧化物薄膜晶体管中所述第二部分在所述衬底基板上的正投影至少部分重叠。
可选的，形成所述氧化物薄膜晶体管的金属氧化物图案，包括：
在所述衬底基板的一侧形成金属氧化物薄膜；
对所述金属氧化物薄膜进行图案化处理，得到金属氧化物结构；
在所述金属氧化物结构远离所述衬底基板的一侧的第一区域涂覆光刻胶，所述金属氧化物结构远离所述衬底基板的一侧还包括第二区域和第三区域，所述第二区域和所述第三区域位于所述第一区域的两侧；
对所述金属氧化物结构远离所述衬底基板的一侧的所述第二区域和所述第三区域进行导体化处理，得到所述金属氧化物图案的第一部分和第二部分；
去除所述光刻胶，得到所述金属氧化物图案的沟道部分。
又一方面，提供了一种显示面板，所述显示面板包括：盖板，液晶层以及如上述方面所述的阵列基板；
所述液晶层位于所述盖板和所述阵列基板之间。
再一方面，提供了一种显示装置，所述显示装置包括：供电组件以及如上述方面所述的显示面板；
所述供电组件用于为所述显示面板供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种阵列基板的结构示意图；
图2是本申请实施例提供的一种衬底基板的俯视图；
图3是本申请实施例提供的一种彩膜层和光源的位置示意图；
图4是相关技术中彩膜层和光源的位置示意图；
图5是本申请实施例提供的另一种阵列基板的结构示意图；
图6是本申请实施例提供的又一种阵列基板的结构示意图；
图7是本申请实施例提供的再一种阵列基板的结构示意图；
图8是本申请实施例提供的一种阵列基板的制备方法的流程图；
图9是本申请实施例提供的另一种阵列基板的制备方法的流程图；
图10是本申请实施例提供的一种形成第二栅极图案以及扫描线的截面图；
图11是本申请实施例提供的一种扫描线的俯视图；
图12是本申请实施例提供的一种形成第一栅极图案的俯视图；
图13是本申请实施例提供的一种形成源漏极图案以及数据线的截面图；
图14是本申请实施例提供的一种形成数据线的俯视图；
图15是本申请实施例提供的一种形成色阻块的俯视图；
图16是本申请实施例提供的一种形成第一过孔的截面图；
图17是本申请实施例提供的一种形成第一过孔的俯视图；
图18是本申请实施例提供的一种形成金属氧化物结构的俯视图；
图19是本申请实施例提供的一种在第一区域涂覆光刻胶的俯视图；
图20是本申请实施例提供的一种在第一区域涂覆光刻胶的截面图；
图21是本申请实施例提供的一种对第二区域和第三区域进行导体化的截面图；
图22是本申请实施例提供的一种高阻区的示意图；
图23是本申请实施例提供的一种形成金属氧化物图案的俯视图；
图24是本申请实施例提供的一种形成公共电极的俯视图；
图25是本申请实施例提供的又一种阵列基板的制备方法的流程图；
图26是本申请实施例提供的另一种形成金属氧化物结构的俯视图；
图27是本申请实施例提供的另一种在第一区域涂覆光刻胶的俯视图；
图28是本申请实施例提供的另一种形成金属氧化物图案的俯视图；
图29是本申请实施例提供的一种形成第二过孔的截面图；
图30是本申请实施例提供的一种形成第二过孔的俯视图；
图31是本申请实施例提供的一种形成像素电极的俯视图；
图32是本申请实施例提供的另一种形成公共电极的俯视图；
图33是本申请实施例提供的再一种阵列基板的制备方法的流程图；
图34是本申请实施例提供的另一种形成第一过孔的截面图；
图35是本申请实施例提供的一种显示面板的结构示意图；
图36是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，显示面板包括驱动电路，以及多个不同颜色的子像素，每个子像素均可以在驱动电路的驱动下发光，实现显示面板的彩色显示。
但是，由于高PPI显示面板中子像素的尺寸较小，且相邻子像素之间的间 距较近，因此各个子像素发出的光线容易出现串色现象，影响显示面板的显示效果。
近年来，随着虚拟现实(virtual reality，VR)应用领域的多元化拓展，VR产品的需求不断增长。其中，由于该VR产品中包括的显示面板是其核心硬件，因此显示面板需要包括较多数量的像素数以还原真实场景。也即是，对VR产品中高PPI显示面板的需求越来越高。
但是，现有VR产品的显示面板中，阵列基板的显示区域的子像素中的薄膜晶体管(thin film transistor，TFT)通常为多晶硅(low temperature poly-silicon，LTPS)薄膜晶体管。该多晶硅薄膜晶体管的漏电流的量级(10 -11)较高，即漏电流较大，在子像素的显示过程中无法保持住子像素的电压稳定，导致高PPI显示面板(例如1000PPI以上的显示面板)无法正常显示。并且，由于高PPI显示面板中单个子像素的尺寸较小，且相邻子像素之间的间距较近，因此各个子像素发出的光线容易出现串色现象，显示面板的显示效果较差。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
图1是本申请实施例提供的一种阵列基板的结构示意图。参考图1可以看出，该阵列基板10可以包括：衬底基板101，间隔的多个氧化物薄膜晶体管102，以及彩膜层103。
图2是本申请实施例提供的一种衬底基板的俯视图。参考图2可以看出， 该衬底基板101可以具有显示区域101a。阵列基板10包括的多个氧化物薄膜晶体管102以及彩膜层103可以均位于衬底基板101的显示区域101a。该显示区域101a还可以称为有效显示(active area，AA)区。
由于氧化物薄膜晶体管102的漏电流的量级(10 -13)较小，即漏电流较小，因此可以提高显示区域101a在显示图像过程中电压的稳定性，确保显示面板能够正常显示。
参考图1，每个氧化物薄膜晶体管102包括金属氧化物图案1021。该金属氧化物图案1021具有依次连接的第一部分10211，沟道部分10212以及第二部分10213，该第一部分10211可以用于接收数据信号。
参考图1，彩膜层103位于金属氧化物图案1021与衬底基板101之间。也即是，金属氧化物图案1021位于彩膜层103远离衬底基板101的一侧。该彩膜层103可以包括与多个氧化物薄膜晶体管102一一对应的不同颜色的多个色阻块1031。例如，图1中示出了三个氧化物薄膜晶体管102和三个色阻块1031，且填充图案不同表示色阻块1031的颜色不同。
其中，每个色阻块1031在衬底基板101上的正投影与对应的氧化物薄膜晶体管102中第二部分10213在衬底基板101上的正投影至少部分重叠。并且，由于色阻块1031与金属氧化物图案1021中第二部分10213至少部分重叠，因此可以减小金属氧化物图案1021和色阻块1031在衬底基板101上的整体占用空间，便于高PPI显示面板的实现。
可选的，彩膜层103包括的多个色阻块1031中任意相邻的两个色阻块1031的颜色可以不同。在本申请实施例中，参考图3，由于彩膜层103设置在阵列基板10的一侧，即该阵列基板10可以为(color film on array，COA)阵列基板，因此位于衬底基板101远离彩膜层103的一侧的光源与彩膜层103之间的距离可以较近，可以避免彩膜层103中每个色阻块1031所在区域的光线从相邻色阻块1031射出，进而避免显示面板出现串色现象，保证显示面板的显示效果。
综上所述，本申请实施例提供了一种阵列基板，该阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离可以较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
可选的，该金属氧化物图案1021的材料包括铟镓锌氧化物(indium gallium zinc oxide，IGZO)。该第一部分10211的导电性和第二部分10213的导电性均可以大于沟道部分10212的导电性。例如，该第一部分10211和第二部分10213可以经过导体化，沟道部分10212可以未经导体化。
可选的，参考图3，该彩膜层103可以包括多个红色色阻块1031，多个绿色色阻块1031以及多个蓝色色阻块1031。该红色色阻块1031可以用于透过红色的光线，绿色色阻块1031可以用于透过绿色的光线，蓝色色阻块1031可以用于透过蓝色的光线。彩膜层103中多个色阻块1031的厚度范围为1微米至2微米。
在高PPI显示面板中，参考图4，当只显示绿色子像素时，绿色子像素的绿色色阻块1031所在区域的光线从相邻的红色色阻块或蓝色色阻块射出发生漏光，从而产生串色现象。为了解决该问题，参考图3，本申请实施例将彩膜层103设置在阵列基板10的一侧，彩膜层103与光源的距离大大缩小，因此当只显示绿色子像素时，绿色子像素的绿色色阻块1031所在区域的光线不会从相邻的红色色阻块或蓝色色阻块射出，从而减少串色现象。
图5是本申请实施例提供的另一种阵列基板的结构示意图。参考图5可以看出，该阵列基板10还可以包括：多个数据线104以及第一绝缘层105。该多个数据线104可以位于金属氧化物图案1021与衬底基板101之间，第一绝缘层105可以位于多个数据线104与金属氧化物图案1021之间，该第一绝缘层105用于使得金属氧化物图案1021与多个数据线104相互绝缘。
其中，该第一绝缘层105可以具有多个第一过孔，每个第一过孔可以用于露出一个数据线104的至少部分。每个金属氧化物图案1021的第一部分10211在衬底基板101上的正投影与一个第一过孔在衬底基板101上的正投影至少部分重叠。例如，每个金属氧化物图案1021的第一部分10211的至少部分可以位于一个第一过孔内，且与该第一过孔露出的一个数据线104电连接。
可选的，每个数据线104可以通过至少一个第一过孔与至少一个氧化物薄膜晶体管102的第一部分10211电连接，从而使得该数据线104为该至少一个氧化物薄膜晶体管102的第一部分10211提供数据信号。
例如，多个数据线104可以均沿像素列方向延伸，第一绝缘层105包括像素列方向排列的多个目标第一过孔，且阵列基板10可以包括沿像素列方向排列的多个第一目标氧化物薄膜晶体管，该沿像素列方向排列的多个第一目标氧化 物薄膜晶体管与沿像素列方向排列的多个目标第一过孔一一对应。每个数据线104与位于一列的第一目标氧化物薄膜晶体管的第一部分10211通过对应的目标第一过孔电连接。
作为一种可选的实现方式，参考图5，该第一绝缘层105为位于多个数据线104和彩膜层103之间的第一钝化层(passivation，PVX)。由于彩膜层103中色阻块1031的厚度较厚，且第一绝缘层105不包括位于彩膜层103远离衬底基板101的一侧的平坦层(planarization layer，PLN)，因此金属氧化物图案1021中和色阻块1031重叠的部分，可以与衬底基板101之间的距离较大，金属氧化物图案1021中和该彩膜层103中色阻块1031不重叠的部分，可以与衬底基板101之间的距离较小。金属氧化物图案1021中和色阻块1031重叠的部分是指：金属氧化物图案1021在衬底基板101上的正投影和色阻块1031在衬底基板101上的正投影重叠的部分。金属氧化物图案1021中和色阻块1031不重叠的部分是指：金属氧化物图案1021在衬底基板101上的正投影和色阻块1031在衬底基板101上的正投影不重叠的部分。
可选的，金属氧化物图案1021的第二部分10213的目标部分靠近衬底基板101的一面与衬底基板101之间的距离h1，大于第一部分10211靠近衬底基板101的一面与衬底基板101之间的距离h2，且大于沟道部分10212靠近衬底基板101的一面与衬底基板101之间的距离h3。其中，目标部分为第二部分10213在衬底基板101上的正投影中与色阻块1031在衬底基板101上的正投影重叠的部分。
参考图5，金属氧化物图案1021的第二部分10213的目标部分靠近衬底基板101的一面，与第一部分10211靠近衬底基板101的一面以及沟道部分10212靠近衬底基板101的一面均不共面。并且，第一部分10211靠近衬底基板101的一面以及沟道部分10212靠近衬底基板101的一面可以共面。也即是，第一部分10211靠近衬底基板101的一面与衬底基板101之间的距离h2，等于沟道部分10212靠近衬底基板101的一面与衬底基板101之间的距离h3，即h2＝h3。
作为另一种可选的实现方式，参考图6，该第一绝缘层105可以包括：位于多个数据线104和彩膜层103之间的第一钝化层1051，位于彩膜层103和金属氧化物图案1021之间的平坦层1052，以及位于平坦层1052和金属氧化物图案1021之间的第二钝化层1053。也即是，第一钝化层1051，平坦层1052，以及第二钝化层1053沿远离衬底基板101的方向依次层叠。
尽管彩膜层103中色阻块1031的厚度较厚，但是由于第一绝缘层105包括位于金属氧化物图案1021与彩膜层103之间的平坦层1052，因此可以使得位于该平坦层1052远离衬底基板101的一面的膜层靠近衬底基板101的一面为平面。其中，平坦层1052远离衬底基板101的一面为平面，且大致平行于衬底基板101的承载面。也即是，通过设置平坦层1052将阵列基板10中色阻块1031的周围填平，即可以平坦化具有色阻块1031的区域和不具有色阻块1031的区域。
可选的，由于第一绝缘层105中位于该平坦层1052远离衬底基板101的一面为第二钝化层1053，因此该第二钝化层1053靠近衬底基板101的一面为平面。并且，由于该第二钝化层1053为整层覆盖，因此不会影响阵列基板10的平坦性，即位于该第二钝化层1053远离衬底基板101的一面的金属氧化物图案1021靠近衬底基板101的一面也为平面。也即是，金属氧化物图案1021的第二部分10213靠近衬底基板101的一面与衬底基板101之间的距离，金属氧化物图案1021的第一部分10211靠近衬底基板101的一面与衬底基板101之间的距离，金属氧化物图案1021的沟道部分10212靠近衬底基板101的一面与衬底基板101之间的距离均相等。
可选的，金属氧化物图案1021的第二部分10213靠近衬底基板101的一面，金属氧化物图案1021的第一部分10211靠近衬底基板101的一面，以及金属氧化物图案1021的沟道部分10212靠近衬底基板101的一面共面。
在本申请实施例中，由于该阵列基板中像素电极(例如图5和图6中的)金属氧化物图案1021的第二部分10213，或者图7中的像素电极107)位于彩膜层103远离衬底基板的一侧，且数据线104位于彩膜层103靠近衬底基板的一侧，因此该阵列基板中像素电极与数据线104沿垂直于衬底基板101的承载面的方向的距离可以较大，可以避免该第二部分10213与数据线104产生的耦合电容对显示效果的影响。
在本申请实施例中，参考图5和图6，阵列基板10还包括：位于第二部分10213远离衬底基板101的一侧的第二绝缘层106，以及位于第二绝缘层106远离衬底基板101的一侧的公共电极107。其中，公共电极107在衬底基板101上的正投影，与第二部分10213在衬底基板101上的正投影至少部分重叠。该第二部分10213可以用于作为像素电极与公共电极107形成电场，以共同驱动液晶偏转。
也即是，在本申请实施例的方案中，无需单独制备一像素电极，可以简化 阵列基板10的结构，减少制备该阵列基板10的制备成本。
对于图5所示的阵列基板10，该阵列基板10中第一绝缘层105不包括平坦层，因此为了保证该阵列基板10的平坦性，可以使得该第二绝缘层106包括：位于金属氧化物图案1021远离衬底基板101的一侧的第二钝化层1061，以及位于第二钝化层1061远离衬底基板101的一侧的平坦层1062。
该平坦层1062远离衬底基板101的一面为平面，且大致平行于衬底基板101的承载面。也即是，通过设置平坦层1062将阵列基板10中色阻块1031的周围填平，即可以平坦化具有色阻块1031的区域和不具有色阻块1031的区域。
对于图6所示的阵列基板10，该阵列基板10中第一绝缘层105包括平坦层1052，因此该阵列基板10的平坦性已经较好，该第二绝缘层106可以为位于金属氧化物图案1021远离衬底基板101的一侧的第三钝化层。
当然，由于图6所示的阵列基板10中，在平坦层1052远离衬底基板101的一侧还具有金属氧化物图案1021，该金属氧化物图案1021并不是整层覆盖，因此该金属氧化物图案1021也会影响阵列基板10的平坦性。由此，图6所示的阵列基板10的第二绝缘层106除了可以包括位于金属氧化物图案1021远离衬底基板101的一侧的第三钝化层之外，还可以包括位于第三钝化层远离衬底基板101的一侧的另一平坦层。公共电极107可以位于该另一平坦层远离衬底基板101的一侧。也即是，该方案中的阵列基板10可以包括两层平坦层。
在本申请实施例中，参考图7，该阵列基板10还可以包括：位于金属氧化物图案1021远离衬底基板101的一侧且沿远离衬底基板101的方向依次层叠的第三绝缘层108，像素电极109，第四绝缘层110以及公共电极107。该像素电极109在衬底基板101上的正投影，可以与公共电极107在衬底基板101上的正投影至少部分重叠。该像素电极109和公共电极107可以形成电场，以共同驱动液晶偏转。
其中，第三绝缘层108可以具有多个第二过孔，每个第二过孔可以用于露出一个氧化物薄膜晶体管102的第二部分10213的至少部分。像素电极109可以通过第二过孔与第二部分10213电连接，从而使得该第二部分10213为像素电极109提供驱动信号。
可选的，本申请实施例中的多个氧化物薄膜晶体管102中的每个氧化物薄膜晶体管102可以对应一个像素电极109。例如，像素电极109通过第二过孔与对应的氧化物薄膜晶体管102的第二部分10213电连接。
对于图7所示的阵列基板10，该阵列基板10中第一绝缘层105包括第一钝化层，不包括平坦层。因此为了保证该阵列基板10的平坦性，可以使得该第四绝缘层110包括：位于像素电极109远离衬底基板101的一侧的第二钝化层1101，以及位于第二钝化层1101远离衬底基板101的一侧的平坦层1102。
该平坦层1102远离衬底基板101的一面为平面，且大致平行于衬底基板101的承载面。也即是，通过设置平坦层1102将阵列基板10中具有色阻块1031的区域和不具有色阻块1031的区域进行平坦化。
在本申请实施例中，参考图5至图7，每个氧化物薄膜晶体管102还可以包括：位于显示区域101a的第一栅极(gate)图案1022。阵列基板10还可以包括：第五绝缘层111。该第一栅极图案1022可以位于金属氧化物图案1021与衬底基板101之间，第五绝缘层111可以位于第一栅极图案1022与金属氧化物图案1021之间。
其中，每个氧化物薄膜晶体管102中，第一栅极图案1022在衬底基板101上的正投影可以覆盖金属氧化物图案1021中沟道部分10212在衬底基板101上的正投影。也即是，沟道部分10212在衬底基板101上的正投影，位于第一栅极图案1022在衬底基板101上的正投影内。
可选的，该第一栅极图案1022的材料可以为氧化铟锡(Indium tin oxide，ITO)。
可选的，参考图5至图7，该阵列基板10还可以包括：多个扫描线112。该多个扫描线112沿像素行方向延伸。该多个扫描线112位于第一栅极图案1022靠近衬底基板101的一侧，且每个扫描线112与至少一个氧化物薄膜晶体管102的第一栅极图案1022的至少部分接触。每个扫描线112可以用于为接触的第一栅极图案1022所属的氧化物薄膜晶体管102提供扫描信号。像素列方向与像素行方向垂直。
示例的，阵列基板10可以包括沿像素行方向排列的多个第二目标氧化物薄膜晶体管，每个扫描线112与位于一行的多个第二目标氧化物薄膜晶体管中的第一栅极图案1022接触。
其中，第一栅极图案1022在衬底基板101上的正投影沿像素列方向的长度，大于扫描线112在衬底基板101上的正投影沿像素列方向的长度。以便该第一栅极图案1022在衬底基板101上的正投影覆盖金属氧化物图案1021中沟道部分10212在衬底基板101上的正投影。
该扫描线112的材料可以为不透光材料，该扫描线除了可以为氧化物薄膜晶体管102的第一栅极图案1022提供扫描信号之外，还可以作为氧化物薄膜晶体管的遮光层，保证背光的影响下，氧化物薄膜晶体管102的特性正常。
参考图2还可以看出，该衬底基板101还可以具有位于显示区域101a一侧的周边区域101b。图2中示出的周边区域101b位于显示区域101a的左侧，当然，周边区域101b也可以位于显示区域101a的右侧，本申请实施例对此不做限定。
可选的，该显示区域101a可以设置有多个子像素，每个子像素包括：发光单元以及像素电路。该阵列基板10中位于显示区域101a的氧化物薄膜晶体管102可以作为子像素的像素电路中的晶体管。并且，阵列基板10可以包括：驱动电路113。该驱动电路可以位于周边区域101b，且可以与多个子像素连接，为多个子像素提供驱动信号。例如，驱动电路可以与子像素的像素电路中的氧化物薄膜晶体管102连接，该驱动电路可以为行驱动电路(gate driver on array，GOA)。
示例的，位于周边区域101b的驱动电路113可以与多个扫描线112连接，多个扫描线112可以与位于显示区域101a的氧化物薄膜晶体管102连接。由此，驱动电路113可以通过该多个扫描线112为氧化物薄膜晶体管102提供扫描信号。
在本申请实施例中，参考图5至图7，该驱动电路113可以包括至少一个多晶硅薄膜晶体管1131。图5至图7中均示出了一个多晶硅薄膜晶体管1131。
由于多晶硅薄膜晶体管1131的驱动能力较好，因此将该驱动电路113中的晶体管设计为多晶硅薄膜晶体管1131，可以保证该驱动电路113对显示区域101a的驱动能力。
可选的，位于周边区域101b的驱动电路113除了包括至少一个多晶硅薄膜晶体管之外，还可以包括氧化物薄膜晶体管102。或者，位于周边区域101b的驱动电路可以不包括多晶硅薄膜晶体管，仅包括氧化物薄膜晶体管102。本申请实施例对驱动电路包括的晶体管的类型不做限定。
参考图5至图7，每个多晶硅薄膜晶体管1131可以包括：第二栅极图案11311和源漏极图案11312。其中，该第二栅极图案11311可以与多个扫描线112位于同层。例如，该第二栅极图案11311与多个扫描线112可以基于相同材料并采用同一次构图工艺制备得到。该源漏极图案11312可以与多个数据线104位于同 层。例如，该源漏极图案11312与多个数据线104可以基于相同材料并采用同一次构图工艺制备得到。
参考图5至图7，每个多晶硅薄膜晶体管还可以包括：有源图案11313。阵列基板10还可以包括：第六绝缘层114。该有源图案11313可以位于第二栅极图案11311与衬底基板101之间，第六绝缘层114可以位于有源图案11313与第二栅极图案11311之间。
其中，源漏极图案11312可以与有源图案11313电连接。源漏极图案11312可以包括间隔设置的源极(source，S)a1和漏极(drain，D)a2。源漏极图案11312与有源图案11313电连接可以是指：源极a1与有源图案11313电连接，且漏极a2与有源图案11313电连接。
参考图5至图7还可以看出，该阵列基板10还可以包括：缓冲层(buffer)115。该缓冲层115可以位于衬底基板101与氧化物薄膜晶体管102之间，且该缓冲层115的一面可以与衬底基板101的一面接触。
综上所述，本申请实施例提供了一种阵列基板，该阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离可以较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
图8是本申请实施例提供的一种阵列基板的制备方法的流程图。参考图8可以看出，该方法可以包括：
步骤201、提供一衬底基板。
该衬底基板101的材料可以为玻璃或聚酰亚胺等。参考图2，该衬底基板101可以具有显示区域101a。
步骤202、在显示区域形成间隔的多个氧化物薄膜晶体管以及彩膜层。
在本申请实施例中，可以在显示区域101a形成间隔的多个氧化物薄膜晶体管102以及彩膜层103。其中，每个氧化物薄膜晶体管102可以包括金属氧化物图案1021。该金属氧化物图案1021具有依次连接的第一部分10211，沟道部分10212以及第二部分10213。该第一部分10211用于接收信号。彩膜层103位于金属氧化物图案1021与衬底基板101之间。该彩膜层103包括与多个氧化物薄 膜晶体管102一一对应的不同颜色的多个色阻块1031。每个色阻块1031在衬底基板101上的正投影与对应的氧化物薄膜晶体管102中第二部分10213在衬底基板101上的正投影至少部分重叠。
由于色阻块1031与金属氧化物图案1021中第二部分10213至少部分重叠，因此可以减小金属氧化物图案1021和色阻块1031在衬底基板101上的整体占用空间，便于高PPI显示面板的实现。
可选的，彩膜层103包括的多个色阻块1031中相邻两个色阻块1031的颜色可以不同。在本申请实施例中，由于制备得到的阵列基板包括彩膜层103，因此位于衬底基板101远离彩膜层103的一侧的光源与彩膜层103之间的距离可以较近，可以避免彩膜层103中每个色阻块1031所在区域的光线从相邻色阻块1031射出，进而避免显示面板出现串色现象，保证显示面板的显示效果。
综上所述，本申请实施例提供了一种阵列基板的制备方法，该方法制备得到的阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
图9是本申请实施例提供的另一种阵列基板的制备方法的流程图。该方法可以用于制备上述实施例提供的阵列基板，例如以制备图5所示的阵列基板为例。参考图9，该方法可以包括：
步骤301、提供一衬底基板。
该衬底基板101的材料可以为玻璃或聚酰亚胺等。参考图2，该衬底基板101可以具有显示区域101a以及位于显示区域101a一侧的周边区域101b。图2中示出的周边区域101b位于显示区域101a的左侧，当然，周边区域101b也可以位于显示区域101a的右侧，本申请实施例对此不做限定。
步骤302、在衬底基板的一侧形成缓冲层。
在本申请实施例中，在获取衬底基板101之后，可以在该衬底基板101的一侧形成缓冲层115。该缓冲层115的作用是降低衬底基板101对后续形成的其他膜层的冲击力，便于后续其他膜层的形成。
步骤303、在缓冲层远离衬底基板的一侧形成多个多晶硅薄膜晶体管的有源 图案。
在本申请实施例中，在形成有缓冲层之后，可以在该缓冲层远离衬底基板101的一侧形成有源薄膜，然后对该有源薄膜进行结晶化处理。之后，对结晶化处理后的有源薄膜远离衬底基板101的一侧设置一图案化掩膜板，并对该结晶化处理后的有源薄膜进行图案化处理以得到多个多晶硅薄膜晶体管的有源图案11313。其中，图案化处理可以包括：光刻胶涂覆，曝光，显影，刻蚀以及去除光刻胶。
可选的，有源薄膜的材料可以为非晶硅(a硅)，结晶化处理后的有源薄膜的材料可以为低温多晶硅(low temperature ploy silicon，LTPS)。其中，该低温多晶硅也可以称为p硅。
该多个多晶硅薄膜晶体管可以作为驱动电路中的晶体管，即驱动电路可以包括多个多晶硅薄膜晶体管，该多个多晶硅薄膜晶体管可以位于周边区域101b。或者，位于周边区域101b的驱动电路除了包括多晶硅薄膜晶体管之外，还可以包括氧化物薄膜晶体管102。又或者，位于周边区域101b的驱动电路可以仅包括氧化物薄膜晶体管102，本申请实施例对此不做限定。其中，本申请实施例以驱动电路中的晶体管为多晶硅薄膜晶体管，显示区域101a的晶体管为氧化物薄膜晶体管102为例对阵列基板的制备方法进行说明。
步骤304、在多个多晶硅薄膜晶体管的有源图案远离衬底基板的一侧形成第六绝缘层。
在本申请实施例中，在形成多晶硅薄膜晶体管的有源图案11313之后，可以在多个多晶硅薄膜晶体管的有源图案11313远离衬底基板101的一侧形成第六绝缘层114。其中，该第六绝缘层114还可以称为栅极绝缘层。
步骤305、在第六绝缘层远离衬底基板的一侧形成多个扫描线，以及多个多晶硅薄膜晶体管的第二栅极图案。
在本申请实施例中，参考图10，在形成第六绝缘层114之后，可以在该第六绝缘层114远离衬底基板101的一侧形成多个扫描线112，以及多个多晶硅薄膜晶体管的第二栅极图案11311。也即是，该多个扫描线112和多个多晶硅薄膜晶体管的第二栅极图案11311位于同层，且可以采用一次构图工艺制备得到。可选的，多个扫描线112，以及多个多晶硅薄膜晶体管的第二栅极图案11311的材料均包括导电材料，例如可以包括金属材料。
在制备多个扫描线112，以及多个多晶硅薄膜晶体管的第二栅极图案11311 时，可以先在第六绝缘层114远离衬底基板101的一侧形成一第一导电薄膜，并在该第一导电薄膜远离衬底基板101的一侧设置一图案化掩膜板，并对该第一导电薄膜进行图案化处理以得到多个扫描线112以及多晶硅薄膜晶体管的第二栅极图案11311。其中，对该第一导电薄膜进行图案化处理所采用的图案化掩膜板，与对结晶化处理后的有源薄膜进行图案化处理所采用的图案化掩膜板为不同的掩膜板。
由于多个扫描线112和多个多晶硅薄膜晶体管的第二栅极图案11311采用一次构图工艺制备得到，因此仅需采用一个图案化掩膜板即可同时制备得到多个扫描线112和多个多晶硅薄膜晶体管的第二栅极图案11311，能够减少制备该阵列基板所需的掩膜板的数量，降低制备成本。
图11是本申请实施例提供的一种扫描线的示意图。参考图11，该多个扫描线112可以位于衬底基板101的显示区域101a，且沿像素行方向X延伸。图11中示出了两个扫描线112。
该多个扫描线112可以用于为显示区域101a后续形成的氧化物薄膜晶体管102提供扫描信号。示例的，位于周边区域101b的驱动电路可以与多个扫描线112连接，驱动电路可以通过该多个扫描线112为后续形成的氧化物薄膜晶体管102提供扫描信号。
可选的，该扫描线112沿像素列方向Y的长度(即扫描线112的宽度)的范围为1.5微米至2.5微米，例如为1.8微米。
步骤306、在多个扫描线远离衬底基板的一侧形成多个氧化物薄膜晶体管的第一栅极图案。
在本申请实施例中，多个氧化物薄膜晶体管102的第一栅极图案1022的材料可以包括导电材料，例如可以包括金属材料。在形成多个扫描线112之后，可以在该多个扫描线112远离衬底基板101的一侧形成第一栅极薄膜，然后在该第一栅极薄膜远离衬底基板101的一侧设置一图案化掩膜板，并对该第一栅极薄膜进行图案化处理以得到多个氧化物薄膜晶体管102的第一栅极图案1022。其中，对不同薄膜进行图案化所采用的图案化掩膜板不同。例如对该第一栅极薄膜进行图案化处理所采用的图案化掩膜板，对第一导电薄膜进行图案化处理所采用的图案化掩膜板，以及对结晶化处理后的有源薄膜进行图案化处理所采用的图案化掩膜板均为不同的掩膜板。
图12是本申请实施例提供的一种形成第一栅极图案的示意图。参考图12， 该第一栅极图案1022在衬底基板101上的正投影沿像素列方向Y的长度，可以大于扫描线112在衬底基板101上的正投影沿像素列方向Y的长度，以便该第一栅极图案1022在衬底基板101上的正投影覆盖后续形成的金属氧化物图案1021中沟道部分10212在衬底基板101上的正投影。像素列方向Y与像素行方向X垂直。
步骤307、在第一栅极图案和第二栅极图案远离衬底基板的一侧形成第五绝缘层。
在本申请实施例中，在形成第一栅极图案1022之后，可以在第一栅极图案1022和第二栅极图案11311远离衬底基板101的一侧形成第五绝缘层111。该第五绝缘层111在衬底基板101上的正投影可以覆盖多个氧化物薄膜晶体管102的第一栅极图案1022在衬底基板101上的正投影，且覆盖多个多晶硅薄膜晶体管1131的第二栅极图案11311在衬底基板101上的正投影。
可选的，该第五绝缘层111可以称为层间介电层(inter layer dielectric，ILD)。该第五绝缘层111的材料可以包括二氧化硅以及氮化硅中的至少一种。其中，由于该第五绝缘层111整层覆盖衬底基板101，因此未采用俯视图示出。
步骤308、在第五绝缘层远离衬底基板的一侧形成多个数据线，以及多个多晶硅薄膜晶体管的源漏极图案。
在本申请实施例中，参考图13，在形成第五绝缘层111之后，可以在该第五绝缘层111远离衬底基板101的一侧形成多个数据线104，以及多个多晶硅薄膜晶体管1131的源漏极图案11312。也即是，该多个数据线104和多个多晶硅薄膜晶体管的源漏极图案11312位于同层，且可以采用一次构图工艺制备得到。可选的，多个数据线104，以及多个多晶硅薄膜晶体管1131的源漏极图案11312的材料均包括导电材料，例如可以包括金属材料。
在制备多个数据线104，以及多个多晶硅薄膜晶体管1131的源漏极图案11312时，可以先在第一绝缘层105远离衬底基板101的一侧形成一第二导电薄膜，并在该第二导电薄膜远离衬底基板101的一侧设置一图案化掩膜板，并对该第二导电薄膜进行图案化处理以得到多个数据线104以及多晶硅薄膜晶体管1131的源漏极图案11312。
由于多个数据线104和多个多晶硅薄膜晶体管1131的源漏极图案11312采用一次构图工艺制备得到，因此仅需采用一个图案化掩膜板即可同时制备得到多个数据线104和多个多晶硅薄膜晶体管的源漏极图案11312，能够减少制备该 阵列基板所需的掩膜板的数量，降低制备成本。
图14是本申请实施例提供的一种形成数据线的示意图。参考图14，该多个数据线104可以位于衬底基板101的显示区域101a，且沿像素列方向Y延伸，用于为显示区域101a后续形成的氧化物薄膜晶体管102的金属氧化物图案1021的第一部分10211提供数据信号。
在本申请实施例中，多晶硅薄膜晶体管1131的源漏极图案11312可以与有源图案11313电连接。例如，多晶硅薄膜晶体管1131的源漏极图案11312可以包括间隔设置的源极a1和漏极a2，第五绝缘层111以及第六绝缘层114中均具有第三过孔以及第四过孔。源极a1可以通过第三过孔与有源图案11313电连接，漏极a2可以通过第四过孔与有源图案11313电连接。
步骤309、在多个数据线和源漏极图案远离衬底基板的一侧形成绝缘材料层。
在本申请实施例中，在制备得到多个数据线104以及源漏极图案11312之后，可以在该多个数据线104以及源漏极图案11312远离衬底基板101的一侧形成绝缘材料层c。该绝缘材料层的材料可以包括二氧化硅(SiO 2)。其中，由于该绝缘材料层为整层覆盖衬底基板101，因此未采用俯视图示出该绝缘材料层。
步骤310、在绝缘材料层远离衬底基板的一侧形成彩膜层。
在本申请实施例中，参考图15，在形成绝缘材料层之后，可以在该绝缘材料层远离衬底基板101的一侧形成彩膜层103。该彩膜层103包括与多个氧化物薄膜晶体管102一一对应的不同颜色的多个色阻块1031。每个色阻块1031可以用于透过对应颜色的光线。
可选的，该彩膜层103可以包括多个红色色阻块，多个绿色色阻块以及多个蓝色色阻块。该红色色阻块可以用于透过红色的光线，绿色色阻块可以用于透过绿色的光线，蓝色色阻块可以用于透过蓝色的光线。
在本申请实施例中，彩膜层103包括的多个红色色阻块可以采用同一次构图工艺制备得到。彩膜层103包括的多个绿色色阻块可以采用同一次构图工艺制备得到。彩膜层103包括的多个蓝色色阻块可以采用同一次构图工艺制备得到。并且，不同颜色的色阻块采用不同的构图工艺制备。也即是，多个红色色阻块1031，多个绿色色阻块，以及多个蓝色色阻块采用三次构图工艺分别制备。
可选的，每种颜色的色阻块1031在制备时，先整层涂覆该颜色的色阻薄膜， 然后在该色阻薄膜远离衬底基板101的一侧设置一图案化掩膜板，并对该色阻薄膜进行图案化处理以得到多个该颜色的色阻块1031。其中，制备不同颜色的色阻块1031所采用的图案化掩膜板不同。
由于三种颜色的色阻块1031分别采用三次构图工艺制备，因此三种颜色的色阻块1031的厚度会存在差异，进而可能导致显示面板中不同颜色的子像素的显示存在一定的差异性。由此，在后续阵列基板制备完成之后，可以在产品调试过程中，通过调整提供给不同颜色的子像素的驱动电压，调整子像素的亮度，进而通过光学校准进行显示修正。
其中，显示面板中的每个子像素包括：像素电路。该阵列基板10包括的氧化物薄膜晶体管102可以作为子像素的像素电路中的晶体管。即该阵列基板10包括的氧化物薄膜晶体管102可以位于衬底基板101的显示区域101a。并且，每个子像素包括一个色阻块1031，用于发出色阻块1031对应的颜色的光线。
步骤311、对绝缘材料层进行刻蚀，得到形成有多个第一过孔的第一绝缘层。
由于阵列基板的显示区域101a具有多个氧化物薄膜晶体管102，因此参考图16和图17，可以对该绝缘材料层进行刻蚀，以得到形成有多个第一过孔105a的第一绝缘层105。其中，对绝缘材料层进行刻蚀的刻蚀工艺可以为干法刻蚀或者湿法刻蚀。该第一绝缘层105中的每个第一过孔105a可以用于露出一个数据线104的至少部分。
在本申请实施例中，为了便于示出第一绝缘层105中的第一过孔105a，图17中采用填充图案表示第一过孔105a。其他未绘制填充图案的区域用于表示第一绝缘层105具有实材的区域。
步骤312、在第一绝缘层远离衬底基板的一侧形成金属氧化物薄膜。
在本申请实施例中，在形成第一绝缘层105之后，可以采用金属氧化物材料在该第一绝缘层105远离衬底基板101的一侧形成金属氧化物薄膜。该金属氧化物薄膜的材料包括金属氧化物。
步骤313、对金属氧化物薄膜进行图案化处理，得到金属氧化物结构。
在本申请实施例中，在形成金属氧化物薄膜之后，可以在该金属氧化物薄膜远离衬底基板101的一侧设置图案化掩膜板，并对该金属氧化物薄膜进行图案化处理以得到金属氧化物结构，例如参考图18，可以得到多个金属氧化物结构b。其中，本申请实施例中对不同薄膜进行图案化处理所采用的图案化掩膜板不同。
可选的，参考图18，沿像素列方向Y相邻的两个金属氧化物结构b之间的距离d1可以为2.5微米。金属氧化物结构的第一区域b1与扫描线112沿像素列方向Y的距离d4可以为0.9微米。金属氧化物结构的第三区域b3具有第一子区域和第二子区域，该第一子区域沿像素行方向X的长度，大于第二子区域沿像素行方向X的长度。该第一子区域沿像素列方向Y的长度可以为9.6微米。该第二子区域与扫描线112沿像素列方向Y的距离d3可以为0.9微米。也即是，距离d3可以与距离d4相等，当然，距离d3与距离d4也可以不相等，本申请实施例对此不做限定。
步骤314、在金属氧化物结构的远离衬底基板的一侧的第一区域涂覆光刻胶。
参考图19和图20，涂覆的光刻胶在衬底基板101上的正投影位于第一栅极图案1022在衬底基板101上的正投影内。该金属氧化物结构b远离衬底基板101的一侧还包括第二区域b2和第三区域b3。该第二区域b2和第三区域b3分别位于第一区域b1的两侧。
步骤315、对金属氧化物结构远离衬底基板的一侧的第二区域和第三区域进行导体化处理，得到金属氧化物图案的第一部分和第二部分。
在本申请实施例中，在第一区域b1涂覆光刻胶之后，参考图21，向金属氧化物结构b注入离子(即离子掺杂)，以对未涂覆光刻胶的第二区域b2和第三区域b3进行导体化处理，得到金属氧化物图案1021的第一部分10211和第二部分10213。其中，注入的离子可以为硼离子或者磷离子。
若上述步骤314涂覆的光刻胶在衬底基板101上的正投影的面积大于第一栅极图案1022在衬底基板101上的正投影的面积，则参考图22，在对第二区域b2和第三区域b3导体化处理之后，除沟道部分之外，还存在部分区域未被导体化。此种情况会在氧化物薄膜晶体管102工作时形成高阻区，影响氧化物薄膜晶体管的特性。
因此本申请实施例中，涂覆的光刻胶在衬底基板101上的正投影的面积位于第一栅极图案1022在衬底基板101上的正投影的面积内，可以保证氧化物薄膜晶体管的正常工作，即保证氧化物薄膜晶体管的特性。
步骤316、去除光刻胶，得到金属氧化物图案的沟道部分。
在本申请实施例中，参考图23，在对金属氧化物结构远离衬底基板101的一侧的第二区域b2和第三区域b3进行导体化处理之后，可以将该金属氧化物 结构b远离衬底基板101的一侧的第一区域的光刻胶去除，以得到金属氧化物图案1021的沟道部分10212。也即是，得到氧化物薄膜晶体管10的金属氧化物图案1021。
步骤317、在金属氧化物结构远离衬底基板的一侧形成第二绝缘层。
在本申请实施例中，在形成金属氧化物图案1021之后，可以在该金属氧化物图案1021远离衬底基板101的一侧形成第二绝缘层106。其中，该第二绝缘层106可以包括沿远离衬底基板101的方向层叠的第二钝化层1061和平坦层1062。
参考图5还可以看出，第二钝化层1061覆盖色阻块1031的部分远离衬底基板101的一面可以与平坦层1062远离衬底基板101的一面共面。当然，第二钝化层1061覆盖色阻块1031的部分远离衬底基板101的一面也可以与平坦层1062远离衬底基板101的一面不共面。例如，平坦层1062远离衬底基板101的一面与衬底基板101之间的距离，可以大于第二钝化层1061覆盖色阻块1031的部分远离衬底基板101的一面与衬底基板101之间的距离，本申请实施例对此不做限定。
可选的，该第二钝化层1061和平坦层1062可以整层覆盖，因此未采用俯视图示出该第二钝化层1061和平坦层1062。该平坦层1062的厚度范围为1微米至2微米。
步骤318、在第二绝缘层远离衬底基板的一侧形成公共电极。
在本申请实施例中，参考图24，在形成第二绝缘层106之后，可以在该第二绝缘层106远离衬底基板101的一侧形成公共电极107。该公共电极107在衬底基板101上的正投影与金属氧化物图案1021中的第三部分10213在衬底基板101上的正投影至少部分重叠。该第三部分10313用于作为像素电极与公共电极107共同驱动液晶偏转。
需要说明的是，本申请实施例提供的阵列基板的制备方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。例如，步骤302至步骤309，步骤311，以及步骤317至步骤318可以根据情况删除，步骤311可以在步骤310之前执行。任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供了一种阵列基板的制备方法，该方法制备得 到的阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
图25是本申请实施例提供的又一种阵列基板的制备方法的流程图。该方法可以用于制备上述实施例提供的阵列基板，例如以制备图7所示的阵列基板为例。参考图25，该方法可以包括：
步骤401、提供一衬底基板。
在本申请实施例中，步骤401的详细内容可以参考上述步骤301的内容，本申请实施例在此不再赘述。
步骤402、在衬底基板的一侧形成缓冲层。
在本申请实施例中，步骤402的详细内容可以参考上述步骤302的内容，本申请实施例在此不再赘述。
步骤403、在缓冲层远离衬底基板的一侧形成多个多晶硅薄膜晶体管的有源图案。
在本申请实施例中，步骤403的详细内容可以参考上述步骤303的内容，本申请实施例在此不再赘述。
步骤404、在多个多晶硅薄膜晶体管的有源图案远离衬底基板的一侧形成第六绝缘层。
在本申请实施例中，步骤404的详细内容可以参考上述步骤304的内容，本申请实施例在此不再赘述。
步骤405、在第六绝缘层远离衬底基板的一侧形成多个扫描线，以及多个多晶硅薄膜晶体管的第二栅极图案。
在本申请实施例中，步骤405的详细内容可以参考上述步骤305的内容，本申请实施例在此不再赘述。
步骤406、在多个扫描线远离衬底基板的一侧形成多个氧化物薄膜晶体管的第一栅极图案。
在本申请实施例中，步骤406的详细内容可以参考上述步骤306的内容，本申请实施例在此不再赘述。
步骤407、在第一栅极图案和第二栅极图案远离衬底基板的一侧形成第五绝缘层。
在本申请实施例中，步骤407的详细内容可以参考上述步骤307的内容，本申请实施例在此不再赘述。
步骤408、在第五绝缘层远离衬底基板的一侧形成多个数据线，以及多个多晶硅薄膜晶体管的源漏极图案。
在本申请实施例中，步骤408的详细内容可以参考上述步骤308的内容，本申请实施例在此不再赘述。
步骤409、在多个数据线和源漏极图案远离衬底基板的一侧形成绝缘材料层。
在本申请实施例中，步骤409的详细内容可以参考上述步骤309的内容，本申请实施例在此不再赘述。
步骤410、在绝缘材料层远离衬底基板的一侧形成彩膜层。
在本申请实施例中，步骤410的详细内容可以参考上述步骤310的内容，本申请实施例在此不再赘述。
步骤411、对绝缘材料层进行刻蚀，得到形成有多个第一过孔的第一绝缘层。
在本申请实施例中，步骤411的详细内容可以参考上述步骤311的内容，本申请实施例在此不再赘述。
步骤412、在第一绝缘层远离衬底基板的一侧形成金属氧化物薄膜。
在本申请实施例中，步骤412的详细内容可以参考上述步骤312的内容，本申请实施例在此不再赘述。
步骤413、对金属氧化物薄膜进行图案化处理，得到金属氧化物结构。
在本申请实施例中，步骤413的详细内容可以参考上述步骤313的内容，本申请实施例在此不再赘述。并且，由于本方法制备得到的阵列基板10中的金属氧化物图案不是作为像素电极，因此该步骤413中得到的用于制备金属氧化物图案的金属氧化物结构在衬底基板101上的正投影的面积，可以小于步骤313中得到的用于制备金属氧化物图案的金属氧化物结构在衬底基板101上的正投影的面积。
示例的，参考图26，该金属氧化物结构b沿像素列方向Y的长度可以较小，只需使得后续形成的像素电极能够与金属氧化物图案的第二部分电连接即可。
步骤414、在金属氧化物结构的远离衬底基板的一侧的第一区域涂覆光刻 胶。
在本申请实施例中，参考图27，涂覆的光刻胶在衬底基板101上的正投影位于第一栅极图案1022在衬底基板101上的正投影内。该金属氧化物结构b远离衬底基板101的一侧还包括第二区域b2和第三区域b3。该第二区域b2和第三区域b3分别位于第一区域b1的两侧。
步骤415、对金属氧化物结构远离衬底基板的一侧的第二区域和第三区域进行导体化处理，得到金属氧化物图案的第一部分和第二部分。
步骤415的详细内容可以参考上述步骤315的内容，本申请实施例在此不再赘述。
步骤416、去除光刻胶，得到金属氧化物图案的沟道部分。
图28是本申请实施例提供的另一种得到金属氧化物图案的示意图。并且，步骤416的详细内容可以参考上述步骤316的内容，本申请实施例在此不再赘述。
步骤417、在金属氧化物结构远离衬底基板的一侧形成第三绝缘层。
在本申请实施例中，参考图29和图30，在形成金属氧化物图案1021之后，可以在该金属氧化物图案1021远离衬底基板101的一侧形成第三绝缘层108。其中，该第三绝缘层108可以为钝化层(passivation，PVX)。可选的，第二绝缘层106的材料可以包括二氧化硅。
参考图29，该第三绝缘层108可以与第二部分10213接触，且该第三绝缘层108可以具有多个第二过孔108a，每个第二过孔108a可以用于露出一个氧化物薄膜晶体管102的第二部分10213的至少部分。
在本申请实施例中，为了便于示出第三绝缘层108中的第二过孔108a，图28中采用填充图案表示第二过孔108a。其他未绘制填充图案的区域用于表示第三绝缘层108具有实材的区域。
步骤418、在第三绝缘层远离衬底基板的一侧形成像素电极。
在本申请实施例中，参考图31，在形成第三绝缘层108之后，可以在该第三绝缘层108远离衬底基板101的一侧形成像素电极109。该像素电极109在衬底基板101上的正投影与第二过孔108a在衬底基板101上的正投影至少部分重叠，该像素电极109通过第二过孔108a与氧化物薄膜晶体管102的第二部分10213电连接。
步骤419、在像素电极远离衬底基板的一侧形成第四绝缘层。
在本申请实施例中，在形成像素电极109之后，可以在该像素电极109远离衬底基板101的一侧形成第四绝缘层110。其中，该第四绝缘层110可以为平坦层(planarization layer，PLN)。该平坦层可以用于平坦化衬底基板101设置有膜层的一侧。
步骤420、在第四绝缘层远离衬底基板的一侧形成公共电极。
在本申请实施例中，参考图32，在形成第四绝缘层110之后，可以在该第四绝缘层110远离衬底基板101的一侧形成公共电极107。该公共电极107在衬底基板101上的正投影与像素电极109在衬底基板101上的正投影至少部分重叠。该导像素电极109与公共电极107共同驱动液晶偏转。
需要说明的是，本申请实施例提供的阵列基板的制备方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。例如，步骤402至步骤409，步骤411，以及步骤417至步骤418可以根据情况删除，步骤411可以在步骤410之前执行。任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供了一种阵列基板的制备方法，该方法制备得到的阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
图33是本申请实施例提供的再一种阵列基板的制备方法的流程图。该方法可以用于制备上述实施例提供的阵列基板，例如以制备图6所示的阵列基板为例。参考图33，该方法可以包括：
步骤501、提供一衬底基板。
在本申请实施例中，步骤501的详细内容可以参考上述步骤301的内容，本申请实施例在此不再赘述。
步骤502、在衬底基板的一侧形成缓冲层。
在本申请实施例中，步骤502的详细内容可以参考上述步骤302的内容，本申请实施例在此不再赘述。
步骤503、在缓冲层远离衬底基板的一侧形成多个多晶硅薄膜晶体管的有源图案。
在本申请实施例中，步骤503的详细内容可以参考上述步骤303的内容，本申请实施例在此不再赘述。
步骤504、在多个多晶硅薄膜晶体管的有源图案远离衬底基板的一侧形成第六绝缘层。
在本申请实施例中，步骤504的详细内容可以参考上述步骤304的内容，本申请实施例在此不再赘述。
步骤505、在第六绝缘层远离衬底基板的一侧形成多个扫描线以及多个多晶硅薄膜晶体管的第二栅极图案。
在本申请实施例中，步骤505的详细内容可以参考上述步骤305的内容，本申请实施例在此不再赘述。
步骤506、在多个扫描线远离衬底基板的一侧形成多个氧化物薄膜晶体管的第一栅极图案。
在本申请实施例中，步骤506的详细内容可以参考上述步骤306的内容，本申请实施例在此不再赘述。
步骤507、在第一栅极图案和第二栅极图案远离衬底基板的一侧形成第五绝缘层。
在本申请实施例中，步骤507的详细内容可以参考上述步骤307的内容，本申请实施例在此不再赘述。
步骤508、在第五绝缘层远离衬底基板的一侧形成多个数据线，以及多个多晶硅薄膜晶体管的源漏极图案。
在本申请实施例中，步骤508的详细内容可以参考上述步骤308的内容，本申请实施例在此不再赘述。
步骤509、在多个数据线和源漏极图案远离衬底基板的一侧形成第一绝缘层中的第一钝化层。
在本申请实施例中，该形成多个数据线和源漏极图案之后，可以在该多个数据线和源漏极图案远离衬底基板的一侧形成第一绝缘层105的第一钝化层1051。
步骤510、在第一绝缘层中的第一钝化层远离衬底基板的一侧形成彩膜层。
在本申请实施例中，步骤510的详细内容可以参考上述步骤310的内容， 本申请实施例在此不再赘述。
步骤511、在彩膜层远离衬底基板的一侧形成第一绝缘层中的平坦层。
在形成彩膜层103之后，为了平坦化衬底基板101上形成的膜层，可以在该彩膜层远离衬底基板101的一侧形成第一绝缘层105中的平坦层1052。
步骤512、在第一绝缘层中的平坦层远离衬底基板的一侧形成第一绝缘层中的第二钝化层。
在本申请实施例中，为了避免在后续退火过程中，平坦层1052中的氢元素扩散至后续形成的金属氧化物图案的沟道部分，导致该沟道部分被导体化，因此在该在形成第一绝缘层105中的平坦层1052之后，可以在该平坦层1052远离衬底基板101的一侧形成第一绝缘层105中的第二钝化层1053。该第二钝化层1053中不具有氢元素，不会对金属氧化物图案的沟道部分造成影响。
参考图34，该第一绝缘层105具有多个第一过孔105a，每个第一过孔105a可以用于露出一个数据线104的至少部分，以便后续形成的金属氧化物图案1021的第一部分10211通过该第一过孔105a与数据线104电连接。由于该第一绝缘层105包括：第一钝化层1051，平坦层1052以及第二平坦层1053，因此该第一钝化层1051，平坦层1052以及第二平坦层1053均具有多个第一过孔105a。
步骤513、在第一绝缘层中的第二钝化层远离衬底基板的一侧形成金属氧化物薄膜。
在形成第二钝化层之后，可以在该第二钝化层远离衬底基板101的一侧形成金属氧化物薄膜。该金属氧化物薄膜的材料包括金属氧化物。
步骤514、对金属氧化物薄膜进行图案化处理，得到金属氧化物结构。
在本申请实施例中，步骤514的详细内容可以参考上述步骤313的内容，本申请实施例在此不再赘述。
步骤515、在金属氧化物结构的远离衬底基板的一侧的第一区域涂覆光刻胶。
在本申请实施例中，步骤515的详细内容可以参考上述步骤314的内容，本申请实施例在此不再赘述。
步骤516、对金属氧化物结构远离衬底基板的一侧的第二区域和第三区域进行导体化处理，得到金属氧化物图案的第一部分和第二部分。
在本申请实施例中，步骤516的详细内容可以参考上述步骤315的内容，本申请实施例在此不再赘述。
步骤517、去除光刻胶，得到金属氧化物图案的沟道部分。
在本申请实施例中，步骤517的详细内容可以参考上述步骤316的内容，本申请实施例在此不再赘述。
步骤518、在金属氧化物结构远离衬底基板的一侧形成第二绝缘层。
在本申请实施例中，由于形成的第一绝缘层105包括位于金属氧化物图案1021与彩膜层103之间的平坦层1052，因此阵列基板10平坦性较好，该第二绝缘层106可以为位于金属氧化物图案1021远离衬底基板101的一侧的第三钝化层。
当然，第二绝缘层106除了可以包括位于金属氧化物图案1021远离衬底基板101的一侧的第三钝化层之外，还可以包括位于第三钝化层远离衬底基板101的一侧的另一平坦层。也即是，该方案中的阵列基板10可以包括两层平坦层。
步骤519、在第二绝缘层远离衬底基板的一侧形成公共电极。
在本申请实施例中，步骤519的详细内容可以参考上述步骤318的内容，本申请实施例在此不再赘述。
需要说明的是，本申请实施例提供的阵列基板的制备方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。例如，步骤302至步骤409，步骤411，以及步骤417至步骤418可以根据情况删除，步骤411可以在步骤410之前执行。任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供了一种阵列基板的制备方法，该方法制备得到的阵列基板中包括彩膜层，因此位于衬底基板远离彩膜层的一侧的光源与彩膜层之间的距离较近，可以避免每个色阻块所在区域的光线从相邻色阻块射出，进而避免显示面板出现串色现象，显示面板的显示效果较好。并且，色阻块与氧化物薄膜晶体管中金属氧化物图案的第二部分至少部分重叠，可以减小该氧化物薄膜晶体管和彩膜层的占用空间，便于高像素密度显示面板的实现。
图35是本申请实施例提供的一种显示面板的结构示意图。参考图35可以看出，该显示面板00可以包括：盖板60，液晶层70，以及如上述实施例提供的阵列基板10。例如，显示面板00中的阵列基板10可以为图5至图7任一所示的阵列基板。其中，液晶层70可以位于盖板60和阵列基板10之间。
对于图5和图6所示的阵列基板，该阵列基板10中金属氧化物结构1021的第二部分10213和公共电极107共同驱动液晶层70中的液晶偏转。
对于图7所示的阵列基板，该阵列基板10中像素电极109和公共电极107共同驱动液晶层70中的液晶偏转。
若显示面板中阵列基板的平坦性较差(例如平坦层存在较深的过孔)，则会导致阵列基板10各个区域的液晶排布和电场异常，进而导致显示面板对应区域的显示异常。由此为了保证显示面板的显示效果，需要在该盖板的一侧设置较大尺寸的黑矩阵，该黑矩阵在阵列基板上的正投影覆盖平坦性较差的区域(例如覆盖平坦层的过孔)。此种方案会导致像素的有效开口率较低。
而在本申请实施例中，参考图5至图7，阵列基板10的平坦性较好，可以保证位于该阵列基板10的一侧的液晶层70的平整性，进而可以保证阵列基板10各个区域的液晶排布和电场的一致性，无需设计较大尺寸的黑矩阵，能够在避免降低像素的开口率的前提下，保证显示面板的显示效果。
图36是本申请实施例提供的一种显示装置的结构示意图。参考图36可以看出，该显示装置可以包括：供电组件002和上述实施例提供的显示面板001。该供电组件002用于为显示面板001供电。
可选的，该显示装置可以为虚拟现实(virtual reality，VR)设备或者为增强现实(augmented reality，AR)设备。当然，该显示装置还可以为电子纸，手机，平板电脑，电视机，显示器，笔记本电脑，数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：
    衬底基板，所述衬底基板具有显示区域；
    位于所述显示区域的间隔的多个氧化物薄膜晶体管，每个所述氧化物薄膜晶体管包括金属氧化物图案，所述金属氧化物图案具有依次连接的第一部分，沟道部分，以及第二部分，所述第一部分用于接收数据信号；
    以及，位于所述显示区域的彩膜层，所述彩膜层位于所述金属氧化物图案与所述衬底基板之间，所述彩膜层包括与所述多个氧化物薄膜晶体管一一对应的不同颜色的多个色阻块，每个所述色阻块在所述衬底基板上的正投影与对应的所述氧化物薄膜晶体管中所述第二部分在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述第一部分的导电性和所述第二部分的导电性均大于所述沟道部分的导电性。
  3. 根据权利要求1或2所述的阵列基板，其特征在于，所述阵列基板还包括：多个数据线以及第一绝缘层；
    所述多个数据线位于所述金属氧化物图案与所述衬底基板之间，所述第一绝缘层位于所述多个数据线与所述金属氧化物图案之间，且所述第一绝缘层具有多个第一过孔；
    其中，每个所述数据线通过至少一个所述第一过孔与至少一个所述氧化物薄膜晶体管的所述第一部分电连接。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述第一绝缘层为位于所述多个数据线和所述彩膜层之间的第一钝化层；
    其中，所述第二部分的目标部分靠近所述衬底基板的一面与所述衬底基板之间的距离，大于所述第一部分靠近所述衬底基板的一面与所述衬底基板之间的距离，且大于所述沟道部分靠近所述衬底基板的一面与所述衬底基板之间的距离，所述目标部分为所述第二部分在所述衬底基板上的正投影中与所述色阻块在所述衬底基板上的正投影重叠的部分。
  5. 根据权利要求3所述的阵列基板，其特征在于，所述第一绝缘层包括：位于所述多个数据线和所述彩膜层之间的第一钝化层，位于所述彩膜层和所述金属氧化物图案之间的平坦层，以及位于所述平坦层和所述金属氧化物图案的第二钝化层。
  6. 根据权利要求1至5任一所述的阵列基板，其特征在于，所述阵列基板还包括：位于所述第二部分远离所述衬底基板的一侧的第二绝缘层，以及位于所述第二绝缘层远离所述衬底基板的一侧的公共电极；
    其中，所述公共电极在所述衬底基板上的正投影，与所述第二部分在所述衬底基板上的正投影至少部分重叠，所述第二部分用于作为像素电极与所述公共电极共同驱动液晶偏转。
  7. 根据权利要求1至5任一所述的阵列基板，其特征在于，所述阵列基板还包括：位于所述金属氧化物图案远离所述衬底基板的一侧且沿远离所述衬底基板的方向依次层叠的第三绝缘层，像素电极，第四绝缘层以及公共电极，所述像素电极在所述衬底基板上的正投影，与所述公共电极在所述衬底基板上的正投影至少部分重叠；
    其中，所述第三绝缘层具有多个第二过孔，每个所述第二过孔用于露出一个所述氧化物薄膜晶体管的所述第二部分的至少部分，所述像素电极通过所述第二过孔与所述第二部分电连接。
  8. 根据权利要求1至7任一所述的阵列基板，其特征在于，每个所述氧化物薄膜晶体管还包括：位于所述显示区域的第一栅极图案；所述阵列基板还包括：第五绝缘层；所述第一栅极图案位于所述金属氧化物图案与所述衬底基板之间，所述第五绝缘层位于所述第一栅极图案与所述金属氧化物图案之间；
    其中，每个所述氧化物薄膜晶体管中，所述第一栅极图案在所述衬底基板上的正投影覆盖所述金属氧化物图案中所述沟道部分在所述衬底基板上的正投影。
  9. 根据权利要求8所述的阵列基板，其特征在于，所述阵列基板还包括：沿像素行方向延伸的多个扫描线；
    所述多个扫描线位于所述第一栅极图案靠近所述衬底基板的一侧，且每个所述扫描线与至少一个所述氧化物薄膜晶体管的所述第一栅极图案至少部分接触，所述第一栅极图案在所述衬底基板上的正投影沿像素列方向的长度，大于所述扫描线在所述衬底基板上的正投影沿所述像素列方向的长度。
  10. 根据权利要求9所述的阵列基板，其特征在于，所述衬底基板还具有位于所述显示区域一侧的周边区域；所述阵列基板还包括：位于所述周边区域的驱动电路；所述驱动电路包括至少一个多晶硅薄膜晶体管；每个所述多晶硅薄膜晶体管包括：第二栅极图案和源漏极图案；
    其中，所述第二栅极图案与所述多个扫描线位于同层，所述源漏极图案与所述阵列基板的多个数据线位于同层。
  11. 根据权利要求10所述的阵列基板，其特征在于，每个所述多晶硅薄膜晶体管还包括：有源图案；所述阵列基板还包括：第六绝缘层；所述有源图案位于所述第二栅极图案与所述衬底基板之间，所述第六绝缘层位于所述有源图案与所述第二栅极图案之间；
    其中，所述源漏极图案与所述有源图案电连接。
  12. 一种阵列基板的制备方法，其特征在于，所述方法包括：
    提供一衬底基板，所述衬底基板具有显示区域；
    在所述显示区域形成间隔的多个氧化物薄膜晶体管以及彩膜层；
    其中，每个所述氧化物薄膜晶体管包括金属氧化物图案，所述金属氧化物图案具有依次连接的第一部分，沟道部分，以及第二部分，所述第一部分用于接收数据信号；所述彩膜层位于所述金属氧化物图案与所述衬底基板之间，所述彩膜层包括与所述多个氧化物薄膜晶体管一一对应的不同颜色的多个色阻块，每个所述色阻块在所述衬底基板上的正投影与对应的所述氧化物薄膜晶体管中所述第二部分在所述衬底基板上的正投影至少部分重叠。
  13. 根据权利要求12所述的制备方法，其特征在于，形成所述氧化物薄膜晶体管的金属氧化物图案，包括：
    在所述衬底基板的一侧形成金属氧化物薄膜；
    对所述金属氧化物薄膜进行图案化处理，得到金属氧化物结构；
    在所述金属氧化物结构远离所述衬底基板的一侧的第一区域涂覆光刻胶，所述金属氧化物结构远离所述衬底基板的一侧还包括第二区域和第三区域，所述第二区域和所述第三区域位于所述第一区域的两侧；
    对所述金属氧化物结构远离所述衬底基板的一侧的所述第二区域和所述第三区域进行导体化处理，得到所述金属氧化物图案的第一部分和第二部分；
    去除所述光刻胶，得到所述金属氧化物图案的沟道部分。
  14. 一种显示面板，其特征在于，所述显示面板包括：盖板，液晶层以及如权利要求1至11任一所述的阵列基板；
    所述液晶层位于所述盖板和所述阵列基板之间。
  15. 一种显示装置，其特征在于，所述显示装置包括：供电组件以及如权利要求14所述的显示面板；
    所述供电组件用于为所述显示面板供电。
PCT/CN2021/127111 2021-04-19 2021-10-28 阵列基板及其制备方法、显示面板、显示装置 WO2022222404A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110417335.3A CN113140575B (zh) 2021-04-19 2021-04-19 阵列基板及其制备方法、显示面板、显示装置
CN202110417335.3 2021-04-19

Publications (1)

Publication Number Publication Date
WO2022222404A1 true WO2022222404A1 (zh) 2022-10-27

Family

ID=76812686

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/127111 WO2022222404A1 (zh) 2021-04-19 2021-10-28 阵列基板及其制备方法、显示面板、显示装置

Country Status (2)

Country Link
CN (1) CN113140575B (zh)
WO (1) WO2022222404A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113140575B (zh) * 2021-04-19 2024-04-19 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278132A1 (en) * 2008-05-09 2009-11-12 Jean-Ho Song Array substrate of liquid crystal display device having thin film transistor on color filter and method of fabricating the same
US20150041813A1 (en) * 2013-08-07 2015-02-12 Samsung Display Co., Ltd. Display panel and method of manufacturing the same
US20160246111A1 (en) * 2015-02-25 2016-08-25 Au Optronics Corp. Display panel and method of fabricating the same
CN111474774A (zh) * 2020-04-29 2020-07-31 厦门天马微电子有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN113140575A (zh) * 2021-04-19 2021-07-20 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493197B (zh) * 2018-04-12 2021-03-02 京东方科技集团股份有限公司 顶栅型阵列基板制备工艺

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278132A1 (en) * 2008-05-09 2009-11-12 Jean-Ho Song Array substrate of liquid crystal display device having thin film transistor on color filter and method of fabricating the same
US20150041813A1 (en) * 2013-08-07 2015-02-12 Samsung Display Co., Ltd. Display panel and method of manufacturing the same
US20160246111A1 (en) * 2015-02-25 2016-08-25 Au Optronics Corp. Display panel and method of fabricating the same
CN111474774A (zh) * 2020-04-29 2020-07-31 厦门天马微电子有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN113140575A (zh) * 2021-04-19 2021-07-20 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置

Also Published As

Publication number Publication date
CN113140575A (zh) 2021-07-20
CN113140575B (zh) 2024-04-19

Similar Documents

Publication Publication Date Title
US8294863B2 (en) Liquid crystal display device and method of producing the same
WO2018209977A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
US9865623B2 (en) Array substrate and manufacturing method thereof, and display device
KR20170054844A (ko) 인셀형 터치 패널을 갖는 백플레인 기판 및 이를 이용한 액정 표시 장치 및 이의 제조 방법
TWI606283B (zh) 顯示裝置
US9478565B2 (en) Array substrate and method for fabricating the same, and display panel
WO2017049842A1 (zh) 阵列基板及其制作方法、显示装置
US11755133B2 (en) Array substrate and method for manufacturing same, and display device
US11233106B2 (en) Array substrate, display apparatus, and method of fabricating array substrate
US11374033B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
WO2018209761A1 (zh) 阵列基板及其制造方法、液晶显示面板
WO2021196362A1 (zh) 低温多晶硅显示面板及其制作方法、液晶显示装置
US11385732B2 (en) Array substrate, manufacturing method thereof, touch display panel and touch display device
WO2023134675A9 (zh) 显示基板和显示装置
US20220406875A1 (en) Display substrate and display device
WO2023155803A1 (zh) 阵列基板和显示器
WO2022222404A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2018219345A1 (zh) 阵列基板、显示面板及显示装置
US20160240557A1 (en) Array substrate and manufacturing method thereof, and display device including the array substrate
JP2000275680A (ja) 反射型液晶表示装置及びそれを用いた表示パネル
US11925074B2 (en) Display panel and electronic apparatus
WO2022133795A1 (zh) 一种有机发光显示基板和显示装置
US20220399433A1 (en) Display Substrate and Display Apparatus
WO2023184406A1 (zh) 基板及其制造方法、显示面板
WO2022116010A1 (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17910525

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21937626

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14-02-2024)