WO2020151475A1 - 一种碳化硅沟槽肖特基二极管器件及其制备方法 - Google Patents
一种碳化硅沟槽肖特基二极管器件及其制备方法 Download PDFInfo
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- WO2020151475A1 WO2020151475A1 PCT/CN2020/070138 CN2020070138W WO2020151475A1 WO 2020151475 A1 WO2020151475 A1 WO 2020151475A1 CN 2020070138 W CN2020070138 W CN 2020070138W WO 2020151475 A1 WO2020151475 A1 WO 2020151475A1
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- 238000002360 preparation method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 31
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 108
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 108
- 238000005530 etching Methods 0.000 claims description 44
- 238000005468 ion implantation Methods 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 24
- 238000000206 photolithography Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- -1 Al 2 0 3 Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 2
- 238000001994 activation Methods 0.000 description 2
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical group C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention belongs to the manufacturing process of semiconductor devices, and particularly relates to a silicon carbide trench Schottky diode device and a manufacturing method thereof.
- SiC Silicon carbide
- SiC Schottky diodes Since its commercialization in 2001, SiC Schottky diodes have been widely used in the market. Si C Schottky diodes from many manufacturers have been updated and iterated many times.
- the mainstream SiC Schott diode structure on the market is the JBS/MPS structure.
- this structure introduces regular P-type regions on the surface of the N-type SiC epitaxial layer by ion implantation.
- the PN junction is used to shield the electric field intensity of the Schottky surface when the device is working in the reverse direction, thereby reducing the reverse leakage current.
- the P+ area is a non-conductive area when working in the forward direction, and the presence of the natural depletion layer of the PN junction, it will greatly increase the on-resistance of the device and reduce the forward characteristics of the device.
- the traditional silicon-based Schottky diode In order to reduce the influence of the natural depletion layer introduced in the P+ region, the traditional silicon-based Schottky diode generally adopts a trench gate Schottky diode (TMBS) structure, as shown in FIG. 2.
- TMBS trench gate Schottky diode
- the reverse leakage current of the device can be reduced by adjusting the trench depth and pitch.
- the forward conduction current density is significantly higher due to the lack of the P+ depletion layer.
- JBS/MPS structure In the traditional JBS/MPS structure.
- the surge performance is regarded as an important characteristic of the silicon carbide Schottky diode.
- the traditional SiC JBS/MPS structure When the device is impacted by a surge current, the conductance modulation effect can be introduced through PiN to resist the surge current.
- the conductance modulation effect cannot improve the surge current resistance capability
- the purpose of the present invention is to overcome the shortcomings of the prior art and provide a silicon carbide trench Schottky diode device and a preparation method thereof, which can improve the forward current density of the device and the surge capability
- a silicon carbide trench Schottky diode device including from bottom to top: a cathode electrode, a substrate layer, an N-type SiC epitaxial layer, a trench, a dielectric layer, a conductive layer and an anode electrode, and a plurality of trenches Located on the top of the N-type SiC epitaxial layer, the dielectric layer and the conductive layer are sequentially filled in the trench, and it also includes a P-type region, which is embedded between part of the trenches and is located at the connection between the N-type SiC epitaxial layer and the anode electrode Place.
- the P-type regions are embedded in a regular array.
- the upper boundary of the P-type region protrudes above the trench and is connected to the anode electrode, and the lower boundary is located on or on the top of the trench.
- the dielectric layer extends upward from the lower boundary of the P-type region to the side boundary of the P-type region.
- the P-type region is located in the N-type SiC epitaxial layer, and the upper boundary of the P-type region is connected to the anode electrode.
- the upper boundary of the P-type region protrudes above the trench and is connected to the anode electrode, and the lower boundary of the P-type region is located in the N-type SiC epitaxial layer.
- the pitch of the trenches embedded in the P-type region is the same as or different from the pitch of the trenches not embedded in the P-type region.
- the doping element of the P-type region is formed by B, Al or B/A1 co-doping, and the doping concentration of the P-type region ranges from 1 E14 cm to 5E21 cm ⁇ 3 .
- the P-type region is formed by ion implantation or epitaxial growth.
- the material of the dielectric layer is one or a combination of SiO 2 , Al 2 O 3 , AlN, and SiN
- the material of the conductive layer is one or more of metal, metal silicide, and polysilicon. kind of combination.
- the doping of polysilicon may be N-type, P-type or intrinsic.
- a manufacturing method of a silicon carbide trench Schottky diode device includes the following steps: N-type SiC epitaxial layer Laminated on the substrate layer, forming a P-type region, forming a trench, forming a dielectric layer and a conductive layer, forming a cathode electrode and an anode electrode.
- Step 1 Laminating the N-type SiC epitaxial layer on the substrate layer
- Step two forming a P-type region: grow an ion implantation mask layer on the N-type SiC epitaxial layer, etch the ion implantation mask layer after photolithography to form an ion implantation region window, ion implantation forms a P-type region, and remove ions After the mask area is implanted, the implanted ions are activated at a high temperature;
- Step three forming a trench: growing an etching mask layer, opening a plurality of trench etching windows on the mask layer after photolithography, etching the mask layer, and etching the N-type SiC epitaxial layer to form a trench , Remove the etching mask layer;
- Step four forming a dielectric layer and a conductive layer: growing a dielectric layer on the bottom and sidewalls of the trench, growing a conductive layer on the dielectric layer, and filling the trench with the conductive layer;
- Step five forming an anode electrode and a cathode electrode: grow an ohmic contact metal on the bottom of the substrate to form a cathode electrode; grow Schottky metal on the top of the N-type SiC epitaxial layer to form an anode electrode.
- a method for manufacturing a silicon carbide trench Schottky diode device includes the following steps: laminating an N-type SiC epitaxial layer on a substrate layer forming a trench forming a P-type region forming a dielectric layer and a conductive layer forming Cathode electrode and anode electrode.
- Step 1 Laminating the N-type SiC epitaxial layer on the substrate layer
- Step two forming a trench: growing an etching mask layer, opening a plurality of trench etching windows on the mask layer after photolithography, etching the mask layer, and etching the N-type SiC epitaxial layer to form a trench , Remove the etching mask layer;
- Step three forming a P-type region: growing an ion implantation mask layer on the N-type SiC epitaxial layer, etching the ion implantation mask layer after photolithography to form an ion implantation region window, ion implantation forming a P-type region, and removing ions After the mask area is implanted, the implanted ions are activated at a high temperature;
- Step four forming a dielectric layer and a conductive layer: growing a dielectric layer on the bottom and sidewalls of the trench, growing a conductive layer on the dielectric layer, and filling the trench with the conductive layer;
- Step five forming an anode electrode and a cathode electrode: grow an ohmic contact metal on the bottom of the substrate to form a cathode electrode; grow a Schottky metal on the top of the N-type SiC epitaxial layer to form an anode electrode.
- a manufacturing method of a silicon carbide trench Schottky diode device includes the following steps: N-type SiC epitaxial layer An epitaxial growth P-type layer is laminated on the substrate layer, a P-type region is formed, a trench is formed, a dielectric layer and a conductive layer are formed, and a cathode electrode and an anode electrode are formed.
- a method for manufacturing a silicon carbide trench Schottky diode device includes the following steps:
- Step 1 Laminating the N-type SiC epitaxial layer on the substrate layer
- Step two epitaxially grow a P-type layer: grow a P-type layer on the N-type SiC epitaxial layer by epitaxial growth;
- Step three form a P-type region: etch SiC to N-type SiC after photolithography On the epitaxial layer, a P-type region is formed;
- Step four forming a trench: growing an etching mask layer, opening a plurality of trench etching windows on the mask layer after photolithography, etching the mask layer, and etching the N-type SiC epitaxial layer to form a trench , Remove the etching mask layer;
- Step five forming a dielectric layer and a conductive layer: growing a dielectric layer on the bottom and sidewalls of the trench, growing a conductive layer on the dielectric layer, and filling the trench with the conductive layer;
- Step 6 forming an anode electrode and a cathode electrode: growing an ohmic contact metal on the bottom of the substrate to form a cathode electrode; growing a Schottky metal on the top of the N-type SiC epitaxial layer to form an anode electrode.
- a P-type region is introduced to form a PN junction diode structure.
- the P junction can be turned on to reduce Forward voltage drop, so that the device has higher anti-surge current capability, so as to meet the requirements of the circuit system;
- FIG. 1 is a schematic cross-sectional structure diagram of an existing JBS/MPS
- FIG. 2 is a schematic cross-sectional structure diagram of a conventional trench Schottky diode
- FIG. 3 is a schematic cross-sectional structure diagram of Embodiment 1 of the present invention.
- FIG. 4 is a schematic cross-sectional structure diagram of the second embodiment of the present invention.
- FIG. 5 is a schematic cross-sectional structure diagram of the third embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional structure diagram of the fourth embodiment of the present invention.
- FIG. 7 is a schematic cross-sectional structure diagram of the fifth embodiment of the present invention.
- FIG. 8 is a schematic cross-sectional structure diagram of a sixth embodiment of the present invention.
- the present invention discloses a silicon carbide trench Schottky diode device, which includes from bottom to top: cathode electrode 1, substrate layer 2, N-type SiC epitaxial layer 3, trench 4, dielectric layer 5, conductive layer 6, and The anode electrode 7, a plurality of trenches 4 are located on the top of the N-type SiC epitaxial layer 3.
- the dielectric layer 5 and the conductive layer 6 are sequentially filled in the trench 4, and also include a P-type region 8, which is embedded in part
- the trenches 4 are located at the junction of the N-type SiC epitaxial layer 3 and the anode electrode 7, and the P-type region 8 and the N-type SiC epitaxial layer 3 form a PN junction diode structure in the vertical direction.
- the device by embedding a P-type region 8 between part of the trenches 4, the device has a higher surge current resistance capability, so as to meet the requirements of the circuit system.
- the P-type regions 8 are embedded in a regular array.
- a P-type region 8 is formed at every interval of two trenches 4.
- it can also be designed as required, for example, every interval Three trenches 4 or four trenches 4 or more. Two trenches 4 can be separated to form a P-type region 8 and then three trenches 4 can be separated to form a P-type region 8.
- the P-type regions 8 are regular It is sufficient to embed in a regular array, and there is no limit to the embedding method of a regular array. I won't repeat them here.
- the pitch of the trench 4 embedded in the P-type region 8 is the same or different from the pitch of the trench 4 not embedded in the P-type region 8.
- the pitch of the trench 4 refers to two adjacent trenches. The distance between 4. In this way, the Schottky contact area can be adjusted according to the actual situation, thereby optimizing the structural design of the device, so that the device has a lower forward specific on-resistance.
- the doping element of the P-type region 8 is formed by B, A1 or B/A1 co-doping, and the doping concentration of the P-type region 8 ranges from 1E14 cm _ 3 to 5E21 cm _ 3 .
- the doping of the P-type region 8 can be adjusted according to the actual situation, so that the performance of the PN junction diode can reach the best state.
- the P-type region 8 is formed by ion implantation or epitaxial growth.
- the top-view shape of the P-type region 8 is square, circular, hexagonal or octagonal.
- a buffer layer is further included, and the buffer layer is located between the substrate layer 2 and the N-type SiC epitaxial layer 3, so that this structure is suitable for different devices.
- the material of the dielectric layer is one or a combination of SiO 2 , Al 2 O 3 , AlN, and SiN.
- the material of the conductive layer is one or a combination of metal, metal silicide, and polysilicon.
- the doping of polysilicon may be N-type, P-type or intrinsic. Adjusting the doping of polysilicon can change the work function of the conductive layer, thereby adjusting the pinch-off performance of the MOS structure.
- Embodiment One is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068] is a liquid crystal [0068]
- a silicon carbide trench Schottky diode device includes from bottom to top: a cathode electrode 1, a substrate layer 2, an N-type SiC epitaxial layer 3, a trench 4, a dielectric layer 5, and a conductive layer.
- the layer 6 and the anode electrode 7, a plurality of trenches 4 are located on the top of the N-type SiC epitaxial layer 3, the dielectric layer 5 and the conductive layer 6 are sequentially filled in the trench 4, and also include a P-type region 8, the P-type region 8 Embedded between part of the trenches 4, at the junction of the N-type SiC epitaxial layer 3 and the anode electrode 7, the P-type region 8 is located in the N-type SiC epitaxial layer 3, and the upper boundary 81 of the P-type region 8 and the anode electrode 7 Connected, the side boundary 83 of the P-type region 8 borders the side wall 43 of the trench 4, and the side boundary 83 is a boundary parallel to the side wall 43 of the trench 4.
- This embodiment is prepared by the following method and includes the following steps:
- Step 1 stacking the N-type SiC epitaxial layer 3 on the substrate layer 2;
- Step two forming the P-type region 8: grow an ion implantation mask layer on the N-type SiC epitaxial layer 3. After photolithography, the ion implantation mask layer is etched to form an ion implantation region window, and ion implantation forms the P-type region 8. , Remove the ion implantation mask High-temperature activation of implanted ions after the membrane area;
- Step three forming trench 4: grow an etching mask layer, open a plurality of trench etching windows on the mask layer after photolithography, etch the mask layer, and etch the N-type SiC epitaxial layer 3 to form Trench 4, removing the etching mask layer;
- Step four forming a dielectric layer 5 and a conductive layer 6: a dielectric layer 5 is grown on the bottom 42 and sidewalls 43 of the trench 4, a conductive layer 6 is grown on the dielectric layer 5, and the conductive layer 6 fills the trench 4 ;
- Step 5 forming anode electrode 7 and cathode electrode 1: grow ohmic contact metal on the bottom of substrate 2 to form cathode electrode 1; grow Schottky metal on top of N-type SiC epitaxial layer 3 to form anode electrode 7.
- the upper boundary 81 of the P-type region 8 protrudes above the trench 4 and is connected to the anode electrode 7, and the lower boundary 82 is located at or on the top 41 of the trench 4.
- This structure enables the P-type region 8 to be directly formed by epitaxial growth, avoiding material damage caused by ion implantation and activation processes, and also simplifies the process.
- the dielectric layer 5 extends upward from the lower boundary 82 of the P-type region 8 to the side boundary of the P-type region, and may extend to the upper boundary 81 of the P-type region 8, and may not extend
- the upper boundary 81 to the P-type area 8 is set according to actual needs.
- the anode electrode 7 can be prevented from being connected to the N-type SiC epitaxial layer 3, and the P-type region 8 and the N-type SiC epitaxial layer 3 can be prevented from being short-circuited, and the PN junction cannot be opened during forward operation.
- This embodiment is prepared by the following method and includes the following steps:
- Step 1 stacking the N-type SiC epitaxial layer 3 on the substrate layer 2;
- Step two epitaxial growth of the P-type layer: the P-type layer is laminated and grown on the N-type SiC epitaxial layer 3 by epitaxial growth
- Step three forming a P-type region 8: etch SiC onto the N-type SiC epitaxial layer 3 after photolithography to form a P-type region 8;
- Step four forming trench 4: grow an etching mask layer, open a plurality of trenches 4 etching windows on the mask layer after photolithography, etch the mask layer, and etch the N-type SiC epitaxial layer 3 A trench 4 is formed, and the etching mask layer is removed;
- Step 5 forming a dielectric layer 5 and a conductive layer 6: a dielectric layer 5 is grown on the bottom 42 and sidewalls 43 of the trench 4, a conductive layer 6 is grown on the dielectric layer 5, and the conductive layer 6 fills the trench 4 ;
- Step 6 forming anode electrode 7 and cathode electrode 1: growing ohmic contact metal on the bottom of substrate 2 to form cathode electrode 1; growing Schottky metal on top of N-type SiC epitaxial layer 3 to form anode electrode 7.
- Embodiment Three As shown in FIG. 5, the difference from the first embodiment is that: the side boundary 83 of the P-type region 8 does not border the side wall 43 of the trench 4.
- the preparation method is the same.
- the upper boundary 81 of the P-type region 8 protrudes above the trench 4 and is connected to the anode electrode 7, and the lower boundary 82 of the P-type region 8 is located at Inside the N-type SiC epitaxial layer 3.
- a trench bottom P-type region 9 is formed on the bottom 42 of the trench 4.
- the P-type region 9 at the bottom of the trench can play a shielding role, reduce the electric field intensity at the bottom 42 of the trench 4, and prevent the destructive breakdown of the dielectric layer 5 when the device works in reverse.
- an internal P-type region 10 is formed inside the N-type SiC epitaxial layer.
- the inner P-type region 10 can play a shielding role, reduce the electric field strength at the bottom 42 of the trench 4, and prevent the destructive breakdown of the dielectric layer 5 when the device is working in reverse; it can also work with the N-type SiC epitaxial layer 3.
- a super junction structure is formed to reduce the specific on-resistance of the device.
- This embodiment is prepared by the following method and includes the following steps:
- Step 1 stacking the N-type SiC epitaxial layer 3 on the substrate layer 2;
- Step two forming an inner P-type region 10: growing an ion implantation mask layer, etching the ion implantation mask layer after photolithography, ion implantation, forming an inner P-type region 10;
- Step three secondary epitaxial growth: continue epitaxial growth on the N-type epitaxial layer 3, increase the thickness of the N-type SiC epitaxial layer 3, and at the same time activate the ions implanted in step two;
- Step four forming trench 4: Growing an etching mask layer, opening a plurality of trench etching windows on the mask layer after photolithography, etching the mask layer, and etching the N-type SiC epitaxial layer 3 to form Trench 4, removing the etching mask layer;
- Step 5 forming the P-type region 8: Growing an ion implantation mask layer on the N-type SiC epitaxial layer 3. After photolithography, the ion implantation mask layer is etched to form the ion implantation region window, and the ion implantation forms the P-type region 8. , After removing the ion implantation mask area, the implanted ions are activated at high temperature;
- Step 6 forming a dielectric layer 5 and a conductive layer 6: a dielectric layer 5 is grown on the bottom 42 and sidewalls 43 of the trench 4, a conductive layer 6 is grown on the dielectric layer 5, and the conductive layer 6 fills the trench 4 ;
- Step 7 forming the anode electrode 7 and the cathode electrode 1: an ohmic contact metal is grown on the bottom of the substrate 2 to form Cathode electrode 1; On top of N-type SiC epitaxial layer 3, Schottky metal is grown to form anode electrode 7.
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CN109801958B (zh) * | 2019-01-21 | 2020-09-15 | 厦门市三安集成电路有限公司 | 一种碳化硅沟槽肖特基二极管器件及其制备方法 |
CN111799336B (zh) * | 2020-07-27 | 2021-09-24 | 西安电子科技大学 | 一种SiC MPS二极管器件及其制备方法 |
CN113851525A (zh) * | 2021-09-18 | 2021-12-28 | 中山大学 | 一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法 |
CN115312591B (zh) * | 2022-10-10 | 2022-12-23 | 深圳市威兆半导体股份有限公司 | 一种快恢复二极管及其制备方法 |
CN116598343A (zh) * | 2023-07-18 | 2023-08-15 | 深圳平创半导体有限公司 | 沟槽型碳化硅二极管器件结构及其制作方法 |
CN118281081B (zh) * | 2024-06-03 | 2024-08-06 | 深圳平创半导体有限公司 | 一种mps二极管元胞结构、版图结构以及制作方法 |
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