WO2020147306A1 - 耐压电平转换电路 - Google Patents

耐压电平转换电路 Download PDF

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Publication number
WO2020147306A1
WO2020147306A1 PCT/CN2019/100234 CN2019100234W WO2020147306A1 WO 2020147306 A1 WO2020147306 A1 WO 2020147306A1 CN 2019100234 W CN2019100234 W CN 2019100234W WO 2020147306 A1 WO2020147306 A1 WO 2020147306A1
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level
tube
pmos
stage inverter
voltage
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PCT/CN2019/100234
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English (en)
French (fr)
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王磊
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南京观海微电子有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Definitions

  • the invention relates to a withstand voltage level conversion circuit, in particular to a withstand voltage level conversion circuit all adopting medium voltage MOSFETs (metal-oxide semiconductor field effect transistors).
  • MOSFETs metal-oxide semiconductor field effect transistors
  • the important element in the level conversion circuit is the metal-oxide semiconductor field effect transistor field effect transistor (MOSFET).
  • the high-voltage MOS tube mentioned in this article refers to the MOSFET with a withstand voltage above 20V.
  • the medium-voltage MOS tube must be able to withstand high voltage. Lower, generally between 3 ⁇ 6v, low-voltage MOS is mainly used for low-voltage resistance.
  • the traditional withstand voltage level conversion circuit usually adopts a high-voltage MOS tube design, which has the advantages of compact circuit structure and good stability. However, the response speed of the high-voltage MOS tube is slower than that of the medium and low-voltage MOS tube. Ron is relatively large and the temperature rises when working under high pressure.
  • the level conversion circuit generally uses a variety of MOS transistors, and a mixed design of multiple MOS transistors with different voltage resistance performance is adopted. The price is several times higher than that of a design using only medium voltage MOS transistors.
  • the present invention proposes a withstand voltage level conversion circuit, which can withstand a larger power supply voltage, has a fast response capability and a lower temperature rise, and also greatly reduces the circuit cost.
  • the technical scheme adopted by the present invention is a withstand voltage level conversion circuit, which includes a level conversion unit, a two-stage inverter and two output PMOS field effect transistors; a level conversion unit and two stages
  • the inverters are powered by a high level and are equipped with two bias voltages, a low level and an intermediate level; the level conversion unit is connected to the first level inverter, and the level conversion unit converts the input level and outputs it to a
  • the first-stage inverter is used to drive the first PMOS tube
  • the second-stage inverter is connected to the first-stage inverter and used to drive the second PMOS tube; the first PMOS tube and the second PMOS tube output converted Level.
  • the level conversion unit includes 4 PMOS tubes, 4 NMOS tubes and a third inverter; the two PMOS tubes connected to the low level are used to raise the third PMOS tube connected to the high level.
  • the drain voltage of the fourth PMOS tube and the fourth PMOS tube, the two NMOS tubes connected to the intermediate level are used to clamp the drain voltage of the third NMOS tube and the fourth NMOS tube; the drain of the fourth PMOS tube and the fourth NMOS tube
  • the drains are respectively the two output terminals of the level conversion unit.
  • the source of the third PMOS tube and the fourth PMOS tube are connected to a high level, the gate of the third PMOS tube is connected to the drain of the fourth PMOS tube, and the gate of the fourth PMOS tube is connected to the third PMOS tube.
  • the drain of the tube is connected.
  • the third inverter is powered by a low level, its input terminal is connected to the input level, and the output terminal is connected to the gate of the fourth NMOS transistor, and is used to provide the fourth NMOS transistor with a polarity corresponding to the input level. The opposite signal.
  • the first-stage inverter is composed of four MOS transistors connected in series, and the eighth PMOS transistor connected to the low level is used to raise the drain voltage of the seventh PMOS transistor connected to the high level, which is higher than the intermediate level.
  • the connected seventh NMOS tube is used to clamp the drain voltage of the eighth NMOS tube.
  • the voltage output by the drain of the seventh PMOS tube and the drain of the eighth NMOS tube is used as the input of the next stage inverter.
  • the eighth PMOS tube The drain is used as the output of the first-stage inverter.
  • the two-stage inverter is composed of four MOS transistors connected in series, and the tenth PMOS transistor connected to the low level is used to raise the drain voltage of the ninth PMOS transistor connected to the high level to the intermediate level.
  • the connected ninth NMOS tube is used to clamp the drain voltage of the tenth NMOS tube, and the drain of the tenth PMOS tube is used as the output terminal of the two-stage inverter.
  • the source of the tenth NMOS transistor is connected to a low level.
  • the withstand voltage level conversion circuit of the present invention has the following advantages: (1) The PMOS tube connected to the low level raises the drain voltage of the PMOS tube connected to the high level , To avoid the breakdown of the PMOS tube with high voltage due to excessive VDS voltage; the NMOS tube connected to the intermediate level can clamp the drain voltage of the NMOS tube with the source grounded, and avoid it from being hit by the excessive voltage Through the above design, the withstand voltage performance of the PMOS tube is improved, so that the medium voltage MOS tube also has a better withstand voltage effect; (2) The design of using the medium voltage MOSFET instead of the high voltage MOSFET greatly reduces the circuit cost.
  • Figure 1 is a structural diagram of the withstand voltage level conversion circuit of the present invention
  • Fig. 2 is a partial timing diagram of the withstand voltage level conversion circuit of the present invention.
  • the withstand voltage level conversion circuit of the present invention includes a level conversion unit, a two-stage inverter and two output PMOS field effect transistors (the first PMOS tube MP1 and the second PMOS Tube MP2); both the level conversion unit and the two-stage inverter are powered by a high-level VH and are provided with two bias voltages, a low-level VL and an intermediate-level VM; the level conversion unit is connected to the first-level inverter , The level conversion unit converts the input level and outputs it to the first-stage inverter.
  • the first-stage inverter is used to drive the first PMOS tube MP1
  • the second-stage inverter is connected to the first-stage inverter and used to drive the second PMOS tube MP2; the first PMOS tube MP1 and the second PMOS tube MP2 output the converted level VOUT.
  • the level conversion unit includes 4 PMOS tubes, 4 NMOS tubes and a third inverter.
  • the sources of the third NMOS tube and the fourth NMOS tube are grounded, the gates of the fifth NMOS tube and the sixth NMOS tube are connected to the intermediate level VM, and their drains are connected to the third NMOS tube and the fourth NMOS tube respectively.
  • the drain is connected to clamp the drain voltage of the third NMOS tube and the fourth NMOS tube.
  • the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the high level VH, the gates of the fifth PMOS tube and the sixth PMOS tube are connected to the low level VL, and the drains of the two are respectively connected to the third NMOS tube It is connected to the drain of the fourth NMOS tube and is used to increase the drain voltage of the third PMOS tube and the fourth PMOS tube.
  • the gate of the third PMOS tube is connected to the drain of the fourth PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube.
  • the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are respectively the two output terminals (yh0, yl0) of the level conversion unit.
  • the third inverter is powered by a low level VL, and provides two NMOS signals with opposite polarities (for example, the input is 0, the output is VL; or the input is VL, the output is 0).
  • the one-stage inverter is composed of four MOS transistors connected in series.
  • the eighth PMOS transistor connected to the low level is used to raise the drain voltage of the seventh PMOS transistor connected to the high level, and the second PMOS transistor connected to the intermediate level Seven NMOS transistors are used to clamp the drain voltage of the eighth NMOS transistor.
  • the output (yh1, yl1) of the drain of the seventh PMOS transistor and the drain of the eighth NMOS transistor are used as the input of the next stage inverter.
  • the eighth PMOS transistor The drain is used as the output terminal (y1) of the first-stage inverter.
  • the one-stage inverter has two input terminals, which are respectively connected to the two output terminals (yh0, yl0) of the level conversion unit.
  • the two output terminals yh0 and yl0 have the same polarity and are both high level or low level. They are just to solve the withstand voltage problem of the device and cannot work at full swing. Use two inputs and a voltage limiting circuit of PMOS and NMOS in series. Solve the pressure problem.
  • the two-stage inverter has the same structure as the one-stage inverter and consists of four MOS transistors connected in series.
  • the tenth PMOS transistor connected to the low level is used to raise the drain of the ninth PMOS transistor connected to the high level.
  • Voltage, the ninth NMOS tube connected to the intermediate level is used to clamp the drain voltage of the tenth NMOS tube, the drain of the tenth PMOS tube is used as the output terminal (y2) of the secondary inverter, and the source of the tenth NMOS tube Connect low level VL.
  • the 4 medium voltage PMOS transistors connected with low level VL can clamp the drain voltage of the upper 4 PMOS transistors to avoid seeing 0v ground, so that the drain voltage of the upper 4 PMOS transistors is in the range of VH ⁇ VL+
  • ) (0 ⁇ VH-VL-
  • ), as long as VDS VH-VL-
  • 6-
  • VGS also meets the requirements.
  • the 4 medium voltage pmos connected to the low level VL, VDS is (VH-VH) ⁇ VL+
  • the VM is both a withstand voltage value and an applied bias voltage. Using the withstand voltage value as the bias voltage can ensure the withstand voltage of the NMOS.
  • the one-stage inverter is used to drive the first PMOS tube MP1, there is a pmos connected to VL under yh0, V(yh0)-VL ⁇ Vt can get VH ⁇ V(yh0) ⁇ VL+Vt, so
  • VH- V(yh0) ⁇ VH-VL-Vt, similarly
  • the first-stage inverter meets the withstand voltage conditions, and the range of the output point y1 is: VH ⁇ y1 ⁇ 0.
  • the two-stage inverter is used to drive the second PMOS transistor MP2, and in the same way, the second-stage inverter can also meet the withstand voltage regulation. But because the source terminal of the second PMOS tube MP2 is connected to VH, if the low level of y2 is 0, it will cause
  • VH-VL, is within the withstand voltage range of the device.
  • the 4 medium voltage NMOS transistors connected to the intermediate level VM clamp the drain voltages of the lower 4 NMOS transistors to avoid seeing VH, so that the range of the drain voltages of the lower 4 NMOS transistors is VM-VT ⁇ 0 ⁇ VM.
  • Vgs of the first PMOS tube MP1 VH-VL ⁇
  • the substrate problem does not need to be specially explained, because the withstand voltage of the general VDB is higher than the withstand voltage of the other ends, so the general NMOS can be grounded, and the PMOS can be connected to a high level. But if the VDB withstand voltage is not enough, the process-provided substrate may not be connected to the NMOS of a unified ground or the substrate is not connected to the PMOS of the unified power supply. Of course, it is safer to connect the substrate to the source.
  • FIG. 2 it is a timing diagram (part) of the withstand voltage level conversion circuit of the present invention.
  • the one-stage inverter When the rising edge of the input voltage arrives, the one-stage inverter outputs a low level 0 and drives the first PMOS transistor to output Vout. It is low level VL to realize the function of level conversion.
  • the two-stage inverter When the input voltage drops to 0, the two-stage inverter outputs a low level VL, and drives the second PMOS tube to output Vout to a high level VH.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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Abstract

一种耐压电平转换电路，该电路包括电平转换单元、两级反相器和两个输出用PMOS场效应晶体管；电平转换单元和两级反相器均由高电平供电并设有低电平和中级电平两个偏置电压；电平转换单元将输入电平进行转换后输出给一级反相器，电平转换单元与一级反相器相连，二级反相器与一级反相器连接，用于驱动输出用PMOS场效应晶体管输出转换电平。该电路提升了PMOS管的耐压性能，从而使用中压MOS管也具有较好的耐压效果，同时具有快速的响应能力以及较低的温升，并降低了电路成本。

Description

耐压电平转换电路 技术领域
本发明涉及一种耐压电平转换电路，尤其涉及一种全部采用中压MOSFET(金属-氧化物半导体场效应晶体管)的耐压电平转换电路。
背景技术
在新一代电子电路设计中，随着不同工作电压的数字IC的不断涌现，低电压逻辑的引入使得逻辑电平转换的必要性更加突出。例如，当1.8V的数字电路与工作在3.3V的模拟电路进行通信时，需要首先解决两种电平的转换问题，这时就需要电平转换。同时，为了减少电子产品功耗需求，很多电子系统持续向更低的电压信号水平转移。更快的整流速度和降低信号噪声等方面的进步既方便了设计者，也向他们提出了新的挑战。微处理器在向较低的电压水平进军的过程中一马当先。处理器I/O电压正从1.8V转移到1.5V，而内核电压能够低于1V。下一代微处理器甚至将采用更低的电压。外围设备组件的电压虽然也在降低，但水平通常落后于处理器一代左右。电压降低方面的发展不均带来了系统设计者必须解决的关键性难题，即如何在信号电平之间进行可靠的转换。正确的信号电平可以保证系统的可靠工作，它们能够防止敏感IC因过高或者过低的电压条件而受损。
电平转换电路中的重要原件是金属-氧化物半导体场效应晶体管场效应管(MOSFET)，本文所述的高压MOS管指耐压在20V以上的MOSFET，中压MOS管对高压的承受能力要低一些，一般在3～6v之间，低压MOS则主要用于耐低压的情况。传统的耐压电平转换电路，通常采用高压MOS管设计，其具有电路结构紧凑、稳定性好的优点。但是，高压MOS管的响应速度相比于中低压MOS管要慢，Ron比较大，在高压下工作时温升高。而且，电平转换电路一般会用到多种MOS管，采用多种耐压性能不同的MOS管混合设计，其价格上来看要比只使用中压MOS管的设计高数倍。
发明内容
发明目的：针对以上问题，本发明提出一种耐压电平转换电路，该电路既能够承受较大的电源电压，具有快速的响应能力以及较低的温升，同时还大大降低了电路成本。
技术方案：本发明所采用的技术方案是一种耐压电平转换电路，该电路包括电平转换单元、两级反相器和两个输出用PMOS场效应晶体管；电平转换单元和两级反相器均由高电平供电并设有低电平和中级电平两个偏置电压；电平转换单元与一级反相器相连，电平转换单元将输入电平进行转换后输出给一级反相器，一级反相器用于驱动第一PMOS管，二级反相器与一级反相器相连并用于驱动第二PMOS管；第一PMOS管和第二PMOS管输出转换后的电平。
进一步的，所述电平转换单元包括4个PMOS管、4个NMOS管和第三反相器；与低电平连接的两个PMOS管分别用于抬高与高电平相连的第三PMOS管和第四PMOS管的漏极电压，与中级电平连接的两个NMOS管用于钳制第三NMOS管和第四NMOS管的漏极电压；第四PMOS管的漏极和第四NMOS管的漏极分别为电平转换单元的两个输出端。所述第三PMOS管和第四PMOS管，二者的源极连接高电平，第三PMOS管的栅极和第四PMOS管的漏极相连，第四PMOS管的栅极和第三PMOS管的漏极相连。所述第三反相器由低电平供电，其输入端与输入电平连接，输出端与所述第四NMOS管的栅极相连，用于向第四NMOS管提供与输入电平极性相反的信号。
进一步的，所述一级反相器由四个MOS管串联组成，与低电平连接的第八PMOS管用于抬高与高电平相连的第七PMOS管的漏极电压，与中级电平连接的第七NMOS管用于钳制第八NMOS管的漏极电压，第七PMOS管的漏极和第八NMOS管的漏极所输出的电压作为下一级反相器的输入，第八PMOS管的漏极作为一级反相器的输出端。
进一步的，所述二级反相器由四个MOS管串联组成，与低电平连接的第十PMOS管用于抬高与高电平相连的第九PMOS管的漏极电压，与中级电平连接的第九NMOS管用于钳制第十NMOS管的漏极电压，第十PMOS管的漏极作为二级反相器的输出端。其中，所述第十NMOS管的源极接低电平。
有益效果：本发明所述的耐压电平转换电路相比现有技术，具有以下优点：(1)与低电平连接的PMOS管抬高了与高电平相连的PMOS管的漏极电压，避免承受高电压的PMOS管出现因VDS电压过大而导致的击穿；与中级电平连接的NMOS管能够钳制源极接地的NMOS管的漏极电压，避免其承受过高的电压而击穿；通过以上设计，提升了PMOS管的耐压性能，从而使用中压MOS管也具有较好的耐压效果；(2)采用中压MOSFET代替耐高压MOSFET的设计，大大降低了电路成本。
附图说明
图1是本发明所述耐压电平转换电路的结构图；
图2是本发明所述耐压电平转换电路的部分时序图。
具体实施方式
下面结合附图和实施例对本发明的技术方案作进一步的说明。
本发明所述的一种耐压电平转换电路，如图1所示，包括电平转换单元、两级反相器和两个输出用PMOS场效应晶体管(第一PMOS管MP1和第二PMOS管MP2)；电平转换单元和两级反相器均由高电平VH供电并设有低电平VL和中级电平VM两个偏置电压；电平转换单元与一级反相器相连，电平转换单元将输入电平进行转换后输出给一级反相器，一级反相器用于驱动第一PMOS管MP1，二级反相器与一级反相器相连并用于驱动第二PMOS管MP2；第一PMOS管MP1和第二PMOS管MP2输出转换后 的电平VOUT。
以下详述各个单元的具体结构：
所述电平转换单元包括4个PMOS管、4个NMOS管和第三反相器。第三NMOS管和第四NMOS管的源极接地，第五NMOS管和第六NMOS管的栅极与中级电平VM连接，二者的漏极分别与第三NMOS管和第四NMOS管的漏极相连，用于钳制第三NMOS管和第四NMOS管的漏极电压。第三PMOS管的源极和第四PMOS管的源极连接高电平VH，第五PMOS管和第六PMOS管的栅极连接低电平VL，二者的漏极分别与第三NMOS管和第四NMOS管的漏极相连，用于抬高第三PMOS管和第四PMOS管的漏极电压。第三PMOS管的栅极和第四PMOS管的漏极相连，第四PMOS管的栅极和第三PMOS管的漏极相连。第四PMOS管的漏极和第四NMOS管的漏极分别为电平转换单元的两个输出端(yh0、yl0)。所述第三反相器由低电平VL供电，给其输入端和输出端的两个NMOS提供两个极性相反的信号(例如，输入是0，输出是VL；或输入是VL，输出是0)。
所述一级反相器由四个MOS管串联组成，与低电平连接的第八PMOS管用于抬高与高电平相连的第七PMOS管的漏极电压，与中级电平连接的第七NMOS管用于钳制第八NMOS管的漏极电压，第七PMOS管的漏极和第八NMOS管的漏极的输出(yh1、yl1)作为下一级反相器的输入，第八PMOS管的漏极作为一级反相器的输出端(y1)。一级反相器有两个输入端，分别接电平转换单元的两个输出端(yh0、yl0)。两个输出端yh0和yl0的极性相同，同为高电平或者低电平，只是为了解决器件耐压问题，不能满摆幅工作，用两输入加串联一个PMOS和NMOS的限压电路来解决耐压问题。
所述二级反相器的结构同一级反相器相同，由四个MOS管串联组成，与低电平连接的第十PMOS管用于抬高与高电平相连的第九PMOS管的漏极电压，与中级电平连接的第九NMOS管用于钳制第十NMOS管的漏极电压，第十PMOS管的漏极作为二级反相器的输出端(y2)，第十NMOS管的源极接低电平VL。
以下具体分析该电路如何满足耐压条件：
低电平VL连接的4个中压PMOS管可以钳制上面4个PMOS管的漏极电压，避免见到0v地，使得上面4个PMOS管的漏极电压的范围是VH～VL+|VT|，VDS范围是VS-VD＝(VH-VH～VH-VL-|VT|)＝(0～VH-VL-|VT|)，只要VDS＝VH-VL-|VT|在中压mos的耐压范围就没问题。例如：VH＝7.5v，VL＝1.5v，中压MOS管为6v元件的情况下，7.5-1.5-|VT|＝6-|VT|＜6V。栅极也加在这里，所以VGS也满足要求。低电平VL所连接的4个中压pmos，VDS为(VH-VH)～VL+|VT|-0，即只要0～VL+|VT|＜VM(VM为中压元件耐压值)，耐压就能满足要求。所述VM既是耐压值，也是所加的偏置电压，用耐压值做偏置电压可以保证NMOS的耐压。
一级反相器用于驱动第一PMOS管MP1，yh0下边有gate接VL的pmos，V(yh0)-VL≥Vt可以得到VH≥V(yh0)≥VL+Vt，所以|Vgs|＝VH-V(yh0)≤VH-VL-Vt，同理|Vds|＝VH-V(yh1)≤VH-VL-Vt，只要该电压范围没有超过第一级反相器pmos的器件的耐压范围就满足电压可靠性问题；同理nmos方向，VM-V(yl0)≥Vt，可得Vgs＝V(yl0)≤VM-Vt，同理Vds＝V(yl1)≤VM-Vt。综上，第一级反相器满足耐压条件，输出点y1的范围是：VH≥y1≥0。二级反相器用于驱动第二PMOS管MP2，同理可得第二级反相器也满足耐压调节。但因为第二PMOS管MP2的源端接VH，如果y2的低电平是0会导致|Vgs|＝VH-0＝VH，超过器件耐压，所以第二级反相器的低电平接VL，使得|Vgs|＝VH-VL，在器件耐压范围内。
中级电平VM连接的4个中压NMOS管钳制下面的4个NMOS管的漏极电压，避免见到VH，使得下面4个NMOS管的漏极电压的范围是VM-VT～0＜VM。VM连接的4个中压NMOS的VDS为：VH-VM+VT～0，只要VH-VM+VT＜VM(VM为中压元件的耐压值)，则满足耐压要求，比如在该实例中7.5-6+VT＝1.5-VT＜6。
第一PMOS管MP1本来就可以使用中压管，因为虽然栅极电压范围是VH～0，但是VS＝VL，VD：VL～VH，所以VGS和VDS的工作范围在实例中没有超过中压管的工作范围。第一PMOS管MP1的Vgs：VH-VL≥|Vgs|≥VL，因Vout：VH≥Vout≥VL，Vds：VH-VL≥|Vds|≥0。因此第一PMOS管MP1满足耐压条件。第二PMOS管MP2也为中压管，但是如果gate电压范围不变还是VH～0，超过了中压管的耐压就会有可靠性问题，所以二级反相器的低电平就不能接0，而是接到VL，使得栅极电压范围是VH～VL，VGS的范围就是VH-VG为VH-VH＝0～VH-VL，VH-VL在实例中7.5-1.5＝6≤6是在中压管的耐压范围内，VDS的范围相同，所以耐压满足要求。
衬底问题不必特殊说明，是因为一般VDB的耐压都比其他两端的耐压高，故，一般NMOS可以接地，PMOS可以接高电平。但如果VDB耐压不够，工艺提供衬底可以不接统一的地的NMOS或衬底不接统一电源的PMOS，衬底接源端当然更安全。
如图2所示，为本发明所述耐压电平转换电路的时序图(部分)，当输入电压上升沿到来时，一级反相器输出低电平0，驱动第一PMOS管输出Vout为低电平VL，实现电平转换的功能。当输入电压降为0时，二级反相器输出低电平VL，驱动第二PMOS管输出Vout为高电平VH。

Claims (7)

  1. 一种耐压电平转换电路，其特征在于：该电路包括电平转换单元、两级反相器和两个输出用PMOS场效应晶体管(MP1、MP2)；电平转换单元和两级反相器均由高电平(VH)供电并设有低电平(VL)和中级电平(VM)两个偏置电压；电平转换单元与一级反相器相连，电平转换单元将输入电平(VIN)进行转换后输出给一级反相器，一级反相器用于驱动第一PMOS管(MP1)，二级反相器与一级反相器相连并用于驱动第二PMOS管(MP2)；第一PMOS管(MP1)和第二PMOS管(MP2)输出转换后的电平。
  2. 根据权利要求1所述的耐压电平转换电路，其特征在于：所述电平转换单元包括4个PMOS管、4个NMOS管和第三反相器；与低电平(VL)连接的两个PMOS管(MP5、MP6)分别用于抬高与高电平(VH)相连的第三PMOS管(MP3)和第四PMOS管(MP4)的漏极电压，与中级电平(VM)连接的两个NMOS管(MN5、MN6)用于钳制第三NMOS管(MN3)和第四NMOS管(MN4)的漏极电压；第四PMOS管(MP4)的漏极和第四NMOS管(MN4)的漏极分别为电平转换单元的两个输出端。
  3. 根据权利要求2所述的耐压电平转换电路，其特征在于：所述第三PMOS管(MP3)和第四PMOS管(MP4)，二者的源极连接高电平(VH)，第三PMOS管(MP3)的栅极和第四PMOS管(MP4)的漏极相连，第四PMOS管(MP3)的栅极和第三PMOS管(MP4)的漏极相连。
  4. 根据权利要求2所述的耐压电平转换电路，其特征在于：所述第三反相器由低电平(VL)供电，其输入端与输入电平(VIN)连接，输出端与所述第四NMOS管的栅极相连，用于向第四NMOS管提供与输入电平(VIN)极性相反的信号。
  5. 根据权利要求1所述的耐压电平转换电路，其特征在于：所述一级反相器由四个MOS管串联组成，与低电平(VL)连接的第八PMOS管(MP8)用于抬高与高电平(VH)相连的第七PMOS管(MP7)的漏极电压，与中级电平(VM)连接的第七NMOS管(MN7)用于钳制第八NMOS管(MN8)的漏极电压，第七PMOS管(MP7)的漏极和第八NMOS管(MN8)的漏极所输出的电压作为下一级反相器的输入，第八PMOS管(MP8)的漏极作为一级反相器的输出端。
  6. 根据权利要求1所述的耐压电平转换电路，其特征在于：所述二级反相器由四个MOS管串联组成，与低电平(VL)连接的第十PMOS管(MP10)用于抬高与高电平(VH)相连的第九PMOS管(MP9)的漏极电压，与中级电平(VM)连接的第九NMOS管(MN9)用于钳制第十NMOS管(MN10)的漏极电压，第十PMOS管(MP10)的漏极作为二级反相器的输出端。
  7. 根据权利要求6所述的耐压电平转换电路，其特征在于：所述第十NMOS管(MN10)的源极接低电平(VL)。
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