WO2022095503A1 - 电平移位电路以及集成电路 - Google Patents

电平移位电路以及集成电路 Download PDF

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WO2022095503A1
WO2022095503A1 PCT/CN2021/106231 CN2021106231W WO2022095503A1 WO 2022095503 A1 WO2022095503 A1 WO 2022095503A1 CN 2021106231 W CN2021106231 W CN 2021106231W WO 2022095503 A1 WO2022095503 A1 WO 2022095503A1
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switch
transistor
switch tube
signal
level shift
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PCT/CN2021/106231
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English (en)
French (fr)
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李臻
南帐镇
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北京奕斯伟计算技术有限公司
合肥奕斯伟集成电路有限公司
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Publication of WO2022095503A1 publication Critical patent/WO2022095503A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00307—Modifications for increasing the reliability for protection in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00376—Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only

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  • the present application relates to the field of integrated circuits, and in particular, to a level shift circuit and an integrated circuit.
  • the level shift circuit converts the low-voltage logic control signal into a high-voltage logic control signal, and realizes the control of the low-voltage logic input stage to the high-voltage logic output stage. It is widely used in display driving and flash memory. In applications such as source driver chips, power management chips, and timing control chips of liquid crystal displays, the level shift circuit requires a lower voltage input on the one hand, and on the other hand, it is required to work normally under the condition of large power supply noise.
  • the related art provides an existing low-voltage input type level shift circuit used in a scan driver of an LCD module, which converts a low-voltage digital signal into a high-voltage digital signal.
  • the level shift circuit includes two LV (low voltage) MOS transistors M1-M2 and four HV (high voltage) MOS transistors M3-M6.
  • the sources and substrates of the two LV NMOS transistors M1 and M2 are connected to the ground voltage VSSA, the drains are respectively connected to the sources of the two HV NMOS transistors M5 and M6, and the substrates of the M5 and M6 are connected to the ground voltage VSSA,
  • the gate is connected to the control signal VB, which has a suitable voltage to keep M5 and M6 on at the same time and protect the LV NMOS M1 and M2 from damage from the high supply voltage VDDA, and the drain is connected to the two HV PMOS transistors respectively
  • the drains of M3 and M4, the sources of M3 and M4, and the substrate are connected to a supply voltage VDDA (eg, 9 volts or 18 volts).
  • the level shift circuit provided by the related art will have some problems. For example: first, the output The time for signal state transitions increases. Second, a DC current path may be created when all six transistors M1-M6 are on, thereby consuming a larger current. Third, switching states fail due to DC current latches. As a result, the level shift circuit provided by the related art is likely to fail to work normally when the input voltage is low and the power supply noise is relatively large.
  • the present application provides a level shift circuit and an integrated circuit, which are used to solve the problem that the level shift circuit is prone to fail to work normally under the condition of low voltage input and relatively large power supply noise.
  • the present application provides a level shift circuit, comprising: a load unit for receiving a power supply voltage signal and a first control signal to generate a gate control signal; an input unit for receiving an input signal to ground the gate control signal; and a plurality of bias units arranged between the load unit and the input unit, the plurality of bias units are used for receiving bias voltage signals to make the A gate control signal is transmitted to the input unit, a plurality of the bias units are connected in series with each other and coupled to the load unit, and the plurality of bias units include a first bias unit, a second bias unit and a first bias unit.
  • the first bias unit is used to limit the drain potential of the input unit
  • the second bias unit is used to limit the drain potential of the first bias unit
  • the third bias unit The unit is used to provide the gate control power supply of the load unit; wherein, the level shift circuit is used to convert a first signal into a second signal, and the voltage of the second signal is greater than the voltage of the first signal.
  • the input unit includes: a first switch transistor and a second switch transistor, the substrates and sources of the first switch transistor and the second switch transistor are both connected to a ground voltage signal, and the first switch transistor and the second switch transistor are connected to a ground voltage signal.
  • the gates of a switch tube and the second switch tube are connected to the input signal and the reverse input signal respectively;
  • the plurality of bias units include: a third switch tube and a fourth switch tube, the third switch tube and the substrates of the fourth switch tube are connected to the ground voltage signal, and the sources of the third switch tube and the fourth switch tube are respectively connected to the drains of the first switch tube and the second switch tube pole, the gates of the third switch tube and the fourth switch tube are connected to the first bias voltage signal; the fifth switch tube and the sixth switch tube, the fifth switch tube and the sixth switch tube
  • the substrates of the transistors are all connected to the ground voltage signal, the sources of the fifth switch transistor and the sixth switch transistor are connected to the drain electrodes of the third switch transistor and the fourth switch transistor, respectively, and the fifth switch transistor and the sixth switch transistor are respectively connected to the drains.
  • the gates of the switch tube and the sixth switch tube are both connected to the second bias voltage signal; the seventh switch tube and the eighth switch tube, the substrates of the seventh switch tube and the eighth switch tube are both connected to power supply voltage signal, the drains of the seventh switch transistor and the eighth switch transistor are respectively connected to the drains of the fifth switch transistor and the sixth switch transistor, the seventh switch transistor and the sixth switch transistor
  • the gates of the eight switch tubes are all connected to the third bias voltage signal;
  • the load unit includes: a ninth switch tube and a tenth switch tube, the substrates and sources of the ninth switch tube and the tenth switch tube are connected to the power supply voltage signal, the drains of the ninth switch transistor and the tenth switch transistor are connected to the sources of the seventh switch transistor and the eighth switch transistor, and the gate of the ninth switch transistor
  • the poles are respectively coupled to the drains of the sixth switch transistor and the eighth switch transistor, and the gates of the tenth switch transistor are respectively coupled to the drains of the fifth switch transistor and the seventh switch transistor wherein, the drains
  • the first switch transistor and the second switch transistor are one of a first N-type transistor or a first P-type transistor.
  • the third switch transistor and the fourth switch transistor are one of a second N-type transistor or a second P-type transistor.
  • the fifth switch transistor and the sixth switch transistor are one of a second N-type transistor or a second P-type transistor.
  • the seventh switch transistor and the eighth switch transistor are one of a second N-type transistor or a second P-type transistor.
  • the ninth switch transistor and the tenth switch transistor are one of a second N-type transistor or a second P-type transistor.
  • the present application provides an integrated circuit including the above-mentioned level shift circuit.
  • the integrated circuit further includes: a bias voltage generator for providing a plurality of bias voltage signals for the level shift circuit, the plurality of bias voltage signals comprising: a power supply voltage signal, A ground voltage signal, a first control voltage signal, a second control voltage signal, and a third control voltage signal.
  • a bias voltage generator for providing a plurality of bias voltage signals for the level shift circuit, the plurality of bias voltage signals comprising: a power supply voltage signal, A ground voltage signal, a first control voltage signal, a second control voltage signal, and a third control voltage signal.
  • the beneficial effects of the present application are: in the case of not increasing too much layout area, the fast transition of the low-voltage input is ensured, and the influence of the power supply noise on the level shift circuit is effectively reduced, thereby increasing the level shift Robustness of the circuit.
  • FIG. 1 is a schematic structural diagram of a level shift circuit provided by the related art
  • FIG. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present application.
  • 3a-3c are circuit simulation diagrams of the level shift circuit shown in FIG. 2 .
  • FIG. 4 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • an embodiment of the present application provides a level shift circuit, the level shift circuit is used to convert a first signal into a second signal, and the voltage of the second signal is greater than the voltage of the first signal .
  • the level shift circuit includes an input unit 21 , a plurality of bias units 22 and a load unit 23 .
  • the plurality of biasing units 22 include a first biasing unit 221 , a second biasing unit 222 and a third biasing unit 223 .
  • the load unit 23 is used for receiving the power supply voltage signal (VDDA) and the first control signal (VDDA) to generate gate control signals (VOUT, VOUTB).
  • a plurality of bias units 22 are provided between the load unit 23 and the input unit 21, and the plurality of bias units 22 are used for receiving bias voltage signals (VB1, VB2, VB3) to transmit gate control signals (VOUT, VOUTB) To the input unit 21 , a plurality of bias units 22 are connected in series with each other and coupled to the load unit 23 .
  • the input unit 21 is used for receiving input signals (VIN, VINB) to ground the gate control signals (VOUT, VOUTB).
  • the input unit 21 includes: a first switch tube M1 and a second switch tube M2.
  • the substrates and sources of the first switch M1 and the second switch M2 are connected to the ground voltage signal (VSSA), and the gates of the first switch M1 and the second switch M2 are respectively connected to the input signal (VIN). ) and the inverted input signal (VINB).
  • VSSA ground voltage signal
  • VINB inverted input signal
  • the first bias unit 221 includes: a third switch M3 and a fourth switch M4.
  • the substrates of the third switch M3 and the fourth switch M4 are both connected to the ground voltage signal (VSSA), and the sources of the third switch M3 and the fourth switch M4 are connected to the first switch M1 and the second switch, respectively
  • the drain of M2 and the gates of the third switch M3 and the fourth switch M4 are all connected to the first bias voltage signal ( VB1 ).
  • the first bias unit 221 is used to limit the drain potentials of the first switch M1 and the second switch M2 in the input unit 21, limit the switching peak current of the level shift circuit itself, reduce power supply noise, and thus speed up the output signal state switching time.
  • the second bias unit 222 includes: a fifth switch M5 and a sixth switch M6.
  • the substrates of the fifth switch M5 and the sixth switch M6 are both connected to the ground voltage signal (VSSA), and the sources of the fifth switch M5 and the sixth switch M6 are respectively connected to the third switch M3 and the fourth switch M3
  • the drain of M4 and the gates of the fifth switch M5 and the sixth switch M6 are all connected to the second bias voltage signal ( VB2 ).
  • the second biasing unit 222 is used to further improve the power supply noise resistance of the circuit, thereby improving the robustness of the level shift circuit.
  • the third bias unit 223 includes: a seventh switch M7 and an eighth switch M8.
  • the substrates of the seventh switch M7 and the eighth switch M8 are both connected to the power supply voltage signal (VDDA), and the drains of the seventh switch M7 and the eighth switch M8 are respectively connected to the fifth switch M5 and the sixth switch M5
  • the drain of M6, the gates of the seventh switch M7 and the eighth switch M8 are all connected to the third bias voltage signal (VB3).
  • the third bias unit 223 is used to limit the currents of the ninth switch M9 and the tenth switch M10 in the load unit 23, and provides a gate-controlled current source to improve the circuit driving capability.
  • Providing a plurality of bias units 22, that is, providing a plurality of switch tubes and applying corresponding bias voltages to them, can reduce the influence of power supply noise on the level shift circuit, thereby avoiding the generation of a DC current path.
  • the load unit 23 includes: a ninth switch M9 and a tenth switch M10.
  • the substrates and sources of the ninth switch M9 and the tenth switch M10 are connected to the power supply voltage signal (VDDA), and the drains of the ninth switch M9 and the tenth switch M10 are connected to the seventh switch M7 and the eighth switch M10.
  • the source of the switch M8, the gate of the ninth switch M9 are respectively coupled to the drains of the sixth switch M6 and the eighth switch M8, and the gate of the tenth switch M10 is respectively coupled to the fifth switch M5 and the drain of the seventh switch M7.
  • the drains of the fifth switch M5 and the seventh switch M7 are the first output terminals of the level shift circuit, and the drains of the sixth switch M6 and the eighth switch M8 are the second output terminals of the level shift circuit.
  • the first switch M1 and the second switch M2 are either a first N-type transistor (low-voltage N-type transistor) or a first P-type transistor (low-voltage P-type transistor).
  • the third switch M3 and the fourth switch M4 are either a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).
  • the fifth switch M5 and the sixth switch M6 are either a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).
  • the seventh switch M7 and the eighth switch M8 are either a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).
  • the ninth switch M9 and the tenth switch M10 are either a second N-type transistor (high-voltage N-type transistor) or a second P-type transistor (high-voltage P-type transistor).
  • the first switch M1 and the second switch M2 are low-voltage N-type transistors
  • the third switch M3 to the sixth switch M6 are high-voltage N-type transistors
  • the tube M10 is a high-voltage P-type transistor.
  • the bias voltage signals VB1, VB2 and VB3 are provided to turn on the third switch M3 to the eighth switch M8.
  • an input signal VIN with a low voltage high logic state eg 1.4 volts
  • an inverting input signal VINB with a low voltage low logic state eg 0 volts
  • the second switch M2 is turned off due to the inversion signal VINB having a low voltage and low logic state (ie 0 volts) applied to its gate, so the output signal VOUT shows the high voltage high logic state of the power supply voltage VDDA,
  • the output signal VOUTB is connected to ground to display the high voltage low logic state of ground voltage VSSA. That is, an input signal VIN of a low-voltage high logic state (eg, 1.4 volts) is converted to an output signal VOUT of a high-voltage high logic state (eg, 9 volts or 18 volts) by a level shift circuit.
  • the first switch M1 When the input signal VIN switches to a low voltage low logic state (0 volts) and the inversion signal VINB switches to a low voltage high logic state (1.4 volts), the first switch M1 is turned off and the second switch M2 is turned on.
  • the gate of the ninth switch M9 is connected to the ground through the turned-on sixth switch M6, the fourth switch M4 and the second switch M2, the ninth switch M9 is thus turned on, and the gate of the tenth switch M10
  • the ninth switch M9 that is turned on is connected to the power supply voltage VDDA, and the tenth switch M10 is thus turned off. Therefore, the output signal VOUT exhibits a high voltage low logic state (0 volts). That is, the low voltage low logic state (0 volts) is converted to the high voltage low logic state (0 volts) by the level shift circuit.
  • FIG. 3a-3c it is a circuit simulation diagram of the level shift circuit of Figure 2 .
  • Curve A is the variation curve of power supply voltage VDDA with time
  • curve B is the variation curve of ground voltage VSSA with time
  • curve C is the variation curve of input signal with time
  • curve D and curve E are the comparison of output voltage, among which curve D is the correlation
  • the E curve is the change curve of the output voltage of the level shift circuit of this embodiment with time. It can be known from Figures 3a-3c that when the input signal rises from 0 volts to 1.4 volts, the output voltage rises from 0 volts to about 13 volts.
  • the level shift circuit of the embodiment of the present application has the functions of low input voltage and power supply noise resistance at the same time.
  • an embodiment of the present application provides an integrated circuit 40 , which includes the above-mentioned level shift circuit 41 and a bias voltage generator 42 .
  • the bias voltage generator 42 is used to provide a plurality of bias voltage signals for the level shift circuit 41, and the plurality of bias voltage signals include: a power supply voltage signal, a ground voltage signal, a first control voltage signal, a second control voltage signal and the third control voltage signal.
  • the beneficial effects of the present application are: without increasing too much layout area, the fast transition of the low voltage input is ensured, and the influence of power supply noise on the level shift circuit is effectively reduced, thereby increasing the robustness of the level shift circuit .

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Abstract

一种电平移位电路以及集成电路，该电平移位电路包括：一负载单元（23），用以接收电源电压信号（VDDA）以及第一控制信号（VDDA）以产生栅极控制信号（VOUTA、VOUTB）；一输入单元（21），用以接收输入信号（VIN、VINB）以使所述栅极控制信号（VOUTA、VOUTB）接地；以及多个偏置单元（22），设于所述负载单元（23）和所述输入单元（21）之间，所述多个偏置单元（22）用以接收偏置电压信号（VB1、VB2、VB3）以使所述栅极控制信号（VOUTA、VOUTB）传输至所述输入单元（21），多个所述偏置单元（22）相互串联并耦接至所述负载单元（23）；其中，所述电平移位电路用于将第一信号转化成第二信号，所述第二信号的电压大于所述第一信号的电压。

Description

电平移位电路以及集成电路
相关申请的交叉引用
本申请主张在2020年11月6日在中国提交的中国专利申请号No.202011229186.X的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及集成电路领域，具体涉及一种电平移位电路以及集成电路。
背景技术
电平移位电路将低压逻辑控制信号转换为高压逻辑控制信号，实现低压逻辑输入级对高压逻辑输出级的控制，在显示驱动以及闪存等方面有广泛的应用。在液晶显示器的源极驱动芯片、电源管理芯片、时序控制芯片等应用中，电平移位电路一方面要求较低电压输入，另一方面又要求能在较大电源噪声的情况下正常工作。
如图1所示，相关技术提供一种用于LCD模块的扫描驱动器的现有低压输入型电平移位电路，其将一低压数字信号转换为高压数字信号。该电平移位电路包含两个LV(低压)MOS晶体管M1-M2和四个HV(高压)MOS晶体管M3-M6。两个LV NMOS晶体管M1及M2的源极及基板(substrate)连接至接地电压VSSA，漏极分别连接至两个HV NMOS晶体管M5及M6的源极，M5和M6的基板连接至接地电压VSSA，栅极连接至控制信号VB，VB具有合适的电压，可以同时保证M5和M6导通，并且保护LV NMOS M1和M2免受来自高电源电压VDDA的损害，漏极分别连接至两个HV PMOS晶体管M3和M4的漏极，M3和M4的源极及基板连接至电源电压VDDA(例如9伏特或18伏特)。然而在多个驱动较大负载的缓冲同时进行翻转工作时，高电压电源容易产生较大噪声，在高电源噪声影响下，相关技术提供的电平移位电路会出现一些问题，例如：首先，输出信号状态切换的时间会增加。第二，可能在所有六个晶体管M1-M6皆导通时产生DC电流路径，从而消耗较大电流。第三，由于DC电流栓锁(latch)而使得转态(switching  states)失败。进而造成相关技术提供的电平移位电路在低电压输入，在较大电源噪声的情况容易出现不能正常工作的问题。
发明内容
本申请提供一种电平移位电路以及集成电路，用以解决电平移位电路在低电压输入，在较大电源噪声的情况容易出现不能正常工作的问题。
根据本申请的第一方面，本申请提供一种电平移位电路，包括：一负载单元，用以接收电源电压信号以及第一控制信号以产生栅极控制信号；一输入单元，用以接收输入信号以使所述栅极控制信号接地；以及多个偏置单元，设于所述负载单元和所述输入单元之间，所述多个偏置单元用以接收偏置电压信号以使所述栅极控制信号传输至所述输入单元，多个所述偏置单元相互串联并耦接至所述负载单元，所述多个偏置单元包括第一偏置单元、第二偏置单元以及第三偏置单元，所述第一偏置单元用于限制所述输入单元的漏极电位，所述第二偏置单元用于限制第一偏置单元的漏极电位，所述第三偏置单元用于提供所述负载单元的栅极控制电源；其中，所述电平移位电路用于将第一信号转化成第二信号，所述第二信号的电压大于所述第一信号的电压。
在一些实施例中，所述输入单元包括：第一开关管以及第二开关管，所述第一开关管和所述第二开关管的基板及源极均连接至接地电压信号，所述第一开关管和所述第二开关管的栅极连接分别连接至输入信号和反向输入信号；所述多个偏置单元包括：第三开关管和第四开关管，所述第三开关管和所述第四开关管的基板均连接至接地电压信号，所述第三开关管和所述第四开关管的源极分别连接至所述第一开关管和所述第二开关管的漏极，所述第三开关管和所述第四开关管的栅极均连接至第一偏置电压信号；第五开关管和第六开关管，所述第五开关管和所述第六开关管的基板均连接至接地电压信号，所述第五开关管和所述第六开关管的源极分别连接至所述第三开关管和所述第四开关管的漏极，所述第五开关管和所述第六开关管的栅极均连接至第二偏置电压信号；第七开关管和第八开关管，所述第七开关管和所述第八开关管的基板均连接至电源电压信号，所述第七开关管和所述第八开关管的漏极分别连接至所述第五开关管和所述第六开关管的漏极，所述第七开关 管和所述第八开关管的栅极均连接至第三偏置电压信号；所述负载单元包括：第九开关管和第十开关管，所述第九开关管和所述第十开关管的基板和源极均连接至电源电压信号，所述第九开关管和所述第十开关管的漏极连接至所述第七开关管和所述第八开关管的源极，所述第九开关管的栅极分别耦接至所述第六开关管和所述第八开关管的漏极，所述第十开关管的栅极分别耦接至所述第五开关管和所述第七开关管的漏极；其中，所述第五开关管和所述第七开关管的漏极为所述电平移位电路的第一输出端，所述第六开关管和所述第八开关管的漏极为所述电平移位电路的第二输出端。
在一些实施例中，所述第一开关管和所述第二开关管为第一N型晶体管或第一P型晶体管的一种。
在一些实施例中，所述第三开关管和所述第四开关管为第二N型晶体管或第二P型晶体管的一种。
在一些实施例中，所述第五开关管和所述第六开关管为第二N型晶体管或第二P型晶体管的一种。
在一些实施例中，所述第七开关管和所述第八开关管为第二N型晶体管或第二P型晶体管的一种。
在一些实施例中，所述第九开关管和所述第十开关管为第二N型晶体管或第二P型晶体管的一种。
根据本申请的第二方面，本申请提供一种集成电路，包括如上述的电平移位电路。
在一些实施例中，所述集成电路还包括：偏置电压发生器，用于为所述电平移位电路提供多个偏置电压信号，所述多个偏置电压信号包括：电源电压信号、接地电压信号、第一控制电压信号、第二控制电压信号以及第三控制电压信号。
与相关技术相比，本申请的有益效果：在不增加过多的版图面积的情况下，保证低压输入的快速转态，同时有效减少电源噪声对电平移位电路的影响，从而增加电平移位电路的鲁棒性。
附图说明
图1为相关技术提供的一种电平移位电路的结构示意图
图2为本申请实施例提供的一种电平移位电路的结构示意图。
图3a-3c为图2所示的电平移位电路的电路仿真图。
图4为本申请实施例提供的一种集成电路的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图2所示，本申请实施例提供一种电平移位电路，该电平移位电路用于将第一信号转化成第二信号，所述第二信号的电压大于所述第一信号的电压。该电平移位电路包括输入单元21、多个偏置单元22以及负载单元23。其中多个偏置单元22包括第一偏置单元221、第二偏置单元222以及第三偏置单元223。
负载单元23用以接收电源电压信号(VDDA)以及第一控制信号(VDDA)以产生栅极控制信号(VOUT、VOUTB)。
多个偏置单元22设于负载单元23和输入单元21之间，多个偏置单元22用以接收偏置电压信号(VB1、VB2、VB3)以使栅极控制信号(VOUT、VOUTB)传输至输入单元21，多个偏置单元22相互串联并耦接至负载单元23。
输入单元21用以接收输入信号(VIN、VINB)以使栅极控制信号(VOUT、VOUTB)接地。
具体的，输入单元21包括：第一开关管M1以及第二开关管M2。第一开关管M1和第二开关管M2的基板及源极均连接至接地电压信号(VSSA)，第一开关管M1和所述第二开关管M2的栅极连接分别连接至输入信号(VIN)和反向输入信号(VINB)。
第一偏置单元221包括：第三开关管M3和第四开关管M4。第三开关管M3和第四开关管M4的基板均连接至接地电压信号(VSSA)，第三开关管 M3和第四开关管M4的源极分别连接至第一开关管M1和第二开关管M2的漏极，第三开关管M3和第四开关管M4的栅极均连接至第一偏置电压信号(VB1)。该第一偏置单元221用于限制输入单元21中第一开关管M1和第二开关管M2的漏极电位，限制电平移位电路自身的转换尖峰电流，降低电源噪声，从而加快输出信号状态的切换时间。
第二偏置单元222包括：第五开关管M5和第六开关管M6。第五开关管M5和第六开关管M6的基板均连接至接地电压信号(VSSA)，第五开关管M5和第六开关管M6的源极分别连接至第三开关管M3和第四开关管M4的漏极，第五开关管M5和第六开关管M6的栅极均连接至第二偏置电压信号(VB2)。该第二偏置单元222用于进一步提高电路的抗电源噪声，进而提高电平移位电路的鲁棒性。
第三偏置单元223包括：第七开关管M7和第八开关管M8。第七开关管M7和第八开关管M8的基板均连接至电源电压信号(VDDA)，第七开关管M7和第八开关管M8的漏极分别连接至第五开关管M5和第六开关管M6的漏极，第七开关管M7和第八开关管M8的栅极均连接至第三偏置电压信号(VB3)。该第三偏置单元223用于限制负载单元23中第九开关管M9和第十开关管M10的电流，同时提供了栅极控制电流源，提高电路驱动能力。
提供多个偏置单元22，即提供多个开关管并对其施加相应的偏置电压，可以降低电源噪声对电平移位电路的影响，从而避免DC电流路径的产生。
负载单元23包括：第九开关管M9和第十开关管M10。第九开关管M9和第十开关管M10的基板和源极均连接至电源电压信号(VDDA)，第九开关管M9和第十开关管M10的漏极连接至第七开关管M7和第八开关管M8的源极，第九开关管M9的栅极分别耦接至第六开关管M6和第八开关管M8的漏极，第十开关管M10的栅极分别耦接至第五开关管M5和第七开关管M7的漏极。
第五开关管M5和第七开关管M7的漏极为电平移位电路的第一输出端，第六开关管M6和第八开关管M8的漏极为电平移位电路的第二输出端。
其中，第一开关管M1和第二开关管M2为第一N型晶体管(低压N型晶体管)或第一P型晶体管(低压P型晶体管)的一种。
第三开关管M3和第四开关管M4为第二N型晶体管(高压N型晶体管)或第二P型晶体管(高压P型晶体管)的一种。
第五开关管M5和第六开关管M6为第二N型晶体管(高压N型晶体管)或第二P型晶体管(高压P型晶体管)的一种。
第七开关管M7和第八开关管M8为第二N型晶体管(高压N型晶体管)或第二P型晶体管(高压P型晶体管)的一种。
第九开关管M9和第十开关管M10为第二N型晶体管(高压N型晶体管)或第二P型晶体管(高压P型晶体管)的一种。
在本申请实施例中，第一开关管M1以及第二开关管M2为低压N型晶体管，第三开关管M3至第六开关管M6为高压N型晶体管，第七开关管M7至第十开关管M10为高压P型晶体管。以本申请实施例对电平移位电路的操作原理说明如下。
提供偏置电压信号VB1、VB2以及VB3以导通第三开关管M3至第八开关管M8。当将一具有低压高逻辑状态(例如1.4伏特)的输入信号VIN施加于第一开关管M1处且一具有低压低逻辑状态(例如0伏特)的反相输入信号VINB施加于第二开关管M2处时，第一开关管M1导通，第十开关管M10的栅极通过第五开关管M5、第三开关管M3与第一开关管M1连接到地，第十开关管M10因此导通。第二开关管M2由于施加于其栅极处的具有低压低逻辑状态(即0伏特)的反相信号VINB而被关闭(turn off)，因此输出信号VOUT显示电源电压VDDA的高压高逻辑状态，输出信号VOUTB连接到地显示地电压VSSA的高压低逻辑状态。亦即，低压高逻辑状态(例如1.4伏特)的输入信号VIN通过电平移位电路被转换为高压高逻辑状态(例如9伏特或18伏特)的输出信号VOUT。当输入信号VIN切换至低压低逻辑状态(0伏特)且反相信号VINB切换至低压高逻辑状态(1.4伏特)时，第一开关管M1得以关闭且第二开关管M2得以导通。第九开关管M9的栅极藉由导通的第六开关管M6、第四开关管M4和第二开关管M2连接到地，第九开关管M9因此导通，第十开关管M10的栅极藉由导通的第九开关管M9连接到电源电压VDDA，第十开关管M10因此关闭。因此，输出信号VOUT显示高压低逻辑状态(0伏特)。亦即，低压低逻辑状态(0伏特)藉由电平移 位电路而被转换为高压低逻辑状态(0伏特)。
参考图3a-3c，为如图2的电平移位电路的电路仿真图。A曲线为电源电压VDDA随时间的变化曲线；B曲线为接地电压VSSA随时间的变化曲线；C曲线为输入信号随时间的变化曲线；D曲线和E曲线为输出电压比较，其中D曲线为相关技术的电平移位电路的输出电压随时间的变化曲线，E曲线为本实施例的电平移位电路的输出电压随时间的变化曲线。由图3a-3c可知，当输入信号由0伏特上升到1.4伏特时，输出电压由0伏特上升到13伏特左右。在输入信号由0伏特上升到1.4伏特的同时，电源电压VDDA和接地电压VSSA同时施加1.5V的噪声，相关技术的电平移位电路状态转换出现问题，无法正常翻转，本实施例的电平移位电路工作正常。因此，本申请实施例的电平移位电路同时具有低输入电压和抗电源噪声的功能。
如图4所示，本申请实施例提供一种集成电路40，包括上文所述的电平移位电路41以及偏置电压发生器42。
偏置电压发生器42用于为电平移位电路41提供多个偏置电压信号，多个偏置电压信号包括：电源电压信号、接地电压信号、第一控制电压信号、第二控制电压信号以及第三控制电压信号。
本申请的有益效果在于：在不增加过多的版图面积的情况下，保证低压输入的快速转态，同时有效减少电源噪声对电平移位电路的影响，从而增加电平移位电路的鲁棒性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (9)

  1. 一种电平移位电路，包括：
    一负载单元，用以接收电源电压信号以及第一控制信号以产生栅极控制信号；
    一输入单元，用以接收输入信号以使所述栅极控制信号接地；以及
    多个偏置单元，设于所述负载单元和所述输入单元之间，所述多个偏置单元用以接收偏置电压信号以使所述栅极控制信号传输至所述输入单元，多个所述偏置单元相互串联并耦接至所述负载单元，所述多个偏置单元包括第一偏置单元、第二偏置单元以及第三偏置单元，所述第一偏置单元用于限制所述输入单元的漏极电位，所述第二偏置单元用于限制第一偏置单元的漏极电位，所述第三偏置单元用于提供所述负载单元的栅极控制电源；
    其中，所述电平移位电路用于将第一信号转化成第二信号，所述第二信号的电压大于所述第一信号的电压，。
  2. 如权利要求1所述的电平移位电路，其中，
    所述输入单元包括：
    第一开关管以及第二开关管，所述第一开关管和所述第二开关管的基板及源极均连接至接地电压信号，所述第一开关管和所述第二开关管的栅极连接分别连接至输入信号和反向输入信号；
    所述多个偏置单元包括：
    第三开关管和第四开关管，所述第三开关管和所述第四开关管的基板均连接至接地电压信号，所述第三开关管和所述第四开关管的源极分别连接至所述第一开关管和所述第二开关管的漏极，所述第三开关管和所述第四开关管的栅极均连接至第一偏置电压信号；
    第五开关管和第六开关管，所述第五开关管和所述第六开关管的基板均连接至接地电压信号，所述第五开关管和所述第六开关管的源极分别连接至所述第三开关管和所述第四开关管的漏极，所述第五开关管和所述第六开关管的栅极均连接至第二偏置电压信号；
    第七开关管和第八开关管，所述第七开关管和所述第八开关管的基板均 连接至电源电压信号，所述第七开关管和所述第八开关管的漏极分别连接至所述第五开关管和所述第六开关管的漏极，所述第七开关管和所述第八开关管的栅极均连接至第三偏置电压信号；
    所述负载单元包括：
    第九开关管和第十开关管，所述第九开关管和所述第十开关管的基板和源极均连接至电源电压信号，所述第九开关管和所述第十开关管的漏极连接至所述第七开关管和所述第八开关管的源极，所述第九开关管的栅极分别耦接至所述第六开关管和所述第八开关管的漏极，所述第十开关管的栅极分别耦接至所述第五开关管和所述第七开关管的漏极；
    其中，所述第五开关管和所述第七开关管的漏极为所述电平移位电路的第一输出端，所述第六开关管和所述第八开关管的漏极为所述电平移位电路的第二输出端。
  3. 如权利要求2所述的电平移位电路，其中，所述第一开关管和所述第二开关管为第一N型晶体管或第一P型晶体管的一种。
  4. 如权利要求2所述的电平移位电路，其中，所述第三开关管和所述第四开关管为第二N型晶体管或第二P型晶体管的一种。
  5. 如权利要求2所述的电平移位电路，其中，所述第五开关管和所述第六开关管为第二N型晶体管或第二P型晶体管的一种。
  6. 如权利要求2所述的电平移位电路，其中，所述第七开关管和所述第八开关管为第二N型晶体管或第二P型晶体管的一种。
  7. 如权利要求2所述的电平移位电路，其中，所述第九开关管和所述第十开关管为第二N型晶体管或第二P型晶体管的一种。
  8. 一种集成电路，包括如权利要求1-7任一项所述的电平移位电路。
  9. 如权利要求8所述的集成电路，其中，所述集成电路还包括：
    偏置电压发生器，用于为所述电平移位电路提供多个偏置电压信号，所述多个偏置电压信号包括：电源电压信号、接地电压信号、第一控制电压信号、第二控制电压信号以及第三控制电压信号。
PCT/CN2021/106231 2020-11-06 2021-07-14 电平移位电路以及集成电路 WO2022095503A1 (zh)

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