WO2020135313A1 - 功率半导体器件及其制造方法 - Google Patents

功率半导体器件及其制造方法 Download PDF

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WO2020135313A1
WO2020135313A1 PCT/CN2019/127355 CN2019127355W WO2020135313A1 WO 2020135313 A1 WO2020135313 A1 WO 2020135313A1 CN 2019127355 W CN2019127355 W CN 2019127355W WO 2020135313 A1 WO2020135313 A1 WO 2020135313A1
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region
conductivity type
contact
semiconductor device
power semiconductor
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PCT/CN2019/127355
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English (en)
French (fr)
Inventor
孙伟锋
娄荣程
肖魁
林峰
魏家行
李胜
刘斯扬
陆生礼
时龙兴
Original Assignee
东南大学
无锡华润上华科技有限公司
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Application filed by 东南大学, 无锡华润上华科技有限公司 filed Critical 东南大学
Priority to EP19904844.8A priority Critical patent/EP3905334A4/en
Priority to JP2021536814A priority patent/JP7198931B2/ja
Priority to US17/417,677 priority patent/US20220115532A1/en
Publication of WO2020135313A1 publication Critical patent/WO2020135313A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present application relates to semiconductor devices, in particular to a power semiconductor device and a manufacturing method thereof.
  • Silicon carbide is one of the wide bandgap semiconductor materials that has developed rapidly in the past decade. Compared with the widely used semiconductor materials silicon, germanium and gallium arsenide, silicon carbide has the advantages of wide band gap, high breakdown electric field, high carrier saturation drift rate, high thermal conductivity and high power density. Ideal material for high power, high frequency devices. At present, developed countries such as the United States, Europe, and Japan have basically solved the problems of silicon carbide single crystal growth and homogeneous epitaxial thin films, occupying a dominant position in the field of high-power semiconductor devices.
  • the traditional silicon carbide power device needs to be used with a freewheeling diode, and the conduction voltage drop of the internal parasitic body diode of the traditional silicon carbide device is very high, so it is often necessary to parallel a diode outside its Application, but because this diode is external to the traditional power device, the integration is very low, the cost is high, and the efficiency is poor.
  • a power semiconductor device includes: a substrate of a first conductivity type; a drain metal provided on a first surface of the substrate; a drift region of a first conductivity type provided on a second of the substrate Surface, the second surface is opposite to the first surface; the base region, which is the second conductivity type, is provided in the drift region; the first conductivity type and the second conductivity type are opposite conductivity types; the gate Structure, including a gate dielectric layer on the drift region and a gate on the gate dielectric layer, the gate structure extends above the base region; the first conductivity type doped region is away from the base region One side of the gate structure is in contact with the base region; the source region, which is of the first conductivity type, is provided in the base region, between the doped region of the first conductivity type and the gate structure; the contact metal is provided in the On the first conductive type doped region, a contact barrier with rectifying characteristics is formed with the first conductive type doped region below, and the size of the contact metal in the first direction is larger than the first conductive
  • a method for manufacturing a power semiconductor device comprising: obtaining a substrate formed with a drift region, the drift region being formed on one side of the substrate, the substrate and the drift region being of a first conductivity type; doped second Conductivity type ions, forming a base region of the second conductivity type in the drift region; the first conductivity type and the second conductivity type are opposite conductivity types; doping the first conductivity type ions in the drift region Forming a doping region of the first conductivity type in contact with the base region; doping the ions of the first conductivity type, forming a source region of the first conductivity type in the base region; on the doping region of the first conductivity type Forming a contact metal, the contact metal forming a contact barrier with a rectifying characteristic with the doped region of the first conductivity type below, and the contact metal extends toward the source region to a base region that does not reach the source region; Forming a gate structure on the drift region, the gate structure including a gate dielectric layer on the drift region and a gate
  • a contact metal with a contact barrier with rectifying characteristics is introduced at the bottom of the source metal, and a doped region of the first conductivity type is added below the contact metal to replace the parasitic body in the traditional power device Diode to complete the function of freewheeling, the freewheeling voltage drop is significantly reduced, and the reverse recovery speed of the device is faster than that of the parasitic body diode of traditional power devices, and the reverse recovery spike current of the improved structure is more The reverse recovery spike current is lower than the parasitic body diode of traditional power devices, and the reliability is higher.
  • FIG. 1 is a perspective view of a power semiconductor device in an embodiment
  • FIG. 2 is a partially cutaway perspective view of a power semiconductor device in another embodiment
  • FIG. 3 is a top cross-sectional view of the power semiconductor device shown in FIG. 2 along another cross-section;
  • FIG. 4 is a current comparison diagram of a device with an embodiment of the present application and a conventional silicon carbide power semiconductor device when the gate drain voltage is zero, the source terminal voltage gradually increases;
  • FIG. 5 is a comparison diagram of the breakdown voltage of the device according to an embodiment of the present application and a conventional silicon carbide power semiconductor device;
  • FIG. 6 is a flowchart of a method of manufacturing a power semiconductor device in an embodiment.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “above”, “above”, etc. It can be used here for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “below” or “below” the elements will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application.
  • the embodiments of the present application should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing.
  • an implanted area shown as a rectangle generally has round or curved features and/or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present application.
  • the semiconductor vocabulary used in this article is a technical vocabulary commonly used by those skilled in the art.
  • the P+ type represents the P type with heavy doping concentration
  • the P type represents the medium P-type doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light-doping concentration N type.
  • FIG. 1 is a perspective view of the structure of a power semiconductor device in an embodiment.
  • the power semiconductor device includes a substrate 1, a drain metal 10, a drift region 2, a base region 3, a first conductivity type doped region 13, a source region 4, a contact metal 11, a source metal 6 and a gate structure (including a gate 8 and gate dielectric layer 7).
  • the power semiconductor device is a silicon carbide power semiconductor device, but the power semiconductor device of this application is also applicable to power semiconductor devices of other substrate materials.
  • the substrate 1 is a substrate of the first conductivity type.
  • the drain metal 10 is provided on the back surface of the substrate 1 (that is, the side facing downward in FIG. 1).
  • the drift region 2 is a drift region of the second conductivity type, which is provided on the front side of the substrate 1 (that is, the upward side in FIG. 1 ).
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the substrate 1 is an N-type substrate
  • the drift region 2 is an N-type drift region.
  • the first conductivity type may be P type
  • the second conductivity type may be N type.
  • the base region 3 is provided in the drift region 2.
  • the base region 3 is a P-type base region.
  • the gate dielectric layer 7 is provided on the drift region 2, and the gate 8 is provided on the gate dielectric layer 7.
  • the source region 4 is an N+ source region in the embodiment shown in FIG. 1 and is provided in the base region 3 between the first conductivity type doped region 13 and the gate structure.
  • the gate structure extends above the base region 3.
  • the first conductivity type doped region 13 is an N-type doped region in the embodiment shown in FIG. 1, and contacts the base region 3 on the side of the base region 3 away from the gate structure.
  • the contact metal 11 is provided on the first conductive type doped region 13 and forms a contact barrier with rectifying characteristics with the first conductive type doped region 13 below, for example, it may be a Schottky barrier.
  • the material of the contact metal 11 may be gold, titanium, nickel, or the like, which has a rectifying characteristic when the barrier formed after contacting the semiconductor.
  • the size of the contact metal 11 in the Y-axis direction is larger than the size of the first conductivity type doped region 13 in the Y-axis direction, so that the contact metal 11 completely covers and extends above the first conductivity type doped region 13 To the base 3 above.
  • the Y-axis direction in FIG. 1 is also the connection direction of the gate 8 and the contact metal 11.
  • the contact metal 11 is only slightly “wider” than the first conductivity type doped region 13 so as not to extend above the source region 4.
  • the source metal 6 wraps the contact metal 11 and contacts the source region 4.
  • a contact metal 11 having a contact barrier with rectifying characteristics is introduced at the bottom of the source metal 6, and a first conductivity type doped region 13 is added below the contact metal 11 to replace the parasitic body in the conventional power device Diode to complete the function of freewheeling, the freewheeling voltage drop is significantly reduced, and the reverse recovery speed of the device is faster than that of the parasitic body diode of traditional power devices, and the reverse recovery spike current of the improved structure is more The reverse recovery spike current is lower than the parasitic body diode of traditional power devices, and the reliability is higher.
  • the power semiconductor device further includes a body contact region 5 of the second conductivity type.
  • the body contact region 5 is provided in the base region 3, between the source region 4 and the first conductivity type doped region 13, and the contact metal 11 is in contact with the body contact region 5.
  • the body contact region 5 is a P+ contact region
  • the contact metal 11 extends above the body contact region 5 in the Y-axis direction
  • the source metal 6 also contacts the body contact region 5.
  • each side of the gate structure has a body contact region 5, and the two individual contact regions 5 are bilaterally symmetric.
  • the power semiconductor device further includes a passivation layer 9.
  • the passivation layer 9 covers the gate structure and wraps both sides of the gate structure.
  • the gate dielectric layer 7 may include conventional dielectric materials such as silicon oxide, nitride, and oxynitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 7 A generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100 may be included.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate 8 is a polysilicon material. In other embodiments, metal, metal nitride, metal silicide, or similar compounds may be used as the material of the gate 8.
  • the power semiconductor device further includes a second conductivity type doped region 12 provided in the drift region 2.
  • the second conductivity type doped region 12 is a P+ doped region.
  • the second conductivity type doped region 12 is disposed under the base region 3 and the first conductivity type doped region 13 (that is, a portion of the second conductivity type doped region 12 is disposed under the base region 3 and a portion is disposed in the first conductivity type doped region Under the impurity region 13) and in contact with the base region 3 and the first conductivity type doped region 13.
  • the first conductivity type doped region 13 is introduced below the base region 3, and the second conductivity type doped region 12 extends below the first conductivity type doped region 13, so that when the power semiconductor device is subjected to reverse withstand voltage, The depletion layer between the second conductivity type doped region 12 and the first conductivity type doped region 13 and the drift region 2 will pinch off, limiting the large electric field outside the first conductivity type doped region 13, so the device can Maintain a high reverse withstand voltage value.
  • the second conductive type doped regions 12 are composed of a plurality of P+ sub-doped regions, and each P+ sub-doped region is distributed at intervals in the X-axis direction. It can be understood that the X axis and the Y axis form a horizontal plane (there is only one plane passing through two intersecting straight lines).
  • the power semiconductor device has P+ sub-doped regions spaced apart under the base region 3 along the gate width direction (ie, the X-axis direction in FIGS. 2 and 3 ).
  • the depletion layer between two adjacent P+ sub-doped regions is pinched off, so it is the same as the device structure where the second conductivity type doped region 12 is a complete region, and Toward the withstand voltage; and when the body diode is forward-conducted, due to the existence of the area between every two adjacent P+ sub-doped regions in the gate width direction, the forward conduction area of the body diode is increased, which further improves the continued Current conduction capability.
  • each P+ sub-doped region is equal in size and distributed at equal intervals in the X-axis direction.
  • the ratio of the dimension a of the pitch of each P+ sub-doped region in the X-axis direction to the dimension b of the P+ sub-doped region in the X-axis direction is 0.2-0.6:1. It should be noted that the sizes of a and b in FIG. 3 do not represent the actual size/ratio of the P+ sub-doped region.
  • the doping concentration of the first conductivity type doping region 13 is greater than that of the drift region 2 and less than that of the source region 4.
  • the first conductivity type doped region 13 is an N-type doped region, and its doping concentration is much lower than that of the N+ source region. Specifically, the concentration of the region can be adjusted according to device parameter requirements.
  • the doping ions in the second conductivity type doping region 12 are aluminum ions
  • the doping ions in the base region 3 are aluminum ions
  • the doping ions in the first conductivity type doping region 13 are nitrogen
  • the doping ions in the body contact region 5 are aluminum ions
  • the doping ions in the source region 4 are nitrogen ions.
  • the structure of the power semiconductor device described above is particularly suitable for silicon carbide power devices.
  • the structure is also applicable to power devices with other substrate materials, such as power devices such as silicon substrates, germanium substrates, and gallium arsenide substrates.
  • FIG. 4 is a current comparison diagram of the voltage at the source end gradually increasing when the gate drain voltage of the device according to an embodiment of the present application and a conventional silicon carbide power semiconductor device are zero. It can be seen that the turn-on voltage of the body diode of the device of the present application is significantly lower than that of the conventional device.
  • FIG. 5 is a comparison diagram of breakdown voltages of a device according to an embodiment of the present application and a conventional silicon carbide power semiconductor device. It can be seen that the breakdown voltage of the device of this application is still maintained at a relatively high value.
  • the present application also provides a method for manufacturing a power semiconductor device, which can be used to manufacture the power semiconductor device of any of the above embodiments.
  • 6 is a flowchart of a method for manufacturing a power semiconductor device in an embodiment, including the following steps:
  • S610 Acquire a substrate formed with a drift region.
  • the drift region is formed on one side of the substrate. Both the substrate and the drift region are of the first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • an N-type epitaxial layer may be epitaxially formed on the surface of the N-type substrate as a drift region.
  • a photoresist can be used as a mask after photolithography to form a P-type base region in the drift region by aluminum ion implantation.
  • photolithography may be performed again, and then a first conductivity type doped region in contact with the base region is formed in the drift region by nitrogen ion implantation.
  • step S630 after removing the photoresist in step S630, photolithography is performed again, and then a source region of the first conductivity type is formed in the base region by nitrogen ion implantation.
  • a contact metal may be deposited, and then the contact metal may be etched and etched.
  • the etched contact metal must have a sufficient width to allow the contact metal to conduct from the first
  • the type doped region extends above the base region, but it should not be too wide to avoid reaching the source region.
  • the contact metal and the underlying doped region of the first conductivity type form a contact barrier with rectifying characteristics, which may be, for example, a Schottky barrier.
  • the material of the contact metal may be gold, titanium, nickel, etc., which have a rectifying characteristic after contact with the semiconductor.
  • the gate oxide layer may be grown after removing the photoresist in step S650, and then polysilicon is deposited, and the polysilicon gate is etched and etched.
  • the metal is deposited after etching the electrode contact area, then the metal is etched to extract the electrode, and finally the passivation treatment is performed.
  • the passivation process includes forming a passivation layer covering the gate structure, the passivation layer wrapping both sides of the gate structure.
  • steps S610 and S620 may further include a step of forming a second conductivity type doped region in the drift region.
  • a photoresist is used as a mask, and aluminum ion implantation is used to form spaced-apart second conductivity type doped regions in the drift region.
  • the second conductivity type doped region is formed below the base region and the first conductivity type doped region, and is in contact with the base region and the first conductivity type doped region.
  • the steps S620 and S650 may further include a step of forming a body contact region in the base region. Specifically, after removing the photoresist, photolithography is performed again, and a P+ type body contact region is formed in the base region by aluminum ion implantation. The body contact region is formed between the source region and the first conductivity type doped region. In one embodiment, the step of forming the body contact region is between steps S630 and S640.

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Abstract

一种功率半导体器件及其制造方法，所述器件包括：衬底(1)；漏极金属(10)；漂移区(2)；基区(3)；栅结构；第一导电类型掺杂区(13)，在基区(3)远离栅结构的一侧与基区(3)接触；源区(4)，设于基区(3)中、第一导电类型掺杂区(13)与栅结构之间；接触金属(11)，设于第一导电类型掺杂区(13)上，与下方的第一导电类型掺杂区(13)形成具有整流特性的接触势垒；源极金属(6)，包裹接触金属(11)，并与源区(4)接触。

Description

功率半导体器件及其制造方法 技术领域
本申请涉及半导体器件，特别是涉及一种功率半导体器件及其制造方法。
背景技术
碳化硅是近十几年来迅速发展起来的宽禁带半导体材料之一。与广泛应用的半导体材料硅、锗以及砷化镓相比，碳化硅具有宽禁带、高击穿电场、高载流子饱和漂移速率、高热导率及高功率密度等优点，是制备高温、大功率、高频器件的理想材料。目前美、欧、日等发达国家已经基本解决了碳化硅单晶生长和同质外延薄膜等问题，在大功率半导体器件领域占据主导地位。
在目前的工业应用中，传统的碳化硅功率器件由于工作要求搭配续流二极管使用，而传统碳化硅器件的内部寄生的体二极管的导通压降很高，因此经常需要在其外部并联一个二极管进行应用，但是由于这个二极管是在传统功率器件的外部，这样做集成度很低，成本很高，并且效率较差。
发明内容
基于此，有必要提供一种体二极管具有较好的正向导通能力的功率半导体器件及其制造方法。
一种功率半导体器件，包括：衬底，为第一导电类型；漏极金属，设于所述衬底的第一面；漂移区，为第一导电类型，设于所述衬底的第二面，所述第二面与所述第一面相对；基区，为第二导电类型，设于所述漂移区中；所述第一导电类型和第二导电类型为相反的导电类型；栅结构，包括所述漂移区上的栅介质层和所述栅介质层上的栅极，所述栅结构延伸到所述基区的上方；第一导电类型掺杂区，在所述基区远离所述栅结构的一侧与基区接触； 源区，为第一导电类型，设于所述基区中、所述第一导电类型掺杂区与栅结构之间；接触金属，设于所述第一导电类型掺杂区上，与下方的第一导电类型掺杂区形成具有整流特性的接触势垒，且所述接触金属在第一方向的尺寸大于所述第一导电类型掺杂区在第一方向的尺寸，从而使得所述接触金属延伸至第一导电类型掺杂区旁的基区上方未到达所述源区的位置，所述第一方向为所述栅极和所述接触金属的连线方向；以及源极金属，包裹所述接触金属，并与所述源区接触。
一种功率半导体器件的制造方法，包括：获取形成有漂移区的衬底，所述漂移区形成于所述衬底的一面，所述衬底和漂移区为第一导电类型；掺杂第二导电类型离子，在所述漂移区中形成第二导电类型的基区；所述第一导电类型和第二导电类型为相反的导电类型；掺杂第一导电类型离子，在所述漂移区中形成与所述基区接触的第一导电类型掺杂区；掺杂第一导电类型离子，在所述基区中形成第一导电类型的源区；在所述第一导电类型掺杂区上形成接触金属，所述接触金属与下方的第一导电类型掺杂区形成具有整流特性的接触势垒，且所述接触金属向所述源区延伸至未到达所述源区的基区上方；在所述漂移区上形成栅结构，所述栅结构包括所述漂移区上的栅介质层和所述栅介质层上的栅极，所述栅结构延伸到所述基区的与所述第一导电类型掺杂区相对的一侧上方；以及形成包裹所述接触金属的源极金属，所述源极金属与所述源区接触。
上述功率半导体器件及其制造方法，在源极金属底部引入具有整流特性的接触势垒的接触金属，同时在接触金属的下方加入第一导电类型掺杂区，替代了传统功率器件中寄生的体二极管来完成续流的功能，续流导通压降明显降低，并且器件的反向恢复速度更快于传统功率器件的寄生体二极管的反向恢复速度，且改进结构的反向恢复尖峰电流更低于传统功率器件的寄生体二极管的反向恢复尖峰电流，可靠性更高。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中功率半导体器件的立体图；
图2是另一实施例中功率半导体器件的局部剖视立体图；
图3是图2所示的功率半导体器件沿另一剖面的俯视剖面图；
图4是本申请一实施例的器件与一传统碳化硅功率半导体器件在栅漏压为零时，源端电压逐渐增大的电流对比图；
图5是本申请一实施例的器件与常规碳化硅功率半导体器件的击穿电压比较图；
图6是一实施例中功率半导体器件的制造方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到” 其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行 时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中功率半导体器件结构立体图。该功率半导体器件包括衬底1、漏极金属10、漂移区2、基区3、第一导电类型掺杂区13、源区4、接触金属11、源极金属6以及栅结构(包括栅极8和栅介质层7)。在本实施例中，该功率半导体器件为碳化硅功率半导体器件，但本申请的功率半导体器件同样适用于其他衬底材质的功率半导体器件。
其中，衬底1为第一导电类型的衬底。漏极金属10设于1衬底的背面(即图1中朝下的一面)。漂移区2为第二导电类型的漂移区，设于衬底1的正面(即图1中朝上的一面)。在图1所示的实施例中，第一导电类型是N型，第二导电类型是P型，及衬底1为N型衬底，漂移区2为N型漂移区。在另一个实施例中，也可以第一导电类型是P型，第二导电类型是N型。
基区3设于漂移区2中，在图1所示的实施例中，基区3为P型基区。栅介质层7设于漂移区2上，栅极8设于栅介质层7上。源区4在图1所示的实施例中为N+源区，设于基区3中、第一导电类型掺杂区13与栅结构之间。栅结构延伸到基区3的上方。在图1所示的实施例中，栅结构的两侧各有一个基区3、各有一个源区4，且这两个基区3(以及两个源区4)左右对称设置。第一导电类型掺杂区13在图1所示的实施例中为N型掺杂区，在基区3远离栅结构的一侧与基区3接触。
接触金属11设于第一导电类型掺杂区13上，与下方的第一导电类型掺杂区13形成具有整流特性的接触势垒，例如可以是肖特基势垒。在一个实施例中，接触金属11的材质可以为金、钛和镍等和半导体接触后形成的势垒具 有整流特性的这类金属。
在图1中，接触金属11在Y轴方向的尺寸大于第一导电类型掺杂区13在Y轴方向的尺寸，从而使得接触金属11完全覆盖第一导电类型掺杂区13的上方、并延伸至基区3上方。图1中的Y轴方向也是栅极8和接触金属11的连线方向。在图1所示的实施例中，接触金属11只比第一导电类型掺杂区13略“宽”，以免延伸至源区4上方。源极金属6包裹接触金属11，并与源区4接触。
上述功率半导体器件，在源极金属6底部引入具有整流特性的接触势垒的接触金属11，同时在接触金属11的下方加入第一导电类型掺杂区13，替代了传统功率器件中寄生的体二极管来完成续流的功能，续流导通压降明显降低，并且器件的反向恢复速度更快于传统功率器件的寄生体二极管的反向恢复速度，且改进结构的反向恢复尖峰电流更低于传统功率器件的寄生体二极管的反向恢复尖峰电流，可靠性更高。
在图1所示的实施例中，功率半导体器件还包括第二导电类型的体接触区5。体接触区5设于基区3中、源区4与第一导电类型掺杂区13之间，接触金属11与体接触区5相接触。在图1所示的实施例中，体接触区5为P+接触区，接触金属11在Y轴方向上延伸至体接触区5的上方，源极金属6也与体接触区5接触。在图1所示的实施例中，栅结构的两侧各有一个体接触区5，且这两个体接触区5左右对称。对第一导电类型掺杂区13来说，其两侧也是各有一个相互对称的体接触区5。
在图1所示的实施例中，功率半导体器件还包括钝化层9。钝化层9将栅结构覆盖，包裹栅结构的两侧。
在一个实施例中，栅介质层7可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅介质层7可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
在一个实施例中，栅极8为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极8的材料。
在图1所示的实施例中，功率半导体器件还包括设于漂移区2中的第二导电类型掺杂区12。在本实施例中，第二导电类型掺杂区12是P+掺杂区。第二导电类型掺杂区12设于基区3和第一导电类型掺杂区13下方(即第二导电类型掺杂区12的一部分设于基区3下方、一部分设于第一导电类型掺杂区13下方)，并与基区3和第一导电类型掺杂区13接触。
参见图1，在一个实施例中，第二导电类型掺杂区12位于基区3下方的部分与位于第一导电类型掺杂区13下方的部分在Y轴方向上的尺寸比例为0.2-0.4:1，即c:d＝0.2-0.4:1。需要说明的是，图1中c和d的尺寸不代表第二导电类型掺杂区12的实际尺寸/比例。
在基区3的下方引入第一导电类型掺杂区13，且第二导电类型掺杂区12延伸至第一导电类型掺杂区13下方，使得功率半导体器件在承受反向耐压的时候，第二导电类型掺杂区12与第一导电类型掺杂区13以及漂移区2之间的耗尽层会夹断，将大电场限制在第一导电类型掺杂区13以外，因而本器件可以维持较高的反向耐压值。
请一并参照图2和图3，第二导电类型掺杂区12由多个P+子掺杂区组成，各P+子掺杂区在X轴方向上间隔分布。可以理解的，X轴和Y轴构成一个水平面(经过两条相交直线的有且仅有一个平面)。在该实施例中，功率半导体器件通过在基区3下方沿着栅宽方向(即图2和图3中的X轴方向)间隔分布P+子掺杂区。在承受反向耐压的时候，相邻两个P+子掺杂区之间的耗尽层夹断，因此其与第二导电类型掺杂区12为一个完整区域的器件结构一样，能够实现反向耐压；而当体二极管正向导通时，由于栅宽方向上每两个相邻的P+子掺杂区之间的区域的存在，使得体二极管正向导通面积增加，从而进一步提升了续流导通能力。
参见图3，在该实施例中，各P+子掺杂区大小相等、且在X轴方向上等间距分布。
参见图3，在一个实施例中，各P+子掺杂区的间距在X轴方向上的尺寸a与P+子掺杂区在X轴方向上的尺寸b比例为0.2-0.6:1。需要说明的是，图3中a和b的尺寸不代表P+子掺杂区的实际尺寸/比例。
在图1所示的实施例中，第一导电类型掺杂区13的掺杂浓度大于漂移区2的掺杂浓度、小于源区4的掺杂浓度。在一个实施例中，第一导电类型掺杂区13为N型掺杂区，其掺杂浓度大大低于N+源区的掺杂浓度，具体可根据器件参数要求调整区域的浓度。
在一个实施例中，第二导电类型掺杂区12中的掺杂离子是铝离子，基区3中的掺杂离子是铝离子，第一导电类型掺杂区13中的掺杂离子是氮离子，体接触区5中的掺杂离子是铝离子，源区4中的掺杂离子是氮离子。
由于碳化硅功率器件通常搭配续流二极管使用，因此上述功率半导体器件的结构尤其适用于碳化硅功率器件。但本领域技术人员可以理解的，该结构同样适用于其他衬底材质的功率器件，例如硅衬底、锗衬底、砷化镓衬底等的功率器件。
图4是本申请一实施例的器件与一传统碳化硅功率半导体器件在栅漏压为零时，源端电压逐渐增大的电流对比图。可以看出本申请器件的体二极管的导通电压要明显低于传统器件。图5是本申请一实施例的器件与常规碳化硅功率半导体器件的击穿电压比较图。可以看出本申请器件击穿电压仍然维持在较高的值。
本申请还提供一种功率半导体器件的制造方法，可以用于制造以上任一实施例的功率半导体器件。图6是一实施例中功率半导体器件的制造方法的流程图，包括以下步骤：
S610，获取形成有漂移区的衬底。
漂移区形成于衬底的一面，衬底和漂移区均为第一导电类型。在本实施例中，第一导电类型是N型，第二导电类型是P型；在另一个实施例中，第一导电类型是P型，第二导电类型是N型。
在一个实施例中，可以通过在N型衬底的表面外延一层N型外延层，作 为漂移区。
S620，掺杂第二导电类型离子，在漂移区中形成第二导电类型的基区。
在一个实施例中，可以在光刻后以光刻胶为掩膜，通过铝离子注入在漂移区中形成P型基区。
S630，掺杂第一导电类型离子，在漂移区中形成与基区接触的第一导电类型掺杂区。
在一个实施例中，可以在去除步骤S620的光刻胶后再次光刻，然后通过氮离子注入在漂移区中形成与基区接触的第一导电类型掺杂区。
S640，掺杂第一导电类型离子，在基区中形成第一导电类型的源区。
在一个实施例中，可以在去除步骤S630的光刻胶后再次光刻，然后通过氮离子注入在基区中形成第一导电类型的源区。
S650，在第一导电类型掺杂区上形成接触金属。
在一个实施例中，可以在去除步骤S640的光刻胶后淀积接触金属，然后光刻并刻蚀该接触金属，刻蚀后的接触金属要保留足够的宽度，使得接触金属从第一导电类型掺杂区上伸出，到达基区上方，但不应太宽以免到达源区的上方。
接触金属与下方的第一导电类型掺杂区形成具有整流特性的接触势垒，例如可以是肖特基势垒。接触金属的材质可以为金、钛和镍等和半导体接触后形成的势垒具有整流特性的这类金属。
S660，在漂移区上形成栅结构。
在一个实施例中，可以在去除步骤S650的光刻胶后生长栅氧化层，然后淀积多晶硅，光刻并刻蚀出多晶硅栅。
S670，形成包裹接触金属的源极金属，源极金属与源区接触。
在本实施例中，是刻蚀电极接触区后淀积金属，再刻蚀金属引出电极，最后进行钝化处理。在本实施例中，钝化处理包括形成将栅结构覆盖的钝化层，该钝化层包裹栅结构的两侧。
在一个实施例中，步骤S610和S620之间还可以包括在漂移区内形成第 二导电类型掺杂区的步骤。具体可以是在光刻后以光刻胶为掩膜，通过铝离子注入在漂移区中形成间隔分布的第二导电类型掺杂区。第二导电类型掺杂区形成于基区和第一导电类型掺杂区的下方，并与所述基区和第一导电类型掺杂区接触。
在一个实施例中，步骤S620和S650之间还可以包括在基区内形成体接触区的步骤。具体可以是去除光刻胶后再次光刻，通过铝离子注入在基区内形成P+型体接触区。体接触区形成于源区与第一导电类型掺杂区之间。在一个实施例中，形成体接触区的步骤是在步骤S630和S640之间。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种功率半导体器件，包括：
    衬底，为第一导电类型；
    漏极金属，设于所述衬底的第一面；
    漂移区，为第一导电类型，设于所述衬底的第二面，所述第二面与所述第一面相对；
    基区，为第二导电类型，设于所述漂移区中；所述第一导电类型和第二导电类型为相反的导电类型；
    栅结构，包括所述漂移区上的栅介质层和所述栅介质层上的栅极，所述栅结构延伸到所述基区的上方；
    第一导电类型掺杂区，在所述基区远离所述栅结构的一侧与基区接触；
    源区，为第一导电类型，设于所述基区中、所述第一导电类型掺杂区与栅结构之间；以及
    接触金属，设于所述第一导电类型掺杂区上，与下方的第一导电类型掺杂区形成具有整流特性的接触势垒，且所述接触金属在第一方向的尺寸大于所述第一导电类型掺杂区在第一方向的尺寸，从而使得所述接触金属延伸至第一导电类型掺杂区旁的基区上方未到达所述源区的位置，所述第一方向为所述栅极和所述接触金属的连线方向；
    源极金属，包裹所述接触金属，并与所述源区接触。
  2. 根据权利要求1所述的功率半导体器件，其中，还包括第二导电类型的体接触区，所述体接触区设于所述基区中、所述源区与第一导电类型掺杂区之间，所述接触金属与所述体接触区相接触。
  3. 根据权利要求1所述的功率半导体器件，其中，还包括设于所述漂移区中的第二导电类型掺杂区，所述第二导电类型掺杂区设于所述基区和第一导电类型掺杂区下方，并与所述基区和第一导电类型掺杂区接触。
  4. 根据权利要求3所述的功率半导体器件，其中，所述第二导电类型掺 杂区由多个子掺杂区组成，各子掺杂区在第二方向上间隔分布，所述第二方向与所述第一方向垂直、且所述第二方向与第一方向构成的面为水平面。
  5. 根据权利要求4所述的功率半导体器件，其中，各所述子掺杂区大小相等、且在所述第二方向上等间距分布，所述间距在第二方向上的尺寸与所述子掺杂区在第二方向上的尺寸比例为0.2-0.6:1。
  6. 根据权利要求3所述的功率半导体器件，其中，所述第二导电类型掺杂区位于所述基区下方的部分与位于所述第一导电类型掺杂区下方的部分在所述第一方向上的尺寸比例为0.2-0.4:1。
  7. 根据权利要求1所述的功率半导体器件，其中，所述第一导电类型掺杂区的掺杂浓度大于所述漂移区的掺杂浓度、小于所述源区的掺杂浓度。
  8. 根据权利要求1所述的功率半导体器件，其中，所述接触金属的材质为金、钛、镍中的至少一种。
  9. 根据权利要求1所述的功率半导体器件，其中，所述具有整流特性的接触势垒为肖特基势垒。
  10. 根据权利要求1所述的功率半导体器件，其中，所述第一导电类型是N型，第二导电类型是P型。
  11. 根据权利要求1-10中任一项所述的功率半导体器件，其中，所述功率半导体器件为碳化硅功率半导体器件。
  12. 一种功率半导体器件的制造方法，包括：
    获取形成有漂移区的衬底，所述漂移区形成于所述衬底的一面，所述衬底和漂移区为第一导电类型；
    掺杂第二导电类型离子，在所述漂移区中形成第二导电类型的基区；所述第一导电类型和第二导电类型为相反的导电类型；
    掺杂第一导电类型离子，在所述漂移区中形成与所述基区接触的第一导电类型掺杂区；
    掺杂第一导电类型离子，在所述基区中形成第一导电类型的源区；
    在所述第一导电类型掺杂区上形成接触金属，所述接触金属与下方的第 一导电类型掺杂区形成具有整流特性的接触势垒，且所述接触金属向所述源区延伸至未到达所述源区的基区上方；
    在所述漂移区上形成栅结构，所述栅结构包括所述漂移区上的栅介质层和所述栅介质层上的栅极，所述栅结构延伸到所述基区的与所述第一导电类型掺杂区相对的一侧上方；以及
    形成包裹所述接触金属的源极金属，所述源极金属与所述源区接触。
  13. 根据权利要求12所述的方法，其中，所述获取形成有漂移区的衬底的步骤之后，所述掺杂第二导电类型离子，在所述漂移区中形成第二导电类型的基区的步骤之前，还包括在漂移区内形成第二导电类型掺杂区的步骤，所述第二导电类型掺杂区形成于基区和第一导电类型掺杂区的下方，并与所述基区和第一导电类型掺杂区接触。
  14. 根据权利要求12所述的方法，其中，所述掺杂第二导电类型离子，在所述漂移区中形成第二导电类型的基区的步骤之后，所述在所述第一导电类型掺杂区上形成接触金属的步骤之前，还包括在基区内形成体接触区的步骤，所述体接触区形成于所述源区与第一导电类型掺杂区之间。
  15. 根据权利要求13所述的方法，其中，所述在漂移区内形成第二导电类型掺杂区的步骤包括在光刻后以光刻胶为掩膜，通过铝离子注入在漂移区中形成间隔分布的第二导电类型掺杂区。
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