WO2020134957A1 - 显示面板、显示面板的制造方法和显示装置 - Google Patents

显示面板、显示面板的制造方法和显示装置 Download PDF

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WO2020134957A1
WO2020134957A1 PCT/CN2019/123580 CN2019123580W WO2020134957A1 WO 2020134957 A1 WO2020134957 A1 WO 2020134957A1 CN 2019123580 W CN2019123580 W CN 2019123580W WO 2020134957 A1 WO2020134957 A1 WO 2020134957A1
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layer
hole
display panel
region
via hole
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French (fr)
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张合静
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HKC Co Ltd
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HKC Co Ltd
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Priority to US17/298,605 priority Critical patent/US12218208B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a method of manufacturing the display panel, and a display device.
  • TFT Thin film transistor
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the purpose of the present application is to provide a display panel, a method of manufacturing the display panel, and a display device.
  • the present application discloses a display panel.
  • the display panel includes: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer, the semiconductor layer including a source region, A drain region and a channel region, the channel region is provided between the source region and the drain region; a gate insulating layer formed at a position of the semiconductor layer corresponding to the channel region; A gate metal layer formed on the gate insulating layer; a dielectric layer covering the buffer layer, the semiconductor layer, and the gate metal layer, the corresponding to the source region and the drain region
  • the dielectric layer includes vias, the vias include a first via and a second via, the first via is connected to the source region or the drain region, and the second via is located at The top of the first via hole communicates with the first via hole, and the second via hole has a larger diameter than the first via hole.
  • the application also discloses a method for manufacturing a display panel, including the following steps:
  • the semiconductor layer including a source region, a drain region, and a channel region, the channel region being disposed between the source region and the drain region;
  • via holes respectively corresponding to the source region and the drain region on the dielectric layer, the via holes including a first via hole and a second via hole, the first via hole and the source A pole region or the drain region is connected, the second via hole is located on top of the first via hole, communicates with the first via hole, and the second via hole has a larger diameter than the first via hole Aperture.
  • the present application also discloses a display device including the above-mentioned display panel.
  • the present invention etches a first via hole and a second via hole on the dielectric layer, the second via hole is located on the top of the first via hole
  • the hole diameter of the second via hole is larger than that of the first via hole.
  • FIG. 1 is a schematic diagram of an exemplary single-hole top-gate thin film transistor
  • FIG. 2 is a schematic diagram of a display panel according to one embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a display panel according to one embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a display panel according to one embodiment of the present invention.
  • FIG. 5 is a schematic diagram of steps of a method for manufacturing a display panel according to one embodiment of the present invention.
  • 6 to 10 are schematic flowcharts of a method for manufacturing a display panel according to one embodiment of the present invention.
  • FIG. 11 is a schematic diagram of steps of a method for manufacturing a display panel according to one embodiment of the present invention.
  • 12 to 14 are schematic flowcharts of a method for manufacturing a display panel according to one embodiment of the present invention.
  • 15 is a schematic diagram of steps of a method for manufacturing a display panel according to one embodiment of the present invention.
  • 16 to 17 are schematic flowcharts of a method for manufacturing a display panel according to one embodiment of the present invention.
  • FIG. 18 is a schematic diagram of a display panel according to one embodiment of the present invention.
  • FIG. 19 is a schematic diagram of a display device according to one embodiment of the present invention.
  • first and second are used only for descriptive purposes and cannot be understood as indicating relative importance, or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, such as fixed connection, detachable connection, or integral connection; may be mechanical connection , It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediate medium, or the internal communication between two components.
  • An active organic light emitting diode display includes an active array substrate and an organic light emitting diode layer.
  • the array substrate contains one or more thin film transistors.
  • the parasitic capacitance of commonly used bottom gate thin film transistors is relatively large, which is not conducive to high resolution and organic light emitting diode display Therefore, high-resolution display panels and active organic light-emitting diode displays often use the form of top-gate thin film transistors.
  • the inventor adopts an undisclosed exemplary display panel structure.
  • the display panel 120 includes a substrate 100; a buffer layer 200 formed on the substrate 100; a semiconductor layer 300 formed on the buffer layer 200.
  • the semiconductor layer 300 includes a source region 310, a drain region 320, and a channel region 330, The channel region 330 is disposed between the source region 310 and the drain region 320; the gate insulating layer 400 formed on the position of the semiconductor layer 300 corresponding to the channel region 330; the gate metal formed on the gate insulating layer 400 Layer 500; a dielectric layer 600 covering the buffer layer 200, the semiconductor layer 300, and the gate metal layer 500, and a source 700 and a drain 800 are formed on the dielectric layer 600, and the source 700 and the drain 800 respectively pass through a single via Connect to the source 310 and the drain region 320, and then cover the passivation layer 900 on the dielectric layer 600, the source 700 and the drain 800.
  • an embodiment of the present invention discloses a display panel 120.
  • the display panel 120 includes: a substrate 100; a buffer layer 200 formed on the substrate 100; and a buffer layer 200 formed on the substrate 100
  • Semiconductor layer 300 the semiconductor layer 300 includes a source region 310, a drain region 320, and a channel region 330, the channel region 330 is disposed between the source region 310 and the drain region 320; formed in the semiconductor layer 300 corresponding to the channel
  • the gate insulating layer 400 at the location of the region 330; the gate metal layer 500 formed on the gate insulating layer 400; the dielectric layer 600 covering the buffer layer 200, the semiconductor layer 300, and the gate metal layer 500, and the source
  • the dielectric layer 600 corresponding to the pole region 310 and the drain region 320 respectively includes a via 610, and the via 610 includes a first via 611 and a second via 612, the first via 611 and the source region 310 or the drain region 320 Connected, the second via 6
  • the thickness of the dielectric layer 600 (In-Layer Dielectric (ILD) layer is often less High ( ⁇ 4000A).
  • ILD In-Layer Dielectric
  • the via hole 610 will be deeper. The deeper and steeper via hole 610 will cause the metal wire to easily contact poorly or even break when it is overlapped with the semiconductor layer 300, reducing product quality and yield.
  • a first via 611 and a second via 612 are formed on the dielectric layer 600 by etching, the second via 612 is located on top of the first via 611, and the second via 612 has a larger diameter than the first via
  • the aperture of 611 forms a buffer structure when overlapping metal wires, slows down the steepness of vias 610, and improves the phenomenon of poor contact or even disconnection when the metal wires and semiconductor layer 300 are overlapped.
  • the first via 611 and the second via 612 are etched along the same axis, and the first via 611 and the second via 612 are coaxial.
  • the metal lines can be guaranteed to uniformly cover the side walls of the first via holes 611 and the second via holes 612, so that the thickness is consistent and not easy Disconnected.
  • the first via 611 and the second via 612 are etched into cylindrical holes.
  • the first via hole 611 and the second via hole 612 are cylindrical holes, and their side walls are all vertical and horizontal lines.
  • the first via 611 and the second via 612 may also have other shapes.
  • the diameter of the first via 611 is from the source region 310 or the drain region 320 to the first via 611.
  • the top gradually increases, and the diameter of the second via 612 gradually increases from the top of the first via 611 to the top of the second via 612.
  • the etched first vias 611 and second vias 612 are shaped like cones, and their side walls are inclined, and the aperture gradually increases from bottom to top. When the metal wire is deposited in the hole, it can slow down the climbing of the metal wire The slope further enhances the thickness of the metal wire covering, making it difficult to break the wire.
  • the etching depth is also related to the deposited metal line.
  • the depth of the first via 611 and the depth of the second via 612 are the same.
  • the deposition is more uniform and the stress is shared.
  • the depth of the first via 611 is greater than the depth of the second via 612.
  • the first via 611 is below the second via 612, the deposited metal wire in the first via 611 is subjected to a greater pressure, and the metal wire is attached to the side wall, the adhesion is better, and it is not easy to break line.
  • the display panel 120 further includes a passivation layer 900, which covers the source 700, the drain 800, and the dielectric layer 600.
  • a metal is deposited in the via 610 to form the source 700 and the drain 800, which are electrically connected to the source region 310 and the drain region 320, respectively, to achieve a conductive effect.
  • a manufacturing method of a display panel 120 including the following steps:
  • the semiconductor layer 300 includes a source region 310, a drain region 320, and a channel region 330.
  • the channel region 330 is disposed between the source region 310 and the drain region 320;
  • S44 deposit a dielectric layer 600 on the surface of the gate metal layer 500, the surface of the semiconductor layer 300, and the surface of the buffer layer 200;
  • S45 Form a via 610 corresponding to the source region 310 and the drain region 320 on the dielectric layer 600 respectively, the via 610 includes a first via 611 and a second via 612, the first via 611 and the source region 310 or the drain region 320 is connected.
  • the second via 612 is located on top of the first via 611 and communicates with the first via 611.
  • the diameter of the second via 612 is larger than that of the first via 611.
  • a substrate 100 is provided.
  • the substrate 100 may be a glass substrate, a quartz substrate, a stainless steel substrate, or a plastic substrate; a buffer layer 200 is formed on the substrate 100, including PVD (Physical vapor deposition, physical vapor deposition method), CVD (chemical vapor deposition, chemical vapor deposition method) or PECVD (plasma enhanced chemical vapor deposition, plasma assisted chemical vapor deposition method) to form the buffer layer 200.
  • the buffer layer 200 can be selectively disposed on the substrate 100 according to actual requirements to prevent impurities in the substrate 100 from diffusing into the subsequently formed material layer during the manufacturing process.
  • the buffer layer 200 is, for example, a silicon oxide layer or nitrogen
  • the single-layer or multi-layer material layer structure composed of the silicon oxide layer and the silicon oxynitride layer is not limited in the present invention.
  • a semiconductor layer 300 is formed on the buffer layer 200.
  • the semiconductor layer 300 is formed by depositing at least one of semiconductor materials such as zinc oxide-based, indium oxide-based, and tin oxide-based.
  • the semiconductor layer 300 includes a source region 310, a drain region 320, and a channel region 330.
  • a gate insulating layer 400 is formed on the corresponding position of the channel region 330 of the semiconductor layer 300. This step may be The gate insulating layer 400 is formed by a deposition method, and is formed by depositing insulating materials such as silicon oxide and silicon nitride, and the gate metal layer 500 is formed on the gate insulating layer 400 by using metal materials such as aluminum, molybdenum, copper, and silver. At least one form.
  • a chemical vapor deposition method is used to deposit the dielectric layer 600 on the surface of the gate metal layer 500, the source region 310 and the drain region 320 of the semiconductor layer 300, and the surface of the buffer layer 200.
  • the material of the dielectric layer 600 is SiO2.
  • the dielectric layer 600 located in the source region 310 and the drain region 320 is etched by dry etching.
  • the etching gas used for etching includes carbon tetrafluoride, forming two first A hole 611 and two second vias 612.
  • the two first vias 611 are respectively connected to the source region 310 and the drain region 320.
  • the second via 612 is located on top of the first via 611 and is connected to the first via 611 communicates, the diameter of the second via 612 is larger than the diameter of the first via 611.
  • the dielectric layer 600 is etched to form a first via 611 and a second via 612 connected to each other.
  • the second via 612 is located on top of the first via 611.
  • the diameter of the second via 612 is larger than that of the first via 611
  • the hole diameter forms a buffer structure when overlapping the metal wires, slows down the steepness of the via 610, and is not easy to break the wire.
  • the specific steps include:
  • S101 forming a photoresist layer 910 on the dielectric layer 600 and performing the first etching to form a photoresist hole 911 and a via 610 connected to the source region 310 and the drain region 320, respectively;
  • the dielectric layer 600 is etched a second time according to the aperture diameter of the photoresist hole 911, and the etching depth is smaller than the thickness of the dielectric layer 600 to form a first via 611 and a second via 612.
  • a yellow mask process is performed using a photomask, a photoresist layer 910 is coated on the dielectric layer 600, and the first etching is performed to form a photoresist hole 911, a source region 310, and a drain, respectively
  • the via 320 in the area 320 is connected.
  • the photoresist layer 910 is ashed to increase the diameter of the photoresist hole 911, which is larger than that of the via hole 610, thereby exposing the dielectric layer 600, so that the photoresist hole 911 and The via hole 610 is coaxial, which is convenient for etching later.
  • the dielectric layer 600 is etched a second time according to the aperture of the photoresist hole 911, the etching depth is less than the thickness of the dielectric layer 600, and a first via 611 and a second via 612 are formed, the second The diameter of the via 612 is larger than the diameter of the first via 611.
  • the manufacturing method of the display panel 120 further includes steps:
  • step S142 deposit metal in the via 610 to form the drain 800 and the source 700, the surface of the source region 310 and the drain region 320 is conductive, the source 700 and the drain 800 pass through the via 610 and the source region 310 and The drain region 320 is electrically connected, and a passivation layer 900 is formed on the source 700, the drain 800, and the dielectric layer 600.
  • a passivation layer 900 is formed on the source 700, the drain 800, and the dielectric layer 600.
  • metal is deposited in the hole to form the source 700 electrically connected to the source region 310 and the drain 800 electrically connected to the drain region 320, and the source region 310 and the drain are formed through a process
  • the surface of the region 320 is conductive, and the drain 800 and the source 700 are respectively connected to the drain region 320 and the source region 310 to achieve a conductive effect.
  • the passivation layer 900 covers the source 700, the drain 800, and the dielectric layer 600 for protection Source electrode 700 and drain electrode 800.
  • the first via 611 is coaxial with the second via 612; the diameter of the first via 611 gradually increases from the source region 310 or the drain region 320 toward the top of the first via 611, The diameter of the second via 612 gradually increases from the top of the first via 611 to the top of the second via 612.
  • the etched first vias 611 and second vias 612 are shaped like cones, and their side walls are inclined, and the aperture gradually increases from bottom to top.
  • a display device 110 is disclosed, including any display panel 120 described above.
  • the technical solution of this application can be widely used in various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment), vertical alignment type ) Display panel, MVA (Multi-Domain Vertical Alignment) display panel, of course, it can also be other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • OLED Organic Light-Emitting Diode

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板（120）、显示面板（120）的制造方法和显示装置（110），显示面板（120）包括源极区（310）和漏极区（320）；覆盖在源极区（310）和漏极区（320）上的介质层（600）分别包括第一过孔（611）和第二过孔（612），第一过孔（611）与源极区（310）或漏极区（320）连接，第二过孔（612）位于第一过孔（611）的顶部，与第一过孔（611）连通，第二过孔（612）的孔径大于第一过孔（611）的孔径。

Description

显示面板、显示面板的制造方法和显示装置
本申请要求于2018年12月17日提交中国专利局，申请号为CN201811542212.7，申请名称为“一种显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、显示面板的制造方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
在显示技术领域，平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。薄膜晶体管(Thin Film Transistor，TFT)是液晶显示装置(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light Emitting Diode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。
底栅结构的薄膜晶体管在制程中，金属线与半导体层搭接时容易接触不良甚至断线。
发明内容
本申请的目的是提供一种显示面板、显示面板的制造方法和显示装置。
本申请公开了一种显示面板，所述的显示面板包括：衬底；形成于所述衬底上的缓冲层；形成于所述缓冲层上的半导体层，所述半导体层包括源极区、漏极区以及沟道区，所述沟道区设置于所述源极区与所述漏极区之间；形成于所述半导体层对应所述沟道区的位置上的栅极绝缘层；形成于所述栅极绝缘层上的栅极金属层；覆盖在所述缓冲层、半导体层以及栅极金属层上的介质层，与所述源极区和所述漏极区对应的所述介质层分别包括过孔，所述过孔包括第一过孔和第二过孔，所述第一过孔与所述源极区或所述漏极区连接，所述第二过孔位于所述第一过孔的顶部，与所述第一过孔连通，所述第二过孔的孔径大于所述第一过孔的孔径。
本申请还公开了一种显示面板的制造方法，包括以下步骤：
提供一衬底，在所述衬底上形成缓冲层；
在所述缓冲层上形成半导体层，所述半导体层包括源极区、漏极区以及沟道区，所述沟道区设置于所述源极区与所述漏极区之间；
在所述半导体层上沟道区对应位置形成栅极绝缘层，在所述栅极绝缘层上形成栅极金属层；
在所述栅极金属层表面、所述半导体层表面及所述缓冲层表面沉积介质层；
在所述介质层上形成分别对应于所述源极区与所述漏极区的过孔，所述过孔包括第一过孔和第二过孔，所述第一过孔与所述源极区或所述漏极区连接，所述第二过孔位于所述第一过孔的顶部，与所述第一过孔连通，所述第二过孔的孔径大于所述第一过孔的孔径。
本申请还公开了一种显示装置，包括上述的显示面板。
相对于介质层上刻蚀一个孔径一致的过孔的方案来说，本发明在介质层上刻蚀形成连通 的第一过孔和第二过孔，第二过孔位于第一过孔的顶部，第二过孔的孔径大于第一过孔的孔径，在搭接金属线时，形成缓冲结构，减缓过孔的陡度，不易断线。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是示例性单一孔的顶栅结构薄膜晶体管的示意图；
图2是本发明的其中一个实施例的一种显示面板的示意图；
图3是本发明的其中一个实施例的一种显示面板的示意图；
图4是本发明的其中一个实施例的一种显示面板的示意图；
图5是本发明的其中一个实施例的一种显示面板的制造方法的步骤示意图；
图6至图10是本发明的其中一个实施例的一种显示面板的制造方法的流程示意图；
图11是本发明的其中一个实施例的一种显示面板的制造方法的步骤的示意图；
图12至图14是本发明的其中一个实施例的一种显示面板的制造方法的流程示意图；
图15是本发明的其中一个实施例的一种显示面板的制造方法的步骤示意图；
图16至图17是本发明的其中一个实施例的一种显示面板的制作方法的流程示意图；
图18是本发明的其中一个实施例的一种显示面板的示意图；
图19是本发明的其中一个实施例的一种显示装置的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
主动式有机发光二极管显示器包括主动阵列基板和有机发光二极管层。阵列基板包含一个或多个薄膜晶体管，随着人们对显示面板的分辨率以及显示品质的需求不断提升，由于常用的底栅型薄膜晶体管寄生电容相对较大，不利于高分辨以及有机发光二极管显示，因此，高分辨的显示面板以及主动式有机发光二极管显示器往往采用顶栅型薄膜晶体管形式。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1所示，发明人采用一种未公开的示例性显示面板结构。
该显示面板120包括衬底100；形成于衬底100上的缓冲层200；形成于缓冲层200上的半导体层300，半导体层300包括源极区310、漏极区320以及沟道区330，沟道区330设置于源极区310与漏极区320之间；形成于半导体层300对应沟道区330的位置上的栅极绝缘层400；形成于栅极绝缘层400上的栅极金属层500；覆盖在缓冲层200、半导体层300以及栅极金属层500上的介质层600，在介质层600上形成源极700和漏极800，源极700和漏极800分别通过单一过孔连接到源极去310和漏极区320，然后在介质层600、源极700和漏极800上再覆盖钝化层900。
如图2至图4和图19所示，本发明实施例公布了一种显示面板120，显示面板120包括：衬底100；形成于衬底100上的缓冲层200；形成于缓冲层200上的半导体层300，半导体层300包括源极区310、漏极区320以及沟道区330，沟道区330设置于源极区310与漏极区320之间；形成于半导体层300对应沟道区330的位置上的栅极绝缘层400；形成于栅极绝缘层400上的栅极金属层500；覆盖在缓冲层200、半导体层300以及栅极金属层500上的介质层600，与源极区310和漏极区320对应的介质层600分别包括过孔610，过孔610包括第一过孔611和第二过孔612，第一过孔611与源极区310或漏极区320连接，第二过孔612位于第一过孔611的顶部，与第一过孔611连通，第二过孔612的孔径大于第一过孔611的孔径。
相对于如图1中所示的示例性技术方案来说，在顶栅型薄膜晶体管制程中，为了达到更好特性的薄膜晶体管特性，介质层600(In-Layer Dielectric，ILD)层厚度往往较高(≥4000A)。介质层600刻蚀后的过孔610会较深，较深较陡的过孔610会引起金属线在与半导体层300搭接时容易接触不良甚至断线，降低产品品质及良率。本发明在介质层600上刻蚀形成连通的第一过孔611和第二过孔612，第二过孔612位于第一过孔611的顶部，第二过孔612的孔径大于第一过孔611的孔径，在搭接金属线时，形成缓冲结构，减缓过孔610的陡度，改善金属线与半导体层300搭接时接触不良甚至断线的现象。
具体的，在刻蚀时，将第一过孔611与第二过孔612按照同一轴心刻蚀，第一过孔611与第二过孔612同轴心。完成刻蚀后，第一过孔611与第二过孔612内沉积金属线时，能够保证金属线均匀地覆盖与第一过孔611和第二过孔612的侧壁，使厚度一致，不易断线。
更具体的，在刻蚀时，将第一过孔611和第二过孔612刻蚀为圆柱孔。第一过孔611和第二过孔612为圆柱孔，其侧壁都是垂直水平线，在刻蚀过程中，比较容易操作和实现。当然，第一过孔611和第二过孔612也可以为其他的形状，如图3所示，第一过孔611的孔径从源极区310或漏极区320往第一过孔611的顶部逐渐增大，第二过孔612的孔径从第一过孔611的顶部往第二过孔612的顶部逐渐增大。刻蚀的第一过孔611和第二过孔612的形状类似圆锥，其侧壁都为斜面，孔径从下往上逐渐增大，在孔内沉积金属线时，能够减缓金属线的爬坡斜度，进一步提升金属线覆盖的的厚度，不易断线。
另一方面，刻蚀的深度也与沉积金属线有关系，在刻蚀的时候，使第一过孔611的深度和所述第二过孔612的深度相同。在沉积金属线时，沉积的更加均匀，分摊应力。当然，为了使金属线的爬坡斜度更好，使第一过孔611的深度大于所述第二过孔612的深度。第一过孔611在第二过孔612之下，在第一过孔611内的沉积的金属线受到的压力较大，会使金属线贴附在侧壁上，附着的更好，不易断线。
在沉积完金属线后还需要进行后续工序，如图4所示，在孔内沉积金属，形成漏极800和源极700，源极区310和漏极区320表面导体化，源极700和漏极800分别通过过孔610 与源极区310和漏极区320电连接，显示面板120还包括钝化层900，钝化层900覆盖源极700、漏极800以及介质层600。在过孔610内沉积金属形成源极700与漏极800，分别与源极区310与漏极区320电连接，实现导电效果。
如图5至图19所示，作为本发明的另一实施例，公开了一种显示面板120的制造方法，包括以下步骤：
S41：提供一衬底100，在衬底100上形成缓冲层200；
S42：在缓冲层200上形成半导体层300，半导体层300包括源极区310、漏极区320以及沟道区330，沟道区330设置于源极区310与漏极区320之间；
S43：在半导体层300上沟道区330对应位置形成栅极绝缘层400，在栅极绝缘层400上形成栅极金属层500；
S44：在栅极金属层500表面、半导体层300表面及缓冲层200表面沉积介质层600；
S45：在介质层600上形成分别对应于源极区310与漏极区320的过孔610，过孔610包括第一过孔611和第二过孔612，第一过孔611与源极区310或漏极区320连接，第二过孔612位于第一过孔611的顶部，与第一过孔611连通，第二过孔612的孔径大于第一过孔611的孔径。
如图6所示及步骤S41，提供一衬底100，衬底100可以是玻璃基板，也可以是石英基板、不锈钢基板或是塑料基板；在衬底100上形成一缓冲层200，包括以PVD(physical vapor deposition,物理气相沉积法)、CVD(chemical vapor deposition,化学气相沉积法)或是PECVD(plasma enhanced chemical vapor deposition,电浆辅助化学气相沉积法)形成缓冲层200。缓冲层200可依据实际需求选择性地设置于衬底100上，以避免衬底100中的不纯物在制作过程中扩散至后续形成的材质层中，缓冲层200例如是氧化硅层、氮化硅层以及氮氧化硅层所组成的单层或是多层结构材质层结构，在本发明不作限定。
如图7所示及步骤S42，在缓冲层200上形成半导体层300，半导体层300采用氧化锌基、氧化铟基、氧化锡基等半导体材料中的至少一种沉积形成。
如图8所示及步骤S43，半导体层300包括源极区310、漏极区320及沟道区330，在半导体层300的沟道区330对应位置上形成栅极绝缘层400，此步骤可采用沉积的方法形成栅极绝缘层400，采用氧化硅、氮化硅等绝缘材料沉积形成，在栅极绝缘层400上形成栅极金属层500，采用铝、钼、铜、银等金属材料的至少一种形成。
如图9所示及步骤S44，在栅极金属层500表面、半导体层300的源极区310及漏极区320表面及缓冲层200表面采用化学气相沉积的方法沉积介质层600，在实施例中，介质层600的材料为SiO2。
如图10所示及步骤S45，通过干法蚀刻，对位于源极区310与漏极区320的介质层600进行蚀刻，蚀刻所使用的蚀刻气体包含四氟化碳，形成两个第一过孔611和两个第二过孔612，两个第一过孔611分别与源极区310和漏极区320连接，第二过孔612位于第一过孔611的顶部，与第一过孔611连通，第二过孔612的孔径大于第一过孔611的孔径。在介质层600上刻蚀形成连通的第一过孔611和第二过孔612，第二过孔612位于第一过孔611的顶部，第二过孔612的孔径大于第一过孔611的孔径，在搭接金属线时，形成缓冲结构，减缓过孔610的陡度，不易断线。
如图11所示，在介质层600上形成分别对应于源极700与漏极800的过孔610，具体步骤包括：
S101：在介质层600上形成光阻层910，进行第一次蚀刻，分别形成光阻孔911、与源极区310和漏极区320连接的过孔610；
S102：将光阻层910灰化处理，使光阻孔911的孔径大于过孔610的孔径；
S102：按照光阻孔911的孔径对介质层600进行第二次刻蚀，蚀刻深度小于介质层600厚度，形成第一过孔611与第二过孔612。
如图12所示及步骤S101，利用光罩进行黄光制程，在介质层600上涂布光阻层910，进行第一次蚀刻，分别形成光阻孔911、与源极区310和漏极区320连接的过孔610。
如图13所示及步骤S102，将光阻层910灰化处理，使光阻孔911的孔径增大，大于过孔610的孔径，进而使得介质层600暴露，使所述光阻孔911与所述过孔610同轴心，方便之后刻蚀。
如图14所示及步骤S103，按照光阻孔911的孔径对介质层600进行第二次刻蚀，蚀刻深度小于介质层600厚度，形成第一过孔611与第二过孔612，第二过孔612的孔径大于第一过孔611的孔径。
在形成第一过孔611和第二过孔612后，如图15所示，显示面板120的制造方法还包括步骤：
S141：通过灰化处理去掉光阻层910；
S142：在过孔610内沉积金属，形成漏极800和源极700，源极区310和漏极区320表面导体化，源极700和漏极800分别通过过孔610与源极区310和漏极区320电连接，在源极700、漏极800以及介质层600上形成钝化层900。如图16所示及步骤S141，通过灰化工艺，去掉介质层600上所对应的光阻层910。
如图17所示及步骤S142，在孔内沉积金属，形成与源极区310电连接的源极700及与漏极区320电连接的漏极800，通过工艺使源极区310和漏极区320表面导体化，漏极800和源极700分别与漏极区320和源极区310连接，实现导电效果，钝化层900覆盖在源极700、漏极800及介质层600上，保护源极700以及漏极800。
如图18所示，第一过孔611与第二过孔612同轴心；第一过孔611的孔径从源极区310或漏极区320往第一过孔611的顶部逐渐增大，第二过孔612的孔径从第一过孔611的顶部往第二过孔612的顶部逐渐增大。刻蚀的第一过孔611和第二过孔612的形状类似圆锥，其侧壁都为斜面，孔径从下往上逐渐增大，在孔内沉积金属线时，能够减缓金属线的爬坡斜度，进一步提升金属线覆盖的的厚度，不易断线，降低接触阻抗。
如图19所示，作为本发明的另一实施例，公开了一种显示装置110，包括上述任意的显示面板120。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本发明的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN(Twisted Nematic，扭曲向列型)显示面板、IPS(In-Plane Switching，平面转换型)显示面板、VA(Vertical Alignment，垂直配向型)显示面板、MVA(Multi-Domain Vertical Alignment，多象限垂直配向型)显示面板，当然，也可以是其他类型的显示面板，如OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，均可适用上述方案。以上内容是结合具体的可选的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (18)

  1. 一种显示面板，包括：
    衬底；
    缓冲层，形成于所述衬底上；
    半导体层，形成于所述缓冲层上，所述半导体层包括源极区、漏极区以及沟道区，所述沟道区设置于所述源极区与所述漏极区之间；
    栅极绝缘层，形成于所述半导体层对应所述沟道区的位置上；
    栅极金属层，形成于所述栅极绝缘层上；以及
    介质层，覆盖在所述缓冲层、半导体层以及栅极金属层上，与所述源极区和所述漏极区对应的所述介质层分别包括过孔；所述过孔包括第一过孔和第二过孔，所述第一过孔与所述源极区或所述漏极区连接；所述第二过孔位于所述第一过孔的顶部，与所述第一过孔连通；所述第二过孔的孔径大于所述第一过孔的孔径。
  2. 如权利要求1所述的显示面板，其中，所述第一过孔与所述第二过孔同轴心。
  3. 如权利要求2所述的显示面板，其中，所述第一过孔和所述第二过孔均为圆柱形的孔。
  4. 如权利要求2所述的显示面板，其中，所述第一过孔的孔径从所述源极区往所述第一过孔的顶部逐渐增大，所述第二过孔的孔径从所述第一过孔的顶部往所述第二过孔的顶部逐渐增大。
  5. 如权利要求2所述的显示面板，其中，所述第一过孔的孔径从所述漏极区往所述第一过孔的顶部逐渐增大，所述第二过孔的孔径从所述第一过孔的顶部往所述第二过孔的顶部逐渐增大。
  6. 如权利要求2所述的显示面板，其中，所述第一过孔的深度和所述第二过孔的深度相同。
  7. 如权利要求2所述的显示面板，其中，所述第一过孔的深度小于所述第二过孔的深度。
  8. 如权利要求1所述的显示面板，其中，所述显示面板还包括源极、漏极以及钝化层，所述源极和所述漏极分别通过所述过孔与所述源极区和漏极区连接，所述钝化层覆盖所述源极、漏极以及介质层。
  9. 一种显示面板的制造方法，包括以下步骤：
    提供一衬底，在所述衬底上形成缓冲层；
    在所述缓冲层上形成半导体层，所述半导体层包括源极区、漏极区以及沟道区，所述沟道区设置于所述源极区与所述漏极区之间；
    在所述半导体层上沟道区对应位置形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极金属层；
    在所述栅极金属层表面、所述半导体层表面及所述缓冲层表面沉积介质层；以及
    在所述介质层上形成分别对应于所述源极区与所述漏极区的过孔；
    其中，所述过孔包括第一过孔和第二过孔，所述第一过孔与所述源极区或所述漏极区连接，所述第二过孔位于所述第一过孔的顶部，与所述第一过孔连通，所述第二过孔的孔径大于所述第一过孔的孔径。
  10. 如权利要求9所述的显示面板的制造方法，其中，在所述介质层上形成分别对应于所述源极与所述漏极的过孔，具体步骤包括：
    在所述介质层上形成光阻层，进行第一次刻蚀，分别形成光阻孔、与所述源极区和漏极区连接的过孔；
    将光阻层灰化处理，使所述光阻孔的孔径大于所述过孔的孔径；以及
    按照所述光阻孔的孔径对所述介质层进行第二次刻蚀，蚀刻深度小于所述介质层厚度，形成第一过孔与第二过孔。
  11. 如权利要求10所述的显示面板的制造方法，其中，还包括步骤：
    通过灰化处理去掉所述光阻层；
    在所述过孔内沉积金属，形成与所述源极区连接的源极以及与所述漏极区连接的漏极；以及
    在所述源极、漏极以及介质层上形成钝化层。
  12. 如权利要求10所述的显示面板的制造方法，其中，将光阻层灰化处理，使所述光阻孔的孔径大于所述过孔的孔径的步骤中，所述光阻孔与所述过孔同轴心。
  13. 如权利要求10所述的显示面板的制造方法，其中，按照所述光阻孔的孔径对所述介质层进行第二次刻蚀，蚀刻深度小于所述介质层厚度，形成第一过孔与第二过孔的步骤中，所述第一过孔的孔径从所述源极区或所述漏极区往所述第一过孔的顶部逐渐增大，所述第二过孔的孔径从所述第一过孔的顶部往所述第二过孔的顶部逐渐增大。
  14. 一种显示装置，包括显示面板，所述显示面板包括：
    衬底；
    缓冲层，形成于所述衬底上；
    半导体层，形成于所述缓冲层上，所述半导体层包括源极区、漏极区以及沟道区，所述沟道区设置于所述源极区与所述漏极区之间；
    栅极绝缘层，形成于所述半导体层对应所述沟道区的位置上；
    栅极金属层，形成于所述栅极绝缘层上；以及
    介质层，覆盖在所述缓冲层、半导体层以及栅极金属层上，与所述源极区和所述漏极区对应的所述介质层分别包括过孔；所述过孔包括第一过孔和第二过孔，所述第一过孔与所述源极区或所述漏极区连接；所述第二过孔位于所述第一过孔的顶部，与所述第一过孔连通；所述第二过孔的孔径大于所述第一过孔的孔径。
  15. 如权利要求14所述的显示装置，其中，所述第一过孔与所述第二过孔同轴心。
  16. 如权利要求14所述的显示装置，其中，所述第一过孔的孔径从所述源极区或所述漏极区往所述第一过孔的顶部逐渐增大，所述第二过孔的孔径从所述第一过孔的顶部往所述第二过孔的顶部逐渐增大。
  17. 如权利要求14所述的显示装置，其中，所述半导体层采用氧化锌基、氧化铟基、氧化锡基等半导体材料中的至少一种沉积形成。
  18. 如权利要求14所述的显示装置，其中，所述介质层采用二氧化硅材料形成。
PCT/CN2019/123580 2018-12-24 2019-12-06 显示面板、显示面板的制造方法和显示装置 Ceased WO2020134957A1 (zh)

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