WO2020125432A1 - 移位暂存器和显示装置 - Google Patents

移位暂存器和显示装置 Download PDF

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Publication number
WO2020125432A1
WO2020125432A1 PCT/CN2019/123387 CN2019123387W WO2020125432A1 WO 2020125432 A1 WO2020125432 A1 WO 2020125432A1 CN 2019123387 W CN2019123387 W CN 2019123387W WO 2020125432 A1 WO2020125432 A1 WO 2020125432A1
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WIPO (PCT)
Prior art keywords
circuit
shift register
switching device
stage
pull
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PCT/CN2019/123387
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Publication of WO2020125432A1 publication Critical patent/WO2020125432A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application relates to the field of display technology, in particular to a shift register and a display device.
  • the line scan signal is realized by an external integrated circuit.
  • the gate drive integration on the array substrate realizes the output of the line scan signal, specifically by integrating the shift register on the array substrate of the display device.
  • the generated scan signal has a low high level, and the waveform of the scan signal is not ideal, resulting in a decline in the output capacity of the shift register.
  • the main purpose of this application is to propose a shift register, which aims to improve the waveform of the scanning signal and enhance the output capability of the shift register.
  • the shift register provided by the present application includes a multi-stage shift register circuit arranged in cascade.
  • the shift register circuit includes an output circuit, and the output circuit includes a first switching device.
  • the gate and drain of the first switching device are connected to the pull-up point of the shift temporary storage circuit at this stage, and the source of the first switching device is connected to the scan signal output terminal of the shift temporary storage circuit at this stage.
  • the present application also proposes a shift register, the shift register includes a multi-stage shift register circuit arranged in cascade, the shift register circuit includes an output circuit, the The output circuit includes a first switching device and a second switching device. The gate and the drain of the first switching device are connected to the pull-up point of the shift temporary storage circuit at this stage.
  • the source of the first switching device is connected to the local The scan signal output terminal of the stage shift temporary storage circuit is connected; the gate of the second switching device is connected to the pull-up point of the stage shift temporary storage circuit, and the drain of the second switching device is connected to the current stage clock signal
  • the source is connected, and the source of the second switching device is connected to the scan signal output terminal of the shift register circuit of the current stage to output the scan signal of the present stage; wherein, when the shift register is operating, the clock signal of the present stage The falling edge of is synchronized with the rising edge of the subsequent clock signal.
  • the present application further proposes a display device, the display device includes a display panel and a driving assembly, the driving assembly includes a shift register, the shift register includes multiple stages arranged in cascade A shift temporary storage circuit, the shift temporary storage circuit includes an output circuit, and the output circuit includes a first switching device, and a gate and a drain of the first switching device are pulled up by the shift temporary storage circuit of the current stage Connected to each other, the source of the first switching device is connected to the scan signal output end of the shift temporary storage circuit at this stage, and the shift temporary storage is integrated on the array substrate of the display panel.
  • the shift register includes a multi-stage shift register circuit arranged in cascade, the shift register circuit includes an output circuit, and the output circuit includes a first switching device, a gate of the first switching device and The drain is connected to the pull-up point of the shift temporary storage circuit at this stage, and the source of the first switching device is connected to the scan signal output end of the shift temporary storage circuit at this stage.
  • the output circuit is turned on, and under the coupling effect of the parasitic capacitance of the output circuit, the first switching device and other devices in the output circuit simultaneously charge the scan signal output terminal, causing the scan signal to rise further To the high level state, thereby improving the waveform of the generated scan signal and enhancing the output capability of the shift register.
  • FIG. 1 is a schematic structural diagram of an nth-stage shift register circuit of a shift register in an example
  • FIG. 2 is a timing diagram of the 4CK shift register in an example
  • FIG. 3 is a schematic structural diagram of an embodiment of a display device according to this application.
  • FIG. 4 is a schematic structural diagram of an nth-stage shift temporary storage circuit in an embodiment of a shift register of the present application
  • FIG. 5 is a timing diagram of a 4CK shift register in a specific example of the shift register of the present application.
  • FIG. 6 is a schematic diagram of the circuit structure of the nth-stage shift register circuit in another specific example of the shift register of the present application.
  • FIG. 1 is a schematic structural diagram of an nth-stage shift register circuit of a shift register in an example, including a charging circuit 111', an output circuit 112', a reset circuit 113', and a voltage regulator circuit 114'.
  • the output circuit 112' is connected to the clock signal source of the current stage to receive the clock signal CK(n)' of the current stage, thereby generating the scan signal of the current stage.
  • 4CK four-clock
  • the falling edge of the clock signal of this stage is synchronized with the rising edge of the clock signal of the subsequent stage, and the second-stage shift register circuit generates the first
  • the charging circuit 111' is connected to the precharge signal source of the shift register circuit at this level to receive the precharge signal ST(n)', where the precharge signal ST(n)' can It is the front stage feedback signal F(ni)'.
  • the charging circuit 111' of the second-stage shift temporary storage circuit pre-pulls the pull-up point of the second-stage shift temporary storage circuit Charging, when the second-stage clock signal CK(2)' transitions to a high state, the output circuit 112' is turned on, and continues to charge the pull-up point under the effect of its parasitic capacitance, thereby generating a second-stage scan signal G(2)'.
  • the output circuit 112' includes a switching device having a gate connected to the pull-up point, a drain connected to the clock signal source, and a source connected to the scan signal output terminal to output the scan signal. Thereafter, under the action of the reset circuit 113' and the voltage stabilizing circuit 114', the second-stage scan signal G(2)' is pulled down to a low-level state, and the second-stage scan signal G(2)' is reset.
  • the shift register 110 includes multiple stages of shift register circuits arranged in cascade.
  • the shift register circuit includes an output circuit 112 and an output circuit 112 Including the first switching device T1, the gate and the drain of the first switching device T1 are connected to the pull-up point of the shift temporary storage circuit of this stage, the source of the first switching device T1 is scanned by the shift temporary storage circuit of this stage The signal output is connected.
  • the display device includes a display panel including an array substrate 100, a color filter substrate 200, and liquid crystal (not shown) filled between the array substrate 100 and the color filter substrate 200.
  • the display panel is provided with a plurality of pixels arranged in a rectangular array, each pixel usually includes a number of sub-pixels, a switching device corresponding to each sub-pixel is provided on the array substrate 100, and each sub-pixel is provided on the color filter substrate 200 The color filter block corresponding to the pixel.
  • the liquid crystal in the area corresponding to each sub-pixel is deflected at a certain angle to achieve the display of a specific image.
  • the array substrate 100 is further provided with a shift register 110 for driving each row of sub-pixels.
  • the shift register 110 is directly integrated on the array substrate 100 through a micro-machining process, so as to save the external shift register, which is beneficial to reduce the material cost and process cost of the display device, and is conducive to the thinning and thinning of the display device And narrow border design.
  • the shift register 110 is developed on the basis of the Thompson circuit, and includes a multi-stage shift register circuit arranged in cascade, in which the feedback signal F(ni) output by the previous stage shift register circuit can be used as the current stage
  • the precharge signal ST(n) of the shift register circuit, the feedback signal F(n+j) output from the shift register circuit of the subsequent stage can be used as the pull-down signal PD(n) of the shift register circuit of this stage, where, i and j are positive integers, and their specific values are related to the timing in the shift register, and will not be repeated here.
  • the scan signal and the feedback signal of the shift storage circuit of the same stage are usually the same.
  • the start signal provided separately can be used as its pull-up signal. Circuit, you can set a redundant shift temporary storage circuit to provide a pull-down signal.
  • the output circuit 112 is additionally provided with a first switching device T1.
  • the gate and drain of the first switching device T1 are connected to the pull-up point of the shift temporary storage circuit at this stage, and the source of the first switching device T1 It is connected to the scan signal output terminal of the shift temporary storage circuit of this stage.
  • the precharge signal ST(n) precharges the pull-up point
  • the gate of the first switching device T1 is in a high state, so the first switching device T1 is turned on, and the pull-up signal PU( n)
  • the scan signal output terminal of the shift temporary storage circuit of this stage is charged through the first switching device T1, so that the scan signal G(n) rises to the next high level state in advance.
  • the output circuit 112 is turned on, and under the coupling effect of the parasitic capacitance of the output circuit 112, etc., the first switching device T1 and other devices in the output circuit 112 simultaneously charge the scan signal output terminal, so that The scan signal G(n) further rises to a high level state.
  • the first switching device T1 is turned on, the second stage scan signal G(2) rises to the second high state, and when the second stage clock signal is in the high state, the second stage scan The signal G(2) further rises to the high state on the basis of the second high state, which is higher than the high level in the example by ⁇ U, thereby improving the waveform of the generated scan signal and improving the shift register Output capability.
  • each stage of the shift temporary storage circuit also includes a charging circuit 111, a reset circuit 113, and a voltage stabilizing circuit 114, and there are various settings for the charging circuit 111, the output circuit 112, the reset circuit 113, and the voltage stabilizing circuit 114. the way.
  • the first end of the charging circuit 111 receives the precharge signal ST(n)
  • the second end of the charging circuit 111 is connected to the first end of the output circuit 112
  • the pull-up point of the temporary storage circuit of this stage, the pull-up signal corresponding to the pull-up point is represented by PU(n).
  • the second terminal of the output circuit 112 receives the clock signal CK(n).
  • the same clock signal is often used to control the multi-stage shift register circuit, for example, for TCK shift
  • the t-th clock signal will control the t+Tm-th shift temporary storage circuit, where m is an integer greater than or equal to zero, and T is the total number of clock signal sources.
  • the third terminal of the output circuit 112 outputs a scan signal G(n), and the fourth terminal outputs a feedback signal F(n) (not shown in the figure), wherein the scan signal G(n) is used to drive the corresponding sub-pixel row,
  • the feedback signal F(n) usually coincides with the scan signal G(n), and is used as a pull-down signal of the previous stage shift register circuit.
  • the first end of the reset circuit 113 is connected to the pull-up point of the shift temporary storage circuit at this stage, the second end of the reset circuit 113 is connected to the third end of the output circuit 112, and the third end of the reset circuit 113 is connected to the low level
  • the fourth end of the reset circuit 113 receives the pull-down signal PD(n) of the shift register circuit of the current stage.
  • the reset circuit 113 pulls down the pull-up point and the scan signal output terminal to a low level to maintain the normal operation of the shift register and realize the progressive scan driving.
  • the shift register circuit further includes a voltage stabilizing circuit 114.
  • the first end of the voltage stabilizing circuit 114 is connected to the pull-up of the current stage shift register circuit At this point, the second end of the voltage stabilizing circuit 114 is connected to the third end of the output circuit 112, and the third end of the voltage stabilizing circuit 114 is connected to the low-level signal source to eliminate timing noise at the pull-up point and the scan signal output end.
  • the shift register 110 includes multiple stages of shift register circuits arranged in cascade, the shift register circuit includes an output circuit 112, and the output circuit 112 includes a first switching device T1 and a first switching device T1
  • the gate and the drain of are connected to the pull-up point of the shift temporary storage circuit at this stage, and the source of the first switching device T1 is connected to the scan signal output terminal of the shift temporary storage circuit at this stage.
  • the output circuit 112 is turned on, and under the coupling effect of the parasitic capacitance of the output circuit 112, etc., the first switching device T1 and other devices in the output circuit 112 simultaneously charge the scan signal output terminal, so that The scan signal further rises to a high level state, thereby improving the waveform of the generated scan signal and enhancing the output capability of the shift register.
  • the output circuit 112 includes a second switching device T2, the gate of the second switching device T2 is connected to the pull-up point of the shift temporary storage circuit at this stage, and the drain of the second switching device T2 is connected to The clock signal source of this stage is connected, and the source of the second switching device T2 is connected to the scan signal output terminal of the shift temporary storage circuit of this stage to output the scan signal of this stage.
  • the second-stage clock signal CK(2 ) Is at a high level, thereby generating a high level of the second-stage scanning signal G(2).
  • a coupling capacitor C (not shown in the figure) may also be provided between the pull-up point of the shift register circuit at this stage and the output terminal of the scan signal, so that the clock signal is better coupled with the pull-up point to generate High level of the scanning signal.
  • a switching device whose connection mode is completely consistent with the second switching device T2 may be additionally provided to output the feedback signal of the shift storage circuit of the current stage to achieve temporary storage with the shift of the previous stage or the subsequent stage
  • the cascade of circuits drives the operation of the shift register.
  • the shift temporary storage circuit includes a reset circuit 113, and the reset circuit 113 includes a third switching device T3 and a fourth switching device T4, and the gate of the third switching device T3 is pulled down by the shift temporary storage circuit at this stage Point connected, the source of the third switching device T3 is connected to the low-level signal source, the drain of the third switching device T3 is connected to the scan signal output terminal of the shift storage circuit of the current stage; the gate of the fourth switching device T4 Connected to the pull-down point of the shift temporary storage circuit at this stage, the source of the fourth switching device T4 is connected to the low-level signal source, and the drain of the fourth switching device T4 is connected to the pull-up point of the shift temporary storage circuit at this stage .
  • the reset circuit 113 is used to pull down the generated scan signal to a low level state. Specifically, as shown in FIG. 5, taking the generation of the scan signal of the second stage as an example, when the pull-down signal PD(2) is in a high-level state, the third switching device T3 and the fourth switching device T4 are turned on, at a low level Under the effect of the level signal VSS, the pull-up point and the output end of the scan signal are pulled down to the low level state to realize the progressive scan.
  • the pull-down point of the current stage shift temporary storage circuit is connected to the scan signal output end of the later stage shift temporary storage circuit, or to the pull-up point of the later stage shift temporary storage circuit, and G(n+j) or PU(n+k) is used as the pull-down signal PD(n) of the shift temporary storage circuit in this stage.
  • G(n+j) or PU(n+k) is used as the pull-down signal PD(n) of the shift temporary storage circuit in this stage.
  • the specific values of j and k are related to the timing of each signal, and will not be repeated here.
  • the shift temporary storage circuit includes a charging circuit 111, and the charging circuit 111 includes a fifth switching device T5.
  • the gate and drain of the fifth switching device T5 are connected to the precharge signal source ST(n) of the current stage.
  • the source of the fifth switching device T5 is connected to the pull-up point of the shift register circuit at this stage.
  • the precharge signal ST(n) may be the previous stage feedback signal F(n-i).
  • the falling edge of the clock signal of this stage is synchronized with the rising edge of the clock signal of the subsequent stage, charging in the n-th stage shift register circuit In the circuit 111, the gate and drain of the fifth switching device T5 receive the feedback signal of the previous stage.
  • the charging circuit receives the first-stage feedback signal F(1) (same as the first-stage scan signal G(1)), when the first-stage feedback signal F(1) is high In the level state, the pull-up point of the second-stage shift temporary storage circuit is charged, so that the pull-up point level PU(2) of the second-stage shift temporary storage circuit rises to the next high level.
  • the feedback signal F(1) of the first stage changes from the high state to the low state
  • the clock signal CK(2) of the second stage starts to change from the low state to the high state.
  • the second-stage clock signal CK(2) will also charge the pull-up point, causing the pull-up point level PU(2) to further rise to a high level, and the output circuit 112 is in the second Under the action of the stage clock signal CK(2), the high level of the second stage scan signal G(2) is generated.
  • the shift temporary storage circuit includes a voltage stabilizing circuit 114.
  • the voltage stabilizing circuit includes a pull-down sub-circuit 114a and a pull-down control sub-circuit 114b.
  • the first end of the pull-down sub-circuit 114a is scanned by the current stage of the shift temporary circuit
  • the signal output terminal is connected, the second terminal of the pull-down sub-circuit 114a is connected to a low-level signal source; the first terminal of the pull-down control sub-circuit 114b is connected to the third terminal of the pull-down sub-circuit 114a, and the second terminal of the pull-down control sub-circuit 114b Connect with low level signal source.
  • the pull-down sub-circuit 114a is used to maintain the pull-up point of the shift register circuit at the preset time at a low level to eliminate timing noise
  • the pull-down control sub-circuit 114b is used to control the pull-down sub-circuit 114a Running.
  • the present application also proposes a display device.
  • the display device includes a display panel 100 and a driving component.
  • the driving component is used to drive the display of the display panel.
  • the driving component includes a shift register 110.
  • the shift register 110 is a gate drive integrated circuit on an array substrate to reduce material cost and process cost.

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  • General Physics & Mathematics (AREA)
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Abstract

一种移位暂存器(110)和显示装置。移位暂存器(110)包括级联设置的多级移位暂存电路，移位暂存电路包括输出电路(112)，输出电路(112)包括第一开关器件(T1)，第一开关器件(T1)的栅极和漏极与本级移位暂存电路的上拉点相连，第一开关器件(T1)的源极与本级移位暂存电路的扫描信号输出端相连。

Description

移位暂存器和显示装置
相关申请
本申请要求2018年12月19日申请的，申请号201811554083.3，名称为“移位暂存器和显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，特别涉及一种移位暂存器和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
在传统的显示装置中，行扫描信号是由外接集成电路实现的，随着显示装置的轻薄化、窄边框化以及低成本化的发展，目前通常采用阵列基板上栅驱动集成（Gate Drive on Array，GOA）实现行扫描信号的输出，具体通过将移位暂存器集成在显示装置的阵列基板上实现。然而，由于移位暂存器中开关器件等性能的限制，所产生的扫描信号中高电平较低，扫描信号的波形不够理想，导致移位暂存器的输出能力下降。
发明内容
本申请的主要目的是提出一种移位暂存器，旨在改善扫描信号的波形，提升移位暂存器的输出能力。
为实现上述目的，本申请提供的移位暂存器，包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括第一开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连。
为实现上述目的，本申请还提出一种移位暂存器，所述移位暂存器包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括第一开关器件以及第二开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连；所述第二开关器件的栅极与本级移位暂存电路的上拉点相连，所述第二开关器件的漏极与本级时钟信号源相连，所述第二开关器件的源极与本级移位暂存电路的扫描信号输出端相连以输出本级扫描信号；其中，当所述移位暂存器运行时，本级时钟信号的下降沿与后一级时钟信号的上升沿相同步。
为实现上述目的，本申请进一步提出一种显示装置，所述显示装置包括显示面板以及驱动组件，所述驱动组件包括移位暂存器，所述移位暂存器包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括第一开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连，且所述移位暂存器集成于所述显示面板的阵列基板上。
在本申请技术方案中，移位暂存器包括级联设置的多级移位暂存电路，移位暂存电路包括输出电路，输出电路包括第一开关器件，第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连。通过在输出电路中增设第一开关器件，且第一开关器件的栅极和漏极与上拉点相连，源极与扫描信号输出端相连，那么，当本级移位暂存电路的上拉点处于被预充的状态时，第一开关器件的栅极处于高电平状态，因此第一开关器件导通，上拉点的上拉信号通过第一开关器件对本级移位暂存电路的扫描信号输出端充电，使扫描信号预先上升至次高电平状态。进一步的，在预充完成后，输出电路导通，在输出电路的寄生电容等的耦合作用下，第一开关器件和输出电路中的其它器件同时对扫描信号输出端充电，使扫描信号进一步上升至高电平状态，从而改善了所产生的扫描信号的波形，提升了移位暂存器的输出能力。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为一范例中移位暂存器的第n级移位暂存电路的结构示意图；
图2为一范例中4CK移位暂存器的时序示意图；
图3为本申请显示装置一实施例的结构示意图；
图4为本申请移位暂存器一实施例中第n级移位暂存电路的结构示意图；
图5为本申请移位暂存器一具体示例中4CK移位暂存器的时序示意图；
图6为本申请移位暂存器另一具体示例中第n级移位暂存电路的电路结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
图1所示为一范例中移位暂存器的第n级移位暂存电路的结构示意图，包括充电电路111’、输出电路112’、复位电路113’和稳压电路114’。其中，输出电路112’与本级时钟信号源相连，以接收本级时钟信号CK(n)’，从而产生本级扫描信号。在图2所示的四时钟（4CK）移位暂存器的时序下，本级时钟信号的下降沿与后一级时钟信号的上升沿相同步，以第2级移位暂存电路产生第2级扫描信号的过程为例，充电电路111’连接于本级移位暂存电路的预充信号源，以接收预充信号ST(n)’，其中，预充信号ST(n)’可以是前级反馈信号F(n-i)’。在第2级时钟信号CK(2)’由低电平转换为高电平之前，第2级移位暂存电路的充电电路111’对第2级移位暂存电路的上拉点进行预充电，当第2级时钟信号CK(2)’转换为高电平状态时，输出电路112’导通，并在其寄生电容的作用下继续对上拉点充电，从而产生第2级扫描信号G(2)’。在一具体示例中，输出电路112’包括一开关器件，该开关器件的栅极与上拉点相连，漏极与时钟信号源相连，而源极与扫描信号输出端相连以输出扫描信号。此后，在复位电路113’和稳压电路114’的作用下，第2级扫描信号G(2)’被下拉至低电平状态，实现第2级扫描信号G(2)’的复位。
本申请提出一种移位暂存器，以改善扫描信号的波形，提升移位暂存器的输出能力。在本申请的一实施例中，如图3和图4所示，移位暂存器110包括级联设置的多级移位暂存电路，移位暂存电路包括输出电路112，输出电路112包括第一开关器件T1，第一开关器件T1的栅极和漏极与本级移位暂存电路的上拉点相连，第一开关器件T1的源极与本级移位暂存电路的扫描信号输出端相连。
后文中将以液晶显示装置为例，对本申请的具体方案进行详细阐述。如图3所示，显示装置包括显示面板，显示面板包括阵列基板100、滤色基板200和填充于阵列基板100与滤色基板200之间的液晶（图中未示出）。显示面板上设置有呈矩形阵列状排布的多个像素，每一像素通常包括若干子像素，阵列基板100上设置有与各个子像素对应的开关器件，滤色基板200上设置有与各个子像素对应的滤色区块。在阵列基板100上开关器件的控制下，各个子像素对应的区域中的液晶按照一定的角度偏转，以实现特定图像的显示。在GOA架构的显示装置中，阵列基板100上还设置有移位暂存器110，用以驱动各行子像素。通过微加工工艺将移位暂存器110直接集成在阵列基板100上，以省去外接的移位暂存器，有利于降低显示装置的材料成本和工艺成本，同时有利于显示装置的轻薄化和窄边框化设计。
移位暂存器110是在汤普森电路的基础上发展的，包括级联设置的多级移位暂存电路，其中，前级移位暂存电路输出的反馈信号F(n-i)可作为本级移位暂存电路的预充信号ST(n)，后级移位暂存电路输出的反馈信号F(n+j)可作为本级移位暂存电路的下拉信号PD(n)，其中，i和j分别为正整数，其具体取值与移位暂存器中的时序相关，在此不再赘述。同一级移位暂存电路的扫描信号和反馈信号通常是一致的，对于第一级移位暂存电路，可以将单独提供的起始信号作为其上拉信号，对于最后一级移位暂存电路，可以设置冗余的移位暂存电路为其提供下拉信号。
如图4所示，输出电路112增设有第一开关器件T1，第一开关器件T1的栅极和漏极连接于本级移位暂存电路的上拉点，第一开关器件T1的源极连接于本级移位暂存电路的扫描信号输出端。当预充信号ST(n)对上拉点进行预充点时，第一开关器件T1的栅极处于高电平状态，因此第一开关器件T1导通，上拉点的上拉信号PU(n)通过第一开关器件T1对本级移位暂存电路的扫描信号输出端充电，使扫描信号G(n)预先上升至次高电平状态。进一步的，在预充完成后，输出电路112导通，在输出电路112的寄生电容等的耦合作用下，第一开关器件T1和输出电路112中的其它器件同时对扫描信号输出端充电，使扫描信号G(n)进一步上升至高电平状态。以图5所示的4CK移位暂存器中第2级扫描信号G(2)的产生为例，当第2级移位暂存电路的上拉信号PU(2)处于高电平状态之前的次高电平状态时，第一开关器件T1导通，第2级扫描信号G(2)上升至次高电平状态，当第2级时钟信号处于高电平状态时，第2级扫描信号G(2)在次高电平状态的基础上进一步上升至高电平状态，相比范例中高电平升高了ΔU，从而改善了所产生的扫描信号的波形，提升了移位暂存器的输出能力。
当然，在每一级移位暂存电路中，还包括充电电路111、复位电路113和稳压电路114，且充电电路111、输出电路112、复位电路113和稳压电路114均存在多种设置方式。如图4所示，充电电路111的第一端接收预充信号ST(n)，充电电路111的第二端与输出电路112的第一端相连，且充电电路111和输出电路112之间为本级移位暂存电路的上拉点，上拉点对应的上拉信号以PU(n)表示。输出电路112的第二端接收时钟信号CK(n)，需要注意的是，在移位暂存器110中，同一时钟信号往往用以控制多级移位暂存电路，例如，对于TCK移位暂存器而言，第t级时钟信号将控制第t+Tm级移位暂存电路，其中，m为大于或等于零的整数，T为时钟信号源的总数。输出电路112的第三端输出扫描信号G(n)，第四端输出反馈信号F(n)（图中未示出），其中，扫描信号G(n)用以驱动相应的子像素行，反馈信号F(n)通常与扫描信号G(n)一致，用以作为前级移位暂存电路的下拉信号。复位电路113的第一端连接于本级移位暂存电路的上拉点，复位电路113的第二端连接于输出电路112的第三端，复位电路113的第三端连接于低电平信号源，复位电路113的第四端接收本级移位暂存电路的下拉信号PD(n)。在下拉信号PD(n)的控制下，复位电路113将上拉点和扫描信号输出端下拉至低电平，以维持移位暂存器的正常运行，实现逐行扫描驱动。为了更好地消除移位暂存器中可能存在的计时杂讯，移位暂存电路还包括稳压电路114，稳压电路114的第一端连接于本级移位暂存电路的上拉点，稳压电路114的第二端连接于输出电路112的第三端，稳压电路114的第三端连接于低电平信号源，以消除上拉点和扫描信号输出端的计时杂讯。
在本实施例中，移位暂存器110包括级联设置的多级移位暂存电路，移位暂存电路包括输出电路112，输出电路112包括第一开关器件T1，第一开关器件T1的栅极和漏极与本级移位暂存电路的上拉点相连，第一开关器件T1的源极与本级移位暂存电路的扫描信号输出端相连。通过在输出电路112中增设第一开关器件T1，当本级移位暂存电路的上拉点处于被预充的状态时，第一开关器件T1导通，上拉点的上拉信号通过第一开关器件T1对本级移位暂存电路的扫描信号输出端充电，使扫描信号预先上升至次高电平状态。进一步的，在预充完成后，输出电路112导通，在输出电路112的寄生电容等的耦合作用下，第一开关器件T1和输出电路112中的其它器件同时对扫描信号输出端充电，使扫描信号进一步上升至高电平状态，从而改善了所产生的扫描信号的波形，提升了移位暂存器的输出能力。
进一步的，如图6所示，输出电路112包括第二开关器件T2，第二开关器件T2的栅极与本级移位暂存电路的上拉点相连，第二开关器件T2的漏极与本级时钟信号源相连，第二开关器件T2的源极与本级移位暂存电路的扫描信号输出端相连以输出本级扫描信号。
如图5所示，以第2级扫描信号G(2)的产生为例，当第二开关器件T2在上拉信号PU(2)的作用下导通时，第2级时钟信号CK(2)处于高电平，从而产生第2级扫描信号G(2)的高电平。
进一步的，在本级移位暂存电路的上拉点和扫描信号输出端之间还可以设置耦合电容C（图中未示出），使时钟信号更好地与上拉点耦合，以产生扫描信号的高电平。当然，在输出电路112中还可以另行设置一连接方式与第二开关器件T2完全一致的开关器件，以输出本级移位暂存电路的反馈信号，实现与前级或后级移位暂存电路的级联，驱动移位暂存器的运行。
如图6所示，移位暂存电路包括复位电路113，复位电路113包括第三开关器件T3和第四开关器件T4，第三开关器件T3的栅极与本级移位暂存电路的下拉点相连，第三开关器件T3的源极与低电平信号源相连，第三开关器件T3的漏极与本级移位暂存电路的扫描信号输出端相连；第四开关器件T4的栅极与本级移位暂存电路的下拉点相连，第四开关器件T4的源极与低电平信号源相连，第四开关器件T4的漏极与本级移位暂存电路的上拉点相连。
复位电路113用以将产生的扫描信号下拉至低电平状态。具体的，如图5所示，以第2级扫描信号的产生为例，当下拉信号PD(2)处于高电平状态时，第三开关器件T3和第四开关器件T4导通，在低电平信号VSS的作用下将上拉点和扫描信号输出端拉低至低电平状态，实现逐行扫描。
其中，本级移位暂存电路的下拉点与后级移位暂存电路的扫描信号输出端相连，或与后级移位暂存电路的上拉点相连，将G(n+j)或PU(n+k)作为本级移位暂存电路的下拉信号PD(n)，j、k的具体取值与各信号时序相关，在此不再赘述。
如图6所示，移位暂存电路包括充电电路111，充电电路111包括第五开关器件T5，第五开关器件T5的栅极和漏极与本级预充信号源ST(n)相连，第五开关器件T5的源极与本级移位暂存电路的上拉点相连。
其中，预充信号ST(n)可以是前级反馈信号F(n-i)。在图5所示的4时钟（4CK）移位暂存器的时序下，本级时钟信号的下降沿与后一级时钟信号的上升沿相同步，在第n级移位暂存电路的充电电路111中，第五开关器件T5的栅极和漏极接收前一级反馈信号。以第2级移位暂存电路为例，充电电路接收第1级反馈信号F(1)（与第1级扫描信号G(1)一致），当第1级反馈信号F(1)处于高电平状态时，对第2级移位暂存电路的上拉点充电，使得第2级移位暂存电路的上拉点电平PU(2)上升至次高电平。当第1级反馈信号F(1)由高电平状态转换为低电平状态时，第2级时钟信号CK(2)开始由低电平状态转换为高电平状态，此时，由于输出电路112中存在的寄生电容的耦合作用，第2级时钟信号CK(2)也会对上拉点充电，使上拉点电平PU(2)进一步上升至高电平，输出电路112在第2级时钟信号CK(2)的作用下产生第2级扫描信号G(2)的高电平。
如图6所示，移位暂存电路包括稳压电路114，稳压电路包括下拉子电路114a和下拉控制子电路114b，下拉子电路114a的第一端与本级移位暂存电路的扫描信号输出端相连，下拉子电路114a的第二端与低电平信号源相连；下拉控制子电路114b的第一端与下拉子电路114a的第三端相连，下拉控制子电路114b的第二端与低电平信号源相连。
具体的，下拉子电路114a用以维持本级移位暂存电路的上拉点在预设时刻处于低电平状态，从而消除计时杂讯，而下拉控制子电路114b用以控制下拉子电路114a的运行。
本申请还提出一种显示装置，如图3所示，该显示装置包括显示面板100以及驱动组件，驱动组件用以驱动显示面板的显示，驱动组件包括移位暂存器110，该移位暂存器110的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。其中，移位暂存器110为阵列基板上栅驱动集成电路，以降低材料成本和工艺成本。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种移位暂存器，其中，所述移位暂存器包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括：
    第一开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连。
  2. 如权利要求1所述的移位暂存器，其中，所述输出电路包括：
    第二开关器件，所述第二开关器件的栅极与本级移位暂存电路的上拉点相连，所述第二开关器件的漏极与本级时钟信号源相连，所述第二开关器件的源极与本级移位暂存电路的扫描信号输出端相连以输出本级扫描信号。
  3. 如权利要求1所述的移位暂存器，其中，所述移位暂存电路包括复位电路，所述复位电路包括：
    第三开关器件，所述第三开关器件的栅极与本级移位暂存电路的下拉点相连，所述第三开关器件的源极与低电平信号源相连，所述第三开关器件的漏极与本级移位暂存电路的扫描信号输出端相连；以及，
    第四开关器件，所述第四开关器件的栅极与本级移位暂存电路的下拉点相连，所述第四开关器件的源极与所述低电平信号源相连，所述第四开关器件的漏极与本级移位暂存电路的上拉点相连。
  4. 如权利要求3所述的移位暂存器，其中，本级移位暂存电路的下拉点与后级移位暂存电路的扫描信号输出端相连，或本级移位暂存电路的下拉点与后级移位暂存电路的上拉点相连。
  5. 如权利要求1所述的移位暂存器，其中，所述移位暂存电路包括充电电路，所述充电电路包括：
    第五开关器件，所述第五开关器件的栅极和漏极与本级预充信号源相连，所述第五开关器件的源极与本级移位暂存电路的上拉点相连。
  6. 如权利要求1所述的移位暂存器，其中，所述移位暂存电路包括稳压电路，所述稳压电路包括：
    下拉子电路，所述下拉子电路的第一端与本级移位暂存电路的扫描信号输出端相连，所述下拉子电路的第二端与低电平信号源相连；以及，
    下拉控制子电路，所述下拉控制子电路的第一端与所述下拉子电路的第三端相连，所述下拉控制子电路的第二端与低电平信号源相连。
  7. 如权利要求1所述的移位暂存器，其中，所述移位暂存电路还包括耦合电容，所述耦合电容连接于本级移位暂存电路的上拉点和扫描信号输出端之间。
  8. 如权利要求1所述的移位暂存器，其中，当所述移位暂存器运行时，本级时钟信号的下降沿与后一级时钟信号的上升沿相同步。
  9. 如权利要求1所述的移位暂存器，其中，前级移位暂存电路输出的反馈信号作为本级移位暂存电路的预充信号，后级移位暂存电路输出的反馈信号作为本级移位暂存电路的下拉信号。
  10. 如权利要求9所述的移位暂存器，其中，同一级移位暂存电路的扫描信号和反馈信号一致。
  11. 如权利要求1所述的移位暂存器，其中，同一时钟信号，被配置为控制多级所述移位暂存电路。
  12. 一种移位暂存器，其中，所述移位暂存器包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括：
    第一开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连；以及，
    第二开关器件，所述第二开关器件的栅极与本级移位暂存电路的上拉点相连，所述第二开关器件的漏极与本级时钟信号源相连，所述第二开关器件的源极与本级移位暂存电路的扫描信号输出端相连以输出本级扫描信号；
    其中，当所述移位暂存器运行时，本级时钟信号的下降沿与后一级时钟信号的上升沿相同步。
  13. 一种显示装置，其中，所述显示装置包括：
    显示面板；以及，
    驱动组件，所述驱动组件包括移位暂存器，且所述移位暂存器集成于所述显示面板的阵列基板上，所述移位暂存器包括级联设置的多级移位暂存电路，所述移位暂存电路包括输出电路，所述输出电路包括：
    第一开关器件，所述第一开关器件的栅极和漏极与本级移位暂存电路的上拉点相连，所述第一开关器件的源极与本级移位暂存电路的扫描信号输出端相连。
  14. 如权利要求13所述的显示装置，其中，所述输出电路包括：
    第二开关器件，所述第二开关器件的栅极与本级移位暂存电路的上拉点相连，所述第二开关器件的漏极与本级时钟信号源相连，所述第二开关器件的源极与本级移位暂存电路的扫描信号输出端相连以输出本级扫描信号。
  15. 如权利要求13所述的显示装置，其中，所述移位暂存电路包括复位电路，所述复位电路包括：
    第三开关器件，所述第三开关器件的栅极与本级移位暂存电路的下拉点相连，所述第三开关器件的源极与低电平信号源相连，所述第三开关器件的漏极与本级移位暂存电路的扫描信号输出端相连；以及，
    第四开关器件，所述第四开关器件的栅极与本级移位暂存电路的下拉点相连，所述第四开关器件的源极与所述低电平信号源相连，所述第四开关器件的漏极与本级移位暂存电路的上拉点相连。
  16. 如权利要求13所述的显示装置，其中，所述移位暂存电路包括充电电路，所述充电电路包括：
    第五开关器件，所述第五开关器件的栅极和漏极与本级预充信号源相连，所述第五开关器件的源极与本级移位暂存电路的上拉点相连。
  17. 如权利要求13所述的显示装置，其中，所述显示面板上设置有矩形阵列排布的多个像素，每个所述像素包括多个子像素，所述阵列基板上设置有与各个子像素对应的开关器件。
  18. 如权利要求13所述的显示装置，其中，所述移位暂存器为所述阵列基板上栅驱动集成电路。
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