WO2019096120A1 - 栅极驱动电路、显示装置及其驱动方法 - Google Patents

栅极驱动电路、显示装置及其驱动方法 Download PDF

Info

Publication number
WO2019096120A1
WO2019096120A1 PCT/CN2018/115206 CN2018115206W WO2019096120A1 WO 2019096120 A1 WO2019096120 A1 WO 2019096120A1 CN 2018115206 W CN2018115206 W CN 2018115206W WO 2019096120 A1 WO2019096120 A1 WO 2019096120A1
Authority
WO
WIPO (PCT)
Prior art keywords
shift register
pull
register unit
circuit
sub
Prior art date
Application number
PCT/CN2018/115206
Other languages
English (en)
French (fr)
Inventor
代弘伟
杨富成
王政
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18877527.4A priority Critical patent/EP3712880B1/en
Priority to US16/474,801 priority patent/US10885825B2/en
Publication of WO2019096120A1 publication Critical patent/WO2019096120A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display devices, and in particular to a gate driving circuit applied to a display panel, a display device including the same, and a driving method of the display device.
  • a gate drive circuit ie, a GOA (Gate driver-on-array) circuit integrated on the array substrate.
  • the gate driving circuit includes a cascaded multi-stage shift register unit for generating a plurality of driving signals for progressive scanning through a plurality of gate lines. This is an efficient way to drive a thin film transistor based pixel array in a display panel to display image frames one after another on a display panel.
  • the present disclosure provides a gate driving circuit for a display panel, the display panel including a plurality of rows of gate lines sequentially arranged, the gate driving circuit including a plurality of shift register units, the plurality of The shift register unit is divided into a first shift register unit group and a second shift register unit group, and the first shift register unit group is configured to provide a scan signal for odd-numbered gate lines in the display panel.
  • the second shift register unit group is configured to provide a scan signal for even-numbered row gate lines in the display panel,
  • the first shift register unit group includes a plurality of first shift register unit sub-groups, each of the first shift register unit sub-groups includes n shift register units, and the first A is electrically connected to the A-line gate line
  • the output terminal of the stage shift register unit is electrically connected to the input end of the A+n stage shift register unit electrically connected to the A+n row gate line, wherein A is an odd number greater than or equal to 1, and n is greater than 2;
  • the second shift register unit group includes a plurality of second shift register unit subgroups, each of the second shift register unit subgroups includes n shift register units electrically connected to the A+1 row gate lines
  • the output end of the A+1th shift register unit is electrically connected to the input end of the A+1+n shift register unit electrically connected to the A+1+n row gate line;
  • the reset end of the A-stage shift register unit is electrically connected to the output end of the A+a+n-stage shift register unit electrically connected to the A+a+n-row gate line, and the A+1-level shift register unit
  • the reset terminal is electrically connected to the output terminal of the A+a+n+1-stage shift register unit electrically connected to the gate line of the A+a+n+1 row, where a is a natural number smaller than n/2.
  • n is an even number greater than two.
  • n 4.
  • a is one.
  • the display panel includes a display area and a peripheral area surrounding the display area, and the first shift register unit group and the second shift register unit group are respectively disposed on the display panel Opposite sides and disposed in the peripheral area.
  • the shift register unit includes an input sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, a pull-down control sub-circuit, and a reset sub-circuit;
  • a control end of the input sub-circuit is connected to an input end of the shift register unit, an input end of the input sub-circuit is connected to a first level signal end, an output end of the input sub-circuit and the pull-up a control circuit of the sub-circuit is connected, the input sub-circuit is configured to, when the input end of the input sub-circuit receives the first level signal, turn on the input end and the output end of the input sub-circuit;
  • An input end of the pull-up sub-circuit is connected to a clock signal line, an output end of the pull-up sub-circuit is connected to an output end of the shift register unit, and the pull-up sub-circuit is configured to be when the pull-up is When the control end of the circuit receives the first level signal, the input end of the pull-up sub-circuit is electrically connected to the output end;
  • a first input end of the pull-down control sub-circuit is connected to a second level signal end
  • a second input end of the pull-down control sub-circuit is connected to the third level signal end
  • the second level signal end Providing a voltage absolute value of the second level signal greater than a voltage absolute value of the first level signal provided by the first level signal terminal, and the second level signal and the first level signal polarity
  • the third level signal provided by the third level signal end is opposite in polarity to the second level signal provided by the second level signal end
  • the control end of the pull-down control sub-circuit is opposite to the upper a control terminal of the pull-down circuit is connected, a first output end of the pull-down control sub-circuit is connected to a control end of the pull-down sub-circuit, and a second output end of the pull-down control sub-circuit is connected to a control end of the pull-up sub-circuit
  • the pull-down control sub-circuit is configured to: when the control end of the pull-down control
  • An input end of the pull-down sub-circuit is connected to a third level signal end, an output end of the pull-down sub-circuit is connected to an output end of the shift register unit, and the pull-down sub-circuit is configured to be when the pull-down sub-circuit When the control terminal receives the first level signal, the input end and the output end of the pull-down sub-circuit are turned on;
  • a control end of the reset sub-circuit is connected to a reset end of the shift register unit, an input end of the reset sub-circuit is connected to a third level signal end, an output end of the reset sub-circuit and the pull-up
  • the control terminals of the sub-circuits are connected, and the reset sub-circuit is configured to: when the control terminal of the reset sub-circuit receives the first level signal, the input end of the reset sub-circuit and the output end of the reset sub-circuit through.
  • the pull-up sub-circuit includes a pull-up transistor and a storage capacitor, a gate of the pull-up transistor is coupled to a control terminal of the pull-up sub-circuit, and a first-pole of the pull-up transistor is An input end of the pull-up sub-circuit is connected, a second end of the pull-up transistor is connected to an output end of the pull-up sub-circuit, and the pull-up transistor is configured to receive a first gate of the pull-up transistor a level signal, the first pole and the second pole of the pull-up transistor being turned on;
  • a first end of the storage capacitor is coupled to a gate of the pull-up transistor, and a second end of the storage capacitor is coupled to a second pole of the pull-up transistor.
  • the pull-down sub-circuit includes a pull-down transistor, a gate of the pull-down transistor is coupled to a control terminal of the pull-down sub-circuit, and a first pole of the pull-down transistor and an input of the pull-down sub-circuit Connected, the second pole of the pull-down transistor is coupled to the output of the pull-down sub-circuit.
  • the pull-down control sub-circuit includes a plurality of pull-down control transistors including a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor a fifth pull-down control transistor and a sixth pull-down control transistor,
  • the gate and the first pole of the first pull-down control transistor are both connected to the second level signal terminal, and the second pole of the first pull-down control transistor is connected to the gate of the second pull-down control transistor;
  • a first pole of the second pull-down control transistor is connected to the second level signal end, and a second pole of the second pull-down control transistor is connected to a first output end of the pull-down control sub-circuit;
  • a gate of the third pull-down control transistor is connected to a control end of the pull-up sub-circuit, and a first pole of the third pull-down control transistor is connected to the third-level signal terminal, the third pull-down control a second pole of the transistor is coupled to the first output of the pull-down control subcircuit;
  • a gate of the fourth pull-down control transistor is connected to a gate of the third pull-down control transistor, and a first pole of the fourth pull-down control transistor is connected to the third level signal terminal, the fourth pulldown a second pole of the control transistor is coupled to the second pole of the first pull-down control transistor;
  • a gate of the fifth pull-down control transistor is connected to a first output end of the pull-down control sub-circuit, and a first pole of the fifth pull-down control transistor is connected to the third level signal end, the fifth a second pole of the pull-down control transistor is coupled to the second output of the pull-down control subcircuit;
  • a gate of the sixth pull-down control transistor is connected to the control signal terminal, a first pole of the sixth pull-down control transistor is connected to the third level signal terminal, and a second pole of the sixth pull-down control transistor is The output ends of the shift register unit are connected;
  • Each of the plurality of pull-down control transistors is configured to: when a gate of a respective one of the plurality of pull-down control transistors receives a first level signal, the first one of the respective one of the pull-down control transistors The pole and the second pole are turned on.
  • the reset subcircuit includes a reset transistor, a gate of the reset transistor is coupled to a control terminal of the reset subcircuit, and a first pole of the reset transistor is coupled to a reference signal terminal, the reset A second pole of the transistor is coupled to the control terminal of the pull-up sub-circuit.
  • the input subcircuit includes an input transistor having a gate coupled to a control terminal of the input subcircuit, a first pole of the input transistor and an input of the input subcircuit Connected, a second pole of the input transistor is coupled to a control terminal of the pull-up sub-circuit, the input transistor configured to input the input transistor when a gate of the input transistor receives a first level signal The first pole and the second pole are turned on.
  • the present disclosure provides a display device including a display panel and a gate driving circuit, the display panel including a plurality of gate lines, wherein the gate driving circuit is any one described herein a gate driving circuit, wherein outputs of the plurality of shift register units of the gate driving circuit are respectively connected in one-to-one correspondence with the plurality of gate lines.
  • the present disclosure provides a driving method of a display device, wherein the display device is any of the display devices described herein, and the driving method includes:
  • the second clock signals are sequentially supplied to the respective shift register units in the second shift register unit group in the order of the number of stages of the respective shift register units in the second shift register unit group.
  • the clock signal input to the adjacent two-stage shift register unit, the clock signal of the shift register unit of the previous stage is advanced T/n by the clock signal of the shift register unit of the subsequent stage;
  • the first initial control signal input is earlier T/n than the first input second initial control signal, and the time interval between two temporally adjacent first initial control signals is 2T/n, temporally adjacent The time interval between the two second initial control signals is 2T/n.
  • T is the duration of the clock signal at a first level in one cycle.
  • the duty cycle of the first clock signal is between 42% and 50% and the duty cycle of the second clock signal is between 42% and 50%.
  • FIG. 1 is a schematic view of a portion of a conventional gate driving circuit on a side of a display panel
  • FIG. 2 is a schematic view of a portion of a conventional gate driving circuit located on the other side of the display panel;
  • FIG. 3 is a schematic diagram of a first shift register unit group in a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a second shift register unit group in a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of a first clock signal and a second clock signal in accordance with an embodiment of the present disclosure
  • FIG. 6 is a circuit diagram of a shift register unit in a gate drive circuit in accordance with an embodiment of the present disclosure
  • FIG. 7 is a timing comparison diagram of a gate driving circuit in an embodiment of the present disclosure and a comparative example
  • FIG. 9 is a simulation result of an output signal, a reset signal, and a clock signal of a first-stage shift register unit in a gate driving circuit of a comparative example, wherein a duty ratio of the clock signal is 50%;
  • FIG. 10 is a simulation result of an output signal, a reset signal, and a clock signal of a first-stage shift register unit in a gate driving circuit according to an embodiment of the present disclosure, wherein a duty ratio of the clock signal is 50%;
  • Figure 11 is a waveform comparison diagram of the reset signal in the comparative example and the reset signal in the embodiment.
  • FIG. 12 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • a scan signal is output using a gate drive circuit to drive a pixel array of the display panel.
  • the gate drive circuit includes a cascaded multi-stage shift register unit.
  • the output terminal of the shift register unit of the previous stage is reset by the output signal of the shift register unit of the subsequent stage.
  • the duty ratio of the clock signal is too large (for example, more than 40%), it may cause an output failure.
  • a clock signal having a small duty ratio is used for output.
  • the duty ratio of the clock signal is small, the charging time of the pixel unit in the display panel is also shortened correspondingly, thereby reducing the display effect.
  • 1 is a schematic view of a portion of a conventional gate drive circuit on the side of a display panel.
  • 2 is a schematic view of a portion of a conventional gate driving circuit located on the other side of the display panel.
  • the one side and the other side may be, for example, opposite sides of the display panel.
  • the gate drive circuitry can be located in opposite sides of the display panel and in a peripheral region surrounding the display area of the display panel.
  • display area refers to an area of an actual display image of a display substrate (eg, an opposite substrate or an array substrate) in a display panel.
  • peripheral region refers to a region of a display substrate (eg, a counter substrate or an array substrate) in a display panel that is provided with various circuits and traces for transmitting signals to the display substrate.
  • a display substrate eg, a counter substrate or an array substrate
  • non-transparent or opaque components of the display device eg, batteries, printed circuit boards, metal frames
  • the gate driving circuit includes a plurality of shift register units (represented by respective blocks in the figure), a first clock signal line group (CLK1, CLK3, CLK5, and CLK7) and a second a clock signal line group (CLK2, CLK4, CLK6, and CLK8), the plurality of shift register units being divided into a first shift register unit group (shift register unit of FIG. 1) and a second shift register unit group ( a shift register unit of FIG. 2, the first shift register unit group is configured to provide scan signals for odd row gate lines in the display panel, and the second shift register unit group is used for the display panel The even-numbered row gate lines provide a scan signal. It can be understood that the display panel includes a plurality of rows of gate lines arranged in sequence.
  • the number of stages of the shift register unit is the same as the number of lines of the gate lines connected to the shift register unit.
  • the shift register unit connected to the “first row” gate line is the first stage shift register unit in the gate drive circuit
  • the shift register unit connected to the “second line” gate line is the gate drive circuit.
  • the second stage shift register unit, ..., the shift register unit connected to the "sixteenth row” gate line is the sixteenth stage shift register unit in the gate drive circuit, and so on.
  • the reset terminal Reset of the A-stage shift register unit is connected to the output terminal Output of the A+4-stage shift register unit, and the A+1-stage shift register unit
  • the reset terminal Reset is connected to the output terminal Output of the A+5-stage shift register unit.
  • each output end of each shift register unit is configured to output an output signal as a scan signal
  • the reset end of each shift register unit is configured to receive an output signal outputted by the output end of the shift register unit of the first stage as a reset The reset signal of the stage shift register unit.
  • the output signal of the shift register unit is used to reset the shift register unit located on the same side of the display panel.
  • the inventors have found that in the gate driving circuit provided in FIG. 1 and FIG. 2, the duty ratio of the clock signal cannot be increased because the latter driving shifting unit is usually used in the gate driving circuit. Reset the shift register unit of the previous stage. When the duty ratio of the clock signal is large, the rising edge of the reset signal of the shift register unit overlaps with the falling edge of the output signal, thereby causing capacitive coupling and affecting the shift register unit. Output voltage.
  • the present disclosure particularly provides a gate driving circuit applied to a display panel, a display device including the same, and a driving method of the display device, which substantially avoids defects due to related art and Limit one or more of the problems caused.
  • a gate driving circuit for a display panel including a plurality of gate lines sequentially arranged is provided.
  • the gate driving circuit includes a plurality of shift register units, a first clock signal line group, and a second clock signal line group, the plurality of shift registers The unit is divided into a first shift register unit group and a second shift register unit group, and the first shift register unit group is configured to provide a scan signal for odd-numbered gate lines in the display panel, the second shift The bit register unit group is used to provide a scan signal for even-numbered row gate lines in the display panel.
  • the first clock signal line group includes a plurality of (eg, n) first clock signal lines
  • the first shift register unit group includes a plurality of first shift register unit sub-groups.
  • the second clock signal line group includes a plurality of (eg, n) second clock signal lines
  • the second shift register unit group includes a plurality of second shift register unit sub-groups.
  • Each of the second shift register unit sub-groups includes n shift register units, and in the same second shift register unit sub-group, the n shift register units are respectively in one-to-one correspondence with the n second clock signal lines Connected, and the output end of the A+1-level shift register unit is electrically connected to the signal input end of the A+1+n-stage shift register unit, and A+1+n and A+1 are gate lines in the display panel. Line number.
  • the reset terminal of the A-stage shift register unit is electrically coupled to the output terminal of the A+a+n-stage shift register unit, and the reset terminal of the A+1-stage shift register unit and the A+ The output terminals of the a+n+1 stage shift register unit are electrically connected, where a is a natural number less than n/2.
  • the first shift register unit group and the second shift register unit group of the gate drive circuit may be respectively located in opposite sides of the display panel and at least partially located in a peripheral area surrounding the display area of the display panel in. That is, the shift register unit for driving the odd-numbered gate lines may be located in the peripheral area of one side of the display panel, and the shift register unit for driving the even-numbered gate lines may be located on the other side of the display panel. In the surrounding area.
  • the gate drive circuit is an on-column gate driver (GOA) circuit.
  • GAA on-column gate driver
  • the number of stages of the shift register unit is the same as the number of lines of the gate lines connected to the shift register unit.
  • the "first row” indicates that the shift register unit is connected to the first row gate line in the display panel, and the shift register unit is the first stage shift register unit in the gate drive circuit.
  • the “third row” indicates that the shift register unit is connected to the third row gate line in the display panel, and the shift register unit is a third-stage shift register unit in the gate drive circuit.
  • the "fifth line” indicates that the shift register unit is connected to the fifth row gate line in the display panel, and the shift register unit is the fifth-stage shift register unit in the gate drive circuit.
  • the “seventh line” indicates that the shift register unit is connected to the seventh row gate line in the display panel, and the shift register unit is a seventh-stage shift register unit in the gate drive circuit.
  • the “ninth line” indicates that the shift register unit is connected to the ninth row gate line in the display panel, and the shift register unit is the ninth stage shift register unit in the gate drive circuit.
  • the “11th row” indicates that the shift register unit is connected to the eleventh row gate line in the display panel, and the shift register unit is the eleventh stage shift register unit in the gate drive circuit.
  • the “13th line” indicates that the shift register unit is connected to the thirteenth row gate line in the display panel, and the shift register unit is the thirteenth stage shift register unit in the gate drive circuit.
  • the "fifteenth row” indicates that the shift register unit is connected to the fifteenth row gate line in the display panel, and the shift register unit is the fifteenth stage shift register unit in the gate drive circuit. And so on.
  • the "second row” indicates that the shift register unit is connected to the second row gate line in the display panel, and the shift register unit is a second-stage shift register unit in the gate drive circuit.
  • the "fourth row” indicates that the shift register unit is connected to the fourth row gate line in the display panel, and the shift register unit is the fourth-stage shift register unit in the gate drive circuit.
  • the "sixth line” indicates that the shift register unit is connected to the sixth row gate line in the display panel, and the shift register unit is a sixth-stage shift register unit in the gate drive circuit.
  • the “eighth row” indicates that the shift register unit is connected to the eighth row gate line in the display panel, and the shift register unit is the eighth-stage shift register unit in the gate drive circuit.
  • the "tenth line” indicates that the shift register unit is connected to the tenth row gate line in the display panel, and the shift register unit is the tenth stage shift register unit in the gate drive circuit.
  • the "twelfth row” indicates that the shift register unit is connected to the twelfth row gate line in the display panel, and the shift register unit is the tenth order shift register unit in the gate drive circuit.
  • the "fourteenth row” indicates that the shift register unit is connected to the fourteenth row gate line in the display panel, and the shift register unit is the fourteenth stage shift register unit in the gate drive circuit.
  • the "16th line” indicates that the shift register unit is connected to the sixteenth row gate line in the display panel, and the shift register unit is the sixteenth stage shift register unit in the gate drive circuit. And so on.
  • first shift register unit subgroups included in the first shift register unit group no special requirement is imposed on the number of first shift register unit subgroups included in the first shift register unit group.
  • first shift register unit sub-sets in the first shift register unit group left side of FIG. 3 and right side of FIG. 3 are shown in FIG.
  • Two first shift register unit sub-sets (left and right sides of FIG. 3) in the second shift register unit group are shown in FIG.
  • A is an odd variable
  • A+1 is an even variable
  • n is a fixed value
  • the clock signal includes a first clock signal supplied to the first clock signal line and a second clock signal supplied to the second clock signal line;
  • the initial control signal includes each of the first shift register unit groups a first initial control signal supplied from an input terminal Input of a first (eg, most upstream) shift register unit in a subset of shift register units and a second shift register unit in a second shift register unit group A second initial control signal provided by the input Input of the first (eg, most upstream) shift register unit in the subset.
  • each of the first shift register units in each of the first shift register unit sub-groups is sequentially sequentially arranged in the order of the number of stages of each of the first shift register units in each of the first shift register unit sub-groups.
  • the second clock signals are sequentially supplied to the respective shift register units in the second shift register unit group in the order of the number of stages of the respective shift register units in the second shift register unit group.
  • the output signal of the A-stage shift register unit is just shifted from the output signal of the A+n-stage shift register unit. That is, the falling edge of the output signal of the A-stage shift register unit coincides with the rising edge of the output signal of the A+n-stage shift register unit.
  • the output signal of the shift register unit of the A+n+a stage is used as the first
  • the A-stage shift register unit performs reset. It can be seen that the reset signal of the shift register unit is delayed by a ⁇ t ( ⁇ t is the interval of the clock signal of the adjacent two-stage shift register unit) than the output signal of the shift register unit of the present stage, and therefore, does not appear in the reset phase.
  • the reset signal is coupled to the output signal resulting in poor output.
  • T which is the duration of the first level of the first clock signal in one cycle
  • the output signal of the A+n+a shift register unit is reset for the A+1 shift register unit, and the shift register unit is reset.
  • the signal is delayed by a ⁇ t than the output signal of the shift register unit of the current stage, and the reset signal does not appear to be coupled with the output signal during the reset phase, resulting in poor output.
  • a ⁇ n/2 the time after the reset signal is pushed back by the output signal is less than T, and the time interval is small, which does not affect the output too much.
  • n is an even number greater than 2.
  • n is four. It should be noted that although in FIG. 3, a total eight-stage shift register unit is shown in two columns, in an actual display device, shift register units that supply scan signals for odd-numbered gate lines are disposed in the same In the column. Likewise, although an eight-stage shift register unit is shown in two columns in FIG. 4, in an actual display device, shift register units that supply scan signals for even-numbered gate lines are disposed in the same column.
  • n 4
  • the first clock signal line group includes the first clock signal line CLK1, the first clock signal line CLK3, and the first clock signal line CLK5. And a first clock signal line CLK7.
  • the second clock signal line group includes a second clock signal line CLK2, a second clock signal line CLK4, a second clock signal line CLK6, and a second clock signal line CLK8.
  • each of the four shift register units is a shift register unit sub-group, and two shift register unit sub-groups are shown in FIG.
  • the first clock signal line CLK1 is connected to the first stage shift register unit and the ninth stage shift register unit
  • the first clock signal line CLK3 is connected to the third stage shift register unit and the eleventh stage shift register unit.
  • a clock signal line CLK5 is connected to the fifth stage shift register unit and the thirteenth stage shift register unit
  • the first clock signal line CLK7 is connected to the seventh stage shift register unit and the fifteenth stage shift register unit.
  • an input signal is supplied to the first-stage shift register unit by the initial signal STV1
  • an input signal is supplied to the third-stage shift register unit by the initial signal STV3.
  • the second clock signal line CLK2 is connected to the second stage shift register unit, the tenth stage shift register unit, the second clock signal line CLK4 and the fourth stage shift register unit, and the tenth stage
  • the shift register unit is connected
  • the second clock signal line CLK6 is connected to the sixth-stage shift register unit
  • the fourteen-stage shift register unit the second clock signal line CLK8 and the eighth-stage shift register unit
  • the sixteenth stage The shift register unit is connected.
  • the input signal is supplied to the second-stage shift register unit by the initial signal STV2
  • the input signal is supplied to the fourth-stage shift register unit by the initial signal STV4.
  • a first initial control signal STV1, a second initial control signal STV2, a first initial control signal STV3, a second initial control signal STV4, and a first initial control signal are sequentially provided.
  • the STV1, the second initial control signal STV2, the first initial control signal STV3, and the second initial control signal STV4 are sequentially pushed back by T/4.
  • the first clock signal supplied from the first clock signal line CLK1 is advanced by a time interval ⁇ t 2 from the second clock signal line CLK2 to be T/n. And so on.
  • the time interval ⁇ t 3 between the first initial control signal STV1 and the second initial control signal STV2 is T/n
  • the time interval ⁇ t 4 between the first initial control signal STV1 and the first initial control signal STV3 is 2T/n, And so on.
  • FIGS. 3 to 5 there is a time interval ⁇ t 1 between adjacent two first clock signals, and a time interval ⁇ t 2 exists between output signals of adjacent two-stage shift register units.
  • a time interval ⁇ t 2 between the signal output from the A+1+n-stage shift register unit and the signal output from the A+n-stage shift register unit.
  • the output signal of the sixth-stage shift register unit is used for resetting by the first-stage shift register unit
  • the output signal of the eighth-stage shift register unit is used for the third-stage shift.
  • the register unit performs resetting, and uses the output signal of the tenth stage shift register unit to reset the fifth stage shift register unit, and uses the output signal of the tenth level shift register unit to reset the seventh stage shift register unit.
  • the output signal of the fourteenth stage shift register unit is reset by the ninth stage shift register unit, and the output signal of the sixteenth stage shift register unit is used for resetting by the eleventh stage shift register unit, using the tenth
  • the output signal of the eight-stage shift register unit is reset by the thirteenth stage shift register unit, and is reset by the output signal of the twentieth stage shift register unit for the fifteenth stage shift register unit.
  • the output signal of the seventh-stage shift register unit is used for resetting by the second-stage shift register unit, and the output signal of the ninth-stage shift register unit is used for the fourth-stage shift.
  • the bit register unit performs resetting, and the output signal of the eleventh stage shift register unit is used for resetting by the sixth stage shift register unit, and the output signal of the thirteenth stage shift register unit is used for the eighth stage shift register unit.
  • the reset is performed by using the output signal of the fifteenth stage shift register unit for the tenth stage shift register unit, and the output signal of the seventeenth stage shift register unit is used for resetting by the tenth level shift register unit.
  • the output signal of the nineteenth stage shift register unit is reset by the fourteenth stage shift register unit, and is reset by the output signal of the twenty-first stage shift register unit for the sixteenth stage shift register unit.
  • the duty ratio of the first clock signal is between 42% and 50%, and the duty ratio of the second clock signal is 42% to Between 50%, which can effectively extend the charging time of the pixel unit and improve the display effect.
  • the shift register unit includes an input sub-circuit 110, a pull-up sub-circuit 120, a pull-down sub-circuit 130, a pull-down control sub-circuit 140, and a reset sub-circuit 150.
  • the control terminal of the input sub-circuit 110 is connected to the input terminal Input of the shift register unit, the input terminal of the input sub-circuit 110 is connected to the first level signal terminal V1, and the output terminal of the input sub-circuit 110 is The control terminal PU of the pull-up sub-circuit 120 is connected.
  • the input terminal of the input sub-circuit 110 receives the first level signal, the input terminal and the output terminal of the input sub-circuit 110 are turned on.
  • the input end of the pull-up sub-circuit 120 is connected to the corresponding clock signal line through the clock signal terminal CLK, and the output end of the pull-up sub-circuit 120 is connected to the output terminal Output of the shift register unit, and the control of the pull-up sub-circuit 120
  • the terminal PU receives the first level signal
  • the input terminal of the pull-up sub-circuit 120 is turned on with the output terminal of the pull-up sub-circuit 120.
  • the first input terminal of the pull-down control sub-circuit 140 is connected to the second level signal terminal V2, the second input terminal of the pull-down control sub-circuit 140 is connected to the third level signal terminal V3, and the second level signal terminal V2 is provided.
  • the absolute value of the voltage of the second level signal is greater than the absolute value of the voltage of the first level signal provided by the first level signal terminal V1.
  • the second level signal is the same polarity as the first level signal.
  • the third level signal provided by the third level signal terminal V3 is opposite in polarity to the second level signal provided by the second level signal terminal V2 (i.e., one polarity is positive and the other polarity is negative).
  • the control terminal of the pull-down control sub-circuit 140 is connected to the control terminal PU of the pull-up sub-circuit 120.
  • the first output terminal of the pull-down control sub-circuit 140 is connected to the control terminal PD of the pull-down sub-circuit 130, and the second output of the control sub-circuit 140 is pulled down.
  • the terminal is connected to the control terminal PU of the pull-up sub-circuit 120.
  • the input end of the pull-down sub-circuit 130 is connected to the third level signal terminal V3, the output end of the pull-down sub-circuit 130 is connected to the output terminal Output of the shift register unit, and the control terminal PD of the pull-down sub-circuit 130 receives the first power.
  • the input terminal of the pull-down sub-circuit 130 and the output terminal of the pull-down sub-circuit 130 are turned on.
  • the control terminal of the pull-down sub-circuit 130 receives the second level signal, the 130 and the input terminal of the pull-down sub-circuit are disconnected from the output of the pull-down sub-circuit 130.
  • the control terminal of the reset sub-circuit 150 is connected to the reset terminal Reset of the shift register unit, and the input terminal of the reset sub-circuit 150 is connected to the third level signal terminal V3.
  • the output terminal of the reset sub-circuit 150 and the pull-up sub-circuit 120 The control terminal PU is connected.
  • the input terminal of the reset sub-circuit 150 is turned on with the output terminal of the reset sub-circuit, thereby pulling down the potential of the control terminal PU of the pull-up sub-circuit 120 to The third level signal provided by the third level signal terminal V3.
  • the polarities of the first level signal, the second level signal, and the third level signal are determined by thin film transistors in the pixel units of the respective display panels.
  • the first level signal and the second level signal are high level signals (ie, positive voltage)
  • the third level signal is low level signal (ie, , negative voltage).
  • the thin film transistor in the pixel unit is an N-type transistor
  • the first level signal and the second level signal are low level signals (ie, negative voltage)
  • the third level signal is high level signal (ie, , positive voltage).
  • the duty cycle of the shift register unit includes an input phase, an output phase, and a pull-down phase.
  • the shift register units are cascaded. Therefore, for the one-stage shift register unit, the first control signal received by the control terminal of the input sub-circuit 110 of the shift register unit of the present stage is actually located before the shift register unit of the current stage, and is shifted register with the current stage.
  • the input terminal and the output terminal of the input sub-circuit 110 are turned on, thereby charging the control terminal PU of the pull-up sub-circuit 120.
  • the clock signal input by the clock signal line is the second level signal, so even if the input end of the pull-up sub-circuit 120 is turned on with the output end of the pull-up sub-circuit, the final output of the shift register unit is still Is the second level signal.
  • the pull-down control sub-circuit 140 outputs the second level signal to the control terminal PD of the pull-down sub-circuit 130, and the input terminal of the pull-down sub-circuit 130 There is a disconnection from the output of the pull-down sub-circuit 130.
  • the first clock signal line provides a first level of clock signal. Since the input end of the input sub-circuit 110 is disconnected from the output end of the input sub-circuit 110, the control terminal PU of the pull-up sub-circuit 120 is floating. Under the bootstrap action, the control terminal PU of the pull-up sub-circuit 120 It is coupled to a voltage having a greater absolute value to maintain a conducting state between the input of the pull-up sub-circuit 120 and the output of the pull-up sub-circuit 120. In the output stage, the first clock signal line supplies a clock signal of a first level, thereby ensuring that the output terminal Output of the shift register unit outputs a first level signal.
  • the first level signal is supplied to the control terminal of the reset sub-circuit 150 through the reset terminal Reset. Therefore, the reset sub-circuit 150 pulls down the control terminal of the pull-up sub-circuit 120 to the third level, and the pull-down control sub-circuit 140 Providing a second level signal to the control terminal PD of the pull-down sub-circuit 130, so that the input end of the pull-down sub-circuit 130 is turned on and the output end of the shift register unit is turned on, and the third-level signal end is turned on. The output of the shift register unit is pulled low to stop the output.
  • the pull-up sub-circuit 120 includes a pull-up transistor M3 and a storage capacitor C1.
  • the gate of the pull-up transistor M3 is connected to the control terminal PU of the pull-up sub-circuit 120, and the pull-up transistor M3
  • the first pole is connected to the input of the pull-up sub-circuit 120 (ie, the first pole of the pull-up transistor M3 is connected to the clock signal line), and the second pole of the pull-up transistor M3 is connected to the output of the pull-up sub-circuit 120 ( That is, the second pole of the pull-up sub-circuit M3 is connected to the output terminal Output of the shift register unit).
  • the pull-up transistor M3 is configured such that when the gate of the pull-up transistor M3 receives the first level signal, the first and second poles of the pull-up transistor M3 are turned on.
  • the first end of the storage capacitor C1 is connected to the gate of the pull-up transistor M3, and the second end of the storage capacitor C1 is connected to the second electrode of the pull-up transistor M3.
  • the storage capacitor C1 When the gate of the pull-up transistor M3 receives the first level signal, the storage capacitor C1 is charged while the first pole and the second pole of the pull-up transistor M3 are turned on. When the gate of the pull-up transistor M3 is floating, the bootstrap action of the storage capacitor C1 couples the gate of the pull-up transistor M3 to a higher voltage, maintaining the on-state of the pull-up transistor M3.
  • the pull-down sub-circuit 130 includes a pull-down transistor M11 whose gate is connected to the control terminal of the pull-down sub-circuit 130, and the first-pole and pull-down sub-circuits 130 of the pull-down transistor M11
  • the input terminal is connected (ie, the first pole of the pull-down transistor M11 is connected to the third level signal terminal V3)
  • the second pole of the pull-down transistor M11 is connected to the output terminal of the pull-down sub-circuit 130 (ie, the second pole of the pull-down transistor M11) Connected to the output of the shift register unit Output).
  • the pull-down transistor M11 is arranged such that when the gate of the pull-down transistor M11 receives the first level signal, the first and second poles of the pull-down transistor M11 are turned on.
  • the pull-down control sub-circuit 140 includes a plurality of pull-down control transistors including a first pull-down control transistor M9, a second pull-down control transistor M5, and a third pull-down control transistor. M6, a fourth pull-down control transistor M8, a fifth pull-down control transistor M10, and a sixth pull-down control transistor M7.
  • the gate and the first pole of the first pull-down control transistor M9 are both connected to the second level signal terminal V2, and the second pole of the first pull-down control transistor M9 is connected to the gate of the second pull-down control transistor M5.
  • the first pole of the second pull-down control transistor M5 is connected to the second level signal terminal V2, and the second pole of the second pull-down control transistor M5 is connected to the first output terminal of the pull-down control sub-circuit 140.
  • the gate of the third pull-down control transistor M6 is connected to the control terminal PU of the pull-up sub-circuit 120, the first pole of the third pull-down control transistor M6 is connected to the third level signal terminal V3, and the second pull-down control transistor M6 is second.
  • the pole is connected to the first output of the pull-down control sub-circuit 140.
  • the M8 gate of the fourth pull-down control transistor is connected to the gate of the third pull-down control transistor M6, the first pole of the fourth pull-down control transistor M8 is connected to the third level signal terminal V3, and the second pull-down control transistor M8 is the second The pole is connected to the second pole of the first pull-down control transistor M9.
  • the gate of the fifth pull-down control transistor M10 is connected to the first output terminal of the pull-down control sub-circuit 140, the first pole of the fifth pull-down control transistor M10 is connected to the third level signal terminal V3, and the fifth pull-down control transistor M10 is The two poles are coupled to the second output of the pull down control subcircuit 140.
  • the gate of the sixth pull-down control transistor M7 is connected to the control signal terminal GCL, the first pole of the sixth pull-down control transistor M7 is connected to the third level signal terminal V3, and the second pole of the sixth pull-down control transistor M7 is connected to the shift The output of the bit register unit is connected.
  • any one pull-down control transistor when the gate of the pull-down control transistor receives the first level signal, the first pole of the pull-down control transistor and the second pole of the pull-down control transistor are turned on .
  • the reset sub-circuit 150 includes a reset transistor M2 whose gate is connected to the control terminal of the reset sub-circuit 150 (ie, the gate of the reset transistor M2 is connected to the reset terminal Reset).
  • the first pole of the reset transistor M2 is connected to the reference signal terminal Vref, and the second pole of the reset transistor M2 is connected to the control terminal PU of the pull-up sub-circuit 120.
  • the gate of the reset transistor M2 receives the first level signal, the first and second poles of the reset transistor M2 are turned on.
  • the input sub-circuit 110 includes an input transistor M1 whose gate is connected to the control terminal of the input sub-circuit 110 (ie, the gate of the input transistor M1 and the shift register unit)
  • the input terminal is connected
  • the first pole of the input transistor M1 is connected to the input terminal of the input sub-circuit 110 (ie, the first stage of the input transistor M1 is connected to the first level signal terminal V1)
  • the second pole of the input transistor M1 is connected. It is connected to the control terminal PU of the pull-up sub-circuit 120.
  • the input transistor M1 is configured to turn on the first and second poles of the input transistor M1 when the gate of the input transistor M1 receives the first level signal.
  • the reference voltage provided by the reference signal terminal may be a third level voltage.
  • the shift register unit provided by the present disclosure is suitable for the case of two-way scanning.
  • the gate driving circuit can sufficiently charge the pixel unit to improve display stability of the display device.
  • a display device including a display panel and a gate driving circuit, the display panel including a plurality of gate lines, wherein the gate driving circuit is the present disclosure
  • the gate driving circuit is provided, and an output end of the plurality of shift register units of the gate driving circuit is connected in one-to-one correspondence with the plurality of gate lines.
  • FIG. 12 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • the display device includes a display panel 100 and a gate driving circuit
  • the gate driving circuit includes a first shift register unit group and a second shift register unit group, which are respectively set In the peripheral area PA surrounding the display area DA of the display panel 100, and disposed on opposite sides of the display area DA.
  • the display panel includes a plurality of gate lines GL arranged in sequence, and output ends of the plurality of shift register units of the gate driving circuit are respectively connected in one-to-one correspondence with the plurality of gate lines.
  • the clock signal is allowed to have a higher duty ratio, so that the pixel unit can be sufficiently charged to improve display stability of the display device.
  • a driving method of a display device wherein the clock signal includes a first clock signal supplied to a first clock signal line and a second clock signal supplied to a second clock signal line
  • the driving method includes:
  • the second clock signals are sequentially supplied to the respective shift register units in the second shift register unit group in the order of the number of stages of the respective shift register units in the second shift register unit group.
  • the clock signal input to the adjacent two-stage shift register unit, the clock signal of the shift register unit of the previous stage is advanced T/n by the clock signal of the shift register unit of the subsequent stage;
  • the first initial control signal input is earlier T/n than the first input second initial control signal, and the time interval between two temporally adjacent first initial control signals is 2T/n, temporally adjacent The time interval between the two second initial control signals is 2T/n.
  • T is the duration during which the clock signal is at the first level in one cycle.
  • the duty cycle of the first clock signal is between 42% and 50% and the duty cycle of the second clock signal is between 42% and 50%.
  • FIG. 7 is a timing comparison diagram of a gate driving circuit in an embodiment of the present disclosure and a comparative example.
  • the gate driving circuit provided by the embodiment of the present disclosure includes a first clock signal line group and a second clock signal line group
  • the first clock signal line group includes four first clock signal lines, which are respectively the first clock signal line CLK1.
  • the second clock signal line group includes a second clock signal line CLK2, a second clock signal line CLK4, a second clock signal line CLK6, and a second clock signal line CLK8. As shown in FIG. 3 and FIG.
  • each shift register unit in the first shift register unit group is cascaded according to the following rules: the output terminal of the A-stage shift register unit and the A+4 shift register
  • the reset terminal of the A-stage shift register unit is electrically connected to the output terminal of the A+5-stage shift register unit.
  • Each shift register unit in the second shift register unit group is cascaded according to the following rule: the output end of the A+1 stage shift register unit is electrically connected to the signal input end of the A+5 stage shift register unit, The reset terminal of the A+1th shift register unit is electrically connected to the output terminal of the A+6 shift register unit.
  • the timing of the first clock signal and the timing of the second clock signal are all shown in FIG.
  • the gate driving circuit in the comparative example is different in that the reset terminal of the A-stage shift register unit is connected to the output terminal of the A+4-stage shift register unit, and the A+1 level The reset terminal of the shift register unit is connected to the output of the A+5 stage shift register unit, for example, as shown in FIGS. 1 and 2.
  • the reset terminal originally receives the reset signal from the ninth-stage shift register unit, and According to the gate driving circuit of the embodiment of the present disclosure shown in FIGS. 3 and 4, the reset terminal receives the reset signal from the tenth stage shift register unit.
  • the reset signal of the shift register circuit of the present disclosure is delayed by T/4 compared to the comparative example, thereby enabling normal output with a larger clock signal duty ratio.
  • Fig. 9 Shown in Fig. 9 is the output waveform of the one-stage shift register unit of the gate drive circuit provided by the comparative example when the duty ratio of the clock signal is 50%. As shown in FIG. 9, the falling edge of the output signal outputted by the output terminal overlaps with the rising edge of the reset signal received by the reset terminal reset. In the reset phase, the potential of the output terminal of the shift register unit is affected by the reset signal, and It was not effectively pulled low, resulting in an output error.
  • the output waveform of the one-stage shift register unit in the gate driving circuit provided by the embodiment of the present disclosure is shown in FIG. 10 when the duty ratio of the clock signal is 50%.
  • FIG. 10 there is a time interval between the rising edge of the reset signal received by the reset terminal reset and the falling edge of the output signal outputted by the output terminal Output. Therefore, the reset signal does not affect the potential of the output terminal, thereby ensuring correctness. Output.
  • Fig. 11 is a waveform diagram of a reset signal used in the comparative example and a waveform diagram of a reset signal used in the gate drive circuit provided by the embodiment of the present disclosure.
  • ⁇ V p is the voltage jump size of the output terminal of the shift register unit per unit time
  • ⁇ V d is the magnitude of the voltage jump of the reset signal per unit time
  • C c is a coupling capacitance of the output terminal of the shift register unit and the reset signal
  • ⁇ C is the sum of the output of the shift register unit and the coupling capacitance of all signals.
  • the rise time Tr of the reset signal is larger than the rise time Tr of the reset signal in the comparative example, and the fall time Tf of the reset signal in the embodiment of the present disclosure is lower than the fall time of the reset signal in the comparative example.
  • the Tf is large, that is, in the present application, the voltage jump ⁇ V d of the reset signal per unit time is smaller, and therefore, the voltage jump ⁇ V of the output terminal of the shift register unit provided by the embodiment of the present disclosure per unit time. p is also smaller. Therefore, the shift register unit output provided by the embodiment of the present disclosure is more stable.

Abstract

一种栅极驱动电路、显示装置及其驱动方法。所述栅极驱动电路包括多个移位寄存单元，多个移位寄存单元被划分为第一移位寄存单元组和第二移位寄存单元组，且第A级移位寄存单元的输出端与第A+n级移位寄存单元的信号输入端电连接，第A+1级移位寄存单元的输出端与第A+1+n级移位寄存单元的信号输入端电连接；第A级移位寄存单元的复位端与第A+a+n级移位寄存单元的输出端电连接，第A+1级移位寄存单元的复位端与第A+a+n+1级移位寄存单元的输出端电连接。

Description

栅极驱动电路、显示装置及其驱动方法
相关申请的交叉引用
本申请要求于2017年11月16日提交的中国专利申请No.201711137684.X的优先权，其全部内容以引用方式并入本文。
技术领域
本公开涉及显示装置领域，具体地，涉及一种应用于显示面板的栅极驱动电路、一种包括该栅极驱动电路的显示装置和一种显示装置的驱动方法。
背景技术
为了实现显示装置的窄边框化，开发了集成在阵列基板上的栅极驱动电路(即，GOA(Gate driver-on-array)电路)。所述栅极驱动电路包括级联的多级移位寄存单元，用于产生多个驱动信号，以通过多条栅线进行逐行扫描。这是驱动显示面板中的基于薄膜晶体管的像素阵列以在显示面板上一个接一个地显示图像帧的有效方式。
发明内容
一方面，本公开提供一种用于显示面板的栅极驱动电路，所述显示面板包括顺序排列的多行栅线，所述栅极驱动电路包括多个移位寄存单元，所述多个所述移位寄存单元被划分为第一移位寄存单元组和第二移位寄存单元组，所述第一移位寄存单元组配置为为所述显示面板中奇数行栅线提供扫描信号，所述第二移位寄存单元组配置为为所述显示面板中偶数行栅线提供扫描信号，
所述第一移位寄存单元组包括多个第一移位寄存单元子组，每个第一移位寄存单元子组包括n个移位寄存单元，同第A行栅线电连接的第A级移位寄存单元的输出端与同第A+n行栅线电连接的第A+n级移位寄存单元的输入端电连接，其中，A为大于等于1的奇数，n大于2；
所述第二移位寄存单元组包括多个第二移位寄存单元子组，每个第二移位寄存单元子组包括n个移位寄存单元，同第A+1行栅线电连接的第A+1级移位寄存单元的输出端与同第A+1+n行栅线电连接的第A+1+n级移位寄存单元的输入端电连接；并且
第A级移位寄存单元的复位端与同第A+a+n行栅线电连接的第A+a+n级移位寄存单元的输出端电连接，第A+1级移位寄存单元的复位端与同第A+a+n+1行栅线电连接的第A+a+n+1级移位寄存单元的输出端电连接，其中，a为小于n/2的自然数。
在一些实施例中，n为大于2的偶数。
在一些实施例中，n为4。
在一些实施例中，a为1。
在一些实施例中，所述显示面板包括显示区域和围绕所述显示区域的周边区域，所述第一移位寄存单元组和所述第二移位寄存单元组分别设置在所述显示面板的相对两侧且设置在所述周边区域中。
在一些实施例中，所述移位寄存单元包括输入子电路、上拉子电路、下拉子电路、下拉控制子电路和复位子电路；
所述输入子电路的控制端与所述移位寄存单元的输入端相连，所述输入子电路的输入端与第一电平信号端相连，所述输入子电路的输出端与所述上拉子电路的控制端相连，所述输入子电路配置为当所述输入子电路的输入端接收到第一电平信号时，将该输入子电路的输入端和输出端导通；
所述上拉子电路的输入端与时钟信号线相连，所述上拉子电路的输出端与所述移位寄存单元的输出端相连，所述上拉子电路配置为当所述上拉子电路的控制端接收到第一电平信号时，所述上拉子电路的输入端与输出端导通；
所述下拉控制子电路的第一输入端与第二电平信号端相连，所述下拉控制子电路的第二输入端与所述第三电平信号端相连，所述第二电平信号端提供的第二电平信号的电压绝对值大于所述第一电平信号端提供的第一电平信号的电压绝对值，且所述第二电平信号与所述第一电平信号极性相同，所述第三电平信号端提供的第三电平信号 与所述第二电平信号端提供的第二电平信号极性相反，所述下拉控制子电路的控制端与所述上拉子电路的控制端相连，所述下拉控制子电路的第一输出端与所述下拉子电路的控制端相连，所述下拉控制子电路的第二输出端与上拉子电路的控制端相连，所述下拉控制子电路配置为当所述下拉控制子电路的控制端接收到第一电平信号时，下拉控制子电路的第二输入端与下拉控制子电路的第一输出端导通；
所述下拉子电路的输入端与第三电平信号端相连，所述下拉子电路的输出端与所述移位寄存单元的输出端相连，所述下拉子电路配置为当所述下拉子电路的控制端接收到第一电平信号时，下拉子电路的输入端和输出端导通；
所述复位子电路的控制端与所述移位寄存单元的复位端相连，所述复位子电路的输入端与第三电平信号端相连，所述复位子电路的输出端与所述上拉子电路的控制端相连，所述复位子电路配置为当所述复位子电路的控制端接收到第一电平信号时，所述复位子电路的输入端与所述复位子电路的输出端导通。
在一些实施例中，所述上拉子电路包括上拉晶体管和存储电容器，所述上拉晶体管的栅极与所述上拉子电路的控制端相连，所述上拉晶体管的第一极与所述上拉子电路的输入端相连，所述上拉晶体管的第二极为所述上拉子电路的输出端相连，所述上拉晶体管配置当所述上拉晶体管的栅极接收到第一电平信号时，所述上拉晶体管的第一极和第二极导通；
所述存储电容器的第一端与所述上拉晶体管的栅极相连，所述存储电容器的第二端与所述上拉晶体管的第二极相连。
在一些实施例中，所述下拉子电路包括下拉晶体管，所述下拉晶体管的栅极与所述下拉子电路的控制端相连，所述下拉晶体管的第一极与所述下拉子电路的输入端相连，所述下拉晶体管的第二极与所述下拉子电路的输出端相连。
在一些实施例中，所述下拉控制子电路包括多个下拉控制晶体管，该多个下拉控制晶体管包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制 晶体管和第六下拉控制晶体管，
所述第一下拉控制晶体管的栅极和第一极均与所述第二电平信号端相连，所述第一下拉控制晶体管的第二极与第二下拉控制晶体管的栅极相连；
所述第二下拉控制晶体管的第一极与所述第二电平信号端相连，所述第二下拉控制晶体管的第二极与所述下拉控制子电路的第一输出端相连；
所述第三下拉控制晶体管的栅极与所述上拉子电路的控制端相连，所述第三下拉控制晶体管的第一极与所述第三电平信号端相连，所述第三下拉控制晶体管的第二极与所述下拉控制子电路的第一输出端相连；
所述第四下拉控制晶体管的栅极与所述第三下拉控制晶体管的栅极相连，所述第四下拉控制晶体管的第一极与所述第三电平信号端相连，所述第四下拉控制晶体管的第二极与所述第一下拉控制晶体管的第二极相连；
所述第五下拉控制晶体管的栅极与所述下拉控制子电路的第一输出端相连，所述第五下拉控制晶体管的第一极与所述第三电平信号端相连，所述第五下拉控制晶体管的第二极与所述下拉控制子电路的第二输出端相连；
所述第六下拉控制晶体管的栅极与控制信号端相连，所述第六下拉控制晶体管的第一极与所述第三电平信号端相连，所述第六下拉控制晶体管的第二极与所述移位寄存单元的输出端相连；
所述多个下拉控制晶体管中的每一个配置为当所述多个下拉控制晶体管中的相应一个下拉控制晶体管的栅极接收到第一电平信号时，所述相应一个下拉控制晶体管的第一极和第二极导通。
在一些实施例中，所述复位子电路包括复位晶体管，所述复位晶体管的栅极与所述复位子电路的控制端相连，所述复位晶体管的第一极与参考信号端相连，所述复位晶体管的第二极与所述上拉子电路的控制端相连。
在一些实施例中，所述输入子电路包括输入晶体管，所述输入 晶体管的栅极与所述输入子电路的控制端相连，所述输入晶体管的第一极与所述输入子电路的输入端相连，所述输入晶体管的第二极与所述上拉子电路的控制端相连，所述输入晶体管配置为当所述输入晶体管的栅极接收到第一电平信号时，将输入晶体管所述的第一极和第二极导通。
另一方面，本公开提供一种显示装置，所述显示装置包括显示面板和栅极驱动电路，所述显示面板包括多条栅线，其中，所述栅极驱动电路为本文所述的任一栅极驱动电路，所述栅极驱动电路的多个移位寄存单元的输出端分别与多条所述栅线一一对应地相连。
另一方面，本公开提供一种显示装置的驱动方法，其中，所述显示装置为本文所述任一显示装置，所述驱动方法包括：
按照各个第一移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第一移位寄存单元子组中的各个第一个移位寄存单元提供多个第一初始控制信号；
按照各个第二移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第二移位寄存单元子组中的各个第一个移位寄存单元提供多个第二初始控制信号；
按照第一移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第一移位寄存单元组中的各个移位寄存单元提供第一时钟信号；
按照第二移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第二移位寄存单元组中的各个移位寄存单元提供第二时钟信号。
在一些实施例中，输入至相邻两级移位寄存单元的时钟信号中，前一级移位寄存单元的时钟信号比后一级移位寄存单元的时钟信号提前T/n；
最先输入的第一初始控制信号比最先输入的第二初始控制信号提前T/n，时间上相邻的两个第一初始控制信号之间的时间间隔为2T/n，时间上相邻的两个第二初始控制信号之间的时间间隔为2T/n。
在一些实施例中，T为时钟信号在一个周期中处于第一电平的持 续时间。
在一些实施例中，所述第一时钟信号的占空比在42％至50％之间，所述第二时钟信号的占空比在42％至50％之间。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是现有的栅极驱动电路中位于显示面板一侧的部分的示意图；
图2是现有的栅极驱动电路中位于显示面板的另一侧的部分的示意图；
图3是本公开实施例所提供的栅极驱动电路中的第一移位寄存单元组的示意图；
图4是本公开实施例所提供的栅极驱动电路中的第二移位寄存单元组的示意图；
图5是根据本公开实施例的第一时钟信号和第二时钟信号的时序图；
图6是根据本公开实施例的栅极驱动电路中的移位寄存单元的电路示意图；
图7是本公开实施例和对比例中的栅极驱动电路的时序对比图；
图8是对比例的栅极驱动电路中一级移位寄存单元的输出信号、复位信号以及时钟信号的模拟结果，其中，时钟信号的占空比为42％；
图9是对比例的栅极驱动电路中一级移位寄存单元的输出信号、复位信号以及时钟信号的模拟结果，其中，时钟信号的占空比为50％；
图10是本公开实施例所提供的栅极驱动电路中一级移位寄存单元的输出信号、复位信号以及时钟信号的模拟结果，其中，时钟信号的占空比为50％；
图11是对比例中复位信号与实施例中复位信号的波形对比图。
图12是根据本公开实施例的显示装置的示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
通常，利用栅极驱动电路输出扫描信号，以驱动显示面板的像素阵列。栅极驱动电路包括级联的多级移位寄存单元。通常，利用后级的移位寄存单元的输出信号对前级的移位寄存单元的输出端进行复位。
但是，对于同一级移位寄存单元而言，如果时钟信号的占空比过大(例如，超过40％)，就可能会引起输出不良。
因此，在相关技术中，采用占空比较小的时钟信号进行输出。但是，由于时钟信号占空比小，因此，对显示面板中像素单元的充电时间也相应缩短，降低了显示效果。
存在提高移位寄存单元中时钟信号的占空比并减轻输出不良的需要。
图1是现有的栅极驱动电路中位于显示面板一侧的部分的示意图。图2是现有的栅极驱动电路中位于显示面板的另一侧的部分的示意图。所述一侧和所述另一侧例如可以为显示面板的相对两侧。例如，栅极驱动电路可以位于显示面板的相对两侧中且位于围绕显示面板的显示区域的周边区域中。本文使用的术语“显示区域”指的是显示面板中显示基板(例如，对置基板或阵列基板)的实际显示图像的区域。本文使用的术语“周边区域”指的是显示面板中的显示基板(例如，对置基板或阵列基板)的设置有用于向显示基板发送信号的各种电路和走线的区域。为了增加显示设备的透明度，显示设备的非透明或不透明部件(例如，电池、印刷电路板、金属框)可以布置在周边区域中而非布置在显示区域中。
如图1和图2所示，所述栅极驱动电路包括多个移位寄存单元(由图中各方框表示)、第一时钟信号线组(CLK1、CLK3、CLK5和CLK7)和第二时钟信号线组(CLK2、CLK4、CLK6和CLK8)，所述多 个移位寄存单元被划分为第一移位寄存单元组(图1的移位寄存单元)、第二移位寄存单元组(图2的移位寄存单元)，所述第一移位寄存单元组用于为所述显示面板中奇数行栅线提供扫描信号，所述第二移位寄存单元组用于为所述显示面板中偶数行栅线提供扫描信号。可以理解的是，显示面板包括顺序排列的多行栅线。在本公开中，移位寄存单元的级数与和该移位寄存单元相连的栅线的行数相同。例如，与“第一行”栅线相连的移位寄存单元为栅极驱动电路中的第一级移位寄存单元，与“第二行”栅线相连的移位寄存单元为栅极驱动电路中的第二级移位寄存单元，……，与“第十六行”栅线相连的移位寄存单元为栅极驱动电路中的第十六级移位寄存单元，以此类推。
在图1和图2的栅极驱动电路中，第A级移位寄存单元的复位端Reset与第A+4级移位寄存单元的输出端Output相连，第A+1级移位寄存单元的复位端Reset与第A+5级移位寄存单元的输出端Output相连。例如，在图1和图2中，第五(A＝5)级移位寄存单元的复位端Reset与第九(A+4＝5+4＝9)级移位寄存单元的输出端Output相连，第六级(A+1＝5+1＝6)级移位寄存单元的复位端Reset与第十(A+5＝5+5＝10)级移位寄存单元的输出端Output相连。这里，各移位寄存单元的各输出端配置为输出作为扫描信号的输出信号，各移位寄存单元的复位端配置为接收后一级移位寄存单元的输出端输出的输出信号，作为复位本级移位寄存单元的复位信号。在图1和图2所提供的栅极驱动电路中，利用移位寄存单元的输出信号为位于显示面板同一侧的移位寄存单元进行复位。
发明人研究发现，图1和图2中所提供的栅极驱动电路中，无法提高时钟信号的占空比，其原因在于，在该栅极驱动电路中，通常利用后一级移位寄存单元对前一级移位寄存单元进行复位，当时钟信号占空比较大时，会导致移位寄存单元的复位信号的上升沿与输出信号的下降沿重叠，从而造成电容耦合，影响移位寄存单元的输出端电压。
因此，本公开特别提供了一种应用于显示面板的栅极驱动电路、一种包括该栅极驱动电路的显示装置和一种显示装置的驱动方法，其 实质上避免了由于相关技术的缺陷和限制所导致的问题中的一个或多个。
作为本公开的一个方面，提供一种用于显示面板的栅极驱动电路，所述显示面板包括顺序地排列的多条栅线。如图3和图4所示，在一些实施例中，所述栅极驱动电路包括多个移位寄存单元、第一时钟信号线组和第二时钟信号线组，所述多个移位寄存单元被划分为第一移位寄存单元组、第二移位寄存单元组，所述第一移位寄存单元组用于为所述显示面板中奇数行栅线提供扫描信号，所述第二移位寄存单元组用于为所述显示面板中偶数行栅线提供扫描信号。
在一些实施例中，所述第一时钟信号线组包括多条(例如，n条)第一时钟信号线，所述第一移位寄存单元组包括多个第一移位寄存单元子组，每个第一移位寄存单元子组包括n个移位寄存单元，在同一个第一移位寄存单元子组中，n个移位寄存单元分别与n条第一时钟信号线一一对应地连接，且第A级移位寄存单元的输出端与第A+n级移位寄存单元的信号输入端电连接，其中，A和A+n均为显示面板中的栅线的行号，且A为奇数，A＝1,3，…，n大于2。
在一些实施例中，所述第二时钟信号线组包括多条(例如，n条)第二时钟信号线，所述第二移位寄存单元组包括多个第二移位寄存单元子组，每个第二移位寄存单元子组包括n个移位寄存单元，在同一个第二移位寄存单元子组中，n个移位寄存单元分别与n条第二时钟信号线一一对应地连接，且第A+1级移位寄存单元的输出端与第A+1+n级移位寄存单元的信号输入端电连接，A+1+n、A+1均为显示面板中栅线的行号。
在一些实施例中，第A级移位寄存单元的复位端与第A+a+n级移位寄存单元的输出端电连接，第A+1级移位寄存单元的复位端与第A+a+n+1级移位寄存单元的输出端电连接，其中，a为小于n/2的自然数。
在一些实施例中，栅极驱动电路的第一移位寄存单元组和第二移位寄存单元组可以分别位于显示面板的相对两侧中且至少部分地位于围绕显示面板的显示区域的周边区域中。也就是说，用于驱动奇 数行栅线的移位寄存单元可以位于显示面板的一侧的周边区域中，而用于驱动偶数行栅线的移位寄存单元可以位于显示面板的另一侧的周边区域中。
在一些实施例中，所述栅极驱动电路为阵列上栅极驱动器(GOA)电路。
如上所述，在本公开中，移位寄存单元的级数与和该移位寄存单元相连的栅线的行数相同。
如图3所示，“第一行”表示该移位寄存单元与显示面板中的第一行栅线相连，该移位寄存单元为栅极驱动电路中的第一级移位寄存单元。“第三行”表示该移位寄存单元与显示面板中的第三行栅线相连，该移位寄存单元为栅极驱动电路中的第三级移位寄存单元。“第五行”表示该移位寄存单元与显示面板中的第五行栅线相连，该移位寄存单元为栅极驱动电路中的第五级移位寄存单元。“第七行”表示该移位寄存单元与显示面板中的第七行栅线相连，该移位寄存单元为栅极驱动电路中的第七级移位寄存单元。“第九行”表示该移位寄存单元与显示面板中的第九行栅线相连，该移位寄存单元为栅极驱动电路中的第九级移位寄存单元。“第十一行”表示该移位寄存单元与显示面板中的第十一行栅线相连，该移位寄存单元为栅极驱动电路中的第十一级移位寄存单元。“第十三行”表示该移位寄存单元与显示面板中的第十三行栅线相连，该移位寄存单元为栅极驱动电路中的第十三级移位寄存单元。“第十五行”表示该移位寄存单元与显示面板中的第十五行栅线相连，该移位寄存单元为栅极驱动电路中的第十五级移位寄存单元。依次类推。
如图4所示，“第二行”表示该移位寄存单元与显示面板中的第二行栅线相连，该移位寄存单元为栅极驱动电路中的第二级移位寄存单元。“第四行”表示该移位寄存单元与显示面板中的第四行栅线相连，该移位寄存单元为栅极驱动电路中的第四级移位寄存单元。“第六行”表示该移位寄存单元与显示面板中的第六行栅线相连，该移位寄存单元为栅极驱动电路中的第六级移位寄存单元。“第八行”表示该移位寄存单元与显示面板中的第八行栅线相连，该移位寄存单元为 栅极驱动电路中的第八级移位寄存单元。“第十行”表示该移位寄存单元与显示面板中的第十行栅线相连，该移位寄存单元为栅极驱动电路中的第十级移位寄存单元。“第十二行”表示该移位寄存单元与显示面板中的第十二行栅线相连，该移位寄存单元为栅极驱动电路中的第十二级移位寄存单元。“第十四行”表示该移位寄存单元与显示面板中的第十四行栅线相连，该移位寄存单元为栅极驱动电路中的第十四级移位寄存单元。“第十六行”表示该移位寄存单元与显示面板中的第十六行栅线相连，该移位寄存单元为栅极驱动电路中的第十六级移位寄存单元。依次类推。
在本公开中，对第一移位寄存单元组中包括的第一移位寄存单元子组的数量并不做特殊的要求。例如，在图3中示出第一移位寄存单元组中的两个第一移位寄存单元子组(图3的左侧和图3的右侧)。在图4中示出第二移位寄存单元组中的两个第一移位寄存单元子组(图3的左侧和右侧)。
在本公开中，A为奇数变量，A+1则为偶数变量，n为定值。
容易理解的是，对于同一级移位寄存单元而言，应当确保该级移位寄存单元的复位信号与本级移位寄存单元的输出信号完全错开，但是，本级移位寄存单元的输出信号与本级移位寄存单元的复位信号之间的时间间隔也不宜过大。下文中将对本级移位寄存单元的输出信号与本级移位寄存单元的复位信号之间的时间间隔进行解释和说明，这里先不赘述。
在利用所述栅极驱动电路驱动显示面板进行显示时，需要向栅极驱动电路提供时钟信号和初始控制信号。其中，所述时钟信号包括向第一时钟信号线提供的第一时钟信号和向第二时钟信号线提供的第二时钟信号；所述初始控制信号包括向第一移位寄存单元组中各个第一移位寄存单元子组中第一个(例如，最上游的)移位寄存单元的输入端Input提供的第一初始控制信号和向第二移位寄存单元组中各个第二移位寄存单元子组中第一个(例如，最上游的)移位寄存单元的输入端Input提供的第二初始控制信号。
具体地，按照各个第一移位寄存单元子组中的各个第一个移位 寄存单元的级数的先后顺序依次向各个第一移位寄存单元子组中的各个第一个移位寄存单元提供多个第一初始控制信号；
按照各个第二移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第二移位寄存单元子组中的各个第一个移位寄存单元提供多个第二初始控制信号；
按照第一移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第一移位寄存单元组中的各个移位寄存单元提供第一时钟信号；
按照第二移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第二移位寄存单元组中的各个移位寄存单元提供第二时钟信号。
对于本公开所提供的栅极驱动电路而言，第A级移位寄存单元的输出信号与第A+n级移位寄存单元的输出信号刚好错开。也就是，第A级移位寄存单元的输出信号的下降沿与第A+n级移位寄存单元的输出信号的上升沿重合。
当对第A级移位寄存单元进行复位时，为了避免输出信号的下降沿与复位信号的上升沿重叠，在本公开中，采用第A+n+a级移位寄存单元的输出信号为第A级移位寄存单元进行复位。由此可知，移位寄存单元的复位信号比本级移位寄存单元的输出信号推后aΔt(Δt为相邻两级移位寄存单元的时钟信号的间隔)，因此，在复位阶段不会出现复位信号与输出信号耦合导致输出不良。此外，由于a＜n/2，因此，复位信号比输出信号推后的时间小于T(其为第一时钟信号在一个周期中为第一电平的持续时间)，该时间间隔较小，并不会对输出造成过多影响。
同样地，对于第A+1移位寄存单元进行复位时，采用第A+n+a级移位寄存单元的输出信号为第A+1级移位寄单元进行复位，移位寄存单元的复位信号比本级移位寄存单元的输出信号推后aΔt，在复位阶段不会出现复位信号与输出信号耦合导致输出不良。此外，由于a＜n/2，因此，复位信号比输出信号推后的时间小于T，该时间间隔较小，并不会对输出造成过多影响。
在本公开中，对n的具体数值并没有特殊的要求。只要n为大于2的偶数即可。在图3和图4中所示的实施方式中，n为4。需要解释的是，虽然在图3中，在两列中示出了共八级移位寄存单元，但是在实际的显示装置中，为奇数行栅线提供扫描信号的移位寄存单元设置在同一列中。同样地，虽然在图4中，在两列中示出了八级移位寄存单元，但是在实际的显示装置中，为偶数行栅线提供扫描信号的移位寄存单元设置在同一列中。
如上文中所述，在图3和图4中所提供的实施方式中，n为4，第一时钟信号线组包括第一时钟信号线CLK1、第一时钟信号线CLK3、第一时钟信号线CLK5和第一时钟信号线CLK7。第二时钟信号线组包括第二时钟信号线CLK2、第二时钟信号线CLK4、第二时钟信号线CLK6和第二时钟信号线CLK8。
如图3中所示，每四个移位寄存单元为一个移位寄存单元子组，图3中示出了两个移位寄存单元子组。第一时钟信号线CLK1与第一级移位寄存单元、第九级移位寄存单元相连，第一时钟信号线CLK3与第三级移位寄存单元、第十一级移位寄存单元相连，第一时钟信号线CLK5与第五级移位寄存单元、第十三级移位寄存单元相连，第一时钟信号线CLK7与第七级移位寄存单元、第十五级移位寄存单元相连。并且，从图3中还可以得知，利用初始信号STV1为第一级移位寄存单元提供输入信号，利用初始信号STV3为第三级移位寄存单元提供输入信号。
如图4中所示，第二时钟信号线CLK2与第二级移位寄存单元、第十级移位寄存单元相连，第二时钟信号线CLK4与第四级移位寄存单元、第十二级移位寄存单元相连，第二时钟信号线CLK6与第六级移位寄存单元、第十四级移位寄存单元相连，第二时钟信号线CLK8与第八级移位寄存单元、第十六级移位寄存单元相连。并且，从图4中还可以得知，利用初始信号STV2为第二级移位寄存单元提供输入信号，利用初始信号STV4为第四级移位寄存单元提供输入信号。
如图5所示，栅极驱动电路工作时，依次提供第一初始控制信号STV1、第二初始控制信号STV2、第一初始控制信号STV3、第二初 始控制信号STV4，并且，第一初始控制信号STV1、第二初始控制信号STV2、第一初始控制信号STV3、第二初始控制信号STV4依次推后T/4。
第一时钟信号线CLK1提供的第一时钟信号比第一时钟信号线CLK3提供的第一时钟信号提前时间间隔Δt 1，其中，该时间间隔Δt 1满足以下公式：Δt 1＝2T/n，其中，T为在第一时钟信号的一个周期中第一时钟信号为第一电平时的持续时间。第一时钟信号线CLK1提供的第一时钟信号比第二时钟信号线CLK2提供的第二时钟信号提前时间间隔为Δt 2为T/n。依次类推。
第一初始控制信号STV1与第二初始控制信号STV2之间的时间间隔Δt 3为T/n，第一初始控制信号STV1与第一初始控制信号STV3之间的时间间隔Δt 4为2T/n，依次类推。
在本公开中，如图3至图5所示，相邻两个第一时钟信号之间存在时间间隔Δt 1，相邻两级移位寄存单元的输出信号之间存在时间间隔Δt 2。第A+1+n级移位寄存单元输出的信号与第A+n级移位寄存单元的输出的信号之间存在时间间隔Δt 2。第A+n级移位寄存单元的输出信号与复位信号之间存在时间间隔，从而避免了输出信号的下降沿与复位信号的上升沿时间重叠而导致的电容耦合扰乱输出。因此，在利用包括本公开所提供的栅极驱动电路驱动显示面板时，可以提高时钟信号的占空比，从而可以延长对像素单元的充电时间，提高显示面板的显示效果。
在本公开图3和图4所提供的具体实施方式中，n为4，也就是说，每组时钟信号包括四条第一时钟信号线。相应地，如图5所示，相邻两个第一时钟信号之间的时间间隔Δt 1为T/2。在一些实施例中，a为1。
在图3和图4中所示的实施方式中，圆圈内的数字表示提供复位信号的移位寄存单元的级数。
在图3中所示的实施方式中，利用第六级移位寄存单元的输出信号为第一级移位寄存单元进行复位，利用第八级移位寄存单元的输出信号为第三级移位寄存单元进行复位，利用第十级移位寄存单元的 输出信号为第五级移位寄存单元进行复位，利用第十二级移位寄存单元的输出信号为第七级移位寄存单元进行复位，利用第十四级移位寄存单元的输出信号为第九级移位寄存单元进行复位，利用第十六级移位寄存单元的输出信号为第十一级移位寄存单元进行复位，利用第十八级移位寄存单元的输出信号为第十三级移位寄存单元进行复位，利用第二十级移位寄存单元的输出信号为第十五级移位寄存单元进行复位。
在图4中所示的具体实施方式中，利用第七级移位寄存单元的输出信号为第二级移位寄存单元进行复位，利用第九级移位寄存单元的输出信号为第四级移位寄存单元进行复位，利用第十一级移位寄存单元的输出信号为第六级移位寄存单元进行复位，利用第十三级移位寄存单元的输出信号为第八级移位寄存单元进行复位，利用第十五级移位寄存单元的输出信号为第十级移位寄存单元进行复位，利用第十七级移位寄存单元的输出信号为第十二级移位寄存单元进行复位，利用第十九级移位寄存单元的输出信号为第十四级移位寄存单元进行复位，利用第二十一级移位寄存单元的输出信号为第十六级移位寄存单元进行复位。
利用本公开所提供的栅极驱动电路驱动显示面板进行显示时，所述第一时钟信号的占空比在42％至50％之间，所述第二时钟信号的占空比在42％至50％之间，从而可以有效延长像素单元的充电时间，提高显示效果。
在本公开中，对移位寄存单元的具体结构并没有特殊的限制。在一些实施例中，如图6所示，所述移位寄存单元包括输入子电路110、上拉子电路120、下拉子电路130、下拉控制子电路140和复位子电路150。
如图6中所示，输入子电路110的控制端与移位寄存单元的输入端Input相连，输入子电路110的输入端与第一电平信号端V1相连，输入子电路110的输出端与上拉子电路120的控制端PU相连，输入子电路110的输入端接收到第一电平信号时，将该输入子电路110的输入端和输出端导通。
上拉子电路120的输入端与通过时钟信号端CLK与相应的时钟信号线相连，上拉子电路120的输出端与所述移位寄存单元的输出端Output相连，上拉子电路120的控制端PU接收到第一电平信号时，上拉子电路120的输入端与该上拉子电路120的输出端导通。
下拉控制子电路140的第一输入端与第二电平信号端V2相连，下拉控制子电路140的第二输入端与所述第三电平信号端V3相连，第二电平信号端V2提供的第二电平信号的电压绝对值大于第一电平信号端V1提供的第一电平信号的电压绝对值。且第二电平信号与第一电平信号极性相同。第三电平信号端V3提供的第三电平信号与第二电平信号端V2提供的第二电平信号极性相反(即，一个极性为正另一个极性为负)。下拉控制子电路140的控制端与上拉子电路120的控制端PU相连，下拉控制子电路140的第一输出端与下拉子电路130的控制端PD相连，下拉控制子电路140的第二输出端与上拉子电路120的控制端PU相连。当下拉控制子电路140的控制端接收到第一电平信号时，该下拉控制子电路140的第二输入端与该下拉控制子电路140的第一输出端导通。
下拉子电路130的输入端与第三电平信号端V3相连，下拉子电路130的输出端与所述移位寄存单元的输出端Output相连，下拉子电路130的控制端PD接收到第一电平信号时，该下拉子电路130的输入端和该下拉子电路130的输出端导通。下拉子电路130的控制端接收到第二电平信号时，下拉子电路的130和输入端与该下拉子电路130的输出端之间断开。
复位子电路150的控制端与所述移位寄存单元的复位端Reset相连，复位子电路150的输入端与第三电平信号端V3相连，复位子电路150的输出端与上拉子电路120的控制端PU相连。复位子电路150的控制端接收到第一电平信号时，该复位子电路150的输入端与该复位子电路的输出端导通，从而将上拉子电路120的控制端PU的电位下拉至第三电平信号端V3提供的第三电平信号。
在本公开中，第一电平信号、第二电平信号、第三电平信号的极性由相应显示面板的像素单元中的薄膜晶体管所决定。例如，当像 素单元中的薄膜晶体管为P型晶体管时，第一电平信号、第二电平信号为高电平信号(即，正电压)，第三电平信号为低电平信号(即，负电压)。反之，当像素单元中的薄膜晶体管为N型晶体管时，第一电平信号、第二电平信号为低电平信号(即，负电压)，第三电平信号为高电平信号(即，正电压)。
移位寄存单元的工作周期包括输入阶段、输出阶段和下拉阶段。如上文中所述，栅极驱动电路中，移位寄存单元是级联的。因此，对于一级移位寄存单元而言，本级移位寄存单元的输入子电路110的控制端接收到的第一控制信号其实是位于本级移位寄存单元之前、与本级移位寄存单元相级联的移位寄存单元的输出信号。
在输入阶段，输入子电路110的输入端与输出端之间导通，从而向上拉子电路120的控制端PU充电。在该输入阶段，时钟信号线输入的时钟信号为第二电平信号，因此，即便上拉子电路120的输入端与该上拉子电路的输出端导通，移位寄存单元最终输出的仍然是第二电平信号。在此阶段，由于上拉子电路120的控制端为第一电平信号，因此，下拉控制子电路140向下拉子电路130的控制端PD输出第二电平信号，下拉子电路130的输入端与该下拉子电路130的输出端之间是断开的。
在输出阶段，第一时钟信号线提供第一电平的时钟信号。由于输入子电路110的输入端与该输入子电路110的输出端之间断开，因此，上拉子电路120的控制端PU浮置，在自举作用下，上拉子电路120的控制端PU被耦合至绝对值更大的电压，从而维持上拉子电路120的输入端与该上拉子电路120的输出端之间的导通状态。在输出阶段，第一时钟信号线提供第一电平的时钟信号，从而可以确保移位寄存单元的输出端Output输出第一电平信号。
在下拉阶段，通过复位端Reset向复位子电路150的控制端提供第一电平信号，因此，复位子电路150将上拉子电路120的控制端下拉至第三电平，下拉控制子电路140向下拉子电路130的控制端PD提供第二电平信号，使得下拉子电路130的输入端与输出端导通，并将移位寄存单元的输出端Output与第三电平信号端导通，以将移 位寄存单元的输出端电位拉低，停止输出。
在图6中所示的实施方式中，上拉子电路120包括上拉晶体管M3和存储电容器C1，上拉晶体管M3的栅极与上拉子电路120的控制端PU相连，上拉晶体管M3的第一极与上拉子电路120的输入端相连(即，上拉晶体管M3的第一极与时钟信号线相连)，上拉晶体管M3的第二极与上拉子电路120的输出端相连(即，上拉子电路M3的第二极与移位寄存单元的输出端Output相连)。上拉晶体管M3配置为当上拉晶体管M3的栅极接收到第一电平信号时，该上拉晶体管M3的第一极和第二极导通。
存储电容器C1的第一端与上拉晶体管M3的栅极相连，存储电容器C1的第二端与上拉晶体管M3的第二极相连。
当上拉晶体管M3的栅极接收到第一电平信号时，对存储电容C1进行充电，同时，上拉晶体管M3的第一极和第二极导通。当上拉晶体管M3的栅极浮置时，存储电容C1的自举作用将上拉晶体管M3的栅极耦合至更高的电压，维持上拉晶体管M3的导通状态。
在图6中所示的实施方式中，下拉子电路130包括下拉晶体管M11，该下拉晶体管M11的栅极与下拉子电路130的控制端相连，下拉晶体管M11的第一极与下拉子电路130的输入端相连(即，下拉晶体管M11的第一极与第三电平信号端V3相连)，下拉晶体管M11的第二极与下拉子电路130的输出端相连(即，下拉晶体管M11的第二极与移位寄存单元的输出端Output相连)。下拉晶体管M11设置为当下拉晶体管M11的栅极接收到第一电平信号时，该下拉晶体管M11的第一极和第二极导通。
在图6中所示的实施方式中，下拉控制子电路140包括多个下拉控制晶体管，该多个下拉控制晶体管包括第一下拉控制晶体管M9、第二下拉控制晶体管M5、第三下拉控制晶体管M6、第四下拉控制晶体管M8、第五下拉控制晶体管M10和第六下拉控制晶体管M7。
第一下拉控制晶体管M9的栅极和第一极均与所述第二电平信号端V2相连，第一下拉控制晶体管M9的第二极与第二下拉控制晶体管M5的栅极相连。
第二下拉控制晶体管M5的第一极与第二电平信号端V2相连，第二下拉控制晶体管M5的第二极与下拉控制子电路140的第一输出端相连。
第三下拉控制晶体管M6的栅极与上拉子电路120的控制端PU相连，第三下拉控制晶体管M6的第一极与第三电平信号端V3相连，第三下拉控制晶体管M6的第二极与下拉控制子电路140的第一输出端相连。
第四下拉控制晶体管的M8栅极与第三下拉控制晶体管M6的栅极相连，第四下拉控制晶体管M8的第一极与第三电平信号端V3相连，第四下拉控制晶体管M8的第二极与第一下拉控制晶体管M9的第二极相连。
第五下拉控制晶体管M10的栅极与下拉控制子电路140的第一输出端相连，第五下拉控制晶体管M10的第一极与第三电平信号端V3相连，第五下拉控制晶体管M10的第二极与下拉控制子电路140的第二输出端相连。
第六下拉控制晶体管M7的栅极与控制信号端GCL相连，第六下拉控制晶体管M7的第一极与第三电平信号端V3相连，第六下拉控制晶体管M7的第二极与所述移位寄存单元的输出端Output相连。
在本公开中，对于任意一个下拉控制晶体管而言，当该下拉控制晶体管的栅极接收到第一电平信号时，该下拉控制晶体管的第一极和该下拉控制晶体管的第二极导通。
在图6中所示的实施方式中，复位子电路150包括复位晶体管M2，该复位晶体管M2的栅极与复位子电路150的控制端相连(即，复位晶体管M2的栅极与复位端Reset相连)，复位晶体管M2的第一极与参考信号端Vref相连，复位晶体管M2的第二极与上拉子电路120的控制端PU相连。复位晶体管M2的栅极接收到第一电平信号时，该复位晶体管M2的第一极和第二极导通。
在图6中所示的实施方式中，输入子电路110包括输入晶体管M1，输入晶体管M1的栅极与输入子电路110的控制端相连(即，输入晶体管M1的栅极与移位寄存单元的输入端Input相连)，输入晶 体管M1的第一极与输入子电路110的输入端相连(即，输入晶体管M1的第一级与第一电平信号端V1相连)，输入晶体管M1的第二极与上拉子电路120的控制端PU相连。输入晶体管M1配置为当输入晶体管M1的栅极接收到第一电平信号时，将输入晶体管M1的第一极和第二极导通。
在本公开中，参考信号端提供的参考电压可以是第三电平电压。本公开所提供的移位寄存单元适用于双向扫描的情况。
如上文中所述，当利用本公开所提供的栅极驱动电路向显示面板提供扫描信号时，对于任意一级移位寄存单元而言，复位信号与输出信号之间不会出现耦合，从而可以在时钟信号具有较高占空比的前提下确保输出正确。由于时钟信号具有较高的占空比，因此，所述栅极驱动电路能够为像素单元进行充分充电，提高显示装置的显示稳定性。
作为本公开的第二个方面，提供一种显示装置，所述显示装置包括显示面板和栅极驱动电路，所述显示面板包括多条栅线，其中，所述栅极驱动电路为本公开所提供的上述栅极驱动电路，所述栅极驱动电路的多个移位寄存单元的输出端与多条栅线一一对应地连接。
图12是根据本公开实施例的显示装置的示意图。如图12所示，在一些实施例中，显示装置包括显示面板100和栅极驱动电路，所述栅极驱动电路包括第一移位寄存单元组和第二移位寄存单元组，其分别设置在围绕显示面板100的显示区域DA的周边区域PA中，且设置在显示区域DA的相对两侧。所述显示面板包括顺序排列的多条栅线GL，并且所述栅极驱动电路的多个移位寄存单元的输出端分别与所述多条栅线一一对应地相连。
如上文中所述，使用了所述栅极驱动电路之后，允许时钟信号具有较高占空比，从而可以为像素单元进行充分充电，提高显示装置的显示稳定性。
作为本公开的第三个方面，提供一种显示装置的驱动方法，其中，所述时钟信号包括向第一时钟信号线提供的第一时钟信号和向第二时钟信号线提供的第二时钟信号，所述驱动方法包括：
按照各个第一移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第一移位寄存单元子组中的各个第一个移位寄存单元提供多个第一初始控制信号；
按照各个第二移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第二移位寄存单元子组中的各个第一个移位寄存单元提供多个第二初始控制信号；
按照第一移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第一移位寄存单元组中的各个移位寄存单元提供第一时钟信号；
按照第二移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第二移位寄存单元组中的各个移位寄存单元提供第二时钟信号。
在一些实施例中，输入至相邻两级移位寄存单元的时钟信号中，前一级移位寄存单元的时钟信号比后一级移位寄存单元的时钟信号提前T/n；
最先输入的第一初始控制信号比最先输入的第二初始控制信号提前T/n，时间上相邻的两个第一初始控制信号之间的时间间隔为2T/n，时间上相邻的两个第二初始控制信号之间的时间间隔为2T/n。T为时钟信号在一个周期中处于第一电平的持续时间。
在一些实施例中，所述第一时钟信号的占空比在42％至50％之间，所述第二时钟信号的占空比在42％至50％之间。
上文中已经结合栅极驱动电路对驱动方法的工作原理和有益效果进行了详细说明，这里不再赘述。
图7是本公开实施例和对比例中的栅极驱动电路的时序对比图。
这里，本公开实施例提供的栅极驱动电路包括第一时钟信号线组和第二时钟信号线组，第一时钟信号线组包括四条第一时钟信号线，分别为第一时钟信号线CLK1、第一时钟信号线CLK3、第一时钟信号线CLK5和第一时钟信号线CLK7。第二时钟信号线组包括第二时钟信号线CLK2、第二时钟信号线CLK4、第二时钟信号线CLK6和第二时钟信号线CLK8。如图3和图4中所示，第一移位寄存单元组中的各个 移位寄存单元按照如下规律进行级联：第A级移位寄存单元的输出端与第A+4级移位寄存单元的输入端电连接，其中，A为移位寄存单元对应的栅线的行数，且A为奇数，A＝1,3，…。第A级移位寄存单元的复位端与第A+5级移位寄存单元的输出端电连接。第二移位寄存单元组中的各个移位寄存单元按照如下规律进行级联：第A+1级移位寄存单元的输出端与第A+5级移位寄存单元的信号输入端电连接，第A+1级移位寄存单元的复位端与第A+6级移位寄存单元的输出端电连接。第一时钟信号的时序以及第二时钟信号的时序均参见图5。
与本公开实施例相比，对比例中的栅极驱动电路的区别在于：第A级移位寄存单元的复位端与第A+4级移位寄存单元的输出端相连，第A+1级移位寄存单元的复位端与第A+5级移位寄存单元的输出端相连，例如，如图1和图2所示。
以与第五行栅线相连接的第五级移位寄存单元为例，根据图1和图2所示的栅极驱动电路，其复位端原本从第九级移位寄存单元接收复位信号，而根据图3和图4所示的本公开实施例提供的栅极驱动电路，其复位端从第十级移位寄存单元接收复位信号。根据实验，本公开的移位寄存电路的复位信号相比对比例而言延迟了T/4，从而使得能够在设置更大的时钟信号占空比的情况下能够正常输出。
图8是对比例的栅极驱动电路中一级移位寄存单元的输出信号、复位信号以及时钟信号的模拟结果，其中，时钟信号的占空比为42％。
如图8所示，输出端Output输出的输出信号与复位端reset接收到的复位信号之间存在时间间隔，在复位阶段，移位寄存单元没有输出。
图9中所示的是时钟信号的占空比为50％时，对比例所提供的栅极驱动电路的其中一级移位寄存单元的输出波形。如图9所示，输出端Output输出的输出信号下降沿与复位端reset接收到的复位信号的上升沿之间重叠，在复位阶段，移位寄存单元的输出端电位受到复位信号的影响，并没有被有效拉低，从而出现了输出错误。
图10中所示的是时钟信号的占空比为50％时，本公开实施例所提供的栅极驱动电路中其中一级移位寄存单元的输出波形。通过图 10可知，复位端reset接收到的复位信号的上升沿与输出端Output输出的输出信号的下降沿之间存在时间间隔，因此，复位信号不会对输出端的电位造成影响，进而确保正确的输出。
图11是对比例中用到的复位信号的波形图以及本公开实施例所提供的栅极驱动电路中用到的复位信号的波形图。
在栅极驱动电路中，复位信号对移位寄存单元的输出端电压的影响如下式所示：
Figure PCTCN2018115206-appb-000001
其中，ΔV p为移位寄存单元的输出端在单位时间内的电压跳变大小；
ΔV d为复位信号在单位时间内的电压跳变大小；
C c为移位寄存单元的输出端与复位信号的耦合电容；
ΣC为移位寄存单元的输出端与所有信号的耦合电容之和。
如图11所示，在本公开实施例中复位信号的上升时间Tr比对比例中复位信号的上升时间Tr大，在本公开实施中复位信号的下降时间Tf比对比例中复位信号的下降时间Tf大，即，在本申请中，复位信号在单位时间内的电压跳变ΔV d更小，因此，本公开实施例所提供的移位寄存单元的输出端在单位时间内的电压跳变ΔV p也更小。因此，本公开实施例所提供的移位寄存单元输出更加稳定。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种用于显示面板的栅极驱动电路，所述显示面板包括顺序排列的多行栅线，所述栅极驱动电路包括多个移位寄存单元，所述多个移位寄存单元被划分为第一移位寄存单元组和第二移位寄存单元组，所述第一移位寄存单元组配置为为所述显示面板中奇数行栅线提供扫描信号，所述第二移位寄存单元组配置为为所述显示面板中偶数行栅线提供扫描信号，
    所述第一移位寄存单元组包括多个第一移位寄存单元子组，每个第一移位寄存单元子组包括n个移位寄存单元，同第A行栅线电连接的第A级移位寄存单元的输出端与同第A+n行栅线电连接的第A+n级移位寄存单元的输入端电连接，A为大于等于1的奇数，n大于2；
    所述第二移位寄存单元组包括多个第二移位寄存单元子组，每个第二移位寄存单元子组包括n个移位寄存单元，同第A+1行栅线电连接的第A+1级移位寄存单元的输出端与同第A+1+n行栅线电连接的第A+1+n级移位寄存单元的输入端电连接；并且
    第A级移位寄存单元的复位端与同第A+a+n行栅线电连接的第A+a+n级移位寄存单元的输出端电连接，第A+1级移位寄存单元的复位端与同第A+a+n+1行栅线电连接的第A+a+n+1级移位寄存单元的输出端电连接，其中，a为小于n/2的自然数。
  2. 根据权利要求1所述的栅极驱动电路，其中，n为大于2的偶数。
  3. 根据权利要求2所述的栅极驱动电路，其中，n为4。
  4. 根据权利要求1至3中任意一项所述的栅极驱动电路，其中，a为1。
  5. 根据权利要求1至4中任一项所述的栅极驱动电路，其中， 所述显示面板包括显示区域和围绕所述显示区域的周边区域，所述第一移位寄存单元组和所述第二移位寄存单元组分别设置在所述显示面板的相对两侧且设置在所述周边区域中。
  6. 根据权利要求1至5中任意一项所述的栅极驱动电路，其中，
    所述移位寄存单元包括输入子电路、上拉子电路、下拉子电路、下拉控制子电路和复位子电路；
    所述输入子电路的控制端与所述移位寄存单元的输入端相连，所述输入子电路的输入端与第一电平信号端相连，所述输入子电路的输出端与所述上拉子电路的控制端相连，所述输入子电路配置为当所述输入子电路的输入端接收到第一电平信号时，将该输入子电路的输入端和输出端导通；
    所述上拉子电路的输入端与时钟信号线相连，所述上拉子电路的输出端与所述移位寄存单元的输出端相连，所述上拉子电路配置为当所述上拉子电路的控制端接收到第一电平信号时，所述上拉子电路的输入端与输出端导通；
    所述下拉控制子电路的第一输入端与第二电平信号端相连，所述下拉控制子电路的第二输入端与所述第三电平信号端相连，所述第二电平信号端提供的第二电平信号的电压绝对值大于所述第一电平信号端提供的第一电平信号的电压绝对值，且所述第二电平信号与所述第一电平信号极性相同，所述第三电平信号端提供的第三电平信号与所述第二电平信号端提供的第二电平信号极性相反，所述下拉控制子电路的控制端与所述上拉子电路的控制端相连，所述下拉控制子电路的第一输出端与所述下拉子电路的控制端相连，所述下拉控制子电路的第二输出端与上拉子电路的控制端相连，所述下拉控制子电路配置为当所述下拉控制子电路的控制端接收到第一电平信号时，下拉控制子电路的第二输入端与下拉控制子电路的第一输出端导通；
    所述下拉子电路的输入端与第三电平信号端相连，所述下拉子电路的输出端与所述移位寄存单元的输出端相连，所述下拉子电路配置为当所述下拉子电路的控制端接收到第一电平信号时，下拉子电路 的输入端和输出端导通；
    所述复位子电路的控制端与所述移位寄存单元的复位端相连，所述复位子电路的输入端与第三电平信号端相连，所述复位子电路的输出端与所述上拉子电路的控制端相连，所述复位子电路配置为当所述复位子电路的控制端接收到第一电平信号时，所述复位子电路的输入端与所述复位子电路的输出端导通。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述上拉子电路包括上拉晶体管和存储电容器，所述上拉晶体管的栅极与所述上拉子电路的控制端相连，所述上拉晶体管的第一极与所述上拉子电路的输入端相连，所述上拉晶体管的第二极与所述上拉子电路的输出端相连，所述上拉晶体管配置当所述上拉晶体管的栅极接收到第一电平信号时，所述上拉晶体管的第一极和第二极导通；
    所述存储电容器的第一端与所述上拉晶体管的栅极相连，所述存储电容器的第二端与所述上拉晶体管的第二极相连。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述下拉子电路包括下拉晶体管，所述下拉晶体管的栅极与所述下拉子电路的控制端相连，所述下拉晶体管的第一极与所述下拉子电路的输入端相连，所述下拉晶体管的第二极与所述下拉子电路的输出端相连。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述下拉控制子电路包括多个下拉控制晶体管，所述多个下拉控制晶体管包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制晶体管和第六下拉控制晶体管，
    所述第一下拉控制晶体管的栅极和第一极均与所述第二电平信号端相连，所述第一下拉控制晶体管的第二极与第二下拉控制晶体管的栅极相连；
    所述第二下拉控制晶体管的第一极与所述第二电平信号端相连，所述第二下拉控制晶体管的第二极与所述下拉控制子电路的第一输 出端相连；
    所述第三下拉控制晶体管的栅极与所述上拉子电路的控制端相连，所述第三下拉控制晶体管的第一极与所述第三电平信号端相连，所述第三下拉控制晶体管的第二极与所述下拉控制子电路的第一输出端相连；
    所述第四下拉控制晶体管的栅极与所述第三下拉控制晶体管的栅极相连，所述第四下拉控制晶体管的第一极与所述第三电平信号端相连，所述第四下拉控制晶体管的第二极与所述第一下拉控制晶体管的第二极相连；
    所述第五下拉控制晶体管的栅极与所述下拉控制子电路的第一输出端相连，所述第五下拉控制晶体管的第一极与所述第三电平信号端相连，所述第五下拉控制晶体管的第二极与所述下拉控制子电路的第二输出端相连；
    所述第六下拉控制晶体管的栅极与控制信号端相连，所述第六下拉控制晶体管的第一极与所述第三电平信号端相连，所述第六下拉控制晶体管的第二极与所述移位寄存单元的输出端相连；
    所述多个下拉控制晶体管中的每一个配置为当所述多个下拉控制晶体管中的相应一个下拉控制晶体管的栅极接收到第一电平信号时，所述相应一个下拉控制晶体管的第一极和第二极导通。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述复位子电路包括复位晶体管，所述复位晶体管的栅极与所述复位子电路的控制端相连，所述复位晶体管的第一极与参考信号端相连，所述复位晶体管的第二极与所述上拉子电路的控制端相连。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述输入子电路包括输入晶体管，所述输入晶体管的栅极与所述输入子电路的控制端相连，所述输入晶体管的第一极与所述输入子电路的输入端相连，所述输入晶体管的第二极与所述上拉子电路的控制端相连，所述输入晶体管配置为当所述输入晶体管的栅极接收到第一电平信号时，将输 入晶体管所述的第一极和第二极导通。
  12. 一种显示装置，包括显示面板和栅极驱动电路，所述显示面板包括多条栅线，所述栅极驱动电路为权利要求1至11中任意一项所述的栅极驱动电路，所述栅极驱动电路的多个移位寄存单元的输出端分别与所述多条栅线一一对应地相连。
  13. 一种显示装置的驱动方法，所述显示装置包括显示面板和栅极驱动电路，
    所述显示面板包括顺序排列的多行栅线；
    所述栅极驱动电路包括：
    多个移位寄存单元，所述多个移位寄存单元被划分为第一移位寄存单元组和第二移位寄存单元组，所述第一移位寄存单元组配置为为所述显示面板中奇数行栅线提供扫描信号，所述第二移位寄存单元组配置为为所述显示面板中偶数行栅线提供扫描信号，
    所述第一移位寄存单元组包括多个第一移位寄存单元子组，每个第一移位寄存单元子组包括n个移位寄存单元，同第A行栅线电连接的第A级移位寄存单元的输出端与同第A+n行栅线电连接的第A+n级移位寄存单元的输入端电连接，A为大于等于1的奇数，n大于2；
    所述第二移位寄存单元组包括多个第二移位寄存单元子组，每个第二移位寄存单元子组包括n个移位寄存单元，同第A+1行栅线电连接的第A+1级移位寄存单元的输出端与同第A+1+n行栅线电连接的第A+1+n级移位寄存单元的输入端电连接；并且
    第A级移位寄存单元的复位端与同第A+a+n行栅线电连接的第A+a+n级移位寄存单元的输出端电连接，第A+1级移位寄存单元的复位端与同第A+a+n+1行栅线电连接的第A+a+n+1级移位寄存单元的输出端电连接，其中，a为小于n/2的自然数；
    所述驱动方法包括：
    按照各个第一移位寄存单元子组中的各个第一个移位寄存单元 的级数的先后顺序依次向各个第一移位寄存单元子组中的各个第一个移位寄存单元提供多个第一初始控制信号；
    按照各个第二移位寄存单元子组中的各个第一个移位寄存单元的级数的先后顺序依次向各个第二移位寄存单元子组中的各个第一个移位寄存单元提供多个第二初始控制信号；
    按照第一移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第一移位寄存单元组中的各个移位寄存单元提供第一时钟信号；
    按照第二移位寄存单元组中的各个移位寄存单元的级数的先后顺序依次向第二移位寄存单元组中的各个移位寄存单元提供第二时钟信号。
  14. 根据权利要求13所述的显示装置的驱动方法，其中，输入至相邻两级移位寄存单元的时钟信号中，前一级移位寄存单元的时钟信号比后一级移位寄存单元的时钟信号提前T/n；
    最先输入的第一初始控制信号比最先输入的第二初始控制信号提前T/n，时间上相邻的两个第一初始控制信号之间的时间间隔为2T/n，时间上相邻的两个第二初始控制信号之间的时间间隔为2T/n，
    其中T为时钟信号在一个周期中处于第一电平的持续时间。
  15. 根据权利要求13或14所述的显示装置的驱动方法，其中，所述第一时钟信号的占空比在42％至50％之间，所述第二时钟信号的占空比在42％至50％之间。
  16. 根据权利要求13至15所述的显示装置的驱动方法，其中，n为大于2的偶数。
  17. 根据权利要求16所述的显示装置的驱动方法，其中，n为4。
  18. 根据权利要求17所述的显示装置的驱动方法，其中，a为1。
PCT/CN2018/115206 2017-11-16 2018-11-13 栅极驱动电路、显示装置及其驱动方法 WO2019096120A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18877527.4A EP3712880B1 (en) 2017-11-16 2018-11-13 Gate driver circuit, display device and driving method therefor
US16/474,801 US10885825B2 (en) 2017-11-16 2018-11-13 Gate driving circuit, dispaly apparatus and driving method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711137684.X 2017-11-16
CN201711137684.XA CN109801577B (zh) 2017-11-16 2017-11-16 栅极驱动电路、显示装置及其驱动方法

Publications (1)

Publication Number Publication Date
WO2019096120A1 true WO2019096120A1 (zh) 2019-05-23

Family

ID=66539380

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/115206 WO2019096120A1 (zh) 2017-11-16 2018-11-13 栅极驱动电路、显示装置及其驱动方法

Country Status (4)

Country Link
US (1) US10885825B2 (zh)
EP (1) EP3712880B1 (zh)
CN (1) CN109801577B (zh)
WO (1) WO2019096120A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022221985A1 (zh) * 2021-04-19 2022-10-27 京东方科技集团股份有限公司 显示面板和显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108364618B (zh) * 2018-03-14 2021-01-01 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN112530332A (zh) * 2019-09-18 2021-03-19 群创光电股份有限公司 电子装置
CN111292664B (zh) * 2020-02-20 2022-08-09 合肥京东方卓印科技有限公司 栅极驱动电路、显示面板及其显示方法
CN111354296B (zh) * 2020-04-16 2023-01-24 京东方科技集团股份有限公司 显示面板、显示装置
CN113853642A (zh) 2020-04-28 2021-12-28 京东方科技集团股份有限公司 显示面板、驱动方法及显示装置
CN112233630B (zh) * 2020-10-15 2021-11-02 Tcl华星光电技术有限公司 栅极驱动电路和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221041A1 (en) * 2005-03-31 2006-10-05 Lg.Philips Lcd Co., Ltd. Gate driver and display device having the same
US20060221042A1 (en) * 2005-03-31 2006-10-05 Lg Philips Lcd.Co., Ltd Gate driver and display device having the same
CN103236273A (zh) * 2013-04-16 2013-08-07 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN104464600A (zh) * 2014-12-26 2015-03-25 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN104505046A (zh) * 2014-12-29 2015-04-08 上海天马微电子有限公司 一种栅极驱动电路、阵列基板、显示面板和显示装置
CN104616618A (zh) * 2015-03-09 2015-05-13 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100544139B1 (ko) 2004-03-10 2006-01-23 삼성에스디아이 주식회사 디스플레이 패널구동장치
CN103426414B (zh) * 2013-07-16 2015-12-09 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
KR102135928B1 (ko) * 2013-12-31 2020-07-20 엘지디스플레이 주식회사 쉬프트 레지스터 및 그 제조방법, 그리고 쉬프트 레지스터를 이용한 영상 표시장치
CN104992682B (zh) * 2015-07-03 2017-10-24 深圳市华星光电技术有限公司 一种扫描驱动电路
KR102541937B1 (ko) * 2015-12-29 2023-06-09 엘지디스플레이 주식회사 쉬프트 레지스터
CN106409211B (zh) * 2016-12-12 2019-06-07 上海天马微电子有限公司 一种栅极驱动电路、阵列基板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221041A1 (en) * 2005-03-31 2006-10-05 Lg.Philips Lcd Co., Ltd. Gate driver and display device having the same
US20060221042A1 (en) * 2005-03-31 2006-10-05 Lg Philips Lcd.Co., Ltd Gate driver and display device having the same
CN103236273A (zh) * 2013-04-16 2013-08-07 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN104464600A (zh) * 2014-12-26 2015-03-25 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN104505046A (zh) * 2014-12-29 2015-04-08 上海天马微电子有限公司 一种栅极驱动电路、阵列基板、显示面板和显示装置
CN104616618A (zh) * 2015-03-09 2015-05-13 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022221985A1 (zh) * 2021-04-19 2022-10-27 京东方科技集团股份有限公司 显示面板和显示装置

Also Published As

Publication number Publication date
US10885825B2 (en) 2021-01-05
EP3712880A1 (en) 2020-09-23
US20200005698A1 (en) 2020-01-02
CN109801577B (zh) 2022-07-19
CN109801577A (zh) 2019-05-24
EP3712880B1 (en) 2023-10-04
EP3712880A4 (en) 2021-08-18

Similar Documents

Publication Publication Date Title
WO2019096120A1 (zh) 栅极驱动电路、显示装置及其驱动方法
CN110808015B (zh) 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
CN108389539B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US10095058B2 (en) Shift register and driving method thereof, gate driving device
US10891913B2 (en) Shift register circuitry, gate driving circuit, and display device
US11295645B2 (en) Shift register and driving method thereof, gate driving circuit and display apparatus
TWI433459B (zh) 雙向移位暫存器
US11200860B2 (en) Shift register unit, gate driving circuit and driving method thereof
EP3217387A1 (en) Shift register unit, gate driving circuit and display device
EP2846332A1 (en) Shift register and display
WO2019200967A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
WO2016127589A1 (zh) 栅极驱动电路及其驱动方法、阵列基板、显示装置
EP3400593A1 (en) Shift register, driving method, and gate electrode drive circuit
JP2014063164A (ja) ゲート駆動回路、アレイ基板及び表示装置
CN110299116B (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN110648621B (zh) 移位寄存器及其驱动方法、栅极驱动电路及显示装置
CN110782940B (zh) 移位寄存单元、栅极驱动电路、阵列基板及显示装置
US11423823B2 (en) Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal
CN110689839B (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN110189681B (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示装置
CN111312136A (zh) 移位寄存器单元、扫描驱动电路、驱动方法和显示装置
CN114038439B (zh) 一种栅极驱动电路及驱动方法、阵列基板、显示装置
CN110534048B (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN108231032B (zh) 移位寄存器、栅极驱动电路、显示装置
CN114613341B (zh) 阵列栅极驱动单元、电路及其驱动方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18877527

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018877527

Country of ref document: EP

Effective date: 20200616