WO2020118876A1 - 一种tft驱动背板 - Google Patents

一种tft驱动背板 Download PDF

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Publication number
WO2020118876A1
WO2020118876A1 PCT/CN2019/072890 CN2019072890W WO2020118876A1 WO 2020118876 A1 WO2020118876 A1 WO 2020118876A1 CN 2019072890 W CN2019072890 W CN 2019072890W WO 2020118876 A1 WO2020118876 A1 WO 2020118876A1
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Prior art keywords
capacitor
insulating layer
notch
opening
hole
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English (en)
French (fr)
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赵加湘
程文锦
贾可然
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/637,796 priority Critical patent/US11177298B2/en
Publication of WO2020118876A1 publication Critical patent/WO2020118876A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT driving backplane.
  • the LTPS process is generally used to form the TFT (thin film transistor) drive backplane required for the OLED.
  • the commonly used drive circuit is shown in Figure 1 as the 7T1C drive circuit.
  • FIG. 2 it illustrates the local opening structure of the LTPS device commonly used in the current circuit design 7T1C drive circuit, including the first via 8, the second via 9, the third via 10, and the fourth via 11. Fifth via 12, sixth via 13, seventh via 14, and eighth via 15.
  • the first via hole 8 is used to connect the SD (secondary data line) and the capacitor lower plate 4 (GE1), and two holes need to be opened during the manufacturing process, the first opening The hole is made directly above the capacitor, and it is necessary to make a hole in the upper electrode plate 3 (GE2) of the capacitor. At the same time, after completing the formation of the ILD (insulating layer) film, another hole is formed to form the first hole 6, and the second hole 7 is located inside the first opening 6.
  • the ILD insulating layer
  • FIG. 3 The cross-sectional view is shown in FIG. 3, in order to connect the secondary data line (1SD) and the capacitor lower plate 5 during the manufacturing process, two holes need to be opened directly above the capacitor, and the first time the first insulating layer 2 (ILD) A hole is formed on the upper plate 3 of the capacitor.
  • the second hole 7 is located inside the first hole 6. The bottom of the second hole 7 is the upper surface of the upper plate 3 of the capacitor.
  • the width of the lower plate 5 of the capacitor is 12 ⁇ m
  • the long side of the lower plate 5 of the capacitor is 20 ⁇ m
  • the area of the lower plate 5 of the capacitor is 12*20 ⁇ m2
  • the diameter of the first opening 6 is 6 ⁇ m
  • the diameter of the second opening 7 is 2 ⁇ m
  • the actual deviation distance (CD) between the first opening 6 and the second opening 7 is 2 ⁇ m.
  • the present invention proposes a TFT drive backplane, to solve the prior art for connecting the secondary data line and the lower plate of the capacitor to punch holes at the center of the capacitor, and requires two holes to be aligned, which requires precision for the photolithography process Extremely high, and the alignment deviation is easy to cause capacitor short circuit, product yield is low; at the same time improve the effective capacitor area loss caused by the photolithography process.
  • a TFT driving backplane which includes a secondary data line, a first insulating layer, a capacitor upper plate, a second insulating layer, and a capacitor lower plate in order from top to bottom.
  • a side of the capacitor superior board is provided with a notch, the notch is filled up by the first insulating layer, and the first insulating layer filling the notch is provided with a vertical downward extension until the capacitor The first via of the plate.
  • the notch is located at a corner of the upper plate of the capacitor.
  • the side length of the square is 3-6 ⁇ m.
  • the first insulating layer covers the upper plate of the capacitor, and the opening of the first via is located on the first insulating layer.
  • the diameter of the opening of the first via hole is 1-3 ⁇ m.
  • the diameter of the opening of the first via hole is 2 ⁇ m.
  • the secondary data line is electrically connected to the lower plate of the capacitor through the first via.
  • the diameter of the first via is smaller than the length of any side of the notch.
  • the invention proposes a TFT driving backplane, which moves the position where the secondary data line is connected to the lower plate of the capacitor to the upper plate of the non-capacitor, without the need to drill holes in the center of the capacitor, and does not require two holes to be aligned. It reduces the extremely high requirements for the alignment accuracy of the lithography process, and effectively avoids the two-hole alignment deviation that is easy to cause a capacitor short circuit and improves the product yield; at the same time, the design margin and one-way offset can avoid the capacitor short circuit. And increase the effective capacitance area.
  • FIG. 1 is a schematic diagram of a 7T1C drive circuit structure of a conventional TFT drive backplane
  • FIG. 2 is a schematic diagram of a partial opening structure of an LTPS device of a 7T1C drive circuit of a conventional TFT drive backplane;
  • FIG. 3 is a schematic view of the opening structure of a cross-sectional view of a conventional TFT drive backplane
  • FIG. 4 is a plan view of a hole structure of a plan view of a conventional TFT drive backplane
  • FIG. 5 is a plan view of a hole structure of a plan view of a TFT drive backplane according to an embodiment of the invention.
  • FIG. 6 is a cross-sectional view of the TFT driving backplane in the direction A-A of FIG. 4 according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a partial opening structure of an LTPS device of a 7T1C driving circuit of a TFT driving backplane according to an embodiment of the present invention.
  • Primary data line 2 first insulation layer, 3 capacitor upper plate, 4 second insulation layer,
  • an embodiment of the present invention provides a TFT drive backplane, which includes a secondary data line 1, a first insulating layer 2, a capacitor upper plate 3, and a second Insulation layer 4 and capacitor lower plate 5.
  • a TFT drive backplane which includes a secondary data line 1, a first insulating layer 2, a capacitor upper plate 3, and a second Insulation layer 4 and capacitor lower plate 5.
  • the side of the capacitor superior board is provided with a notch, the notch is filled up by the first insulating layer 2, and the first insulating layer 2 filling the notch is provided with a vertical downward extension until the The first via 8 of the lower plate 5 of the capacitor.
  • the notch is located at a corner of the upper plate 3 of the capacitor, or may be located at a certain edge of the upper plate 3 of the capacitor.
  • the notch is rectangular, preferably square.
  • the arrangement of the square can keep the deviation distance between the first via 8 and each side consistent.
  • the side length of the square is 3-6 ⁇ m, preferably the side length of the square is 4 ⁇ m.
  • the first insulating layer 2 covers the upper plate 3 of the capacitor, and the opening of the first via 8 is located on the first insulating layer 2.
  • the diameter of the opening of the first via 8 is 1 to 3 ⁇ m, preferably the diameter of the opening of the first via 8 is 2 ⁇ m.
  • the secondary data line 1 is electrically connected to the lower capacitor plate 5 through the first via 8.
  • the diameter of the first via 8 is smaller than the length of any side of the notch.
  • the first via 8 is avoided from the overlapping place of the capacitors, and the first via 8 is formed once by a photolithography process, and the design does not form two overlapping opening alignments.
  • the process requirements of the process (PH) and the etching process (Etch) are simple. Only the existing technology is required to offset the opening of the inorganic insulating layer to the missing angle of the upper left corner of the upper plate 3 of the capacitor and set a certain margin to ensure It will not cause a capacitor short circuit due to two alignments of the photolithography process, thereby improving the performance and yield of the product.
  • the width W of the lower plate 5 of the capacitor is 12 ⁇ m
  • the long side L of the lower plate 5 of the capacitor is 20 ⁇ m
  • the area of the lower plate 5 of the capacitor is 12*20 ⁇ m2
  • the missing corner of the upper left corner of the upper plate 3 of the capacitor is square, square
  • the side length is 4 ⁇ m
  • the diameter of the first via 8 is 2 ⁇ m, so as to ensure that the opening is within the range of 2 ⁇ m to meet the production requirements.
  • FIG. 7 illustrates a schematic view of a partial opening structure of the LTPS device of the TFT driving backplane 7T1C driving circuit of an embodiment of the present invention.
  • the lower plate 5 of the capacitor corresponds to the corresponding structure in the prior art.
  • the change of the present invention is to leave a gap at the corner of the upper plate 3 of the capacitor, which is required for subsequent ILD hole connection.
  • the first via 8 forms a capacitor lower plate 5 through the gap.
  • the exposure margin is adjusted to the upper left of the image, and the margin of the hole can also be set to the upper left by design to ensure that the hole will not win the exposure short-circuit caused by the capacitive offset, and can be improved Capacitor area.
  • Subsequent design of other vias, such as second via 9, third via 10, fourth via 11, fifth via 12, sixth via 13, seventh via 14, eighth via 15, etc. It can be kept unchanged according to the original structure. In order to avoid unnecessary repetition, it will not be repeated here.
  • the present invention proposes a TFT drive backplane, which moves the position where the source-drain electrode is connected to the lower plate of the capacitor to the upper plate of the non-capacitor, without drilling holes in the center of the capacitor.
  • Two opening alignments are required, which reduces the extremely high accuracy of the alignment of the lithography process, and effectively avoids the deviation of the two opening alignments that is easy to cause a capacitor short circuit and improves the product yield; at the same time, through the design margin and unidirectional Offset can avoid capacitor short circuit and increase the effective capacitor area.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种TFT驱动背板，从上至下依次包括次数据线（1）、第一绝缘层（2）、电容上极板（3）、第二绝缘层（4）和电容下极板（5），其中所述电容上极板（3）的侧部设置有一缺口，所述缺口处被所述第一绝缘层（2）向上填充，并且填充所述缺口处的第一绝缘层（2）设置有一竖直向下延伸直至所述电容下极板（5）的第一过孔（8）。通过将次数据线（1）与电容下极板（5）连接的位置移开至非电容上极板（3）处，不需在电容中心位置打孔，不需要两次开孔对位，降低了光刻工艺的对位精度要求，且有效避免两次开孔对位偏差容易造成电容短路，提高了产品良率；同时通过设计余量及单向偏移，可避免电容短路，并增加有效电容面积。

Description

一种TFT驱动背板 技术领域
本发明涉及显示技术领域，特别涉及一种TFT驱动背板。
 背景技术
柔性OLED因其广色域、高对比度、大视角、反应速率快、轻薄等优势而逐渐呈现出取代TFT-LCD（薄膜晶体管液晶显示屏）的趋势。在手机、手表、Pad等应用领域，随着消费者对大屏的钟爱，屏幕的屏占比要求越来越高。OLED最具有明显的优势是可以通过PI制程工艺形成柔性的屏体。
对于主动有机发光二极体（AMOLED）来说，一般采用LTPS工艺形成OLED所需的TFT（薄膜晶体管）驱动背板，常用的驱动电路如图1所示为7T1C驱动电路。
如图2所示，其图示了目前业界常用的电路设计7T1C驱动电路LTPS器件的局部开孔结构，包括第一过孔8、第二过孔9、第三过孔10、第四过孔11、第五过孔12、第六过孔13、第七过孔14、第八过孔15。
其中以第一过孔8为例，所述第一过孔8用于连接SD（次数据线）和电容下极板4（GE1），在制程过程中需要开两次孔，第一次开孔是在电容正上方进行，需要在电容上极板3（GE2）上开孔，同时在完成ILD（绝缘层）成膜后再一次开孔以形成第一开孔6，而第二开孔7位于第一开孔6的内部。
其截面图如图3所示，为连接次数据线（1SD）和电容下极板5在制程过程中需要在电容正上方开两次孔，第一次需要将第一绝缘层2（ILD）及电容上极板3开孔，第二开孔7位于第一开孔6的内部，第二开孔7孔底为电容上极板3上表面。由于需要开两次孔，如果第二开孔7与第一开孔6对位出现微小偏差，将会导致电容下极板5和电容上极板3的将会形成短路，因此对于光刻工艺（PH）和蚀刻工艺（Etch）要求极高，且第一开孔6的直径设计要求一定足够大，而第二开孔7尽量小，如果第一开孔6的孔太大，造成电容面积减小；在改电路设计中，只有第一开孔6需要两次对位，因此对PH和Etch开孔对位的精度要求极为严格。
如图4所示，设计电容下极板5宽边为12μm，电容下极板5长边为20μm，电容下极板5的面积为12*20μm2，第一开孔6的直径为6μm，第二开孔7的直径为2μm，实际第一开孔6和第二开孔7之间的偏差距离（CD）为2μm，当PH覆盖大于1.5μm后，可能就造成电容短路。
 技术问题
本发明提出一种TFT驱动背板，以解决现有技术为连接次数据线和电容下极板在电容中心位置打孔，且需要两次开孔对位，对光刻工艺的对位精度要求极高，且对位偏差容易造成电容短路，产品良率低；同时改善因光刻工艺造成的有效电容面积损失。
 技术解决方案
为了实现上述目的，本发明采用了如下的技术方案：
本发明的一实施例中，提供一种TFT驱动背板，从上至下依次包括次数据线、第一绝缘层、电容上极板、第二绝缘层和电容下极板。其中所述电容上级板的侧部设置有一缺口，所述缺口处被所述第一绝缘层向上填充，并且填充所述缺口处的第一绝缘层设置有一竖直向下延伸直至所述电容下极板的第一过孔。
进一步的，其中所述缺口位于所述电容上极板边角处。
进一步的，其中所述缺口为正方形。
进一步的，其中所述正方形的边长为3~6μm。
进一步的，其中所述正方形的边长为4μm。
进一步的，其中所述第一绝缘层覆盖所述电容上极板，所述第一过孔的开口位于所述第一绝缘层上。
进一步的，其中所述第一过孔的开口的直径为1~3μm。
进一步的，其中所述第一过孔的开口的直径为2μm。
进一步的，其中所述次数据线通过所述第一过孔与所述电容下极板电连接。
进一步的，其中所述第一过孔的直径小于所述缺口的任一边长。
 有益效果
本发明提出一种TFT驱动背板，将次数据线与电容下极板连接的位置移开至非电容上极板处，不需在电容中心位置打孔，不需要两次开孔对位，降低了光刻工艺的对位精度要求极高，且有效避免两次开孔对位偏差容易造成电容短路，提高了产品良率；同时通过设计余量及单向偏移，可避免电容短路，并增加有效电容面积。
 附图说明
图1为现有技术TFT驱动背板7T1C驱动电路结构示意图；
图2为现有技术TFT驱动背板7T1C驱动电路LTPS器件局部开孔结构示意图；
图3为现有技术TFT驱动背板截面图开孔结构示意图；
图4为现有技术TFT驱动背板平面图开孔结构俯视图；
图5为本发明一实施例TFT驱动背板平面图开孔结构俯视图；
图6为本发明一实施例TFT驱动背板在图4的A-A方向截面图；
图7为本发明一实施例TFT驱动背板7T1C驱动电路LTPS器件局部开孔结构示意图。
图中部件标识如下：
1次数据线、2第一绝缘层、3电容上极板、4第二绝缘层、
5电容下极板、6第一开孔、7第二开孔、8第一过孔、
9第二过孔、10第三过孔、11第四过孔、12第五过孔、
13第六过孔、14第七过孔、15第八过孔。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参阅图5、图6所示，本发明的一实施例中提供一种TFT驱动背板，从上至下依次包括次数据线1、第一绝缘层2、电容上极板3、第二绝缘层4和电容下极板5。其中所述电容上级板的侧部设置有一缺口，所述缺口处被所述第一绝缘层2向上填充，并且填充所述缺口处的第一绝缘层2设置有一竖直向下延伸直至所述电容下极板5的第一过孔8。
其中所述缺口位于所述电容上极板3边角处，也可位于所述电容上极板3某一边上。
其中所述缺口为矩形，优选为正方形。正方形的设置方式可以让第一过孔8形成时与各边的偏差距离范围保持一致。
其中所述正方形的边长为3~6μm，优选所述正方形的边长为4μm。
其中所述第一绝缘层2覆盖所述电容上极板3，所述第一过孔8的开口位于所述第一绝缘层2上。
其中所述第一过孔8的开口的直径为1~3μm，优选所述第一过孔8的开口的直径为2μm。
其中所述次数据线1通过所述第一过孔8与所述电容下极板5电连接。
其中所述第一过孔8的直径小于所述缺口的任一边长。
本发明一优选实施例中，将第一过孔8避开电容重叠处，所述第一过孔8通过光刻工艺一次成型，该设计不会形成两次重叠开孔对位，对光刻工艺（PH）和蚀刻工艺（Etch）的工艺要求简单，仅需要现有技术在无机绝缘层开孔向电容上极板3左上角的缺失角方向偏移并设置一定的余量，就可以保障不会造成因光刻工艺两次对位造成电容短路，从而提升产品的性能和良率。例如设计电容下极板5宽边W为12μm，电容下极板5长边L为20μm，电容下极板5的面积为12*20μm2，电容上极板3左上角的缺失角为正方形，正方形边长为4μm，第一过孔8的直径为2μm，这样保障开孔在2μm余量范围就可满足成产要求，在不改变电容下极板5大小时电容有效面积为S=W*L=12*20=226μm2，即电容实际有效面积为226μm2；另外，现有技术设计第一开孔6的直径为6μm，第二开孔7的直径为2μm，现有技术电容有效面积为S=W*L-π（D/2）2=12*20-9π=211.72μm2，因此本发明的电容实际有效面积也显著增加。
请参阅图7所示，其图示了本发明一实施例TFT驱动背板7T1C驱动电路LTPS器件局部开孔结构示意图。其中电容下极板5与现有技术中的相应结构对应不变，本发明的改变之处在于将电容上极板3在角落位置处留出一缺口，其为后续ILD打孔连接所需，如图中所示，所述第一过孔8通过该缺口形成电容下极板5上。进一步的，其中在不同实施方式中，Etch ILD时将曝光的余量向图像的左上方调整余量，也可通过设计将该孔的余量设置向左上方，以保证该孔不会赢曝光对位偏移造成电容短路，同时可提高电容面积。后续其他过孔的设计，如第二过孔9、第三过孔10、第四过孔11、第五过孔12、第六过孔13、第七过孔14、第八过孔15等，可按原有的结构保持不变，为避免不必要的重复，此处不再赘述。
与现有技术的区别在于，本发明提出一种TFT驱动背板，将源漏电极与电容下极板连接的位置移开至非电容上极板处，不需在电容中心位置打孔，不需要两次开孔对位，降低了光刻工艺的对位精度要求极高，且有效避免两次开孔对位偏差容易造成电容短路，提高了产品良率；同时通过设计余量及单向偏移，可避免电容短路，并增加有效电容面积。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种TFT驱动背板，从上至下依次包括次数据线、第一绝缘层、电容上极板、第二绝缘层和电容下极板，其中所述电容上级板的侧部设置有一缺口，所述缺口处被所述第一绝缘层向上填充，并且填充所述缺口处的第一绝缘层设置有一竖直向下延伸直至所述电容下极板的第一过孔。
  2. 根据权利要求1所述的TFT驱动背板，其中，所述缺口位于所述电容上极板边角处。
  3. 根据权利要求1所述的TFT驱动背板，其中，所述缺口为正方形。
  4. 根据权利要求3所述的TFT驱动背板，其中，所述正方形的边长为3~6μm。
  5. 根据权利要求4所述的TFT驱动背板，其中，所述正方形的边长为4μm。
  6. 根据权利要求1所述的TFT驱动背板，其中，所述第一绝缘层覆盖所述电容上极板，所述第一过孔的开口位于所述第一绝缘层上。
  7. 根据权利要求6所述的TFT驱动背板，其中，所述第一过孔的开口的直径为1~3μm。
  8. 根据权利要求6所述的TFT驱动背板，其中，所述第一过孔的开口的直径为2μm。
  9. 根据权利要求1所述的TFT驱动背板，其中，所述次数据线通过所述第一过孔与所述电容下极板电连接。
  10. 根据权利要求1所述的TFT驱动背板，其中，所述第一过孔的直径小于所述缺口的任一边长。
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