WO2020113767A1 - Circuit goa et écran d'affichage - Google Patents

Circuit goa et écran d'affichage Download PDF

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Publication number
WO2020113767A1
WO2020113767A1 PCT/CN2019/071071 CN2019071071W WO2020113767A1 WO 2020113767 A1 WO2020113767 A1 WO 2020113767A1 CN 2019071071 W CN2019071071 W CN 2019071071W WO 2020113767 A1 WO2020113767 A1 WO 2020113767A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
signal
level
node
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PCT/CN2019/071071
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English (en)
Chinese (zh)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020113767A1 publication Critical patent/WO2020113767A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver on Array
  • Chinese full name: integrated gate drive circuit integrates the gate drive circuit on the array substrate of the display panel, so that the gate drive integrated circuit part can be omitted, from the material cost and The production process reduces the product cost in two aspects.
  • the existing GOA circuit has a short charging time and a heavy resistive load, which results in very serious distortion of the scan signal. That is, the value of the fall time of the scan signal at this stage is large, and the risk of wrong charging is high, which leads to poor display panel quality.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem of poor quality of the display panel due to the large value of the fall time of the scan signal, which causes a high risk of wrong charging.
  • An embodiment of the present application provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module and a bootstrap capacitance;
  • the pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal
  • the scan signal is output to the first node
  • the download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;
  • the pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential
  • the pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal;
  • the period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the phase difference between the first high-frequency clock signal and the second high-frequency clock signal is not zero;
  • the potential of the first reference low-level signal is less than the potential of the second reference low-level signal.
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
  • the download module includes: a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
  • the pull-up module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.
  • the pull-down module includes: a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the scan signal of the next stage; the source of the fourth transistor is electrically connected to the second high-frequency clock signal , The source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically Is connected to the scan signal of the current level.
  • the pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit, the first pull-down sustaining unit and the second pull-down sustaining unit are in the pull-down module After pulling down the potential of the first node and the potential of the current-level scanning signal, alternately maintaining the potential of the first node at the potential of the second reference low-level signal, and scanning the current level The potential of the signal is maintained at the potential of the first reference low-level signal.
  • the first pull-down sustaining unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate and source of the sixth transistor and the source of the seventh transistor are electrically connected to the first low-frequency clock signal; the drain of the sixth transistor and the gate of the seventh transistor And the drain of the eighth transistor; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor Connected; the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the first node; the source of the eighth transistor, the source of the ninth transistor, and all The source of the tenth transistor is electrically connected to the second reference low-level signal, and the source of the eleventh transistor is electrically connected to the first reference low-level signal; the tenth transistor The drain of is electrically connected to the first node; the drain of the eleventh transistor is electrically connected to the current scan signal;
  • the second pull-down maintenance unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are electrically connected to the second low-frequency clock signal; the drain of the twelfth transistor and the thirteenth transistor The gate of the transistor and the drain of the fourteenth transistor are electrically connected; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor and the The gate of the seventeenth transistor is electrically connected; the gate of the fourteenth transistor and the gate of the fifteenth transistor are both electrically connected to the first node; the source of the fourteenth transistor , The source of the fifteenth transistor and the source of the sixteenth transistor are both electrically connected to the second reference low-level signal; the source of the seventeenth transistor is electrically connected to the The first reference low-level signal; the drain of the sixteenth transistor is electrically connected to the first node; the drain of the seventeenth transistor is electrically connected to the current scan signal.
  • An embodiment of the present application further provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module and a self-sustaining module Lift capacitance
  • the pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal
  • the scan signal is output to the first node
  • the download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;
  • the pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential
  • the pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal.
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
  • the download module includes: a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
  • the pull-up module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.
  • the pull-down module includes: a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the scan signal of the next stage; the source of the fourth transistor is electrically connected to the second high-frequency clock signal , The source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically Is connected to the scan signal of the current level.
  • the pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit, the first pull-down sustaining unit and the second pull-down sustaining unit are in the pull-down module After pulling down the potential of the first node and the potential of the current-level scanning signal, alternately maintaining the potential of the first node at the potential of the second reference low-level signal, and scanning the current level The potential of the signal is maintained at the potential of the first reference low-level signal.
  • the gate and source of the sixth transistor and the source of the seventh transistor are electrically connected to the first low-frequency clock signal; the drain of the sixth transistor and the gate of the seventh transistor And the drain of the eighth transistor; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor Connected; the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the first node; the source of the eighth transistor, the source of the ninth transistor, and all The source of the tenth transistor is electrically connected to the second reference low-level signal, and the source of the eleventh transistor is electrically connected to the first reference low-level signal; the tenth transistor The drain of is electrically connected to the first node; the drain of the eleventh transistor is electrically connected to the current scan signal;
  • the second pull-down maintenance unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are electrically connected to the second low-frequency clock signal; the drain of the twelfth transistor and the thirteenth transistor The gate of the transistor and the drain of the fourteenth transistor are electrically connected; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor and the The gate of the seventeenth transistor is electrically connected; the gate of the fourteenth transistor and the gate of the fifteenth transistor are both electrically connected to the first node; the source of the fourteenth transistor , The source of the fifteenth transistor and the source of the sixteenth transistor are both electrically connected to the second reference low-level signal; the source of the seventeenth transistor is electrically connected to the The first reference low-level signal; the drain of the sixteenth transistor is electrically connected to the first node; the drain of the seventeenth transistor is electrically connected to the current scan signal.
  • the period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the first high-frequency clock signal and the second high-frequency clock The phase difference between the signals is not zero.
  • the potential of the first reference low-level signal is less than the potential of the second reference low-level signal.
  • An embodiment of the present application further provides a display panel including a GOA circuit
  • the GOA circuit includes: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, Pull-down module, pull-down maintenance module and bootstrap capacitor;
  • the pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal
  • the scan signal is output to the first node
  • the download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;
  • the pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential
  • the pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal.
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
  • the download module includes: a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
  • the pull-up module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.
  • the time when the first node is pulled down can be delayed ;
  • the phase difference between the second high-frequency clock signal and the first high-frequency clock signal due to the phase difference between the second high-frequency clock signal and the first high-frequency clock signal, during the pull-down module function makes the scan signal output low potential of the first high-frequency clock signal, so that the fall time of the scan signal can be reduced To reduce the risk of mischarging, thereby improving the display quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in a GOA circuit provided by an embodiment of the present application.
  • FIG. 3 is a signal timing diagram of a GOA unit in a GOA circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the transistors used in all the embodiments of this application may be thin film transistors, field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called a source electrode, and the other electrode is called a drain electrode. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a source, and the output end is a drain.
  • the transistors used in the embodiments of the present application may include two types of P-type transistors and/or N-type transistors, where the P-type transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type transistor is at The gate turns on when the gate is high, and turns off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • the GOA circuit provided by the embodiment of the present application includes multi-level cascaded GOA units.
  • Fig. 1 takes the cascaded n-4th level GOA unit, nth level GOA unit and N+4th level GOA unit as examples.
  • the scan signal output by the n-th stage GOA unit is at a high potential, which is used to turn on the transistor switch of each pixel in a row in the display panel, and perform the pixel electrode in each pixel through the data signal Charging; the nth stage transmission signal is used to control the operation of the n+4th stage GOA unit; when the n+4th stage GOA unit is working, the scan signal output by the n+4th stage GOA unit is high potential, while the nth The scan signal output by the stage GOA unit is low.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the GOA unit includes a pull-up control module 101, a download module 102, a pull-up module 103, a pull-down module 104, a pull-down maintenance module 105, and a bootstrap capacitor Cb.
  • the pull-up control module 101 is connected to the upper-level transmission signal ST (n-4) and the upper-level scanning signal G (n-4), and is electrically connected to the first node Q (n), used for Under the control of the upper stage transmission signal ST (n-4), the upper stage scanning signal G (n-4) is output to the first node Q (n).
  • the download module 102 is connected to the first high-frequency clock signal CK1 and is electrically connected to the first node Q(n), and is used to output the current stage transmission signal ST under the potential control of the first node Q(n) (N).
  • the pull-up module 103 is connected to the first high-frequency clock signal CK1, and is electrically connected to the first node Q(n), and is used to output the current scan signal G(( n).
  • the pull-down module 104 is connected to the next-level scan signal G(n+4), the second high-frequency clock signal CK2, and the first reference low-level signal VSSG, and is electrically connected to the first node Q(n) and the local node
  • the level scan signal G(n) is used to output the high potential of the second high-frequency clock signal CK2 to the first node Q(n) under the control of the next level scan signal G(n+4).
  • the potential of the scan signal G(n) reaches the low potential of the first high-frequency clock signal CK1.
  • the pull-down maintenance module 105 is connected to the first low-frequency clock signal LC1, the second low-frequency clock signal LC2, the first reference low-level signal VSSG and the second reference low-level signal VSSQ, and is electrically connected to the first node Q ( n) and the current scan signal G(n), used to pull down the potential of the first node Q(n) and the potential of the current scan signal G(n) in the pull-down module 104 Maintain the potential of the second reference low-level signal VSSQ, and maintain the potential of the current-level scan signal G(n) at the potential of the first reference low-level signal VSSG.
  • one end of the bootstrap capacitor Cb is electrically connected to the first node Q(n), and the other end of the bootstrap capacitor Cb is electrically connected to the scan signal G(n) of the current stage.
  • the difference between the GOA circuit provided by the embodiment of the present application and the existing GOA circuit is that the GOA circuit of the embodiment of the present application is connected to the second high-frequency clock signal CK2 at the pull-down module 104 by the first high
  • the phase difference between the high-frequency clock signal CK1 and the second high-frequency clock signal CK2 causes the current scan signal G(n) to output the low potential of the first high-frequency clock signal CK1 during the action of the pull-down module 104, thereby reducing the cost
  • the fall time of the level scan signal G(n) reduces the risk of mischarging and further improves the display quality of the display panel.
  • the pull-up control module 101 includes: a first transistor T1; the gate of the first transistor T1 is electrically connected to the previous stage signal ST(n-4), the first The source of the transistor T1 is electrically connected to the scan signal G(n-4) of the previous stage, and the drain of the first transistor T1 is electrically connected to the first node Q(n).
  • the download module 102 includes: a first transistor T2; the gate of the first transistor T2 is electrically connected to the first node Q(n), and the source of the first transistor T2 is electrically It is electrically connected to the first high-frequency clock signal CK1, and the drain of the third transistor T3 is electrically connected to the current stage signal ST(n).
  • the pull-up module 103 includes: a third transistor T3; the gate of the third transistor T3 is electrically connected to the first node Q(n), and the source of the third transistor T3 is electrically Is connected to the first high-frequency clock signal CK1, and the drain of the third transistor T3 is electrically connected to the scan signal G(n) of the current stage.
  • the pull-down module 104 includes: a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are electrically connected to the next stage Scan signal G(n+4); the source of the fourth transistor T4 is electrically connected to the second high-frequency clock signal CK2, and the source of the fifth transistor T5 is electrically connected to the first reference low-level signal VSSG; the fourth The drain of the transistor T4 is electrically connected to the first node Q(n), and the drain of the fifth transistor T5 is electrically connected to the scan signal G(n) of the current stage.
  • the pull-down maintenance module 105 includes a first pull-down maintenance unit 1051 and a second pull-down maintenance unit 1052.
  • the first pull-down maintenance unit 1051 and the second pull-down maintenance unit 1052 are in the pull-down module 104. After pulling down the potential of the first node Q(n) and the potential of the current scanning signal G(n), the potential of the first node Q(n) is alternately maintained at the potential of the second reference low-level signal VSSQ, and the The potential of the scan signal G(n) at this stage is maintained at the potential of the first reference low-level signal VSSG.
  • the first pull-down sustaining unit 1051 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11; a gate and a source of the sixth transistor T6 And the source of the seventh transistor T7 is electrically connected to the first low-frequency clock signal LC1; the drain of the sixth transistor T6, the gate of the seventh transistor T7 and the drain of the eighth transistor T8; the seventh transistor The drain of T7, the drain of the ninth transistor T9, the gate of the tenth transistor T10, and the gate of the eleventh transistor T11 are electrically connected; the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are all electrically Connected to the first node Q(n); the source of the eighth transistor T8, the source of the ninth transistor T9 and the source of the tenth transistor T10 are all electrically connected to the second reference low level signal VSSQ, the tenth The source of a transistor T11 is electrically connected to
  • the second pull-down sustaining unit 1052 includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17; a twelfth transistor T12
  • the gate, the source, and the source of the thirteenth transistor T13 are electrically connected to the second low-frequency clock signal LC2; the drain of the twelfth transistor T12, the gate of the thirteenth transistor T13, and the fourteenth transistor T14
  • the drain is electrically connected; the drain of the thirteenth transistor T13, the drain of the fifteenth transistor T15, the gate of the sixteenth transistor T16, and the gate of the seventeenth transistor T17; the fourteenth transistor T14 Of the gate and the gate of the fifteenth transistor T15 are electrically connected to the first node Q(n); the source of the fourteenth transistor T14, the source of the fifteenth transistor T15 and the source of the sixteenth transistor T16
  • the electrodes are
  • FIG. 2 and FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the polarities of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite.
  • the period of the first high-frequency clock signal CK1 is the same as the period of the second high-frequency clock signal CK2, and the phase difference between the first high-frequency clock signal CK1 and the second high-frequency clock signal CK2 is not zero.
  • the potential of the first reference low-level signal VSSG is less than the potential of the second reference low-level signal VSSQ.
  • the upper stage signal ST(n-4) is at a high potential, and the first transistor T1 is turned on, because at this time, the upper stage scan signal G(n- 4) It is a high potential, so that the potential of the first node Q(n) is raised, and the first transistor T2 and the third transistor T3 are turned on; at this time, because the first high-frequency clock signal CK1 is a low potential, the current stage is transmitted.
  • the signal ST(n) and the scanning signal G(n) of this stage are both low potential.
  • the upper stage signal ST(n-4) is at a low potential, the first transistor T1 is turned off, and the potential of the first node Q(n) continues to be at a high potential.
  • the first transistor T2 and the first The three transistor T3 is still turned on.
  • the first high-frequency clock signal CK1 is at a high potential, and therefore, the stage transmission signal ST(n) and the stage scanning signal G(n) are both high potential.
  • the scanning signal G(n) at this stage is at a high potential, so that the scanning line corresponding to the GOA unit at this stage is charged, and the row of pixels corresponding to the scanning line at this stage is turned on, and the pixels in this row are lit.
  • the scanning signal G(n) at this stage is at a high potential
  • the potential of the first node Q(n) is further raised under the action of the bootstrap capacitor Cb, ensuring the first transistor T2 and the third
  • the turning on of the transistor T3 and the signal ST(n) and the scanning signal G(n) at the current stage are both high potential signals.
  • the first high-frequency clock signal CK1 is at a low potential
  • the second high-frequency clock signal CK2 is at a high potential. Since the scan signal G(n+4) of the next stage is a high potential signal, the fourth transistor T4 and the fifth transistor T5 are turned on, directly connecting the first node Q(n) with the second high-frequency clock signal CK2, and the The scan signal G(n) of this stage is connected to the first reference low-level signal VSSG, and the high potential of the second high-frequency clock signal CK2 is output to the first node Q(n), so that the third transistor T3 is turned on at this time.
  • the role of the fifth transistor T5 can be ignored, and only the role of the third transistor T3 is considered. That is, at this time, the potential of the scan signal G(n) of the current stage is pulled down to the potential of the first high-frequency clock signal CK1.
  • the eighth transistor T8 and the ninth transistor T9 are turned off.
  • the first low-frequency clock signal LC1 is at a high potential
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the tenth transistor T10 and the eleventh transistor T11 are turned on
  • the first node Q(n) is lowered from the second reference
  • the level signal VSSQ is connected
  • the current scan signal G(n) is connected to the first reference low level signal VSSG to maintain the potential of the first node Q(n) at the potential of the second reference low level signal VSSQ, And maintain the potential of the scan signal G(n) of the current stage at the potential of the first reference low-level signal VSSG.
  • the second pull-down sustaining unit 1052 is used to maintain the potential of the first node Q(n) at the second reference low-level signal
  • the potential of VSSQ and the potential of maintaining the scan signal G(n) of the current level at the potential of the first reference low-level signal VSSG are similar to those of the first pull-down sustaining unit 1051, and will not be repeated here.
  • the scan signal outputs the low potential of the first high-frequency clock signal CK1 during the action of the pull-down module 104 Therefore, the fall time of the scanning signal can be reduced, the risk of mischarging can be reduced, and the display quality of the display panel can be improved.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes a display area 100 and a GOA circuit 200 integrated on the edge of the display area 100; wherein, the structure and principle of the GOA circuit 200 is similar to the GOA circuit described above, and will not be repeated here.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention concerne un circuit GOA (200) et un écran d'affichage. En accédant à un second signal de verrouillage à haute fréquence dans un module de rappel vers le niveau bas (104), et en commandant le potentiel d'un premier nœud au moyen du second signal d'horloge à haute fréquence, l'instant auquel le premier nœud est rappelé vers le niveau bas peut être retardé ; en outre, en raison d'une différence de phase entre le second signal de verrouillage à haute fréquence et un premier signal d'horloge à haute fréquence, un signal de balayage produit en sortie le faible potentiel du premier signal d'horloge à haute fréquence durant l'action du module de rappel vers le bas (104), de telle sorte que le temps de chute du signal de balayage puisse être réduit.
PCT/CN2019/071071 2018-12-03 2019-01-10 Circuit goa et écran d'affichage WO2020113767A1 (fr)

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CN109935191A (zh) * 2019-04-10 2019-06-25 深圳市华星光电技术有限公司 Goa电路及显示面板
CN110164391A (zh) * 2019-04-25 2019-08-23 昆山龙腾光电有限公司 行驱动电路、显示装置及行驱动方法
CN111145680B (zh) 2020-02-24 2021-07-27 苏州华星光电技术有限公司 驱动电路及显示面板
CN111312146B (zh) * 2020-03-04 2021-07-06 Tcl华星光电技术有限公司 Goa电路及显示面板
CN111462672A (zh) * 2020-03-20 2020-07-28 上海中航光电子有限公司 移位寄存器及其控制方法、显示面板
CN111312188A (zh) * 2020-03-31 2020-06-19 深圳市华星光电半导体显示技术有限公司 Goa电路及显示装置
CN111445880B (zh) * 2020-04-30 2022-04-05 深圳市华星光电半导体显示技术有限公司 Goa器件及栅极驱动电路
CN111477156A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN113189806B (zh) * 2021-05-10 2023-08-01 深圳市华星光电半导体显示技术有限公司 Goa电路、液晶面板及其驱动方法、显示装置
CN115410506A (zh) * 2021-05-28 2022-11-29 北京京东方显示技术有限公司 显示面板及显示装置
CN113889018B (zh) * 2021-10-18 2023-07-04 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN114360431B (zh) 2022-01-28 2023-08-22 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN114842786A (zh) * 2022-04-26 2022-08-02 Tcl华星光电技术有限公司 Goa电路及显示面板

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