WO2019006812A1 - Circuit goa et appareil d'affichage à cristaux liquides - Google Patents

Circuit goa et appareil d'affichage à cristaux liquides Download PDF

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Publication number
WO2019006812A1
WO2019006812A1 PCT/CN2017/095743 CN2017095743W WO2019006812A1 WO 2019006812 A1 WO2019006812 A1 WO 2019006812A1 CN 2017095743 W CN2017095743 W CN 2017095743W WO 2019006812 A1 WO2019006812 A1 WO 2019006812A1
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Prior art keywords
thin film
film transistor
pole
input end
node
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PCT/CN2017/095743
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English (en)
Chinese (zh)
Inventor
李文英
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深圳市华星光电技术有限公司
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Priority to US15/578,524 priority Critical patent/US10896654B2/en
Publication of WO2019006812A1 publication Critical patent/WO2019006812A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a GOA circuit and a liquid crystal display device.
  • the liquid crystal display has become a display terminal in mobile communication devices, computers, televisions, etc. due to its high display quality, low price, and convenient carrying.
  • the panel driving technology of TV liquid crystal displays generally adopts the Gate Driver on Array (GOA) technology, which uses the original process of the flat panel display panel to make the driving circuit of the horizontal scanning line of the panel.
  • GOA technology can simplify the manufacturing process of the flat panel display panel, eliminating the bonding process in the horizontal scanning line direction, which can increase the productivity and reduce the product cost, and at the same time improve the integration of the display panel. It is more suitable for making narrow border or borderless display products to meet the visual pursuit of modern people.
  • each pixel has a thin film transistor (TFT) whose gate is connected to the scan line, the drain is connected to the data line, and the source is connected to the pixel electrode. Applying sufficient voltage on the scan line will cause all the thin film transistors on the line to be turned on. At this time, the display signal voltage on the data line is written into the pixel to control the transmittance of different liquid crystals to achieve the effect of controlling the color.
  • TFT thin film transistor
  • Existing GOA circuits typically include a plurality of cascaded GOA units, each stage of which corresponds to driving a level one horizontal scan line.
  • the GOA unit mainly includes a pull-up part, a pull-up control part, a transfer part, a key pull-down part, and a pull-down sustain circuit (Pull- Down Holding Part), and the bootstrap capacitor responsible for potential lift.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the downlink signal or the Gate signal transmitted from the GOA unit of the previous stage.
  • the pull-down circuit is responsible for pulling the Gate signal low to the low level at the first time, that is, turning off the Gate signal; the pull-down maintaining circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit in the off state, usually having two pull-down maintenance modules. Alternate action; the bootstrap capacitor (C boast) is responsible for the secondary rise of the Q point, which is beneficial to the G(N) input of the pull-up circuit. Out.
  • a multi-level connection method for a GOA circuit for flat panel display wherein a first low frequency clock signal LC1, a second low frequency clock signal LC2, a direct current low voltage VSS, and 4
  • the metal wires of the high frequency clock signals CK1 to CK4 are placed on the periphery of the GOA circuits at the left and right sides of the panel.
  • each pixel P is electrically connected to one data line and one scan line; and several shift registers are sequentially arranged S(n-3) (not shown), S(n-2) (not shown), S(n-1) (not shown), S(n) (not shown)
  • Each of the shift registers outputs a gate signal to scan a corresponding gate line in the display device, and each shift register is electrically connected to the first low frequency clock signal LC1 and the second low frequency clock signal, respectively.
  • LC2 a direct current low voltage VSS, and one of the four high frequency clock signals CK1 to CK4.
  • the nth stage GOA circuit respectively receives the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and one of the high frequency clock signals CK1 to CK4, the n-2th stage.
  • Fig. 2 shows the voltage at the Q point when the external conditions deteriorate. As can be seen from Fig. 2, the voltage at the Q point cannot be maintained (as shown at A in Fig. 2), which in turn affects the driving performance of the GOA circuit.
  • the present invention provides a GOA circuit and a liquid crystal display device for solving the technical problem that the Q-point voltage of the GOA circuit in the prior art cannot be maintained, thereby affecting the driving performance of the GOA circuit.
  • An aspect of the present invention provides a GOA circuit including a plurality of cascaded GOA sub-circuits, each of the GOA sub-circuits including a pull-up control unit, a pull-up unit, a downlink unit, a pull-down unit, a pull-down maintaining unit, and a bootstrap unit;
  • the pull-up control unit is connected to the first signal input end, the second signal input end and the first node, and is configured to output the voltage signal of the second signal input end to the first node under the control of the first signal input end;
  • the pull-up unit is connected to the high-frequency clock signal input end, the first signal output end and the first node, and is configured to input the clock signal of the high-frequency clock signal input end to the first signal output end;
  • the downlink unit is connected to the high frequency clock signal input end, the first node and the second signal output end, and is configured to provide a voltage signal for the second signal input end of the other stage GOA sub-circuit;
  • the pull-down maintaining unit is connected to the first node, the DC low voltage input terminal, the first low frequency clock signal input end, the second low frequency clock signal input end and the first signal output end, for maintaining the output signal of the first signal output end low Potential state
  • the bootstrap unit is connected to the first node and the first signal output end for raising the voltage at the first node;
  • the pull-down unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, wherein the first pole, the second pole, and the gate of the first thin film transistor are respectively connected to the first node, the first pole of the second thin film transistor, and The third signal input end is connected in one-to-one correspondence; the second pole and the gate of the second thin film transistor are respectively connected with the DC low voltage input end and the third signal input end, respectively; the first pole and the second of the third thin film transistor The pole and the gate are respectively connected in one-to-one correspondence with the first signal output end, the DC low voltage input end and the third signal input end.
  • the pull-up control unit comprises a fourth thin film transistor and a fifth thin film transistor;
  • the first pole, the second pole, and the gate of the fourth thin film transistor are respectively connected to the first signal input end, the first pole of the fifth thin film transistor, and the second signal input end in a one-to-one correspondence;
  • the second pole and the gate of the fifth thin film transistor are respectively connected in one-to-one correspondence with the first node and the second signal input end.
  • the pull-down maintaining unit includes a first pull-down maintaining circuit and a second pull-down maintaining circuit;
  • the first pull-down maintaining circuit is connected to the first node, the DC low voltage input terminal, the first low frequency clock signal input end and the first signal output end, and is configured to maintain the output signal of the first signal output end in a low potential state;
  • the second pull-down maintaining circuit is connected to the first node, the DC low voltage input terminal, the second low frequency clock signal input terminal and the first signal output terminal for maintaining the output signal of the first signal output terminal in a low potential state.
  • the first pull-down sustaining circuit includes a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, and a twelfth thin film transistor;
  • the first pole, the second pole, and the gate of the sixth thin film transistor are respectively connected to the first node, the first pole of the seventh thin film transistor, and the first pole of the eleventh thin film transistor in one-to-one correspondence;
  • a second pole and a gate of the seventh thin film transistor are respectively connected in one-to-one correspondence with the direct current low voltage input end and the first pole of the eleventh thin film transistor;
  • the first pole, the second pole and the gate of the eighth thin film transistor are respectively connected in one-to-one correspondence with the first signal output end, the direct current low voltage input end and the first pole of the eleventh thin film transistor;
  • a first pole and a gate of the ninth thin film transistor are both connected to the first low frequency clock signal input end, and a second pole of the ninth thin film transistor is connected to the first pole of the twelfth thin film transistor;
  • the first pole, the second pole and the gate of the tenth thin film transistor are respectively connected to the first low frequency clock signal input end, the first pole of the eleventh thin film transistor and the first pole of the twelfth thin film transistor in one-to-one correspondence;
  • a second pole and a gate of the eleventh thin film transistor are respectively connected to the DC low voltage input end and the first node in one-to-one correspondence;
  • the second pole and the gate of the twelfth thin film transistor are respectively connected to the DC low voltage input terminal and the first node in one-to-one correspondence.
  • the second pull-down maintaining circuit comprises a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film.
  • the first pole, the second pole, and the gate of the thirteenth thin film transistor are respectively connected to the first node, the first pole of the fourteenth thin film transistor, and the first pole of the eighteenth thin film transistor in one-to-one correspondence;
  • a second pole and a gate of the fourteenth thin film transistor are respectively connected in one-to-one correspondence with the direct current low voltage input terminal and the first pole of the eighteenth thin film transistor;
  • the first pole, the second pole and the gate of the fifteenth thin film transistor are respectively connected in one-to-one correspondence with the first signal output end, the direct current low voltage input end and the first pole of the eighteenth thin film transistor;
  • the first pole and the gate of the sixteenth thin film transistor are both connected to the second low frequency clock signal input end, and the second pole of the sixteenth thin film transistor is connected to the first pole of the nineteenth thin film transistor;
  • a first pole, a second pole, and a gate of the seventeenth thin film transistor are respectively connected to the second low frequency clock signal input end, the first pole of the eighteenth thin film transistor, and the first pole of the nineteenth thin film transistor;
  • the second pole and the gate of the eighteenth thin film transistor are respectively connected to the DC low voltage input end and the first node in one-to-one correspondence;
  • the second pole and the gate of the nineteenth thin film transistor are respectively connected to the DC low voltage input terminal and the first node in one-to-one correspondence.
  • the downlink unit comprises a twentieth thin film transistor, and the first pole, the second pole and the gate of the twentieth thin film transistor respectively correspond to the high frequency clock signal input end, the second signal output end and the first node. connection.
  • the pull-up unit comprises a 21st thin film transistor, and the first pole, the second pole and the gate of the 21st thin film transistor are respectively connected to the high frequency clock signal input end, the first signal output end and the first node A corresponding connection.
  • the bootstrap unit comprises a capacitor, the first end of the capacitor is connected to the first node, and the second end of the capacitor is connected to the first signal output end.
  • the first extreme drain and the second extreme source are preferably the first extreme drain and the second extreme source.
  • Another aspect of the present invention provides a liquid crystal display device including the above GOA circuit.
  • the first thin film transistor and the second thin film transistor are connected in series in the pull-down unit, which reduces the Q point in the GOA circuit (ie, at the first node m). Leakage current, and because the first thin film transistor is connected in series with the second thin film transistor, the voltage carried on the first thin film transistor or the second thin film transistor is reduced, and the deterioration of the first thin film transistor or the second thin film transistor is weakened to some extent. The speed increases the service life, which improves the stability of the GOA circuit in harsh environments and enhances the reliability of the LCD panel.
  • FIG. 1 is a schematic diagram of a GOA multi-level drive architecture in the prior art
  • FIG. 3 is a schematic structural diagram of a GOA sub-circuit according to an embodiment of the present invention.
  • FIG. 5 is a waveform diagram of voltages at a Q point of a GOA circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a GOA sub-circuit according to an embodiment of the present invention.
  • an embodiment of the present invention provides a GOA circuit including a plurality of cascaded GOA sub-circuits, each of which includes a pull-up The control unit 1, the pull-up unit 2, the downlink unit 3, the pull-down unit 4, the pull-down maintaining unit 5, and the bootstrap unit 6.
  • the GOA circuit includes a start signal STV, a first low frequency clock signal LC1, a second low frequency clock signal LC2, a direct current low voltage VSS, and four high frequency clock signals CK1 to CK4.
  • the start signal is used to start the first two stages of the GOA T11, and the last two stages of the T31 and T41 are pulled down.
  • the low frequency signals LC1 and LC2 alternately perform the pull-down maintenance of the GOA circuit.
  • the GOA circuit is mainly maintained when the Gate signal is off.
  • Gn is at a stable low potential, and the Gn signal required for the scan line is mainly outputted through one of the four high-frequency signals, so that the gate signal of the display panel can be well turned on to control the data signal. Input into the thin film transistor in the pixel, so that the pixel can be normally charged and discharged.
  • the Nth stage GOA sub-circuit receives the first low frequency clock signal LC1, the second low frequency clock signal LC2, the DC low voltage signal VSS, the high frequency clock signal CK1-CK4, and the N-2th GOA sub-circuit respectively.
  • the N-2th stage gate signal G(N-2) (output by the first signal output terminal o1 of the N-2th GOA sub-circuit) and the N-2th stage start signal ST(N-2) (by The second signal output terminal o2 of the N-2th GOA sub-circuit is output) and the N+2th gate signal G(N+2) generated by the N+2th GOA sub-circuit (by the N+2th GOA)
  • the first signal output terminal o1 of the sub-circuit outputs), and generates an Nth-stage gate signal G(N) and an Nth-stage downlink signal ST(N) (ie, an activation signal ST of the N+2th GOA sub-circuit ( N)) and the first node m
  • the Nth stage first node outputs a signal Q(N).
  • the Nth-level GOA sub-circuit is taken as an example, wherein the signal provided by the first signal input terminal i1 is the N-2th-level gate signal G generated by the N-2th GOA sub-circuit ( N-2); the signal provided by the second signal input terminal i2 is the N-2th stage downlink signal ST(N-2) generated by the N-2th GOA sub-circuit; the signal provided by the third signal input terminal i3 is The N+2th stage gate signal G(N+2) generated by the N+2th GOA sub-circuit.
  • the signal outputted by the first signal output terminal o1 is the Nth-level gate signal G(N) generated by the Nth stage GOA sub-circuit, and the first signal output terminal o1 is connected to the scan line to turn the Nth-level gate signal G ( N) is supplied to the Nth-level scan line;
  • the signal outputted by the second signal output terminal o2 is the Nth-stage downlink signal ST(N) generated by the Nth stage GOA sub-circuit;
  • the signal output by the first node m is the N-th stage The Nth stage first node output signal Q(N) generated by the GOA sub-circuit.
  • the first low frequency clock signal input terminal i7 provides a first low frequency clock signal LC1; the second low frequency clock signal input terminal i8 provides a second low frequency clock signal LC2; the DC low voltage input terminal i9 provides a DC low voltage signal VSS; the high frequency clock signal input Terminal i5 provides one of the high frequency clock signals CK1-CK4.
  • an external enable signal STV is supplied to the first signal input terminal i1 of the GOA sub-circuit of the first two stages and the third signal input terminal i3 of the GOA sub-circuit of the last two stages.
  • 4 is a timing chart of each of the above signals.
  • CK(1), CK(2), CK(3), and CK(4) indicate a CK1 signal, a CK2 signal, a CK3 signal, and a CK4 signal, respectively.
  • the pull-up control unit 1 is connected to the first signal input terminal i1, the second signal input terminal i2 and the first node m for controlling the voltage signal of the second signal input terminal i2 under the control of the first signal input terminal i1. Output to the first node m.
  • the pull-up unit 2 is connected to the high-frequency clock signal input terminal i4, the first signal output terminal o1 and the first node m for inputting the clock signal of the high-frequency clock signal input terminal i4 to the first signal output terminal o1.
  • the downlink unit 3 is connected to the high frequency clock signal input terminal i4, the first node m and the second signal output terminal o2 for supplying a voltage signal to the second signal input terminal i2 of the other stage GOA sub-circuit.
  • the pull-down maintaining unit 5 is connected to the first node m, the DC low voltage input terminal i9, the first low frequency clock signal input terminal i7, the second low frequency clock signal input terminal i8 and the first signal output terminal o1 for outputting the first signal.
  • the output signal of terminal o1 is maintained at a low potential state.
  • the bootstrap unit 6 is connected to the first node m and the first signal output terminal o1 for raising the voltage at the first node m.
  • the pull-down unit 4 includes a first thin film transistor T41', a second thin film transistor T41, and a third thin film transistor T31, wherein the first, second, and second gates of the first thin film transistor T41' are respectively associated with the first node m,
  • the first pole and the third signal input terminal i3 of the second thin film transistor T41 are connected one by one; the second pole and the gate of the second thin film transistor T41 are respectively corresponding to the DC low voltage input terminal i9 and the third signal input terminal i3.
  • Connecting; the first pole, the second pole and the gate of the third thin film transistor T31 are respectively connected to the first signal output terminal o1, the DC low voltage input terminal i9 and the third signal
  • the inbound i3 is connected one by one.
  • the pull-down unit 4 is for pulling the Nth-level gate signal G(N) low to be low, that is, turning off the N-th gate signal G(N).
  • the first thin film transistor T41' and the second thin film transistor T41 are connected in series in the pull-down unit 4, that is, the first, second, and gate of the first thin film transistor T41' are respectively Connected to the first node m, the first pole of the second thin film transistor T41 and the third signal input terminal i3 in one-to-one correspondence, the second pole and the gate of the second thin film transistor T41 are respectively connected with the DC low voltage input terminal i9 and the third
  • the signal input terminals i3 are connected one by one in a one-to-one manner, which reduces the leakage current at the Q point (ie, at the first node m) in the GOA circuit, and because the first thin film transistor T41' is connected in series with the second thin film transistor T41, The voltage carried on the thin film transistor T41' or the second thin film transistor T41 is reduced, which weakens the deterioration speed of the first thin film transistor T41' or the second thin film transistor T41 to a certain
  • the pull-up control unit 1 includes a fourth thin film transistor T11 and a fifth thin film transistor T11'; wherein the first, second, and second gates of the fourth thin film transistor T11 are respectively associated with the first The signal input terminal i1, the first pole of the fifth thin film transistor T11' and the second signal input terminal i2 are connected in one-to-one correspondence; the second pole and the gate of the fifth thin film transistor T11' are respectively connected to the first node m and the second signal The input terminals i2 are connected one by one.
  • the fourth thin film transistor T11 and the fifth thin film transistor T11' in the above pull-up control unit 1 are also connected in series, thereby further reducing the leakage current at the Q point in the GOA circuit, and due to the fourth thin film transistor T11 and the fifth
  • the thin film transistor T11' is connected in series such that the voltage carried on the fourth thin film transistor T11 or the fifth thin film transistor T11' is reduced, and the deterioration speed of the fourth thin film transistor T11 or the fifth thin film transistor T11' is weakened to some extent, and the speed is improved. Its service life improves the stability of the GOA circuit in harsh environments and enhances the reliability of the LCD panel.
  • the pull-down maintaining unit 5 includes a first pull-down maintaining circuit 51 and a second pull-down maintaining circuit 52; wherein, the first pull-down maintaining circuit 51 and the first node m, the DC low voltage input terminal i9 The first low frequency clock signal input terminal i7 and the first signal output terminal o1 are connected to maintain the output signal of the first signal output terminal o1 in a low potential state; the second pulldown maintaining circuit 52 is low with the first node m and the direct current The voltage input terminal i9, the second low frequency clock signal input terminal i8 and the first signal output terminal o1 are connected to maintain the output signal of the first signal output terminal o1 in a low potential state.
  • the first low frequency clock signal LC1 provided by the first low frequency clock signal input terminal i7 and the second low frequency clock signal LC2 provided by the second low frequency clock signal input terminal i8 alternately perform pull-down maintenance of the GOA sub-circuit to turn the gate signal and The output signal of the pull unit 2 is maintained in the off state.
  • the first pull-down maintaining circuit 51 includes a sixth thin film transistor T42', a seventh thin film transistor T42, an eighth thin film transistor T32, a ninth thin film transistor T51, and a tenth thin film transistor T53.
  • the first poles of the eleventh thin film transistor T54 are connected one-to-one; the second pole and the gate of the seventh thin film transistor T42 are respectively connected to the first poles of the direct current low voltage input terminal i9 and the eleventh thin film transistor T54.
  • the first pole, the second pole and the gate of the eighth thin film transistor T32 are respectively connected in one-to-one correspondence with the first signal output terminal o1, the direct current low voltage input terminal i9 and the first pole of the eleventh thin film transistor T54;
  • the first pole and the gate of the thin film transistor T51 are both connected to the first low frequency clock signal input terminal i7, the second pole of the ninth thin film transistor T51 is connected to the first pole of the twelfth thin film transistor T52; and the tenth thin film transistor T53
  • the first pole, the second pole and the gate are respectively connected to the first low frequency clock signal input terminal i7, the first pole of the eleventh thin film transistor T54 and the first pole of the twelfth thin film transistor T52;
  • Thin film transistor T54 The pole and the gate are respectively connected to the DC low voltage input terminal i9 and the first node m in one-to-one correspondence; the second pole and the gate of the twelfth thin film transistor T52 are respectively connected to the DC
  • the sixth thin film transistor T42' is connected in series with the seventh thin film transistor T42, further reducing the leakage current at the Q point in the GOA circuit, and because the sixth thin film transistor T42' and the seventh thin film transistor
  • the series connection of T42 reduces the voltage carried on the sixth thin film transistor T42' or the seventh thin film transistor T42, which weakens the deterioration speed of the sixth thin film transistor T42' or the seventh thin film transistor T42 to a certain extent, and improves the service life thereof. This improves the stability of the GOA circuit in harsh environments and enhances the reliability of the LCD panel.
  • the second pull-down maintaining circuit 52 includes a thirteenth thin film transistor T43', a fourteenth thin film transistor T43, a fifteenth thin film transistor T33, a sixteenth thin film transistor T61, and a seventeenth thin film.
  • the first pole and the first pole of the eighteenth thin film transistor T64 are connected in one-to-one correspondence;
  • the second pole and the gate of the fourteenth thin film transistor T43 are respectively connected to the direct current low voltage input terminal i9 and the eighteenth thin film transistor T64 One pole one by one corresponding connection;
  • the first pole, the second pole and the gate of the fifteenth thin film transistor T33 and the first signal output terminal o1 the DC low voltage input terminal i9 and the first pole of the eighteenth thin film transistor T64 One-to-one correspondence;
  • the first pole and the gate of the sixteenth thin film transistor T61 are both connected to the second low frequency clock signal input terminal i8, and the second pole of the sixteenth thin film transistor T61 and the
  • the thirteenth thin film transistor T43' is connected in series with the fourteenth thin film transistor T43, further reducing the leakage current at the Q point in the GOA circuit, and because the thirteenth thin film transistor T43' and the tenth
  • the four thin film transistors T43 are connected in series, so that the voltage carried on the thirteenth thin film transistor T43' or the fourteenth thin film transistor T43 is reduced, and the deterioration of the thirteenth thin film transistor T43' or the fourteenth thin film transistor T43 is weakened to some extent.
  • the speed increases the service life, thereby improving the stability of the GOA circuit in a harsh environment and enhancing the reliability of the liquid crystal panel.
  • the waveform of the Q point in the GOA circuit is as shown in FIG. 5.
  • the GOA circuit provided in this embodiment realizes the Q point voltage maintenance, as shown at B in FIG.
  • the downlink unit 3 includes a twentieth thin film transistor T22, and the first pole, the second pole, and the gate of the twentieth thin film transistor T22 are respectively coupled to the high frequency clock signal input terminal i4 and the second
  • the signal output end o2 is connected to the first node m one by one.
  • the downlink unit 3 is configured to supply a voltage signal to the second signal input terminal i2 of the other stage GOA sub-circuit, that is, the signal output from the second signal output terminal o2 of the downlink unit 3 as the start signal of the other stage GOA sub-circuit .
  • the pull-up unit 2 includes a second eleventh thin film transistor T21, and the first, second, and second gates of the twenty-first thin film transistor T21 are respectively coupled to the high frequency clock signal input terminal i4,
  • the first signal output terminal o1 is connected to the first node m one by one.
  • the pull-up unit 2 is mainly responsible for outputting the high-frequency clock signal CK (which is one of CK1-CK4) input from the high-frequency clock signal input terminal i4 as the N-th gate signal G(N).
  • the bootstrap unit 6 includes a capacitor Cb.
  • the first end of the capacitor Cb is connected to the first node m, and the second end of the capacitor Cb is connected to the first signal output terminal o1.
  • the first of the thin film transistors has a first drain and a second source.
  • the embodiment of the invention further provides a liquid crystal display device comprising the GOA circuit in the above embodiment.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Circuit GOA et appareil d'affichage à cristaux liquides. Le circuit GOA comprend une pluralité de sous-circuits GOA en cascade, et, dans une unité de rappel vers le niveau bas (4) de chaque sous-circuit GOA, une connexion est réalisée au moyen du montage en série d'un premier transistor à couches minces (T41') et d'un second transistor à couches minces (T41). Ce procédé de connexion réduit le courant de fuite à un point Q dans un circuit GOA, améliore la stabilité du circuit GOA dans un environnement exigent, et rend un panneau à cristaux liquides plus fiable.
PCT/CN2017/095743 2017-07-04 2017-08-03 Circuit goa et appareil d'affichage à cristaux liquides WO2019006812A1 (fr)

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