WO2020113767A1

WO2020113767A1 - Goa circuit and display panel

Info

Publication number: WO2020113767A1
Application number: PCT/CN2019/071071
Authority: WO
Inventors: 朱静
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2018-12-03
Filing date: 2019-01-10
Publication date: 2020-06-11
Also published as: CN109448624B; CN109448624A

Abstract

A GOA circuit (200) and a display panel. By accessing a second high frequency lock signal at a pulldown module (104), and controlling the potential of a first node by means of the second high frequency clock signal, the time when the first node is pulled down can be delayed; moreover, due to a phase difference between the second high frequency lock signal and a first high frequency clock signal, a scan signal outputs the low potential of the first high frequency clock signal during the action of the pulldown module (104), so that the fall time of the scan signal can be reduced.

Description

GOA circuit and display panel

Technical field

This application relates to the field of display technology, in particular to a GOA circuit and a display panel.

Background technique

GOA (English full name: Gate Driver on Array, Chinese full name: integrated gate drive circuit) technology integrates the gate drive circuit on the array substrate of the display panel, so that the gate drive integrated circuit part can be omitted, from the material cost and The production process reduces the product cost in two aspects.

The existing GOA circuit has a short charging time and a heavy resistive load, which results in very serious distortion of the scan signal. That is, the value of the fall time of the scan signal at this stage is large, and the risk of wrong charging is high, which leads to poor display panel quality.

technical problem

The purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem of poor quality of the display panel due to the large value of the fall time of the scan signal, which causes a high risk of wrong charging.

Technical solution

An embodiment of the present application provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module and a bootstrap capacitance;

The pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal The scan signal is output to the first node;

The download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;

The pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;

The pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential

The pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;

One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal;

The period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the phase difference between the first high-frequency clock signal and the second high-frequency clock signal is not zero; The potential of the first reference low-level signal is less than the potential of the second reference low-level signal.

In the GOA circuit described in this application, the pull-up control module includes: a first transistor;

The gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.

In the GOA circuit described in this application, the download module includes: a second transistor;

The gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.

In the GOA circuit described in this application, the pull-up module includes: a third transistor;

The gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.

In the GOA circuit described in this application, the pull-down module includes: a fourth transistor and a fifth transistor;

The gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the scan signal of the next stage; the source of the fourth transistor is electrically connected to the second high-frequency clock signal , The source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically Is connected to the scan signal of the current level.

In the GOA circuit described in this application, the pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit, the first pull-down sustaining unit and the second pull-down sustaining unit are in the pull-down module After pulling down the potential of the first node and the potential of the current-level scanning signal, alternately maintaining the potential of the first node at the potential of the second reference low-level signal, and scanning the current level The potential of the signal is maintained at the potential of the first reference low-level signal.

In the GOA circuit described in this application, the first pull-down sustaining unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

The gate and source of the sixth transistor and the source of the seventh transistor are electrically connected to the first low-frequency clock signal; the drain of the sixth transistor and the gate of the seventh transistor And the drain of the eighth transistor; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor Connected; the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the first node; the source of the eighth transistor, the source of the ninth transistor, and all The source of the tenth transistor is electrically connected to the second reference low-level signal, and the source of the eleventh transistor is electrically connected to the first reference low-level signal; the tenth transistor The drain of is electrically connected to the first node; the drain of the eleventh transistor is electrically connected to the current scan signal;

The second pull-down maintenance unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

The gate and source of the twelfth transistor and the source of the thirteenth transistor are electrically connected to the second low-frequency clock signal; the drain of the twelfth transistor and the thirteenth transistor The gate of the transistor and the drain of the fourteenth transistor are electrically connected; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor and the The gate of the seventeenth transistor is electrically connected; the gate of the fourteenth transistor and the gate of the fifteenth transistor are both electrically connected to the first node; the source of the fourteenth transistor , The source of the fifteenth transistor and the source of the sixteenth transistor are both electrically connected to the second reference low-level signal; the source of the seventeenth transistor is electrically connected to the The first reference low-level signal; the drain of the sixteenth transistor is electrically connected to the first node; the drain of the seventeenth transistor is electrically connected to the current scan signal.

An embodiment of the present application further provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module and a self-sustaining module Lift capacitance

The download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level transmission signal under the potential control of the first node;

One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal.

In the GOA circuit described in this application, the period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the first high-frequency clock signal and the second high-frequency clock The phase difference between the signals is not zero.

In the GOA circuit described in this application, the potential of the first reference low-level signal is less than the potential of the second reference low-level signal.

An embodiment of the present application further provides a display panel including a GOA circuit, the GOA circuit includes: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, Pull-down module, pull-down maintenance module and bootstrap capacitor;

In the display panel described in this application, the pull-up control module includes: a first transistor;

In the display panel described in this application, the download module includes: a second transistor;

In the display panel described in this application, the pull-up module includes: a third transistor;

Beneficial effect

In the GOA circuit and the display panel provided by the embodiments of the present application, by connecting the second high-frequency clock signal to the pull-down module and controlling the potential of the first node by the second high-frequency clock signal, the time when the first node is pulled down can be delayed ; And due to the phase difference between the second high-frequency clock signal and the first high-frequency clock signal, during the pull-down module function makes the scan signal output low potential of the first high-frequency clock signal, so that the fall time of the scan signal can be reduced To reduce the risk of mischarging, thereby improving the display quality of the display panel.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.

FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.

2 is a schematic circuit diagram of a GOA unit in a GOA circuit provided by an embodiment of the present application.

FIG. 3 is a signal timing diagram of a GOA unit in a GOA circuit provided by an embodiment of the present application.

4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

Embodiments of the invention

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the protection scope of the present application.

The transistors used in all the embodiments of this application may be thin film transistors, field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called a source electrode, and the other electrode is called a drain electrode. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a source, and the output end is a drain. In addition, the transistors used in the embodiments of the present application may include two types of P-type transistors and/or N-type transistors, where the P-type transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type transistor is at The gate turns on when the gate is high, and turns off when the gate is low.

Please refer to FIG. 1, which is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application. As shown in FIG. 1, the GOA circuit provided by the embodiment of the present application includes multi-level cascaded GOA units. Among them, Fig. 1 takes the cascaded n-4th level GOA unit, nth level GOA unit and N+4th level GOA unit as examples.

When the n-th stage GOA unit is working, the scan signal output by the n-th stage GOA unit is at a high potential, which is used to turn on the transistor switch of each pixel in a row in the display panel, and perform the pixel electrode in each pixel through the data signal Charging; the nth stage transmission signal is used to control the operation of the n+4th stage GOA unit; when the n+4th stage GOA unit is working, the scan signal output by the n+4th stage GOA unit is high potential, while the nth The scan signal output by the stage GOA unit is low.

Further, please refer to FIG. 2, which is a schematic circuit diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application. As shown in FIG. 2, the GOA unit includes a pull-up control module 101, a download module 102, a pull-up module 103, a pull-down module 104, a pull-down maintenance module 105, and a bootstrap capacitor Cb.

Among them, the pull-up control module 101 is connected to the upper-level transmission signal ST (n-4) and the upper-level scanning signal G (n-4), and is electrically connected to the first node Q (n), used for Under the control of the upper stage transmission signal ST (n-4), the upper stage scanning signal G (n-4) is output to the first node Q (n).

Wherein, the download module 102 is connected to the first high-frequency clock signal CK1 and is electrically connected to the first node Q(n), and is used to output the current stage transmission signal ST under the potential control of the first node Q(n) (N).

The pull-up module 103 is connected to the first high-frequency clock signal CK1, and is electrically connected to the first node Q(n), and is used to output the current scan signal G(( n).

The pull-down module 104 is connected to the next-level scan signal G(n+4), the second high-frequency clock signal CK2, and the first reference low-level signal VSSG, and is electrically connected to the first node Q(n) and the local node The level scan signal G(n) is used to output the high potential of the second high-frequency clock signal CK2 to the first node Q(n) under the control of the next level scan signal G(n+4). The potential of the scan signal G(n) reaches the low potential of the first high-frequency clock signal CK1.

The pull-down maintenance module 105 is connected to the first low-frequency clock signal LC1, the second low-frequency clock signal LC2, the first reference low-level signal VSSG and the second reference low-level signal VSSQ, and is electrically connected to the first node Q ( n) and the current scan signal G(n), used to pull down the potential of the first node Q(n) and the potential of the current scan signal G(n) in the pull-down module 104 Maintain the potential of the second reference low-level signal VSSQ, and maintain the potential of the current-level scan signal G(n) at the potential of the first reference low-level signal VSSG.

Wherein, one end of the bootstrap capacitor Cb is electrically connected to the first node Q(n), and the other end of the bootstrap capacitor Cb is electrically connected to the scan signal G(n) of the current stage.

It should be noted that the difference between the GOA circuit provided by the embodiment of the present application and the existing GOA circuit is that the GOA circuit of the embodiment of the present application is connected to the second high-frequency clock signal CK2 at the pull-down module 104 by the first high The phase difference between the high-frequency clock signal CK1 and the second high-frequency clock signal CK2 causes the current scan signal G(n) to output the low potential of the first high-frequency clock signal CK1 during the action of the pull-down module 104, thereby reducing the cost The fall time of the level scan signal G(n) reduces the risk of mischarging and further improves the display quality of the display panel.

Please continue to refer to FIG. 2. In some embodiments, the pull-up control module 101 includes: a first transistor T1; the gate of the first transistor T1 is electrically connected to the previous stage signal ST(n-4), the first The source of the transistor T1 is electrically connected to the scan signal G(n-4) of the previous stage, and the drain of the first transistor T1 is electrically connected to the first node Q(n).

Please continue to refer to FIG. 2. In some embodiments, the download module 102 includes: a first transistor T2; the gate of the first transistor T2 is electrically connected to the first node Q(n), and the source of the first transistor T2 is electrically It is electrically connected to the first high-frequency clock signal CK1, and the drain of the third transistor T3 is electrically connected to the current stage signal ST(n).

Please continue to refer to FIG. 2. In some embodiments, the pull-up module 103 includes: a third transistor T3; the gate of the third transistor T3 is electrically connected to the first node Q(n), and the source of the third transistor T3 is electrically Is connected to the first high-frequency clock signal CK1, and the drain of the third transistor T3 is electrically connected to the scan signal G(n) of the current stage.

Please continue to refer to FIG. 2. In some embodiments, the pull-down module 104 includes: a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are electrically connected to the next stage Scan signal G(n+4); the source of the fourth transistor T4 is electrically connected to the second high-frequency clock signal CK2, and the source of the fifth transistor T5 is electrically connected to the first reference low-level signal VSSG; the fourth The drain of the transistor T4 is electrically connected to the first node Q(n), and the drain of the fifth transistor T5 is electrically connected to the scan signal G(n) of the current stage.

Please continue to refer to FIG. 2. In some embodiments, the pull-down maintenance module 105 includes a first pull-down maintenance unit 1051 and a second pull-down maintenance unit 1052. The first pull-down maintenance unit 1051 and the second pull-down maintenance unit 1052 are in the pull-down module 104. After pulling down the potential of the first node Q(n) and the potential of the current scanning signal G(n), the potential of the first node Q(n) is alternately maintained at the potential of the second reference low-level signal VSSQ, and the The potential of the scan signal G(n) at this stage is maintained at the potential of the first reference low-level signal VSSG.

The first pull-down sustaining unit 1051 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11; a gate and a source of the sixth transistor T6 And the source of the seventh transistor T7 is electrically connected to the first low-frequency clock signal LC1; the drain of the sixth transistor T6, the gate of the seventh transistor T7 and the drain of the eighth transistor T8; the seventh transistor The drain of T7, the drain of the ninth transistor T9, the gate of the tenth transistor T10, and the gate of the eleventh transistor T11 are electrically connected; the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are all electrically Connected to the first node Q(n); the source of the eighth transistor T8, the source of the ninth transistor T9 and the source of the tenth transistor T10 are all electrically connected to the second reference low level signal VSSQ, the tenth The source of a transistor T11 is electrically connected to the first reference low-level signal VSSG; the drain of the tenth transistor T10 is electrically connected to the first node Q(n); the drain of the eleventh transistor T11 is electrically connected to Scan signal G(n) at this level.

The second pull-down sustaining unit 1052 includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17; a twelfth transistor T12 The gate, the source, and the source of the thirteenth transistor T13 are electrically connected to the second low-frequency clock signal LC2; the drain of the twelfth transistor T12, the gate of the thirteenth transistor T13, and the fourteenth transistor T14 The drain is electrically connected; the drain of the thirteenth transistor T13, the drain of the fifteenth transistor T15, the gate of the sixteenth transistor T16, and the gate of the seventeenth transistor T17; the fourteenth transistor T14 Of the gate and the gate of the fifteenth transistor T15 are electrically connected to the first node Q(n); the source of the fourteenth transistor T14, the source of the fifteenth transistor T15 and the source of the sixteenth transistor T16 The electrodes are electrically connected to the second reference low-level signal VSSQ; the source of the seventeenth transistor T17 is electrically connected to the first reference low-level signal VSSG; the drain of the sixteenth transistor T16 is electrically connected to the first Node Q(n); the drain of the seventeenth transistor T17 is electrically connected to the scan signal G(n) of the current stage.

Specifically, please refer to FIG. 2 and FIG. 3, which is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application. The polarities of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite. The period of the first high-frequency clock signal CK1 is the same as the period of the second high-frequency clock signal CK2, and the phase difference between the first high-frequency clock signal CK1 and the second high-frequency clock signal CK2 is not zero. The potential of the first reference low-level signal VSSG is less than the potential of the second reference low-level signal VSSQ.

In the first time period t1, the upper stage signal ST(n-4) is at a high potential, and the first transistor T1 is turned on, because at this time, the upper stage scan signal G(n- 4) It is a high potential, so that the potential of the first node Q(n) is raised, and the first transistor T2 and the third transistor T3 are turned on; at this time, because the first high-frequency clock signal CK1 is a low potential, the current stage is transmitted. The signal ST(n) and the scanning signal G(n) of this stage are both low potential.

In the second time period t2, the upper stage signal ST(n-4) is at a low potential, the first transistor T1 is turned off, and the potential of the first node Q(n) continues to be at a high potential. The first transistor T2 and the first The three transistor T3 is still turned on. At this time, the first high-frequency clock signal CK1 is at a high potential, and therefore, the stage transmission signal ST(n) and the stage scanning signal G(n) are both high potential. At this stage, the scanning signal G(n) at this stage is at a high potential, so that the scanning line corresponding to the GOA unit at this stage is charged, and the row of pixels corresponding to the scanning line at this stage is turned on, and the pixels in this row are lit.

At the same time, at this stage, since the scanning signal G(n) at this stage is at a high potential, the potential of the first node Q(n) is further raised under the action of the bootstrap capacitor Cb, ensuring the first transistor T2 and the third The turning on of the transistor T3 and the signal ST(n) and the scanning signal G(n) at the current stage are both high potential signals.

In the third time period t3, the first high-frequency clock signal CK1 is at a low potential, and the second high-frequency clock signal CK2 is at a high potential. Since the scan signal G(n+4) of the next stage is a high potential signal, the fourth transistor T4 and the fifth transistor T5 are turned on, directly connecting the first node Q(n) with the second high-frequency clock signal CK2, and the The scan signal G(n) of this stage is connected to the first reference low-level signal VSSG, and the high potential of the second high-frequency clock signal CK2 is output to the first node Q(n), so that the third transistor T3 is turned on at this time. In addition, due to the difference in the manufacturing processes of the third transistor T3 and the fifth transistor T5, at this time, the role of the fifth transistor T5 can be ignored, and only the role of the third transistor T3 is considered. That is, at this time, the potential of the scan signal G(n) of the current stage is pulled down to the potential of the first high-frequency clock signal CK1.

In the fourth time period t4, since the potential of the first node Q(n) is pulled down, the eighth transistor T8 and the ninth transistor T9 are turned off. At this time, the first low-frequency clock signal LC1 is at a high potential, the fifth transistor T5 and the sixth transistor T6 are turned on, the tenth transistor T10 and the eleventh transistor T11 are turned on, and further the first node Q(n) is lowered from the second reference The level signal VSSQ is connected, and the current scan signal G(n) is connected to the first reference low level signal VSSG to maintain the potential of the first node Q(n) at the potential of the second reference low level signal VSSQ, And maintain the potential of the scan signal G(n) of the current stage at the potential of the first reference low-level signal VSSG.

Of course, if the second low-frequency clock signal LC2 is high and the first low-frequency clock signal LC1 is low, then the second pull-down sustaining unit 1052 is used to maintain the potential of the first node Q(n) at the second reference low-level signal The potential of VSSQ and the potential of maintaining the scan signal G(n) of the current level at the potential of the first reference low-level signal VSSG are similar to those of the first pull-down sustaining unit 1051, and will not be repeated here.

In the embodiment of the present application, by connecting the second high-frequency clock signal CK2 to the pull-down module 104 and controlling the potential of the first node Q(n) by the second high-frequency clock signal CK2, the first node Q(n ) The time when it is pulled low; and due to the phase difference between the second high-frequency clock signal CK2 and the first high-frequency clock signal CK1, the scan signal outputs the low potential of the first high-frequency clock signal CK1 during the action of the pull-down module 104 Therefore, the fall time of the scanning signal can be reduced, the risk of mischarging can be reduced, and the display quality of the display panel can be improved.

Please refer to FIG. 4, which is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 4, the display panel includes a display area 100 and a GOA circuit 200 integrated on the edge of the display area 100; wherein, the structure and principle of the GOA circuit 200 is similar to the GOA circuit described above, and will not be repeated here.

The above are only the embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by the description and drawings of the present invention, or directly or indirectly used in other related technical fields, The same reason is included in the patent protection scope of the present invention.

Claims

A GOA circuit includes a multi-level cascaded GOA unit. Each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module, and a bootstrap capacitor;

The pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal The scan signal is output to the first node;

The download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;

The pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;

The pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential

The pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;

One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal;

The period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the phase difference between the first high-frequency clock signal and the second high-frequency clock signal is not zero; The potential of the first reference low-level signal is less than the potential of the second reference low-level signal.
The GOA circuit according to claim 1, wherein the pull-up control module comprises: a first transistor;

The gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
The GOA circuit according to claim 1, wherein the download module comprises: a second transistor;

The gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
The GOA circuit according to claim 1, wherein the pull-up module includes: a third transistor;

The gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.
The GOA circuit according to claim 1, wherein the pull-down module comprises: a fourth transistor and a fifth transistor;

The gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the scan signal of the next stage; the source of the fourth transistor is electrically connected to the second high-frequency clock signal , The source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically Sexually connected to the current scan signal.
The GOA circuit according to claim 1, wherein the pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit, the first pull-down sustaining unit and the second pull-down sustaining unit are in the After the pull-down module pulls down the potential of the first node and the potential of the current scanning signal, it alternately maintains the potential of the first node at the potential of the second reference low-level signal, and the The potential of the level scan signal is maintained at the potential of the first reference low-level signal.
The GOA circuit according to claim 6, wherein the first pull-down sustain unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

The gate and source of the sixth transistor and the source of the seventh transistor are electrically connected to the first low-frequency clock signal; the drain of the sixth transistor and the gate of the seventh transistor And the drain of the eighth transistor; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor Connected; the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the first node; the source of the eighth transistor, the source of the ninth transistor, and all The source of the tenth transistor is electrically connected to the second reference low-level signal, and the source of the eleventh transistor is electrically connected to the first reference low-level signal; the tenth transistor The drain of is electrically connected to the first node; the drain of the eleventh transistor is electrically connected to the current scan signal;

The second pull-down maintenance unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

The gate and source of the twelfth transistor and the source of the thirteenth transistor are electrically connected to the second low-frequency clock signal; the drain of the twelfth transistor and the thirteenth transistor The gate of the transistor and the drain of the fourteenth transistor are electrically connected; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor and the The gate of the seventeenth transistor is electrically connected; the gate of the fourteenth transistor and the gate of the fifteenth transistor are both electrically connected to the first node; the source of the fourteenth transistor , The source of the fifteenth transistor and the source of the sixteenth transistor are both electrically connected to the second reference low-level signal; the source of the seventeenth transistor is electrically connected to the The first reference low-level signal; the drain of the sixteenth transistor is electrically connected to the first node; the drain of the seventeenth transistor is electrically connected to the current scan signal.
A GOA circuit includes a multi-level cascaded GOA unit. Each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, a pull-down maintenance module, and a bootstrap capacitor;

The pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal The scan signal is output to the first node;

The download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;

The pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;

The pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential

The pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;

One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal.
The GOA circuit according to claim 8, wherein the pull-up control module comprises: a first transistor;

The gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
The GOA circuit according to claim 8, wherein the download module comprises: a second transistor;

The gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
The GOA circuit according to claim 8, wherein the pull-up module comprises: a third transistor;

The gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.
The GOA circuit according to claim 8, wherein the pull-down module comprises: a fourth transistor and a fifth transistor;

The gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the scan signal of the next stage; the source of the fourth transistor is electrically connected to the second high-frequency clock signal , The source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically Is connected to the scan signal of the current level.
The GOA circuit according to claim 8, wherein the pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit, the first pull-down sustaining unit and the second pull-down sustaining unit are in the After the pull-down module pulls down the potential of the first node and the potential of the current scanning signal, it alternately maintains the potential of the first node at the potential of the second reference low-level signal, and the The potential of the level scan signal is maintained at the potential of the first reference low-level signal.
The GOA circuit according to claim 13, wherein the first pull-down sustain unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

The gate and source of the sixth transistor and the source of the seventh transistor are electrically connected to the first low-frequency clock signal; the drain of the sixth transistor and the gate of the seventh transistor And the drain of the eighth transistor; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor Connected; the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the first node; the source of the eighth transistor, the source of the ninth transistor, and all The source of the tenth transistor is electrically connected to the second reference low-level signal, and the source of the eleventh transistor is electrically connected to the first reference low-level signal; the tenth transistor The drain of is electrically connected to the first node; the drain of the eleventh transistor is electrically connected to the current scan signal;

The second pull-down maintenance unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

The gate and source of the twelfth transistor and the source of the thirteenth transistor are electrically connected to the second low-frequency clock signal; the drain of the twelfth transistor and the thirteenth transistor The gate of the transistor and the drain of the fourteenth transistor are electrically connected; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor and the The gate of the seventeenth transistor is electrically connected; the gate of the fourteenth transistor and the gate of the fifteenth transistor are both electrically connected to the first node; the source of the fourteenth transistor , The source of the fifteenth transistor and the source of the sixteenth transistor are both electrically connected to the second reference low-level signal; the source of the seventeenth transistor is electrically connected to the The first reference low-level signal; the drain of the sixteenth transistor is electrically connected to the first node; the drain of the seventeenth transistor is electrically connected to the current scan signal.
The GOA circuit according to claim 8, wherein the period of the first high-frequency clock signal is the same as the period of the second high-frequency clock signal, and the first high-frequency clock signal and the second high-frequency clock signal The phase difference between frequency clock signals is not zero.
The GOA circuit according to claim 8, wherein the potential of the first reference low-level signal is smaller than the potential of the second reference low-level signal.
A display panel includes a GOA circuit, the GOA circuit includes: a multi-level cascaded GOA unit, each level of GOA unit includes: a pull-up control module, a download module, a pull-up module, a pull-down module, pull-down maintenance Module and bootstrap capacitor;

The pull-up control module accesses the upper-level transmission signal and the upper-level scanning signal, and is electrically connected to the first node, and is used to connect the upper-level transmission signal under the control of the upper-level transmission signal The scan signal is output to the first node;

The download module is connected to a first high-frequency clock signal, and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;

The pull-up module is connected to the first high-frequency clock signal, and is electrically connected to the first node, and is used to output a current-level scan signal under the potential control of the first node;

The pull-down module is connected to the next-level scan signal, the second high-frequency clock signal, and the first reference low-level signal, and is electrically connected to the first node and the current-level scan signal for use in the Under the control of the next-level scan signal, the high potential of the second high-frequency clock signal is output to the first node, and the potential of the current-level scan signal is pulled down to the low of the first high-frequency clock signal Potential

The pull-down maintenance module accesses the first low-frequency clock signal, the second low-frequency clock signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the The current level scan signal is used to maintain the potential of the first node at the second reference low level signal after the pull-down module pulls down the potential of the first node and the potential of the current level scan signal A potential, and maintaining the potential of the current scan signal at the potential of the first reference low-level signal;

One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current scan signal.
The display panel of claim 17, wherein the pull-up control module comprises: a first transistor;

The gate of the first transistor is electrically connected to the signal of the upper stage, the source of the first transistor is electrically connected to the scan signal of the upper stage, and the drain of the first transistor is electrically Sexually connected to the first node.
The display panel of claim 17, wherein the download module comprises: a second transistor;

The gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected Transmit signals at this level.
The display panel of claim 17, wherein the pull-up module comprises: a third transistor;

The gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first high-frequency clock signal, and the drain of the third transistor is electrically connected For the scan signal at this level.