CN113889018B

CN113889018B - GOA circuit and display panel

Info

Publication number: CN113889018B
Application number: CN202111208599.4A
Authority: CN
Inventors: 吴小玲
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-10-18
Filing date: 2021-10-18
Publication date: 2023-07-04
Anticipated expiration: 2041-10-18
Also published as: CN113889018A

Abstract

The GOA circuit and the display panel provided by the embodiment of the application comprise an input module, an output control module and an inverter module. The inverter module is of a Darlington structure, so that the high potential of the stable fifth node can be kept, and the high potential output of the enabling signal in the light emitting period is kept; the potential of the first low-level signal is smaller than that of the second low-level signal, so that the phenomenon that the current level transmission signal, the first scanning signal and the second scanning signal cannot vibrate is ensured, and the first node can be prevented from generating a leakage phenomenon; so that the stability of the GOA circuit can be improved.

Description

GOA circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

The grid driving technology (Gate Driveron Array, abbreviated as GOA) of the array substrate integrates a grid driving circuit on the array substrate of the display panel to realize a progressive scanning driving mode, so that a grid driving circuit part can be omitted, the display panel has the advantages of reducing production cost and realizing narrow frame design of the panel, and is used for various displays.

Here, the GOA circuits need to output not only the scan signal but also the enable signal, and thus various GOA circuits need to be provided. In order to reduce the production cost and realize the design of the narrow frame of the panel, the existing panel manufacturer sets a GOA circuit capable of outputting the scanning signal and the enabling signal at the same time, but the enabling signal of the GOA circuit cannot maintain the high-potential output of the enabling signal and has a leakage path, which is not beneficial to the stability of the GOA circuit.

Therefore, how to improve the stability of the output of the GOA circuit is a difficult problem that the existing panel manufacturers need to strive to overcome.

Disclosure of Invention

The embodiment of the application provides a GOA circuit and a display panel, which are used for solving the technical problem that the output of the GOA circuit in the prior art is unstable.

The application provides a GOA circuit, including the GOA unit of multistage level transmission, GOA unit includes: the device comprises an input module, an output control module and an inverter module;

the input module is connected with a high-level signal, a clock control signal, a superior level transmission signal and a first low-level signal, and is electrically connected with a first node, a second node, a third node and a fourth node, and the input module is used for controlling the potentials of the first node, the second node, the third node and the fourth node;

the output module is connected to a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and is electrically connected to the first node, the second node, the third node, the fourth node, the current-stage signal transmission end, a first scanning signal end, a second scanning signal end and a light-emitting control signal end, and is used for outputting the current-stage signal transmission at the current-stage signal transmission end, outputting a first scanning signal at the first scanning signal end, outputting a second scanning signal at the second scanning signal end and outputting a light-emitting control signal at the light-emitting control signal end;

The output control module is connected to the first low-level signal, the second low-level signal and the high-level signal, and is electrically connected to the first node, the second node, the third node, the fourth node, the current level transmission signal end, the first scanning signal end, the second scanning signal end, the light-emitting control signal end and the fifth node, and the output control module is used for controlling the potentials of the first node, the second node, the third node, the fourth node, the current level transmission signal end, the first scanning signal end, the second scanning signal end and the light-emitting control signal end;

the inverter module is connected to the high-level signal and the second low-level signal, and is electrically connected to the first node and the fifth node, and is used for keeping the electric potential of the first node and the electric potential of the fifth node in opposite phases; wherein the potential of the first low-level signal is smaller than the potential of the second low-level signal.

In the GOA circuit provided by the application, the input module includes a first input transistor, a second input transistor, a third input transistor, a fourth input transistor and a fifth output transistor, wherein gates of the first input transistor, the second input transistor, the third input transistor and the fourth input transistor are all connected with the previous-stage transmission signal, sources of the first input transistor, the second input transistor, the third input transistor and the fourth input transistor are all connected with the high-level signal, a drain of the first input transistor is electrically connected with the first node, a drain of the second input transistor is electrically connected with the second node, a drain of the third input transistor is electrically connected with the third node, a drain of the fourth input transistor is electrically connected with the fourth node, a gate of the fifth input transistor is connected with the clock control signal, a source of the fifth input transistor is connected with the low-level signal, and the drain of the fifth input transistor is electrically connected with the first node.

In the GOA circuit provided by the application, the output module includes a sixth input transistor, a seventh input transistor and an eighth input transistor, gates of the sixth input transistor and the seventh input transistor are all connected to the upper-level signal, sources of the sixth input transistor and the seventh input transistor are all connected to the high-level signal, a drain of the sixth input transistor is electrically connected to the first node, a drain of the seventh input transistor is electrically connected to the second node, the third node and the fourth node, a gate of the eighth input transistor is connected to the clock control signal, a source of the eighth input transistor is connected to the first low-level signal, and a drain of the eighth input transistor is electrically connected to the first node.

In the GOA circuit provided by the present application, the output module includes a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a first storage capacitor, a second storage capacitor, a third storage capacitor and a fourth storage capacitor, where a gate of the first output transistor is electrically connected to the first node, a source of the first output transistor is connected to the first clock signal, a drain of the first output transistor is electrically connected to the primary signal terminal, a gate of the second output transistor is electrically connected to the second node, a source of the second output transistor is connected to the second clock signal, a drain of the second output transistor is electrically connected to the first scanning signal terminal, a gate of the third output transistor is electrically connected to the third node, a source of the third output transistor is connected to the third clock signal, a drain of the third output transistor is electrically connected to the second scanning signal terminal, a drain of the fourth output transistor is electrically connected to the first node, a source of the fourth output transistor is electrically connected to the second node, a source of the third output transistor is electrically connected to the second clock signal terminal, a source of the third output transistor is electrically connected to the third node, a source of the third output transistor is electrically connected to the third clock signal, and a third output transistor is electrically connected to the third node, one end of the fourth storage capacitor is electrically connected to the fourth node, and the other end of the fourth storage capacitor is electrically connected to the light-emitting control signal end.

In the GOA circuit provided in the present application, the output control module includes a first output control transistor, a second output control transistor, a third output control transistor, a fourth output control transistor, a fifth output control transistor, a sixth output control transistor, a seventh output control transistor, and an eighth output control transistor, where sources of the first output control transistor, the second output control transistor, the third output control transistor, the fourth output control transistor, the fifth output control transistor, the sixth output control transistor, the seventh output control transistor, and the eighth output control transistor are all electrically connected to the fifth node, sources of the first output control transistor, the third output control transistor, the fifth output control transistor, and the seventh output control transistor are all connected to the first low level signal, sources of the second output control transistor, the fourth output control transistor, and the sixth output control transistor are all electrically connected to the fifth node, drains of the fourth output control transistor, and the eighth output control transistor are electrically connected to the fifth node, the fourth output control transistor, the fifth output control transistor, and the fifth output control transistor are electrically connected to the fifth node, the fifth output control transistor, the fifth output transistor, and the fifth output control transistor are electrically connected to the fifth node, the fifth output transistor, the fifth output control transistor, and the fifth output transistor and the fifth output control transistor are electrically connected to the fifth output gate, the drain electrode of the seventh output control transistor is electrically connected to the fourth node, and the drain electrode of the eighth output control transistor is electrically connected to the light-emitting control signal terminal.

In the GOA circuit provided by the application, the output control module includes a ninth output control transistor, a tenth output control transistor and an eleventh output control transistor, gates of the ninth output control transistor, the tenth output control transistor and the eleventh output control transistor are all electrically connected to the fifth node, a source of the ninth output control transistor is connected to the first low level signal, a source of the tenth output control transistor is connected to the second low level signal, a source of the eleventh output control transistor is connected to the high level signal, a drain of the ninth output control transistor is electrically connected to the first node, the second node, the third node and the fourth node, a drain of the tenth output control transistor is electrically connected to the current level signal end, the first scanning signal end and the second scanning signal end, and a drain of the eleventh output control transistor is electrically connected to the light emitting control signal end.

In the GOA circuit provided by the application, the inverter module includes a first inverter transistor, a second inverter transistor, a third inverter transistor and a fourth inverter transistor, where the gate of the first inverter transistor, the source of the first inverter transistor and the source of the second inverter transistor are all connected to the high-level signal, the drain of the first inverter transistor is electrically connected to a sixth node, the gate of the second inverter transistor is electrically connected to the sixth node, the drain of the second inverter transistor is electrically connected to the fifth node, the gates of the third inverter transistor and the fourth inverter transistor are electrically connected to the first node, the sources of the third inverter transistor and the fourth inverter transistor are all connected to the second low-level signal, the drain of the third inverter transistor is electrically connected to the sixth node, and the drain of the fourth inverter transistor is electrically connected to the fifth node.

In the GOA circuit provided by the application, when the first node is at a high potential, the third inverting transistor and the fourth inverting transistor are turned on, and the fifth node is pulled down to the potential of the second low-level signal.

In the GOA circuit provided by the application, when the first node is at a low potential, the third inverting transistor and the fourth inverting transistor are turned off, the fifth node is pulled up to the potential of the high-level signal, the first node, the second node, the third node and the fourth node are pulled down to the potential of the first low-level signal, and the present-level transmission signal, the first scanning signal and the second scanning signal are pulled down to the potential of the second low-level signal.

Correspondingly, the application further provides a display panel, which comprises a display area and the GOA circuit as claimed in any one of the above, wherein the GOA circuit is integrated on the edge of the display area.

The GOA circuit and the display panel provided by the embodiment of the application comprise an input module, an output control module and an inverter module. The inverter module is of a Darlington structure, so that the high potential of the stable fifth node voltage can be kept, and the high potential output of the light-emitting control signal in the light-emitting period is kept; the output control module is used for enabling the first node, the second node, the third node and the fourth node to maintain the electric potential of the first low-level signal, and also is used for enabling the current level transmission signal, the first scanning signal and the second scanning signal to maintain the electric potential of the second low-level signal, wherein the electric potential of the first low-level signal is smaller than the electric potential of the second low-level signal, so that the current level transmission signal, the first scanning signal and the second scanning signal are ensured not to vibrate, and the first node can be prevented from generating electric leakage phenomenon; so that the stability of the GOA circuit can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a first GOA unit in the GOA circuit according to the embodiment of the present application;

FIG. 4 is a second schematic circuit diagram of a GOA unit in the GOA circuit according to the embodiment of the present application;

FIG. 5 is a schematic diagram of a third GOA unit in the GOA circuit according to the embodiment of the present application;

FIG. 6 is a signal timing diagram corresponding to a first circuit of a GOA unit in the GOA circuit according to the embodiment of the present application;

fig. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and drain of the transistors used herein are symmetrical, so that the source and drain may be interchanged. In the embodiment of the present application, to distinguish between two electrodes of the transistor except the gate, one electrode is referred to as a source electrode and the other electrode is referred to as a drain electrode. The middle terminal of the switching transistor is defined as a gate, the signal input terminal is a drain, and the output terminal is a source according to the form in the figure. In addition, the transistors used in the embodiments of the present application may include two types of P-type transistors and/or N-type transistors, where the P-type transistors are turned on when the gate is at a low level, turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level, and turned off when the gate is at a low level.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present application. As shown in fig. 1, the GOA circuit provided in the embodiment of the present application includes a GOA unit with multiple stages of cascade. Fig. 1 exemplifies an n-1 st level GOA unit, an n-th level GOA unit, and an n+1 th level GOA unit of the hierarchical transmission.

When the nth GOA unit works, the scanning signal output by the nth GOA unit is at a high potential and is used for turning on a transistor switch of each pixel in one row of the display panel and charging a pixel electrode in each pixel through a data signal; the nth stage signaling is used for controlling the operation of the n+1st stage GOA unit; when the n+1th GOA unit works, the scanning signal output by the n+1th GOA unit is at a high potential, and the scanning signal output by the n GOA unit is at a low potential.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a GOA unit in a GOA circuit according to an embodiment of the present application. As shown in fig. 2, the GOA unit includes an input module 101, an output module 102, an output control module 103, and an inverter module 104.

The input module 101 is connected to the high level signal VGH, the clock control signal VE, the upper level signal Cout (n-1), and the first low level signal VSSQ. The input module 101 is electrically connected to the first node QA, the second node QB, the third node QC, and the fourth node QD. The input module 101 is used for controlling the potentials of the first node QA, the second node QB, the third node QC, and the fourth node QD.

The output module 102 is connected to the first clock signal VA, the second clock signal VB, the third clock signal VC and the fourth clock signal VD. The output module 102 is electrically connected to the first node QA, the second node QB, the third node QC, the fourth node QD, the present level transmission signal end QE, the first scan signal end QF, the second scan signal end QG, and the light emission control signal end QH. The output module 102 is configured to output the current-stage signal Cout (n) at the current-stage signal end QE, output the first Scan signal Scan1 at the first Scan signal end QF, output the second Scan signal Scan2 at the second Scan signal end QG, and output the emission control signal EM at the emission control signal end QH.

The output control module 103 accesses the first low level signal VSSQ, the second low level signal VSSG, and the high level signal VGH. The output control module 105 is electrically connected to the first node QA, the second node QB, the third node QC, the fourth node QD, the fifth node QA', the present level transmission signal end QE, the first scan signal end QF, the second scan signal end QG, and the light emission control signal end QH. The output control module 105 is configured to control the first node QA, the second node QB, the third node QC, and the fourth node QD. The current stage transmits the potential of the signal Cout (n), the first Scan signal Scan1, the second Scan signal Scan2, and the emission control signal EM. Wherein, the potential of the first low level signal VSSQ is smaller than the potential of the second low level signal VSSG.

The inverter module 104 accesses the high level signal VGH and the second low level signal VSSG. The inverter module 106 is electrically connected to the first node QA and the fifth node QA'. The inverter module 106 is configured to maintain the potential of the first node QA and the potential of the fifth node QA' in an inverted state.

The output control module 105 may maintain the first node QA, the second node QB, the third node QC, and the fourth node QD at the first low level signal VSSQ, and may maintain the current level of the transmission signal Cout (n), the first Scan signal Scan1, and the second Scan signal Scan2 at the second low level signal VSSG. The potential of the first low level signal VSSQ is smaller than that of the second low level signal VSSG, so that the current level signal Cout (n), the first Scan signal Scan1 and the second Scan signal Scan2 are ensured not to oscillate, the leakage phenomenon of the first node QA can be prevented, and the stability of the GOA circuit can be improved.

It should be noted that, the voltage difference between the first low level signal VSSQ and the second low level signal VSSG is set according to the threshold voltage of the thin film transistor.

Referring to fig. 3, fig. 3 is a schematic diagram of a first circuit of a GOA unit in a GOA circuit according to an embodiment of the present application. As shown in fig. 3, in the GOA circuit provided in the present application, the input module 101 includes a first input transistor T11, a second input transistor T12, a third input transistor T13, a fourth input transistor T14, and a fifth input transistor T15. The gates of the first input transistor T11, the second input transistor T12, the third input transistor T13 and the fourth input transistor T14 are connected to the upper-stage signal Cout (n-1). Sources of the first input transistor T11, the second input transistor T12, the third input transistor T13 and the fourth input transistor T14 are connected to the high level signal VGH. The drain of the first input transistor T11 is electrically connected to the first node QA. The drain of the second input transistor T12 is electrically connected to the second node QB. The drain of the third input transistor T13 is electrically connected to the third node QC. The drain of the fourth input transistor T14 is electrically connected to the fourth node QD. The gate of the fifth input transistor T15 is connected to the clock control signal VE, the source of the fifth input transistor T15 is connected to the first low level signal VSSQ, and the drain of the fifth input transistor T15 is electrically connected to the first node QA.

The output module 102 includes a first output transistor T21, a second output transistor T22, a third output transistor T23, a fourth output transistor T24, a first storage capacitor C1, a second storage capacitor C2, a third storage capacitor C3, and a fourth storage capacitor C4. The gate of the first output transistor T21 is electrically connected to the first node QA, the source of the first output transistor T21 is connected to the first clock signal VA, and the drain of the first output transistor T21 is electrically connected to the current-stage signal transmission terminal QE. The gate of the second output transistor T22 is electrically connected to the second node QB, the source of the second output transistor T22 is connected to the second clock signal VB, and the drain of the second output transistor T22 is electrically connected to the first scan signal terminal QF. The gate of the third output transistor T23 is electrically connected to the third node QC, the source of the third output transistor T23 is connected to the third clock signal VC, and the drain of the third output transistor T23 is electrically connected to the second scan signal terminal QG. The gate of the fourth output transistor T24 is electrically connected to the fourth node QD, the source of the fourth output transistor T24 is connected to the fourth clock signal VD, and the drain of the fourth output transistor T24 is electrically connected to the light emitting control signal terminal QH. One end of the first storage capacitor C1 is electrically connected to the first node QA, and the other end of the first storage capacitor C1 is electrically connected to the current level signal end QE. One end of the second storage capacitor C2 is electrically connected to the second node QB, and the other end of the second storage capacitor C2 is electrically connected to the first scanning signal terminal QF. One end of the third storage capacitor C3 is electrically connected to the third node QC, and the other end of the third storage capacitor C3 is electrically connected to the second scanning signal terminal QG. One end of the fourth storage capacitor C4 is electrically connected to the fourth node QD, and the other end of the fourth storage capacitor C4 is electrically connected to the light emission control signal terminal QH.

The pull-up maintaining module 103 includes a pull-up maintaining transistor T31. The gate of the pull-up maintaining transistor T31 is electrically connected to the fifth node QA', the source of the pull-up maintaining transistor T31 is connected to the high level signal VGH, and the drain of the pull-up maintaining transistor T31 is electrically connected to the light emitting control signal terminal QH.

The output control module 103 includes a first output control transistor T31, a second output control transistor T32, a third output control transistor T33, a fourth output control transistor T34, a fifth output control transistor T35, a sixth output control transistor T36, a seventh output control transistor T37, and an eighth output control transistor T38. The gates of the first output control transistor T31, the second output control transistor T32, the third output control transistor T33, the fourth output control transistor T34, the fifth output control transistor T35, the sixth output control transistor T36, the seventh output control transistor T37 and the eighth output control transistor T38 are electrically connected to the fifth node QA'. Sources of the first output control transistor T31, the third output control transistor T33, the fifth output control transistor T35, and the seventh output control transistor T37 are connected to the first low level signal VSSQ. Sources of the second output control transistor T32, the fourth output control transistor T34, and the sixth output control transistor T36 are connected to the second low level signal VSSG. The source of the eighth output control transistor T38 is connected to the high level signal VGH. The drain of the first output control transistor T31 is electrically connected to the first node QA. The drain of the second output control transistor T32 is electrically connected to the current-stage signal terminal QE. The drain of the third output control transistor T33 is electrically connected to the second node QB. The drain of the fourth output control transistor T34 is electrically connected to the first scan signal terminal QF. The drain of the fifth output control transistor T35 is electrically connected to the third node QC. The drain of the sixth output control transistor T36 is electrically connected to the second scan signal terminal QG. The drain of the seventh output control transistor T37 is electrically connected to the fourth node QD. The drain of the eighth output control transistor T38 is electrically connected to the light-emitting control signal terminal QH.

The inverter module 104 includes a first inverter transistor T41, a second inverter transistor T42, a third inverter transistor T43, and a fourth inverter transistor T44. The gate of the first inverter transistor T41, the source of the first inverter transistor T41 and the source of the second inverter transistor T42 are all connected to the high-level signal VGH, the drain of the first inverter transistor T41 is electrically connected to the sixth node P, the gate of the second inverter transistor T42 is electrically connected to the sixth node P, the drain of the second inverter transistor T42 is electrically connected to the fifth node QA ', the gates of the third inverter transistor T43 and the fourth inverter transistor T44 are all electrically connected to the first node QA, the sources of the third inverter transistor T43 and the fourth inverter transistor T44 are all connected to the second low-level signal VSSG, the drain of the third inverter transistor T43 is electrically connected to the sixth node P, and the drain of the fourth inverter transistor T44 is electrically connected to the fifth node QA'.

It should be noted that, the inverter module 104 has a darlington structure, so that a stable high voltage of the fifth node QA' can be maintained, and a high voltage output of the emission control signal EM during the emission period can be maintained, thereby improving the stability of the GOA circuit.

Note that the first, third, fifth and seventh output control transistors T31, T33, T35 and T37 may pull down the potentials of the first, second, third and fourth nodes QA, QB, QC to the first low level signal VSSQ. The second, fourth and sixth output control transistors T32, T34 and T36 may pull down the potentials of the current-stage transmission signal Cout (n), the first Scan signal Scan1 and the second Scan signal Scan2 to the second low-level signal VSSG. The potential of the first low level signal VSSQ is smaller than that of the second low level signal VSSG, so that the current level signal Cout (n), the first Scan signal Scan1 and the second Scan signal Scan2 are ensured not to oscillate, the leakage phenomenon of the first node QA can be prevented, and the stability of the GOA circuit can be improved.

Specifically, referring to fig. 4, fig. 4 is a second circuit schematic of a GOA unit in the GOA circuit provided in the embodiment of the present application, and the circuit of the GOA unit shown in fig. 4 is different from the circuit of the GOA unit shown in fig. 3 in that: the input module 101 includes a sixth input transistor T16, a seventh input transistor T17, and an eighth input transistor T18. The gates of the sixth input transistor T16 and the seventh input transistor T17 are connected to the upper stage signal Cout (n-1). The sources of the sixth input transistor T16 and the seventh input transistor T17 are connected to the high level signal VGH. The drain of the sixth input transistor T16 is electrically connected to the first node QA. The drain of the seventh input transistor T17 is electrically connected to the second node QB, the third node QC, and the fourth node QD. The gate of the eighth input transistor T18 is connected to the clock control signal VE, the source of the eighth input transistor T18 is connected to the first low level signal VSSQ, and the drain of the eighth input transistor T18 is electrically connected to the first node QA.

It should be noted that, the sixth input transistor T16 may replace the first input transistor T1, the seventh input transistor T17 may replace the second input transistor T12, the third input transistor T13, and the fourth input transistor T14, and the eighth input transistor T18 may replace the fifth input transistor T15, so that the number of transistors is reduced without affecting the function of the input module 101, thereby contributing to reducing the production cost and realizing the design of the narrow frame of the panel.

Specifically, referring to fig. 5, fig. 5 is a second circuit schematic of a GOA unit in the GOA circuit provided in the embodiment of the present application, and the circuit of the GOA unit shown in fig. 5 is different from the circuit of the GOA unit shown in fig. 3 in that: the output control module 103 includes a ninth output control transistor T39 and tenth output control transistor T310 and eleventh output control transistor T311. The gates of the ninth output control transistor T39, the tenth output control transistor T310 and the eleventh output control transistor T311 are electrically connected to the fifth node QA', the source of the ninth output control transistor T39 is connected to the first low level signal VSSQ, the source of the tenth output control transistor T310 is connected to the second low level signal VSSG, the source of the eleventh output control transistor T311 is connected to the high level signal VGH, the drain of the ninth output control transistor T39 is electrically connected to the first node QA, the second node QB, the third node QC and the fourth node QD, the drain of the tenth output control transistor T310 is electrically connected to the current level signal terminal QE, the first scanning signal terminal QF and the second scanning signal terminal QG, and the drain of the eleventh output control transistor T311 is electrically connected to the light emitting control signal terminal QH.

It should be noted that, the ninth output control transistor T39 may replace the first output control transistor T31, the third output control transistor T33, the fifth output control transistor T35, and the seventh output control transistor T37, the tenth output control transistor T310 may replace the second output control transistor T32, the fourth output control transistor T34, and the sixth output control transistor T36, and the eleventh output control transistor T311 may replace the eighth output control transistor T38, so that the number of transistors is reduced without affecting the function of the output control module 105, thereby contributing to reducing the production cost and realizing the narrow frame design of the panel.

Specifically, referring to fig. 6, fig. 6 is a signal timing diagram corresponding to a first circuit of a GOA unit in a GOA circuit according to an embodiment of the present application.

In the P1 stage, the upper stage transmission signal Cout (n-1) is at a high level, the first, second, third and fourth input transistors T11, T12, T13 and T14 are turned on, the first, second, third and fourth nodes QA, QB, QC and QD are charged to a high level, and the first, second, third and fourth output transistors T21, T22, T23 and T24 are turned on, outputting the present stage transmission signal Cout (n), the first, second, scan signals Scan1, scan2 and the emission control signal EM. Meanwhile, since the first node QA is at a high potential, the third and fourth inverting transistors T43 and T44 are turned on, and the fifth node QA' is pulled down to the second low level signal VSSG.

In the P1 stage, the first clock signal VA, the second clock signal VB, the third clock signal VC, and the fourth clock signal VD are all low-level signals, and therefore, the present-stage transmission signal Cout (n), the first Scan signal Scan1, the second Scan signal Scan2, and the emission control signal EM are all low-level signals.

In the P2 stage, the first output transistor T21, the second output transistor T22, the third output transistor T23 and the fourth output transistor T24 are kept in an on state, and the output of the current-stage transmission signal Cout (n), the first Scan signal Scan1, the second Scan signal Scan2 and the emission control signal EM is ensured.

In the P2 stage, the first, second, third and fourth clock signals VA, VB, VC and VD are different in timing, so that the current-stage transmission signal Cout (n), the first, second and emission control signals Scan1, scan2 and EM are different in performance. In addition, each time the current-stage transmission signal Cout (n), the first Scan signal Scan1, the second Scan signal Scan2, and the emission control signal EM become high, the first storage capacitor C1, the second storage capacitor C2, the third storage capacitor C3, and the fourth storage capacitor C4 are bootstrapped to higher voltages, so that the driving capability is enhanced, and the stability of the GOA circuit is further improved.

In the P3 stage, the first node QA, the second node QB, the third node QC and the fourth node QD remain at the high level, so as to ensure the output of the current-stage transmission signal Cout (n), the first Scan signal Scan1, the second Scan signal Scan2 and the emission control signal EM.

In the P3 stage, the current-stage transmission signal Cout (n), the first Scan signal Scan1, and the second Scan signal Scan2 are discharged to the low level under the timing control of the first clock signal VA, the second clock signal VB, and the third clock signal VC. The emission control signal EM is charged to a high level under timing control of the fourth clock signal VD.

In the P4 stage, the clock control signal VE is switched to the high level, the fifth input transistor T15 is turned on, and the first node QA is discharged to the potential of the first low level signal VSSQ. Meanwhile, since the first node QA is at a low potential, the third inverting transistor T43 and the fourth inverting transistor T44 are turned off, the fifth node QA' is pulled up to the potential of the high level signal VGH, the first output control transistor T31, the second output control transistor T32, the third output control transistor T33, the fourth output control transistor T34, the fifth output control transistor T35, the sixth output control transistor T36, the seventh output control transistor T37 and the eighth output control transistor T38 are turned on, the first node QA, the second node QB, the third node QC and the fourth node QD maintain the potential of the first low level signal VSSQ, the present stage transmission signal Cout (n), the first scan signal scan1 and the second scan signal scan2 maintain the potential of the second low level signal VSSG, and the light emission control signal EM maintains the potential of the high level signal VGH.

It should be noted that, the potential of the first low level signal VSSQ is smaller than that of the second low level signal VSSG, so that the current level signal Cout (n), the first Scan signal Scan1 and the second Scan signal Scan2 are ensured not to oscillate, so that the leakage phenomenon of the first node QA can be prevented, and the stability of the GOA circuit can be improved. In addition, since the fifth node QA' can secure a stable high potential in the P4 stage, a stable high potential output of the emission control signal EM can be secured, and thus the stability of the GOA circuit can be improved.

According to the GOA circuit provided by the embodiment of the application, the inverter module is of a Darlington structure, so that the high potential of the stable fifth node voltage can be kept, and the high potential output of a light-emitting control signal in a light-emitting period is kept; the output control module is used for enabling the first node, the second node, the third node and the fourth node to maintain the electric potential of the first low-level signal, and also is used for enabling the current level transmission signal, the first scanning signal and the second scanning signal to maintain the electric potential of the second low-level signal, wherein the electric potential of the first low-level signal is smaller than the electric potential of the second low-level signal, so that the current level transmission signal, the first scanning signal and the second scanning signal are ensured not to vibrate, and the first node can be prevented from generating electric leakage phenomenon; so that the stability of the GOA circuit can be improved.

It should be noted that, as shown in fig. 7, the pixel circuit provided in the embodiment of the present application is a technology understood by those skilled in the art, and will not be described herein.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 8, the display panel includes a display area and a GOA circuit 200 integrally disposed on an edge of the display area 100; the GOA circuit 200 is similar to the GOA circuit described above in structure and principle, and will not be described herein.

The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A GOA circuit comprising a multistage-transferred GOA unit, the GOA unit comprising: the device comprises an input module, an output control module and an inverter module;

2. The GOA circuit of claim 1, wherein the input module comprises a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, and a fifth input transistor, wherein gates of the first input transistor, the second input transistor, the third input transistor, and the fourth input transistor are all connected to the upper level pass signal, sources of the first input transistor, the second input transistor, the third input transistor, and the fourth input transistor are all connected to the high level signal, a drain of the first input transistor is electrically connected to the first node, a drain of the second input transistor is electrically connected to the second node, a drain of the third input transistor is electrically connected to the third node, a drain of the fourth input transistor is electrically connected to the fourth node, a gate of the fifth input transistor is connected to the clock control signal, and a drain of the fifth input transistor is connected to the low level signal.

3. The GOA circuit of claim 1, wherein the output module comprises a sixth input transistor, a seventh input transistor, and an eighth input transistor, gates of the sixth input transistor and the seventh input transistor are both connected to the upper level signal, sources of the sixth input transistor and the seventh input transistor are both connected to the high level signal, a drain of the sixth input transistor is electrically connected to the first node, a drain of the seventh input transistor is electrically connected to the second node, the third node, and the fourth node, a gate of the eighth input transistor is connected to the clock control signal, a source of the eighth input transistor is connected to the first low level signal, and a drain of the eighth input transistor is electrically connected to the first node.

4. The GOA circuit of claim 1, wherein the output module comprises a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a first storage capacitor, a second storage capacitor, a third storage capacitor, and a fourth storage capacitor, wherein a gate of the first output transistor is electrically connected to the first node, a source of the first output transistor is connected to the first clock signal, a drain of the first output transistor is electrically connected to the current-stage signaling terminal, a gate of the second output transistor is electrically connected to the second node, a source of the second output transistor is connected to the second clock signal, a drain of the second output transistor is electrically connected to the first scanning signal terminal, a gate of the third output transistor is electrically connected to the third node, a source of the third output transistor is connected to the third clock signal, a drain of the third output transistor is electrically connected to the second scanning signal terminal, a drain of the fourth output transistor is electrically connected to the first node, a source of the fourth output transistor is electrically connected to the second node, a source of the fourth output transistor is electrically connected to the third scanning signal terminal, a source of the fourth output transistor is electrically connected to the third node, a source of the fourth output transistor is electrically connected to the fourth node, and a source of the fourth output transistor is electrically connected to the third node, the other end of the third storage capacitor is electrically connected to the second scanning signal end, one end of the fourth storage capacitor is electrically connected to the fourth node, and the other end of the fourth storage capacitor is electrically connected to the light-emitting control signal end.

5. The GOA circuit of claim 1, wherein the output control module comprises a first output control transistor, a second output control transistor, a third output control transistor, a fourth output control transistor, a fifth output control transistor, a sixth output control transistor, a seventh output control transistor, and an eighth output control transistor, wherein the gates of the first output control transistor, the second output control transistor, the third output control transistor, the fourth output control transistor, the fifth output control transistor, the sixth output control transistor, the seventh output control transistor, and the eighth output control transistor are all electrically connected to the fifth node, the sources of the first output control transistor, the fifth output control transistor, and the seventh output control transistor are all connected to the first low level signal, the drains of the second output control transistor, the fourth output control transistor, and the sixth output control transistor are all electrically connected to the drain of the first output control transistor, the drain of the fourth output control transistor is electrically connected to the fourth output control transistor, the gates of the fourth output control transistor, the source of the eighth output control transistor is electrically connected to the fifth output control transistor, the source of the fifth output control transistor, and the source of the seventh output control transistor is electrically connected to the fourth output control transistor, the source of the seventh output control transistor is electrically connected to the fourth node, the drain electrode of the sixth output control transistor is electrically connected to the second scan signal terminal, the drain electrode of the seventh output control transistor is electrically connected to the fourth node, and the drain electrode of the eighth output control transistor is electrically connected to the light-emitting control signal terminal.

6. The GOA circuit of claim 1, wherein the output control module comprises a ninth output control transistor, a tenth output control transistor, and an eleventh output control transistor, wherein gates of the ninth output control transistor, the tenth output control transistor, and the eleventh output control transistor are all electrically connected to the fifth node, a source of the ninth output control transistor is connected to the first low level signal, a source of the tenth output control transistor is connected to the second low level signal, a source of the eleventh output control transistor is connected to the high level signal, a drain of the ninth output control transistor is electrically connected to the first node, the second node, the third node, and the fourth node, a drain of the tenth output control transistor is electrically connected to the current stage signal terminal, the first scan signal terminal, and the second scan signal terminal, and a drain of the eleventh output control transistor is electrically connected to the light emitting control signal terminal.

7. The GOA circuit of claim 1, wherein the inverter module comprises a first inverter transistor, a second inverter transistor, a third inverter transistor, and a fourth inverter transistor, wherein the gates of the first inverter transistor, the sources of the first inverter transistor, and the sources of the second inverter transistor are all connected to the high level signal, the drain of the first inverter transistor is electrically connected to a sixth node, the gate of the second inverter transistor is electrically connected to the sixth node, the drain of the second inverter transistor is electrically connected to the fifth node, the gates of the third inverter transistor and the fourth inverter transistor are all electrically connected to the first node, the sources of the third inverter transistor and the fourth inverter transistor are all connected to the second low level signal, the drain of the third inverter transistor is electrically connected to the sixth node, and the drain of the fourth inverter transistor is electrically connected to the fifth node.

8. The GOA circuit of claim 7, wherein the third and fourth inverting transistors are turned on when the first node is at a high potential, and the fifth node is pulled down to a potential of the second low level signal.

9. The GOA circuit of claim 7, wherein when the first node is at a low potential, the third and fourth inverting transistors are turned off, the fifth node is pulled up to the potential of the high level signal, the first, second, third, and fourth nodes are pulled down to the potential of the first low level signal, and the current-level, first, and second scan signals are pulled down to the potential of the second low level signal.

10. A display panel comprising a display area and the GOA circuit of any one of claims 1-9 integrated on an edge of the display area.