WO2020103341A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法

Info

Publication number
WO2020103341A1
WO2020103341A1 PCT/CN2019/074828 CN2019074828W WO2020103341A1 WO 2020103341 A1 WO2020103341 A1 WO 2020103341A1 CN 2019074828 W CN2019074828 W CN 2019074828W WO 2020103341 A1 WO2020103341 A1 WO 2020103341A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
photoresist
notch
exposed
light
Prior art date
Application number
PCT/CN2019/074828
Other languages
English (en)
French (fr)
Inventor
唐甲
任章淳
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020103341A1 publication Critical patent/WO2020103341A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the invention relates to a display panel and a manufacturing method thereof, in particular to a display panel using a top gate metal oxide thin film transistor backplane manufacturing process and a manufacturing method thereof.
  • Flat display devices have many advantages, such as thin body, power saving, no radiation, etc., and are widely used.
  • Existing flat display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and Organic Light Emitting Devices Display, OLED), organic electroluminescent display devices, because they also have self-luminous, no backlight, high contrast, thin thickness, wide viewing angle, fast response, can be used in flexible panels, wide temperature range, structure and process Simpler and other excellent features are considered to be the next-generation flat panel display emerging application technology.
  • Thin film transistors are widely used as switching devices and driving devices in electronic devices.
  • TFTs Thin film transistors
  • LCD liquid crystal display devices
  • OLED organic light emitting display devices
  • EPD electrophoretic display devices
  • the thin film transistor not only requires more than two photomask processes, but the storage capacitor (Cst) of the thin film transistor is formed by a metal layer (gate layer) and an indium tin oxide layer (ITO),
  • the thin film transistor is working, it is easy to cause the light shielding metal layer (LightShieldingMetal) to generate induced charge, which is equivalent to another gate (Gate), and the electric field strength generated by the gate is unstable, which is electrical It can also have uncontrollable effects.
  • An object of the present invention is to provide a display panel and a method of manufacturing the same, using a light-shielding metal layer, a buffer layer, and a semiconductor layer corresponding to the first block of a glass substrate to form a storage capacitor, capable of transferring the induced charge of the storage capacitor, To improve the electrical properties of thin film transistors.
  • an embodiment of the invention provides a method for manufacturing a display panel.
  • the method for manufacturing a display panel includes a semiconductor layer forming step, a light-shielding metal layer is deposited on a glass substrate, and Depositing a buffer layer on the light-shielding metal layer, and then depositing a semiconductor layer on the buffer layer, wherein the semiconductor layer is an indium gallium zinc oxide layer; a photoresist forming step, forming a photoresist on the semiconductor layer, And exposing the photoresist to form a first photoresist layer, a second photoresist layer and a gap, wherein the first photoresist layer is located in a first area of the glass substrate , The second photoresist layer is located in a second section of the glass substrate, the semiconductor layer is exposed at the bottom of the notch; a notch etching step, in the notch, the semiconductor layer is sequentially ,
  • the buffer layer and the light-shielding metal layer are
  • the photoresist in the step of forming the photoresist, is exposed using a half-tone mask as a tool.
  • the semiconductor layer exposed at the bottom of the notch is first wet-etched to expose the buffer layer at the bottom of the notch.
  • the buffer layer exposed at the bottom of the notch is dry-etched to make the The bottom of the notch exposes the light-shielding metal layer.
  • the light-shielding metal layer exposed at the bottom of the notch is wet-etched or dried Etching to expose the glass substrate at the bottom of the notch.
  • the photoresist ashing etching is performed by plasma, so that the second photoresist layer forms two depressions.
  • the first photoresist layer and the second photoresist layer are stripped by a stripping solution.
  • an embodiment of the invention provides a display panel including a glass substrate, a light-shielding metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, and a gate Layer, an interlayer dielectric layer and a source-drain contact layer, wherein the light-shielding metal layer is formed on the glass substrate, the buffer layer is formed on the light-shielding metal layer, and the semiconductor layer is formed on the On the buffer layer; wherein the glass substrate defines a first block and a second block through a notch of a center line, the gate insulating layer is formed on the semiconductor layer corresponding to the second block On, the gate layer is formed on the gate insulating layer, the interlayer dielectric layer is formed on the gate layer, and the source-drain contact layer is formed on the interlayer dielectric layer And the source-drain contact layer contacts the semiconductor layer corresponding to the second block, the light-shielding metal layer corresponding to the second block, and the semiconductor layer corresponding
  • the light-shielding metal layer, the buffer layer and the semiconductor layer corresponding to the first block of the glass substrate are defined as a storage capacitor.
  • the light-shielding metal layer, the buffer layer, the semiconductor layer, the gate insulating layer, and the gate layer corresponding to the second block of the glass substrate And the source-drain contact layer is defined as a thin film transistor.
  • an embodiment of the invention provides a method for manufacturing a display panel.
  • the method for manufacturing a display panel includes a semiconductor layer forming step, a light-shielding metal layer is deposited on a glass substrate, and Depositing a buffer layer on the light-shielding metal layer, and then depositing a semiconductor layer on the buffer layer; a photoresist forming step, forming a photoresist on the semiconductor layer, and exposing the photoresist to expose the light Forming a first photoresist layer, a second photoresist layer and a gap, wherein the first photoresist layer is located in a first area of the glass substrate, and the second photoresist layer is located on the glass In a second block of the substrate, the semiconductor layer is exposed at the bottom of the notch; a notch etching step, in which the semiconductor layer, the buffer layer, and the light-shielding metal layer are sequentially performed in the notch Etching to expose the glass substrate at the
  • the photoresist in the step of forming the photoresist, is exposed using a half-tone mask as a tool.
  • the semiconductor layer exposed at the bottom of the notch is first wet-etched to expose the buffer layer at the bottom of the notch.
  • the buffer layer exposed at the bottom of the notch is dry-etched to make the The bottom of the notch exposes the light-shielding metal layer.
  • the light-shielding metal layer exposed at the bottom of the notch is wet-etched or dried Etching to expose the glass substrate at the bottom of the notch.
  • the photoresist ashing etching is performed by plasma, so that the second photoresist layer forms two depressions.
  • the first photoresist layer and the second photoresist layer are stripped by a stripping solution.
  • an embodiment of the invention provides a display panel including a glass substrate, a light-shielding metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, and a gate Layer, an interlayer dielectric layer and a source-drain contact layer, wherein the light-shielding metal layer is formed on the glass substrate, the buffer layer is formed on the light-shielding metal layer, and the semiconductor layer is formed on the On the buffer layer; wherein the glass substrate defines a first block and a second block through a notch of a center line, the gate insulating layer is formed on the semiconductor layer corresponding to the second block On, the gate layer is formed on the gate insulating layer, the interlayer dielectric layer is formed on the gate layer, and the source-drain contact layer is formed on the interlayer dielectric layer And the source-drain contact layer contacts the semiconductor layer corresponding to the second block, the light-shielding metal layer corresponding to the second block, and the semiconductor layer corresponding
  • the light-shielding metal layer, the buffer layer and the semiconductor layer corresponding to the first block of the glass substrate are defined as a storage capacitor.
  • the light-shielding metal layer, the buffer layer, the semiconductor layer, the gate insulating layer, and the gate layer corresponding to the second block of the glass substrate And the source-drain contact layer is defined as a thin film transistor.
  • the beneficial effect of the present invention is that the present invention uses only a single mask process to form the storage capacitor corresponding to the first block of the glass substrate, the buffer layer and the semiconductor layer into the storage capacitor
  • the light-shielding metal layer is connected to the source-drain contact layer, so that the induced charge of the storage capacitor can be transferred out.
  • the problem that the thin film transistor (TFT) is sensitive to light can also be improved, and the overall manufacturing process is optimized, while saving costs and improving the electrical properties of the TFT.
  • FIG. 1 is a schematic diagram of a preferred embodiment of the display panel of the present invention.
  • FIG. 2 is a flowchart of a preferred embodiment of the method for manufacturing a display panel of the present invention.
  • FIG. 3 is a schematic diagram of the semiconductor layer forming step of the flowchart in FIG. 2.
  • FIG. 4 is a schematic diagram of the photoresist forming step of the flowchart in FIG. 2.
  • 5 to 7 are schematic diagrams of the notch etching step of the flowchart in FIG. 2.
  • FIG. 8 is a schematic diagram of the second photoresist layer etching step of the flowchart in FIG. 2.
  • FIG. 9 is a schematic diagram of the recess etching step of the flowchart in FIG. 2.
  • FIG. 10 is a schematic diagram of the photoresist removal step of the flowchart in FIG. 2.
  • FIG. 11 is a schematic diagram of the gate layer forming step of the flowchart in FIG. 2.
  • FIG. 1 is a schematic diagram of a preferred embodiment of the display panel of the present invention.
  • the display panel includes a glass substrate 2, a light-shielding metal layer 3, a buffer layer 4, a semiconductor layer 5, a gate insulating layer 6, a gate layer 7, an interlayer dielectric layer 8, and a source-drain ⁇ contact ⁇ 9.
  • the present invention will describe in detail the detailed structure, assembling relationship and operation principle of the above-mentioned components of each embodiment in the following.
  • the light-shielding metal layer 3 is formed on the glass substrate 2
  • the buffer layer 4 is formed on the light-shielding metal layer 3
  • the semiconductor layer 5 is formed on the buffer layer 4
  • the semiconductor layer 5 is an Indium Gallium Zinc Oxide (IGZO) layer; wherein the glass substrate 2 defines a first block A1 and a middle line L1 through a notch 101 and A second block A2, the first block A1 and the second block A2 are located on opposite sides of the center line L1 of the gap 101, respectively.
  • IGZO Indium Gallium Zinc Oxide
  • the gate insulating layer 6 is formed on the semiconductor layer 5 corresponding to the second block A2, and the gate layer 7 is formed on the gate insulating layer 6.
  • the interlayer dielectric layer 8 is formed on the gate layer 7, the semiconductor layer 5, the buffer layer 4, the light-shielding metal layer 3, and the glass substrate 2, and the source-drain contact layer 9 Formed on the interlayer dielectric layer 8, and the source-drain contact layer 9 contacts the semiconductor layer 5 corresponding to the second block A2 and the light-shielding metal corresponding to the second block A2 Layer 3 and the semiconductor layer 5 corresponding to the first block A1.
  • the light-shielding metal layer 3, the buffer layer 4 and the semiconductor layer 5 corresponding to the first block A1 of the glass substrate 2 are defined as a memory capacitance.
  • the source-drain contact layer 9 is defined as a thin film transistor.
  • the present invention uses only a single mask process to form the light-shielding metal layer 3, the buffer layer 4 and the semiconductor layer 5 corresponding to the first block A1 of the glass substrate 2 A storage capacitor, and the light-shielding metal layer 3 is connected to the source-drain contact layer 9, so that the induced charge of the storage capacitor can be transferred out.
  • the problem that the thin film transistor (TFT) is sensitive to light can also be improved, and the overall manufacturing process is optimized, while saving costs and improving the electrical properties of the TFT.
  • the manufacturing method includes a semiconductor layer forming step S201, a photoresist forming step S202, a notch etching step S203, a second photoresist layer etching step S204, a recess etching step S205, a photoresist removing step S206, a gate An electrode layer forming step S207 and a source-drain contact layer forming step S208.
  • a semiconductor layer forming step S201 a photoresist forming step S202, a notch etching step S203, a second photoresist layer etching step S204, a recess etching step S205, a photoresist removing step S206, a gate An electrode layer forming step S207 and a source-drain contact layer forming step S208.
  • a light-shielding metal layer 3 is deposited on a glass substrate 2, and a buffer layer 4 is deposited on the light-shielding metal layer 3, Next, a semiconductor layer 5 is deposited on the buffer layer 4.
  • a photoresist 10 is formed on the semiconductor layer 5, and the photoresist is exposed to form a photoresist Notch 101, a first photoresist layer 102 and a second photoresist layer 103, wherein the first photoresist layer 102 is located above a first block A1 of the glass substrate 2, the second photoresist layer 103 is located above a second block A2 of the glass substrate 2, and the semiconductor layer 5 is exposed at the bottom of the notch 101.
  • the photoresist 10 is exposed using a half-tone mask as a tool to form the notch 101.
  • the semiconductor layer 5, the buffer layer 4 and all The light-shielding metal layer 3 is etched to expose the glass substrate 2 at the bottom of the notch 101.
  • the semiconductor layer 5 exposed at the bottom of the notch 101 shown in FIG. 4 is wet-etched to expose the buffer layer 4 shown in FIG. 5 at the bottom of the notch 101;
  • the buffer layer 4 exposed at the bottom of the notch 101 is dry-etched to expose the bottom of the notch 101 as shown in FIG.
  • the second photoresist layer etching step S204 the second photoresist layer 103 is etched so that the second photoresist layer 103 forms two recesses 104 , Wherein the semiconductor layer 5 is exposed at the bottom of the two recesses 104.
  • the photoresist ashing etching is performed by plasma, so that the second photoresist layer 103 forms the two recesses 104.
  • the semiconductor layer 5 exposed at the bottom of the second recess 104 is etched to expose the bottom of the second recess 104 ⁇ Buffer layer 4.
  • the first photoresist layer 102 and the second photoresist layer 103 are removed so as to correspond to the second block
  • the semiconductor layer 5 of A2 is located between the two recesses 104, and the semiconductor layer 5 corresponding to the first block A1 is located on one side of the notch 101.
  • the first photoresist layer 102 and the second photoresist layer 103 are stripped by a stripping solution.
  • a gate insulating layer 6 and a first metal layer are sequentially deposited, and the first metal layer is patterned as a gate Electrode layer 7, then an interlayer dielectric layer 8 is deposited on the gate layer 7, and the interlayer dielectric layer 8 is formed by etching to reach the semiconductor layer 5 and the light-shielding metal layer 3 Multiple grooves 105.
  • the light-shielding metal layer 3, the buffer layer 4 and the semiconductor layer 5 corresponding to the first block A1 of the glass substrate 2 can be defined as a storage capacitor.
  • the source-drain contact layer 9 can be defined as a thin film transistor.
  • the present invention uses only a single mask process to form the light-shielding metal layer 3, the buffer layer 4 and the semiconductor layer 5 corresponding to the first block A1 of the glass substrate 2 A storage capacitor, and the light-shielding metal layer 3 is connected to the source-drain contact layer 9, so that the induced charge of the storage capacitor can be transferred out.
  • the problem that the thin film transistor (TFT) is sensitive to light can also be improved, and the overall manufacturing process is optimized, while saving costs and improving the electrical properties of the TFT.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明公开一种显示面板及其制作方法，所述显示面板包括一玻璃基板、一遮光金属层、一缓冲层、一半导体层、一栅极绝缘层、一栅极层、一层间介电层及一源漏极接触层，利用对应所述玻璃基板的第一区块的所述遮光金属层、所述缓冲层及所述半导体层组成一存储电容，能够将所述存储电容的感应电荷传递出去，以改善薄膜晶体管的电性。

Description

显示面板及其制作方法 技术领域
本发明是有关于一种显示面板及其制作方法，特别是有关于一种使用顶栅极金属氧化物薄膜晶体管背板制程的显示面板及其制作方法。
 背景技术
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display, LCD)及有机电致发光显示器件(Organic Light Emitting Display, OLED)、有机电致发光显示器件由于同时具备自发光，不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异之特性，被认为是下一代的平面显示器新兴应用技术。
薄膜晶体管(TFT)在电子装置中被广泛地作为开关装置和驱动装置使用。具体地，因为薄膜晶体管可形成在玻璃基板或塑料基板上，所以它们通常用在诸如液晶显示装置(LCD)、有机发光显示装置(OLED)、电泳显示装置(EPD)等平板显示装置领域。
然而，所述薄膜晶体管不仅需要二次以上的光罩制程，而且所述薄膜晶体管的存储电容(Cst)是由金属层(栅极层)及铟锡氧化层(Indium Tin Oxide, ITO)形成，当所述薄膜晶体管在工作时，容易造成遮光金属层(LightShieldingMetal)生成感应电荷，等同存在另一个栅极(Gate)，而且所述栅极产生的电场强度不稳定，对整个薄膜晶体管的电性也会产生无法掌控的影响。
 技术问题
本发明的目的在于提供一种显示面板及其制作方法，利用对应玻璃基板的第一区块的遮光金属层、缓冲层及半导体层组成存储电容，能够将所述存储电容的感应电荷传递出去，以改善薄膜晶体管的电性。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
为达成本发明的前述目的，本发明一实施例提供一种显示面板的制作方法，所述显示面板的制作方法包括一半导体层形成步骤，在一玻璃基板上沉积一遮光金属层，又在所述遮光金属层上沉积一缓冲层，接着在所述缓冲层上沉积一半导体层，其中所述半导体层为氧化铟镓锌层；一光阻形成步骤，在所述半导体层形成一光阻，并对所述光阻曝光，使所述光阻形成一第一光阻层、一第二光阻层及一缺口，其中所述第一光阻层位于所述玻璃基板的一第一区块，所述第二光阻层位于所述玻璃基板的一第二区块，所述缺口的底部露出有所述半导体层；一缺口蚀刻步骤，在所述缺口中，依序对所述半导体层、所述缓冲层及所述遮光金属层进行蚀刻，使所述缺口的底部露出有所述玻璃基板；一第二光阻层蚀刻步骤，对所述第二光阻层进行蚀刻，使得所述第二光阻层形成二凹陷，其中所述二凹陷的底部露出有所述半导体层；一凹陷蚀刻步骤，对所述二凹陷的底部露出的所述半导体层进行蚀刻，使所述二凹陷的底部露出有所述缓冲层；一光阻去除步骤，将所述第一光阻层及所述第二光阻层去除，使得对应所述第二区块的所述半导体层位于所述二凹陷之间，对应所述第一区块的所述半导体层位于所述缺口的一侧；一栅极层形成步骤，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着将一层间介电层沉积在所述栅极层上，并且通过蚀刻在所述层间介电层形成到达所述半导体层及所述遮光金属层的多个沟槽；以及一源漏极接触层形成步骤，在所述沟槽沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层。
在本发明的一实施例中，在所述光阻形成步骤中，是利用一半色调掩膜板为工具对所述光阻进行曝光。
在本发明的一实施例中，在所述缺口蚀刻步骤中，先对所述缺口的底部露出的所述半导体层进行湿蚀刻，使所述缺口的底部露出有所述缓冲层。
在本发明的一实施例中，在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述缓冲层时，对所述缺口的底部露出的所述缓冲层进行干蚀刻，使所述缺口的底部露出有所述遮光金属层。
在本发明的一实施例中，在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述遮光金属层时，对所述缺口的底部露出的所述遮光金属层进行湿蚀刻或干蚀刻，使所述缺口的底部露出有所述玻璃基板。
在本发明的一实施例中，在所述第二光阻层蚀刻步骤中，是通过等离子体进行光阻灰化蚀刻，使得所述第二光阻层形成二凹陷。
在本发明的一实施例中，在所述光阻去除步骤中，是通过一剥离液将所述第一光阻层及所述第二光阻层剥离。
为达成本发明的前述目的，本发明一实施例提供一种显示面板，所述显示面板包括一玻璃基板、一遮光金属层、一缓冲层、一半导体层、一栅极绝缘层、一栅极层、一层间介电层及一源漏极接触层，其中所述遮光金属层形成在所述玻璃基板上，所述缓冲层形成在所述遮光金属层上，所述半导体层形成在所述缓冲层上；其中所述玻璃基板通过一缺口的一中线来定义一第一区块及一第二区块，所述栅极绝缘层形成在对应所述第二区块的所述半导体层上，所述栅极层形成在所述栅极绝缘层上，所述层间介电层形成在所述栅极层上，所述源漏极接触层形成在所述层间介电层上，而且所述源漏极接触层接触对应所述第二区块的所述半导体层、对应所述第二区块的所述遮光金属层以及对应所述第一区块的所述半导体层。
在本发明的一实施例中，对应所述玻璃基板的所述第一区块的所述遮光金属层、所述缓冲层及所述半导体层定义为一存储电容。
在本发明的一实施例中，对应所述玻璃基板的所述第二区块的所述遮光金属层、所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极层及所述源漏极接触层定义为一薄膜晶体管。
为达成本发明的前述目的，本发明一实施例提供一种显示面板的制作方法，所述显示面板的制作方法包括一半导体层形成步骤，在一玻璃基板上沉积一遮光金属层，又在所述遮光金属层上沉积一缓冲层，接着在所述缓冲层上沉积一半导体层；一光阻形成步骤，在所述半导体层形成一光阻，并对所述光阻曝光，使所述光阻形成一第一光阻层、一第二光阻层及一缺口，其中所述第一光阻层位于所述玻璃基板的一第一区块，所述第二光阻层位于所述玻璃基板的一第二区块，所述缺口的底部露出有所述半导体层；一缺口蚀刻步骤，在所述缺口中，依序对所述半导体层、所述缓冲层及所述遮光金属层进行蚀刻，使所述缺口的底部露出有所述玻璃基板；一第二光阻层蚀刻步骤，对所述第二光阻层进行蚀刻，使得所述第二光阻层形成二凹陷，其中所述二凹陷的底部露出有所述半导体层；一凹陷蚀刻步骤，对所述二凹陷的底部露出的所述半导体层进行蚀刻，使所述二凹陷的底部露出有所述缓冲层；一光阻去除步骤，将所述第一光阻层及所述第二光阻层去除，使得对应所述第二区块的所述半导体层位于所述二凹陷之间，对应所述第一区块的所述半导体层位于所述缺口的一侧；一栅极层形成步骤，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着将一层间介电层沉积在所述栅极层上，并且通过蚀刻在所述层间介电层形成到达所述半导体层及所述遮光金属层的多个沟槽；以及一源漏极接触层形成步骤，在所述沟槽沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层。
在本发明的一实施例中，在所述光阻形成步骤中，是利用一半色调掩膜板为工具对所述光阻进行曝光。
在本发明的一实施例中，在所述缺口蚀刻步骤中，先对所述缺口的底部露出的所述半导体层进行湿蚀刻，使所述缺口的底部露出有所述缓冲层。
在本发明的一实施例中，在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述缓冲层时，对所述缺口的底部露出的所述缓冲层进行干蚀刻，使所述缺口的底部露出有所述遮光金属层。
在本发明的一实施例中，在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述遮光金属层时，对所述缺口的底部露出的所述遮光金属层进行湿蚀刻或干蚀刻，使所述缺口的底部露出有所述玻璃基板。
在本发明的一实施例中，在所述第二光阻层蚀刻步骤中，是通过等离子体进行光阻灰化蚀刻，使得所述第二光阻层形成二凹陷。
在本发明的一实施例中，在所述光阻去除步骤中，是通过一剥离液将所述第一光阻层及所述第二光阻层剥离。
为达成本发明的前述目的，本发明一实施例提供一种显示面板，所述显示面板包括一玻璃基板、一遮光金属层、一缓冲层、一半导体层、一栅极绝缘层、一栅极层、一层间介电层及一源漏极接触层，其中所述遮光金属层形成在所述玻璃基板上，所述缓冲层形成在所述遮光金属层上，所述半导体层形成在所述缓冲层上；其中所述玻璃基板通过一缺口的一中线来定义一第一区块及一第二区块，所述栅极绝缘层形成在对应所述第二区块的所述半导体层上，所述栅极层形成在所述栅极绝缘层上，所述层间介电层形成在所述栅极层上，所述源漏极接触层形成在所述层间介电层上，而且所述源漏极接触层接触对应所述第二区块的所述半导体层、对应所述第二区块的所述遮光金属层以及对应所述第一区块的所述半导体层。
在本发明的一实施例中，对应所述玻璃基板的所述第一区块的所述遮光金属层、所述缓冲层及所述半导体层定义为一存储电容。
在本发明的一实施例中，对应所述玻璃基板的所述第二区块的所述遮光金属层、所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极层及所述源漏极接触层定义为一薄膜晶体管。
 有益效果
本发明的有益效果为：本发明利用仅单一个光罩制程将对应所述玻璃基板的所述第一区块的所述遮光金属层、所述缓冲层及所述半导体层组成所述存储电容，而且所述遮光金属层与所述源漏极接触层连接，因而能够将所述存储电容的感应电荷传递出去。同时，通过设置所述遮光金属层也能够改善薄膜晶体管(TFT)对于光敏感的问题，整体优化了制程，同时节省成本，改善了TFT电性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明显示面板的一优选实施例的一示意图。
图2是本发明显示面板的制作方法的一优选实施例的一流程图。
图3是图2中的流程图的半导体层形成步骤的一示意图。
图4是图2中的流程图的光阻形成步骤的一示意图。
图5至7是图2中的流程图的缺口蚀刻步骤的一示意图。
图8是图2中的流程图的第二光阻层蚀刻步骤的一示意图。
图9是图2中的流程图的凹陷蚀刻步骤的一示意图。
图10是图2中的流程图的光阻去除步骤的一示意图。
图11是图2中的流程图的栅极层形成步骤的一示意图。
 本发明的实施方式
以上对本发明实施例提供的液晶显示组件进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参照图1所示，为本发明显示面板的一优选实施例的一示意图。所述显示面板包括一玻璃基板2、一遮光金属层3、一缓冲层4、一半导体层5、一栅极绝缘层6、一栅极层7、一层间介电层8以及一源漏极接触层9。本发明将于下文详细说明各实施例上述各组件的细部构造、组装关系及其运作原理。
续参照图1所示，所述遮光金属层3形成在所述玻璃基板2上，所述缓冲层4形成在所述遮光金属层3上，所述半导体层5形成在所述缓冲层4上，在本实施例中，所述半导体层5为氧化铟镓锌层(Indium Gallium Zinc Oxide, IGZO)；其中所述玻璃基板2通过一缺口101的一中线L1来定义一第一区块A1及一第二区块A2，所述第一区块A1及所述第二区块A2分别位于所述缺口101的中线L1的相对两侧。
续参照图1所示，所述栅极绝缘层6形成在对应所述第二区块A2的所述半导体层5上，所述栅极层7形成在所述栅极绝缘层6上，所述层间介电层8形成在所述栅极层7、所述半导体层5、所述缓冲层4、所述遮光金属层3及所述玻璃基板2上，所述源漏极接触层9形成在所述层间介电层8上，而且所述源漏极接触层9接触对应所述第二区块A2的所述半导体层5、对应所述第二区块A2的所述遮光金属层3以及对应所述第一区块A1的所述半导体层5。
续参照图1所示，在本实施例中，对应所述玻璃基板2的所述第一区块A1的所述遮光金属层3、所述缓冲层4及所述半导体层5定义为一存储电容。对应所述玻璃基板2的所述第二区块A2的所述遮光金属层3、所述缓冲层4、所述半导体层5、所述栅极绝缘层6、所述栅极层7及所述源漏极接触层9定义为一薄膜晶体管。
如上所述，本发明利用仅单一个光罩制程将对应所述玻璃基板2的所述第一区块A1的所述遮光金属层3、所述缓冲层4及所述半导体层5组成所述存储电容，而且所述遮光金属层3与所述源漏极接触层9连接，因而能够将所述存储电容的感应电荷传递出去。同时，通过设置所述遮光金属层3也能够改善薄膜晶体管(TFT)对于光敏感的问题，整体优化了制程，同时节省成本，改善了TFT电性。
请参照图2并配合图1、3至11所示，为本发明显示面板的制作方法的一优选实施例的一流程图。所述制造方法包括一半导体层形成步骤S201、一光阻形成步骤S202、一缺口蚀刻步骤S203、一第二光阻层蚀刻步骤S204、一凹陷蚀刻步骤S205、一光阻去除步骤S206、一栅极层形成步骤S207及一源漏极接触层形成步骤S208。本发明将于下文详细说明各步骤的关系及其运作原理。
续请参照图2并配合图3所示，在所述半导体层形成步骤S201中，在一玻璃基板2上沉积一遮光金属层3，又在所述遮光金属层3上沉积一缓冲层4，接着在所述缓冲层4上沉积一半导体层5。
续请参照图2并配合图4所示，在所述光阻形成步骤S202中，在所述半导体层5形成一光阻10，并对所述光阻进行曝光，使所述光阻形成一缺口101、一第一光阻层102及一第二光阻层103，其中所述第一光阻层102位于所述玻璃基板2的一第一区块A1上方，所述第二光阻层103位于所述玻璃基板2的一第二区块A2上方，所述缺口101的底部露出有所述半导体层5。在本实施例中，是利用一半色调掩膜板为工具对所述光阻10进行曝光，以形成所述缺口101。
续请参照图2并配合图4、5、6及7所示，在所述缺口蚀刻步骤S203中，在所述缺口101中，依序对所述半导体层5、所述缓冲层4及所述遮光金属层3进行蚀刻，使所述缺口101的底部露出有所述玻璃基板2。在本实施例中，先对图4所示的所述缺口101的底部露出的所述半导体层5进行湿蚀刻，使所述缺口101的底部露出有如图5所示所述缓冲层4；接着当所述缺口101的底部露出有所述缓冲层4时，对所述缺口101的底部露出的所述缓冲层4进行干蚀刻，使所述缺口101的底部露出有如图6所示所述遮光金属层3；接着当所述缺口101的底部露出有所述遮光金属层3时，对所述缺口101的底部露出的所述遮光金属层3进行湿蚀刻或干蚀刻，使所述缺口101的底部露出有如图7所示所述玻璃基板2。
续请参照图2并配合图8所示，在所述第二光阻层蚀刻步骤S204中，对所述第二光阻层103进行蚀刻，使得所述第二光阻层103形成二凹陷104，其中所述二凹陷104的底部露出有所述半导体层5。在本实施例中，是通过等离子体进行光阻灰化蚀刻，使得所述第二光阻层103形成所述二凹陷104。
续请参照图2并配合图9所示，在所述凹陷蚀刻步骤S205中，对所述二凹陷104的底部露出的所述半导体层5进行蚀刻，使所述二凹陷104的底部露出有所述缓冲层4。
续请参照图2并配合图10所示，在所述光阻去除步骤S206中，将所述第一光阻层102及所述第二光阻层103去除，使得对应所述第二区块A2的所述半导体层5位于所述二凹陷104之间，对应所述第一区块A1的所述半导体层5位于所述缺口101的一侧。在本实施例中，是通过一剥离液将所述第一光阻层102及所述第二光阻层103剥离。
续请参照图2并配合图11所示，在所述栅极层形成步骤S207中，依次沉积一栅极绝缘层6及一第一金属层，并图案化所述第一金属层作为一栅极层7，接着将一层间介电层8沉积在所述栅极层7上，并且通过蚀刻在所述层间介电层8形成到达所述半导体层5以及所述遮光金属层3的多个沟槽105。
续请参照图2并配合图1所示，在所述源漏极接触层形成步骤S208中，在所述多个沟槽105沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层9。因此，对应所述玻璃基板2的所述第一区块A1的所述遮光金属层3、所述缓冲层4及所述半导体层5能定义为一存储电容。对应所述玻璃基板2的所述第二区块A2的所述遮光金属层3、所述缓冲层4、所述半导体层5、所述栅极绝缘层6、所述栅极层7及所述源漏极接触层9能定义为一薄膜晶体管。
如上所述，本发明利用仅单一个光罩制程将对应所述玻璃基板2的所述第一区块A1的所述遮光金属层3、所述缓冲层4及所述半导体层5组成所述存储电容，而且所述遮光金属层3与所述源漏极接触层9连接，因而能够将所述存储电容的感应电荷传递出去。同时，通过设置所述遮光金属层3也能够改善薄膜晶体管(TFT)对于光敏感的问题，整体优化了制程，同时节省成本，改善了TFT电性。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (17)

  1. 一种显示面板的制作方法，其中：所述制作方法包括步骤：
    一半导体层形成步骤，在一玻璃基板上沉积一遮光金属层，又在所述遮光金属层上沉积一缓冲层，接着在所述缓冲层上沉积一半导体层，其中所述半导体层为氧化铟镓锌层；
    一光阻形成步骤，在所述半导体层形成一光阻，并对所述光阻曝光，使所述光阻形成一第一光阻层、一第二光阻层及一缺口，其中所述第一光阻层位于所述玻璃基板的一第一区块，所述第二光阻层位于所述玻璃基板的一第二区块，所述缺口的底部露出有所述半导体层；
    一缺口蚀刻步骤，在所述缺口中，依序对所述半导体层、所述缓冲层及所述遮光金属层进行蚀刻，使所述缺口的底部露出有所述玻璃基板；
    一第二光阻层蚀刻步骤，对所述第二光阻层进行蚀刻，使得所述第二光阻层形成二凹陷，其中所述二凹陷的底部露出有所述半导体层；
    一凹陷蚀刻步骤，对所述二凹陷的底部露出的所述半导体层进行蚀刻，使所述二凹陷的底部露出有所述缓冲层；
    一光阻去除步骤，将所述第一光阻层及所述第二光阻层去除，使得对应所述第二区块的所述半导体层位于所述二凹陷之间，对应所述第一区块的所述半导体层位于所述缺口的一侧；
    一栅极层形成步骤，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着将一层间介电层沉积在所述栅极层上，并且通过蚀刻在所述层间介电层形成到达所述半导体层及所述遮光金属层的多个沟槽；及
    一源漏极接触层形成步骤，在所述沟槽沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层。
  2. 如权利要求1所述的制作方法，其中：在所述光阻形成步骤中，是利用一半色调掩膜板为工具对所述光阻进行曝光。
  3. 如权利要求1所述的制作方法，其中：在所述缺口蚀刻步骤中，先对所述缺口的底部露出的所述半导体层进行湿蚀刻，使所述缺口的底部露出有所述缓冲层。
  4. 如权利要求3所述的制作方法，其中：在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述缓冲层时，对所述缺口的底部露出的所述缓冲层进行干蚀刻，使所述缺口的底部露出有所述遮光金属层。
  5. 如权利要求4所述的制作方法，其中：在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述遮光金属层时，对所述缺口的底部露出的所述遮光金属层进行湿蚀刻或干蚀刻，使所述缺口的底部露出有所述玻璃基板。
  6. 如权利要求1所述的制作方法，其中：在所述第二光阻层蚀刻步骤中，是通过等离子体进行光阻灰化蚀刻，使得所述第二光阻层形成二凹陷。
  7. 如权利要求1所述的制作方法，其中：在所述光阻去除步骤中，是通过一剥离液将所述第一光阻层及所述第二光阻层剥离。
  8. 一种显示面板，其中：所述显示面板包括一玻璃基板、一遮光金属层、一缓冲层、一半导体层、一栅极绝缘层、一栅极层、一层间介电层及一源漏极接触层，其中所述遮光金属层形成在所述玻璃基板上，所述缓冲层形成在所述遮光金属层上，所述半导体层形成在所述缓冲层上；
    其中所述玻璃基板通过一缺口的一中线来定义一第一区块及一第二区块，所述栅极绝缘层形成在对应所述第二区块的所述半导体层上，所述栅极层形成在所述栅极绝缘层上，所述层间介电层形成在所述栅极层上，所述源漏极接触层形成在所述层间介电层上，而且所述源漏极接触层接触对应所述第二区块的所述半导体层、对应所述第二区块的所述遮光金属层以及对应所述第一区块的所述半导体层。
  9. 如权利要求8所述的显示面板，其中：对应所述玻璃基板的所述第一区块的所述遮光金属层、所述缓冲层及所述半导体层定义为一存储电容。
  10. 如权利要求8所述的显示面板，其中：对应所述玻璃基板的所述第二区块的所述遮光金属层、所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极层及所述源漏极接触层定义为一薄膜晶体管。
  11. 一种显示面板的制作方法，其中：所述制作方法包括步骤：
    一半导体层形成步骤，在一玻璃基板上沉积一遮光金属层，又在所述遮光金属层上沉积一缓冲层，接着在所述缓冲层上沉积一半导体层；
    一光阻形成步骤，在所述半导体层形成一光阻，并对所述光阻曝光，使所述光阻形成一第一光阻层、一第二光阻层及一缺口，其中所述第一光阻层位于所述玻璃基板的一第一区块，所述第二光阻层位于所述玻璃基板的一第二区块，所述缺口的底部露出有所述半导体层；
    一缺口蚀刻步骤，在所述缺口中，依序对所述半导体层、所述缓冲层及所述遮光金属层进行蚀刻，使所述缺口的底部露出有所述玻璃基板；
    一第二光阻层蚀刻步骤，对所述第二光阻层进行蚀刻，使得所述第二光阻层形成二凹陷，其中所述二凹陷的底部露出有所述半导体层；
    一凹陷蚀刻步骤，对所述二凹陷的底部露出的所述半导体层进行蚀刻，使所述二凹陷的底部露出有所述缓冲层；
    一光阻去除步骤，将所述第一光阻层及所述第二光阻层去除，使得对应所述第二区块的所述半导体层位于所述二凹陷之间，对应所述第一区块的所述半导体层位于所述缺口的一侧；
    一栅极层形成步骤，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着将一层间介电层沉积在所述栅极层上，并且通过蚀刻在所述层间介电层形成到达所述半导体层及所述遮光金属层的多个沟槽；及
    一源漏极接触层形成步骤，在所述沟槽沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层。
  12. 如权利要求11所述的制作方法，其中：在所述光阻形成步骤中，是利用一半色调掩膜板为工具对所述光阻进行曝光。
  13. 如权利要求11所述的制作方法，其中：在所述缺口蚀刻步骤中，先对所述缺口的底部露出的所述半导体层进行湿蚀刻，使所述缺口的底部露出有所述缓冲层。
  14. 如权利要求13所述的制作方法，其中：在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述缓冲层时，对所述缺口的底部露出的所述缓冲层进行干蚀刻，使所述缺口的底部露出有所述遮光金属层。
  15. 如权利要求14所述的制作方法，其中：在所述缺口蚀刻步骤中，当所述缺口的底部露出有所述遮光金属层时，对所述缺口的底部露出的所述遮光金属层进行湿蚀刻或干蚀刻，使所述缺口的底部露出有所述玻璃基板。
  16. 如权利要求11所述的制作方法，其中：在所述第二光阻层蚀刻步骤中，是通过等离子体进行光阻灰化蚀刻，使得所述第二光阻层形成二凹陷。
  17. 如权利要求11所述的制作方法，其中：在所述光阻去除步骤中，是通过一剥离液将所述第一光阻层及所述第二光阻层剥离。
PCT/CN2019/074828 2018-11-21 2019-02-12 显示面板及其制作方法 WO2020103341A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811393924.7A CN109659315B (zh) 2018-11-21 2018-11-21 显示面板及其制作方法
CN201811393924.7 2018-11-21

Publications (1)

Publication Number Publication Date
WO2020103341A1 true WO2020103341A1 (zh) 2020-05-28

Family

ID=66111515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/074828 WO2020103341A1 (zh) 2018-11-21 2019-02-12 显示面板及其制作方法

Country Status (2)

Country Link
CN (1) CN109659315B (zh)
WO (1) WO2020103341A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110289307A (zh) * 2019-06-27 2019-09-27 京东方科技集团股份有限公司 薄膜晶体管驱动背板及其制备方法、显示面板
CN110444567B (zh) * 2019-07-26 2021-09-24 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制作方法
CN110504212A (zh) * 2019-08-12 2019-11-26 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制作方法
CN110649037B (zh) * 2019-09-04 2022-05-31 深圳市华星光电半导体显示技术有限公司 一种阵列基板的制备方法及显示面板
CN111370429A (zh) * 2020-03-27 2020-07-03 武汉华星光电技术有限公司 一种显示面板的制备方法、显示面板
TWI774223B (zh) * 2021-02-02 2022-08-11 元太科技工業股份有限公司 電泳顯示裝置及其製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030004782A (ko) * 2001-07-06 2003-01-15 엘지.필립스 엘시디 주식회사 액정표시장치용 어레이기판
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板
CN105097898A (zh) * 2015-06-02 2015-11-25 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100368917C (zh) * 2005-09-27 2008-02-13 广辉电子股份有限公司 液晶显示器的阵列基板及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030004782A (ko) * 2001-07-06 2003-01-15 엘지.필립스 엘시디 주식회사 액정표시장치용 어레이기판
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板
CN105097898A (zh) * 2015-06-02 2015-11-25 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法

Also Published As

Publication number Publication date
CN109659315A (zh) 2019-04-19
CN109659315B (zh) 2020-12-25

Similar Documents

Publication Publication Date Title
WO2020103341A1 (zh) 显示面板及其制作方法
US9368637B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
JP6521534B2 (ja) 薄膜トランジスタとその作製方法、アレイ基板及び表示装置
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
KR102318054B1 (ko) Tft 기판 및 이의 제조 방법
US9171941B2 (en) Fabricating method of thin film transistor, fabricating method of array substrate and display device
US20210126022A1 (en) Array substrate and method for manufacturing same
WO2020056803A1 (zh) 显示面板及其制作方法、显示模组
US10153377B2 (en) Dual-gate thin film transistor and manufacturing method thereof and array substrate
US9142653B2 (en) Method for manufacturing thin-film transistor array substrate
TWI590423B (zh) 顯示裝置
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
JP6440228B2 (ja) 薄膜トランジスタ基板の製造方法
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same
US20170160613A1 (en) Tft substrates, tft transistors and the manufacturing methods thereof
WO2020113856A1 (zh) 阵列基板的制备方法、阵列基板、显示面板和显示装置
WO2019100492A1 (zh) 背沟道蚀刻型tft基板及其制作方法
WO2020019606A1 (zh) Tft阵列基板及其制作方法
JP2017500727A (ja) 薄膜トランジスタ基板の製造方法及び前記方法によって製造された薄膜トランジスタ基板
US10901282B2 (en) Thin film transistor substrate and manufacturing method thereof
US9082664B2 (en) Method for manufacturing thin-film transistor substrate and thin-film transistor substrate manufactured with same
US20200185424A1 (en) Method of fabricating array substrate, array substrate, display panel, and display device
WO2021114398A1 (zh) 显示面板的制造方法及显示面板
WO2019127793A1 (zh) 薄膜晶体管及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19886824

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19886824

Country of ref document: EP

Kind code of ref document: A1