WO2020082623A1 - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

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Publication number
WO2020082623A1
WO2020082623A1 PCT/CN2019/071733 CN2019071733W WO2020082623A1 WO 2020082623 A1 WO2020082623 A1 WO 2020082623A1 CN 2019071733 W CN2019071733 W CN 2019071733W WO 2020082623 A1 WO2020082623 A1 WO 2020082623A1
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Prior art keywords
source
layer
film transistor
thin film
drain
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French (fr)
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朱茂霞
徐洪远
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof.
  • Thin-film transistor liquid crystal display TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the function of thin film transistor TFT is equivalent to a switch tube.
  • a commonly used TFT is a three-terminal device.
  • a semiconductor layer is prepared on a glass substrate, and a source electrode and a drain electrode connected thereto are provided at both ends, and the current applied between the source electrode and the drain electrode is controlled by the voltage applied to the gate electrode.
  • the channel is equivalent to a resistor, and the current is proportional to the channel width-to-length ratio (W / L).
  • W / L channel width-to-length ratio
  • the resistance of the channel needs to be small enough to meet a certain The on-state current and a certain charging rate, but due to the limitation of the pixel aperture ratio, the channel width W cannot be too large, so in order to increase the on-state current, the channel length L is reduced to a trend of designing large-size panels, and the traditional method Due to the limitation of exposure accuracy, which affects the yield, it is impossible to realize ultra-short channel TFTs for large-size panels.
  • the present disclosure provides a thin film transistor and a manufacturing method thereof, which can solve how to shorten the TFT channel length and reduce AS Technical problems with tail.
  • An embodiment of the present disclosure provides a thin film transistor, including:
  • An active layer above the gate insulating layer includes a first convex portion and a second convex portion;
  • a source electrode and a drain electrode located above the active layer the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the first An edge of a convex portion coincides, an edge of the drain and the second convex portion coincide, a region between the source and the drain corresponding to the active layer is a channel, and the length of the channel Less than 2 ⁇ m.
  • An embodiment of the present disclosure provides a thin film transistor, including:
  • An active layer above the gate insulating layer includes a first convex portion and a second convex portion;
  • the region between the poles corresponding to the active layer is a channel.
  • the channel length is less than 2 ⁇ m.
  • the source electrode coincides with the edge of the first convex portion
  • the drain electrode coincides with the edge of the second convex portion
  • Embodiments of the present disclosure provide a method for manufacturing a thin film transistor, including the following steps:
  • S10 forming a gate, a gate insulating layer, an active layer, and a first source-drain metal layer in sequence on the base substrate;
  • S70 Use the second photoresist layer to etch the over-etched area and the second source-drain metal layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode correspond to the The area of the source layer is the channel;
  • S80 Etching the active layer with the second photoresist layer to remove both end regions of the active layer
  • S100 Using the source electrode and the drain electrode as masks to etch the active layer to form a first convex portion and a second convex portion electrically connected to the source electrode and the drain electrode, respectively.
  • the step S10 specifically includes the following steps:
  • S104 Form the first source-drain metal layer on the active layer.
  • the gate insulating layer, the active layer, and the first source-drain metal layer are sequentially formed by methods such as deposition, coating, and sputtering.
  • step S30 a wet etching method is used to etch the first source-drain metal layer under the first photoresist layer The over-etched area is formed.
  • a second source-drain metal layer is formed on the surface of the active layer by methods such as deposition, coating, and sputtering.
  • the first source-drain metal layer and the second source-drain metal layer are made of the same material.
  • the step S50 uses a photoresist stripping solution to strip the first photoresist layer.
  • step S70 a wet etching method is used to etch the over-etched region and the second source-drain metal layer to form the source and Drain.
  • the etching method used in the step S80 is a dry etching method.
  • the step S90 uses a photoresist stripping solution to strip the second photoresist layer.
  • the etching method used in the step S100 is a dry etching method.
  • the present disclosure manufactures the source and drain of the thin film transistor TFT through two patterning processes, and a channel is formed between the source and drain, wherein the channel is over-etched by wet etching
  • the formation of the region not only shortens the channel length of the TFT and improves the channel width-to-length ratio, but also reduces the AS tail in the channel, which improves the electrical performance and light stability of the TFT, thereby increasing the charging rate of the large-size panel.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the disclosure
  • FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • the thin film transistor 100 includes a base substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, and a source 8. Drain 9; the gate 2 is provided on the base substrate 1, the gate insulating layer 3 is provided on the base substrate 1 and covers the gate 2, the active layer 4 is provided on Above the gate insulating layer 3, the active layer 4 includes a first convex portion 41 and a second convex portion 42, the source electrode 8 is disposed above the first convex portion 41, and the drain electrode 9 is disposed on Above the second convex portion 42, that is, the source electrode 8 is electrically connected to the first convex portion 41, and the drain 9 is electrically connected to the second convex portion 42, that is, the source electrode 8 is connected to all A channel 10 is formed in the region corresponding to the active layer 4 between the drain 9, and the length of the channel 10 is less than 2 ⁇ m, which is formed through two patterning processes compared with the thin film
  • the size of the AS tail (not shown in the figure) can be The reduction to 0 ⁇ m effectively improves the light stability of the thin film transistor 100.
  • FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor 100 according to an embodiment of the present disclosure; the The production method includes the following steps:
  • Step S10 forming the gate electrode 2, the gate insulating layer 3, the active layer 4 and the first source-drain metal layer 51 on the base substrate 1 in this order;
  • the gate electrode 2 is formed on the base substrate through a photolithography process, and then the gate electrode 1 and the gate electrode 2 can be selected according to different materials, and the gate electrode can be sequentially formed by deposition, coating, sputtering, etc.
  • the three steps of the insulating layer 3, the active layer 4, and the first source-drain metal layer 51 are as follows:
  • S104 Form the first source-drain metal layer 51 on the active layer 4.
  • This step is the same as the traditional 4mask process, and the structure shown in Figure 3-1 can be obtained by the above preparation method.
  • Step S20 forming a first photoresist layer 61 on the first source-drain metal layer 51;
  • a layer of photoresist may be coated on the first source-drain metal layer 51 formed in step S10, and the photoresist may be exposed using a halftone mask or a gray tone mask After development, the remaining part of the photoresist forms a first photoresist layer 61, and the first photoresist layer 61 corresponds to a region of the first source-drain metal layer 51.
  • Step S30 etching the first photoresist layer 61 on the side of the first source-drain metal layer 51 to form an over-etched region 7;
  • the first source-drain metal layer 51 is etched by a wet etching method to etch away a portion of the first part that is not protected by the first photoresist layer 61 Since the source-drain metal layer 51 is etched isotropically by the wet etching method, the over-etched region 7 is formed under the first photoresist layer 61.
  • Step S40 forming a second source-drain metal layer 52 on the surfaces of the first photoresist layer 61 and the gate insulating layer 3;
  • the surface of the first photoresist layer 61 and the active layer 4 is covered with a second source-drain metal layer 52.
  • the second source-drain metal layer 52 can be deposited, coated, sputtered, etc.
  • the second source-drain metal layer 52 and the first source-drain metal layer 51 can be selected from the same material. Therefore, the preparation process can use the same method, which simplifies the preparation process of the thin film transistor and improves To improve production efficiency and reduce costs.
  • the over-etched area 7 is formed under the first photoresist layer 61, when the second source-drain metal layer 52 is covered, the second source-drain metal layer 52 will be in the over-etched area The thickness of 7 places becomes thinner, and then breaks, forming the structure shown in Figure 3-4.
  • Step S50 stripping the first photoresist layer 61;
  • the first photoresist layer 61 may be removed by a stripping process. As described in step S40, since the second source-drain metal layer 52 breaks at the over-etched region 7, the photoresist stripping liquid may The first photoresist layer 61 is contacted from both sides of the over-etched area 7, and the first photoresist layer 61 is dissolved in the photoresist stripping solution.
  • 3-5 are schematic structural diagrams of the thin film transistor after stripping the first photoresist layer 61.
  • Step S60 forming a second photoresist layer 62 on the over-etched region 7 and the second source-drain metal layer 52;
  • a photoresist may be covered on the surface of the over-etched area 7 and the second source / drain metal layer 52 .
  • a half-tone mask or a gray-tone mask can be used to expose and develop the photoresist, and the remaining part of the photoresist forms a second photoresist layer 62, and the second photoresist layer 62 corresponds to the over-etched area 7 and part of the region of the second source-drain metal layer 52.
  • Step S70 the second photoresist layer 62 is etched into the over-etched region 7 and the second source-drain metal layer 52 to form a source electrode 8 and a drain electrode 9, the source electrode 8 and the drain electrode
  • the region between the poles 9 corresponding to the active layer 4 is a channel;
  • the over-etched area 7 and the second source-drain metal layer 52 are etched by a wet etching method, Etching away part of the over-etched region 7 and part of the second source-drain metal layer 52 that are not protected by the second photoresist layer 62, due to the wet etching method, the material is etched to be isotropic Therefore, a source electrode 8 and a drain electrode 9 can be formed under the second photoresist layer 62, and a region between the source electrode 8 and the drain electrode 9 corresponding to the active layer 4 forms a channel 10.
  • the length of the channel 10 can be greatly shortened, and the length of the channel 10 obtained by this preparation method can be less than 2 ⁇ m
  • the electrical performance of the thin film transistor is improved, and the charging efficiency of the thin film transistor is greatly improved.
  • the edge of the active layer 4 and the source electrode 8 and the drain electrode 9 after the etching process have a certain difference, the active layer 4 protrudes from the source electrode 8, the The AS tail region 11 of the drain 9 has no metal to shield the upper part of the AS tail region 11, so when light is irradiated to the upper part of the thin film transistor, the leakage current will increase, so that the device cannot shut down normally, affecting the thin film transistor performance.
  • Step S80 Etching the active layer 4 with the second photoresist layer 62 to remove both end regions of the active layer 4;
  • a dry etching method may be used, and the active layer 4 is etched using the second photoresist layer 62 as a mask, thereby removing the active layer 4
  • the regions at both ends make the edge of the active layer 4 coincide with the edge of the gate insulating layer 3.
  • Step S90 stripping the second photoresist layer 62;
  • the second photoresist layer 62 uses a stripping process, and a photoresist stripping solution is used to contact the second photoresist layer 62, and The two photoresist layers 62 are dissolved in the photoresist stripping solution.
  • 3-9 are schematic structural diagrams of the thin film transistor after stripping the second photoresist layer 62. as well as
  • Step S100 etching the active layer 4 using the source electrode 8 and the drain electrode 9 as a mask to form a first convex portion 41 and a second electrode electrically connected to the source electrode 8 and the drain electrode 9, respectively Convex part 42.
  • the active layer 4 may be etched using a dry etching method, but the difference is that the step S80 is based on The second photoresist layer 62 is a mask to etch the active layer 4, and in this step S100, the source electrode 8 and the drain electrode 9 formed in the above steps are directly used as a mask, The active layer 4 is etched without the need to provide a mask plate, which simplifies the manufacturing process.
  • the dry etching process is performed directly using the source electrode and the drain electrode as masks. Since the dry etching method etches the material to be anisotropic, the active layer can be formed after the etching process The first convex portion 41 and the second convex portion 42, the edge of the first convex portion coincides with the edge of the source, and the second convex portion coincides with the edge of the drain. Therefore, the AS The length of tail 11 (not shown in the figure) can be reduced to 0 ⁇ m, thereby improving the light stability of the thin film transistor.
  • An embodiment of the present disclosure provides an array substrate including the thin film transistor provided in the above embodiment.
  • the channel length of the thin-film transistor can be reduced, the channel width-to-length ratio is improved, and the AS in the channel can also be made Tail reduction makes the thin film transistor have good electrical performance and light stability. Therefore, the array substrate using the thin film transistor also has good electrical performance and light stability.
  • This embodiment provides a display device including the array substrate provided in Embodiment 5.
  • the thin film transistor used in the array substrate provided in the fifth embodiment is manufactured by two patterning processes to make the source electrode and the drain electrode, the channel length of the thin film transistor can be reduced, the channel width-to-length ratio can be improved, and the trench Intra-AS Tail reduction makes the array substrate using the thin film transistor have good electrical performance and light stability. Therefore, the display device using the array substrate also has good electrical performance.
  • the display device provided in this embodiment may be any product or component with a display function such as a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. .

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Abstract

一种薄膜晶体管（100）及其制造方法，薄膜晶体管（100）包括：衬底基板（1）、栅极（2）、栅绝缘层（3）、有源层（4），有源层（4）包括第一凸部（41）与第二凸部（42），源极（8）与第一凸部（41）电连接，漏极（9）与第二凸部（42）电连接，通过两次构图工艺制作源极（8）和漏极（9），可使沟道（10）长度缩短及沟道（10）内AS tail缩减，提升了薄膜晶体管（100）的电学性能、光照稳定性及大尺寸面板的充电率。

Description

薄膜晶体管及其制造方法 技术领域
本揭示涉及显示技术领域，尤其涉及一种薄膜晶体管及其制造方法。
 背景技术
在薄膜晶体管液晶显示器TFT-LCD（Thin Film Transistor-Liquid Crystal Display）中，薄膜晶体管TFT的功能相当于一个开关管。常用的TFT是三端器件，一般在玻璃基板上制备半导体层，在其两端设置与之相连的源极和漏极，利用施加在栅极上的电压来控制源、漏电极间的电流。
TFT器件工作在线性区，沟道相当于一个电阻，电流和沟道宽长比（W/L）呈正比，为了提升大尺寸面板的充电率，需要沟道的电阻够小才能够满足一定的开态电流和一定的充电率，但是由于像素开口率的限制，沟道宽度W不能过大，所以为了增大开态电流，将沟道长度L缩小成为设计大尺寸面板的趋势，而传统方法由于曝光精度限制而影响良率，所以无法实现大尺寸面板的超短沟道TFT。
现有技术制备薄膜晶体管TFT中，在有源层及源漏极金属层边缘会存在一定差异，将有源层突出源漏极金属层的部分称之为非晶硅尾纤AS tail(Amorphous Silicon tail，简称a-Si tail或AS tail)，目前无法避免会产生AS tail。由于AS tail上部没有金属进行遮光，所以当有光照射到TFT上时，则器件电性会恶化，较明显的是漏电流增加，使得器件无法正常关闭，所以缩减AS tail成为TFT当前设计的主流趋势。
因此，需要提供一种新的薄膜晶体管及其制造方法、阵列基板、显示装置，来解决上述问题。
 技术问题
本揭示提供一种薄膜晶体管及其制造方法，能够解决如何缩短TFT沟道长度及缩减AS tail的技术问题。
 技术解决方案
为解决上述问题，本揭示实施例提供的技术方案如下：
本揭示实施例提供一种薄膜晶体管，包括：
衬底基板；
位于所述衬底基板上的栅极；
位于所述衬底基板上的栅绝缘层，覆盖所述栅极；
位于所述栅绝缘层上方的有源层，所述有源层包括第一凸部与第二凸部；以及
位于所述有源层上方的源极、漏极；所述源极与所述第一凸部电连接，所述漏极与所述第二凸部电连接，所述源极与所述第一凸部的边缘重合，所述漏极与所述第二凸部的边缘重合，所述源极与所述漏极之间对应所述有源层的区域为沟道，所述沟道长度小于2μm。
本揭示实施例提供一种薄膜晶体管，包括：
衬底基板；
位于所述衬底基板上的栅极；
位于所述衬底基板上的栅绝缘层，覆盖所述栅极；
位于所述栅绝缘层上方的有源层，所述有源层包括第一凸部与第二凸部；以及
位于所述有源层上方的源极、漏极；所述源极与所述第一凸部电连接，所述漏极与所述第二凸部电连接，所述源极与所述漏极之间对应所述有源层的区域为沟道。
在本揭示实施例提供的薄膜晶体管中，所述沟道长度小于2μm。
在本揭示实施例提供的薄膜晶体管中，所述源极与所述第一凸部的边缘重合，所述漏极与所述第二凸部的边缘重合。
本揭示实施例提供一种薄膜晶体管的制备方法，包括以下步骤：
S10：在衬底基板上依次形成栅极、栅绝缘层、有源层以及第一源漏极金属层；
S20：在所述第一源漏极金属层上形成第一光阻层；
S30：在所述第一源漏极金属层一侧采用所述第一光阻层刻蚀形成过刻区；
S40：在所述第一光阻层与所述有源层表面形成第二源漏极金属层；
S50：剥离所述第一光阻层；
S60：在所述过刻区及所述第二源漏极金属层上形成第二光阻层；
S70：对所述过刻区及所述第二源漏极金属层采用所述第二光阻层刻蚀形成源极及漏极，所述源极与所述漏极之间对应所述有源层的区域为沟道；
S80：对所述有源层采用所述第二光阻层刻蚀清除所述有源层的两端区域；
S90：剥离所述第二光阻层；以及
S100：对所述有源层采用所述源极、漏极作为掩膜刻蚀形成分别与所述源极、所述漏极电连接的第一凸部与第二凸部。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S10具体包括以下步骤：
S101：在衬底基板上形成所述栅极；
S102：在所述栅极上方形成所述栅绝缘层；
S103：在所述栅绝缘层上形成所述有源层；以及
S104：在所述有源层上形成所述第一源漏极金属层。
在本揭示实施例提供的薄膜晶体管的制备方法中，通过沉积、涂敷、溅射等方法依次形成所述栅绝缘层、有源层、第一源漏极金属层。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S30中，采用湿法刻蚀方法对所述第一源漏极金属层进行刻蚀处理，在所述第一光阻层下方形成所述过刻区。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S40中，通过沉积、涂敷、溅射等方法在所述有源层表面形成第二源漏极金属层。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述第一源漏极金属层与所述第二源漏极金属层选用相同的材料。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S50采用光阻剥离液对所述第一光阻层进行剥离。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S70中采用湿法刻蚀方法对所述过刻区及所述第二源漏极金属层进行刻蚀处理，形成源极与漏极。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S80中采用的刻蚀方法为干法刻蚀方法。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S90采用光阻剥离液对所述第二光阻层进行剥离。
在本揭示实施例提供的薄膜晶体管的制备方法中，所述步骤S100中采用的刻蚀方法为干法刻蚀方法。
 有益效果
本揭示的有益效果：本揭示通过两次构图工艺制作薄膜晶体管TFT的源极和漏极，所述源极和漏极之间形成沟道，其中，所述沟道通过湿法刻蚀过刻区形成，不仅可使TFT沟道长度缩短，提高了沟道宽长比，而且可将沟道内AS tail缩减，提升了TFT的电学性能及光照稳定性，进而提升了大尺寸面板的充电率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例提供的一种薄膜晶体管的结构示意图；
图2为本揭示实施例提供的一种薄膜晶体管的制作方法的流程图；
图3-1~3-10为本揭示实施例提供的一种薄膜晶体管的制作方法的示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以实例本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下 ]、[前]、 [后]、 [左]、 [右]、 [内]、 [外]、 [侧面 ]、[竖直]、[水平]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
实施例一
如图1所示为本揭示实施例提供的一种薄膜晶体管100的结构示意图，所述薄膜晶体管100包括衬底基板1、栅极2、栅绝缘层3、有源层4、源极8、漏极9；所述栅极2设置于所述衬底基板1上，所述栅绝缘层3设置于所述衬底基板1上并覆盖所述栅极2，所述有源层4设置于所述栅绝缘层3上方，所述有源层4包括第一凸部41与第二凸部42，所述源极8设置于所述第一凸部41上方，所述漏极9设置于所述第二凸部42上方，即所述源极8与所述第一凸部41电连接，所述漏极9与所述第二凸部42电连接，即所述源极8与所述漏极9之间对应所述有源层4的区域形成沟道10，所述沟道10长度小于2μm，与由传统制备工艺制成的薄膜晶体管沟道相比，经过两次构图工艺形成所述源极8及所述漏极9，可使该沟道10的沟道长度大大缩短，有效提高了薄膜晶体管100的电学性能。
由于所述源极8与所述第一凸部41的边缘重合，所述漏极9与所述第二凸部42的边缘重合，因此所述AS tail（图中未示出）的尺寸可缩减为0μm,有效提高了该薄膜晶体管100的光照稳定性。
实施例二
如图2为本揭示实施例提供的一种薄膜晶体管100的制作方法的流程图；如图3-1~3-10为本揭示实施例提供的一种薄膜晶体管100的制作方法的示意图；该制作方法具体包括以下步骤：
步骤S10：在衬底基板上1依次形成栅极2、栅绝缘层3、有源层4以及第一源漏极金属层51；
首先通过光刻工艺在所述衬底基板上形成栅极2，接着在所述衬底基板1及栅极2上可根据不同的材料择优选择通过沉积、涂敷、溅射等方法依次形成栅绝缘层3、有源层4、第一源漏极金属层51等三层薄膜，具体步骤如下：
S101：在所述衬底基板1上形成所述栅极2；
S102：在所述栅极2上方形成所述栅绝缘层3，所述栅绝缘层3覆盖所述栅极2；
S103：在所述栅绝缘层3上形成所述有源层4；以及
S104：在所述有源层4上形成所述第一源漏极金属层51。
该步骤与传统的4mask制程相同，通过上述制备方法可得到如图3-1所示的结构。
步骤S20：在所述第一源漏极金属层51上形成第一光阻层61；
如图3-2所示，可在步骤S10中形成的所述第一源漏极金属层51上涂覆一层光阻，利用半色调掩膜版或者灰色调掩膜版对光阻进行曝光以及显影，保留下来的部分光阻形成第一光阻层61，所述第一光阻层61对应部分所述第一源漏极金属层51的区域。
步骤S30：在所述第一源漏极金属层51一侧采用所述第一光阻层61刻蚀形成过刻区7；
如图3-3所示，采用湿法刻蚀方法对所述第一源漏极金属层51进行刻蚀处理，刻蚀掉未被所述第一光阻层61保护的部分所述第一源漏极金属层51，由于湿法刻蚀方法对材料的刻蚀为各向同性，因此在所述第一光阻层61下方形成所述过刻区7。
步骤S40：在所述第一光阻层61与所述栅绝缘层3表面形成第二源漏极金属层52；
在所述第一光阻层61及所述有源层4表面覆盖一层第二源漏极金属层52，所述第二源漏极金属层52可通过沉积、涂敷、溅射等多种方法制备，所述第二源漏极金属层52与所述第一源漏极金属层51可选用相同的材料，因此，制备工艺可采用同一种方式，简化了薄膜晶体管的制备工艺，提高了制作效率，降低了成本。
由于在所述第一光阻层61下方形成有过刻区7，因此当覆盖所述第二源漏极金属层52时，所述第二源漏极金属层52将于所述过刻区7处厚度变薄，进而会发生断裂，形成如图3-4所示的结构。
步骤S50：剥离所述第一光阻层61；
可采用剥离工艺将所述第一光阻层61清除，如步骤S40中所述，由于所述第二源漏极金属层52于所述过刻区7处发生断裂，因此光阻剥离液可从过刻区7处两侧与所述第一光阻层61进行接触，所述第一光阻层61溶解于所述光阻剥离液中。如图3-5为剥离所述第一光阻层61之后的薄膜晶体管的结构示意图。
步骤S60：在所述过刻区7及所述第二源漏极金属层52上形成第二光阻层62；
如图3-6所示，同所述步骤S20中第一光阻层61的制备方法相似，可在所述过刻区7及所述第二源漏极金属层52表面覆盖一层光阻，可利用半色调掩膜版或者灰色调掩膜版对光阻进行曝光以及显影，保留下来的部分光阻形成第二光阻层62，所述第二光阻层62对应所述过刻区7及部分所述第二源漏极金属层52的区域。
步骤S70：对所述过刻区7及所述第二源漏极金属层52采用所述第二光阻层62刻蚀形成源极8及漏极9，所述源极8与所述漏极9之间对应所述有源层4的区域为沟道；
如图3-7所示，同步骤S30中过刻区7的制备方法相似，采用湿法刻蚀方法对所述过刻区7及所述第二源漏极金属层52进行刻蚀处理，刻蚀掉未被所述第二光阻层62保护的部分所述过刻区7及部分所述第二源漏极金属层52，由于湿法刻蚀方法对材料的刻蚀为各向同性，因此在所述第二光阻层62下方可形成源极8与漏极9，所述源极8与漏极9之间对应所述有源层4的区域形成沟道10。由于所述源极8和漏极9通过上述两次构图工艺制作而成，因此所述沟道10的长度可大大缩短，经此制备方法得到的所述沟道10的长度可小于2μm，提升了薄膜晶体管的电学性能，进而大幅提升薄膜晶体管的充电效率。
同时，由于经刻蚀处理后的所述有源层4与所述源极8、所述漏极9的边缘存在一定的差异，所述有源层4存在突出所述源极8、所述漏极9的AS tail 区11，由于所述AS tail 区11上部没有金属进行遮光，因此当有光线照射到薄膜晶体管上部时，将会使漏电流增加，使得器件无法正常关闭，影响薄膜晶体管的性能。
步骤S80：对所述有源层4采用所述第二光阻层62刻蚀清除所述有源层4的两端区域；
如图3-8所示，可采用干法刻蚀方法，同时以所述第二光阻层62为掩膜对所述有源层4进行刻蚀处理，进而清除所述有源层4的两端区域，使所述有源层4的边缘与所述栅绝缘层3的边缘相重合。
步骤S90：剥离所述第二光阻层62；
同步骤S50中剥离所述第一光阻层61的方法相似，所述第二光阻层62采用剥离工艺，利用光阻剥离液与所述第二光阻层62进行接触，将所述第二光阻层62溶解于所述光阻剥离液中。如图3-9为剥离所述第二光阻层62之后的薄膜晶体管的结构示意图。以及
步骤S100：对所述有源层4采用所述源极8、漏极9作为掩膜刻蚀形成分别与所述源极8、所述漏极9电连接的第一凸部41与第二凸部42。
如图3-10所示，同步骤S80中的工艺相似，可采用干法刻蚀方法对所述有源层4进行刻蚀处理，但与之不同的地方在于，所述步骤S80中是以所述第二光阻层62为掩膜对所述有源层4进行刻蚀，而本步骤S100则是直接以上述步骤中形成的所述源极8和所述漏极9为掩膜，对所述有源层4进行刻蚀处理，不需要另外提供掩膜板，简化了制备流程。
同时，直接以所述源极和漏极为掩膜进行干法刻蚀处理，由于干法刻蚀方法对材料的刻蚀为各向异性，因此所述有源层经过刻蚀处理之后可形成所述第一凸部41与所述第二凸部42，所述第一凸部的边缘所述源极的边缘重合、所述第二凸部与所述漏极的边缘重合。因此，所述AS tail 11（图中未示出）的长度可缩减至0μm，进而提高了薄膜晶体管的光照稳定性。
实施例三
本揭示实施例提供一种阵列基板，该阵列基板包括上述实施例提供的薄膜晶体管。
由于上述薄膜晶体管中通过两次构图工艺制作制作源极与漏极，因此可使薄膜晶体管的沟道长度缩减，提高了沟道宽长比，同时可使沟道内AS tail缩减，使得该薄膜晶体管具有良好的电学性能及光照稳定性，因此，利用该薄膜晶体管的阵列基板同样具有良好的电学性能及光照稳定性。
实施例四
本实施例提供一种显示装置，该显示装置包括实施例五提供的阵列基板。
由于实施例五提供的阵列基板所采用的薄膜晶体管，通过两次构图工艺制作制作源极与漏极，因此可使薄膜晶体管的沟道长度缩减，提高了沟道宽长比，同时可使沟道内AS tail缩减，使得利用该薄膜晶体管的阵列基板具有良好的电学性能及光照稳定性。因此，利用该阵列基板的显示装置同样具有良好的电学性能。
在具体实施时，本实施例提供的显示装置可以为液晶面板、电子纸、OLED 面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种薄膜晶体管，包括：
    衬底基板；
    位于所述衬底基板上的栅极；
    位于所述衬底基板上的栅绝缘层，覆盖所述栅极；
    位于所述栅绝缘层上方的有源层，所述有源层包括第一凸部与第二凸部；以及
    位于所述有源层上方的源极、漏极；所述源极与所述第一凸部电连接，所述漏极与所述第二凸部电连接，所述源极与所述第一凸部的边缘重合，所述漏极与所述第二凸部的边缘重合，所述源极与所述漏极之间对应所述有源层的区域为沟道，所述沟道长度小于2μm。
  2. 一种薄膜晶体管，包括：
    衬底基板；
    位于所述衬底基板上的栅极；
    位于所述衬底基板上的栅绝缘层，覆盖所述栅极；
    位于所述栅绝缘层上方的有源层，所述有源层包括第一凸部与第二凸部；以及
    位于所述有源层上方的源极、漏极；所述源极与所述第一凸部电连接，所述漏极与所述第二凸部电连接，所述源极与所述漏极之间对应所述有源层的区域为沟道。
  3. 根据权利要2所述的薄膜晶体管，其中所述沟道长度小于2μm。
  4. 根据权利要求2所述的薄膜晶体管，其中所述源极与所述第一凸部的边缘重合，所述漏极与所述第二凸部的边缘重合。
  5. 一种薄膜晶体管的制备方法，其中包括以下步骤：
    S10：在衬底基板上依次形成栅极、栅绝缘层、有源层以及第一源漏极金属层；
    S20：在所述第一源漏极金属层上形成第一光阻层；
    S30：在所述第一源漏极金属层上采用所述第一光阻层刻蚀形成过刻区；
    S40：在所述第一光阻层与所述有源层表面形成第二源漏极金属层；
    S50：剥离所述第一光阻层；
    S60：在所述过刻区及所述第二源漏极金属层上形成第二光阻层；
    S70：对所述过刻区及所述第二源漏极金属层采用所述第二光阻层刻蚀形成源极及漏极，所述源极与所述漏极之间对应所述有源层的区域为沟道；
    S80：对所述有源层采用所述第二光阻层刻蚀清除所述有源层的两端区域；
    S90：剥离所述第二光阻层；以及
    S100：对所述有源层采用所述源极、漏极作为掩膜刻蚀形成分别与所述源极、所述漏极电连接的第一凸部与第二凸部。
  6. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S10具体包括以下步骤：
    S101：在所述衬底基板上形成所述栅极；
    S102：在所述栅极上方形成所述栅绝缘层；
    S103：在所述栅绝缘层上形成所述有源层；以及
    S104：在所述有源层上形成所述第一源漏极金属层。
  7. 根据权利要求6所述的薄膜晶体管的制备方法，其中通过沉积、涂敷、溅射等方法依次形成所述栅绝缘层、有源层、第一源漏极金属层。
  8. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S30中，采用湿法刻蚀方法对所述第一源漏极金属层进行刻蚀处理，在所述第一光阻层下方形成所述过刻区。
  9. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S40中，通过沉积、涂敷、溅射等方法在所述有源层表面形成第二源漏极金属层。
  10. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述第一源漏极金属层与所述第二源漏极金属层选用相同的材料。
  11. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S50采用光阻剥离液对所述第一光阻层进行剥离。
  12. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S70中采用湿法刻蚀方法对所述过刻区及所述第二源漏极金属层进行刻蚀处理，形成源极与漏极。
  13. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S80中采用的刻蚀方法为干法刻蚀方法。
  14. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S90采用光阻剥离液对所述第二光阻层进行剥离。
  15. 根据权利要求5所述的薄膜晶体管的制备方法，其中所述步骤S100中采用的刻蚀方法为干法刻蚀方法。
PCT/CN2019/071733 2018-10-26 2019-01-15 薄膜晶体管及其制造方法 Ceased WO2020082623A1 (zh)

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