WO2020082245A1 - 单片集成baw谐振器制作方法 - Google Patents

单片集成baw谐振器制作方法 Download PDF

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WO2020082245A1
WO2020082245A1 PCT/CN2018/111496 CN2018111496W WO2020082245A1 WO 2020082245 A1 WO2020082245 A1 WO 2020082245A1 CN 2018111496 W CN2018111496 W CN 2018111496W WO 2020082245 A1 WO2020082245 A1 WO 2020082245A1
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layer
mask
piezoelectric
substrate
grooves
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PCT/CN2018/111496
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English (en)
French (fr)
Inventor
何正宇
徐慧龙
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华为技术有限公司
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Priority to CN201880098865.2A priority Critical patent/CN112913141B/zh
Priority to EP18937563.7A priority patent/EP3863176B1/en
Priority to PCT/CN2018/111496 priority patent/WO2020082245A1/zh
Publication of WO2020082245A1 publication Critical patent/WO2020082245A1/zh
Priority to US17/237,611 priority patent/US20210242848A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/205—Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0421—Modification of the thickness of an element
    • H03H2003/0428—Modification of the thickness of an element of an electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0421—Modification of the thickness of an element
    • H03H2003/0435—Modification of the thickness of an element of a piezoelectric layer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0471—Resonance frequency of a plurality of resonators at different frequencies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0478—Resonance frequency in a process for mass production

Definitions

  • the present application relates to the technical field of resonant devices, in particular to a monolithic integrated BAW resonator and its manufacturing method, filter and terminal.
  • the RF filter is one of the most important components in the RF front-end. Its main function is to pass electromagnetic waves with a specific frequency range. This kind of electromagnetic wave frequency selectivity can be achieved by various technologies, but now it is generally used in mobile phones and other terminals to complete this task by piezoelectric resonators, common piezoelectric resonators such as (Bulk Acoustic Wave, BAW) resonance
  • BAW Bulk Acoustic Wave
  • the embodiments of the present application provide a method for manufacturing a monolithic integrated BAW resonator that can realize multi-band, small size, and simple manufacturing process.
  • An embodiment of the present application provides a method for manufacturing a monolithic integrated BAW resonator.
  • the method includes:
  • Step 1 Prepare an imprinting template, including a pressing plate and a plurality of stamping dies protruding on the surface of the pressing plate, at least two of the plurality of stamping dies are protruding from the surface of the pressing plate The height is different.
  • Step 2 Form a mask material layer on the substrate.
  • the material of the mask material layer is a polymer
  • the substrate is an insulating material including but not limited to silicon dioxide / silicon.
  • Step 3 Using the imprint template, press the mask material layer toward the substrate to imprint a plurality of masks with a depth consistent with the height of the imprint film on the mask material layer Groove.
  • the mask groove may be a through groove penetrating the mask material layer according to different depths, or may be a groove shape with a bottom that does not penetrate.
  • Step 4 Using the mask material layer as a mask, plasma etching the substrate to form a groove on the surface of the substrate corresponding to the positions of the mask grooves. At least two of the grooves have different depths. In this step, the mask groove penetrates through the corresponding groove.
  • Step 5 forming a bottom electrode layer, a piezoelectric layer and a top electrode layer that are sequentially stacked in the several grooves; then, after removing the mask pattern layer, resonators with different frequencies are formed at each groove position ; Wherein, in the direction perpendicular to the substrate, the thickness of the several bottom electrode layers is the same and both are less than the depth of the groove; the thickness of the piezoelectric layer of at least two of the several resonators is different, Or at least two resonators have different top electrode layer thicknesses.
  • an imprint template and a mask pattern layer are used to form a mask, and a plurality of grooves forming the resonator are defined on the substrate, and several grooves are formed At least two of the grooves have different depths, and according to the different depths of the grooves, and using the grooves as the thickness-defining region of the resonator, piezoelectric layers with different thicknesses formed in the grooves by a patterning process Or a top electrode layer with different thicknesses to achieve different center frequencies of the resonator, and then form a multi-band resonator on the same substrate to achieve miniaturization; further, in the method of the present application, imprinting technology is used on the substrate The thickness-defining regions of the (groove) resonators of different depths are directly defined on the top, which can avoid the use of photolithography.
  • each resonator can be realized only by one photolithography process, and it is not necessary for each resonator to go through one photolithography to achieve different thickness of the piezoelectric layer, which greatly simplifies the manufacturing process. Technology, a significant reduction in manufacturing costs.
  • the steps of depositing and forming the bottom electrode layer, the piezoelectric layer and the top electrode layer stacked in sequence in the several grooves include:
  • a same photolithography process is used to form a piezoelectric layer on the bottom electrode layers, so that the thickness of the bottom electrode layer and the piezoelectric layer in each of the grooves The sum is equal to or less than the depth of the groove.
  • the thicknesses of the bottom electrode layers are the same.
  • the thickness of the material layer forming the piezoelectric layer is the same.
  • the piezoelectric layer located in the groove can be realized by increasing or decreasing the overall thickness, that is, several piezoelectric layers have the same thickness; the piezoelectric layer protruding from the groove can also be formed to realize piezoelectric layers of different thicknesses.
  • BAW resonators of different frequencies are realized by top electrode layers of different thicknesses and piezoelectric layers of different thicknesses, respectively. Therefore, in the method of the present application, the center frequency of the resonator can be changed in two ways by changing the thickness of the piezoelectric layer or the thickness of the top electrode layer, thereby improving the flexibility of manufacturing.
  • the same patterning process is used to form a piezoelectric layer on the bottom electrode layers, so that the sum of the thickness of the bottom electrode layer and the piezoelectric layer in each of the grooves is equal to or less than
  • the step of the depth of the groove includes,
  • each piezoelectric material layer protruding from the surface of the substrate provided with grooves;
  • the piezoelectric material layer is polished until the surface of the piezoelectric material layer is flush with the surface of the substrate to form the piezoelectric layer.
  • the thickness of the piezoelectric layer can be made thinner and smoother, and the resonance frequency of the resonator can be increased.
  • the thickness of the piezoelectric material layer formed in the groove is naturally different, and then the piezoelectric material layer is polished based on the surface of the substrate, and finally
  • the steps of depositing and forming the bottom electrode layer, the piezoelectric layer and the top electrode layer stacked in sequence in the several grooves include the steps including,
  • the top electrode material layer is formed through a patterning process to form a top electrode layer on each piezoelectric layer, and the thickness of the top electrode layers is the same.
  • the lateral width of the top electrode layer perpendicular to the thickness direction is the same as the lateral width of the piezoelectric layer.
  • the step of depositing and forming sequentially stacked bottom electrode layers, piezoelectric layers, and top electrode layers in the grooves includes using the mask pattern layer as a mask in the Forming a piezoelectric layer on the bottom electrode layer in several grooves, so that the sum of the thickness of the bottom electrode layer and the piezoelectric layer is less than the depth of the groove, and the thickness of the piezoelectric layers in the several grooves is the same; By making the top electrode layer to achieve the difference in resonance frequency.
  • the slot is full.
  • the lithography process will process the top electrode material base layer to form a top electrode material layer that covers and corresponds to several piezoelectric layers one by one.
  • the thickness of several piezoelectric layers is the same, the thickness of the bottom electrode layer The same, so the thickness of the top electrode material layer is different.
  • the protruding portion of the top electrode material layer is polished until the surface of the top electrode material layer is flush with the surface of the substrate to form the top electrode layer.
  • the bottom electrode layer, the piezoelectric layer, and the top electrode layer are all made of the mask pattern layer as a mask, without the need to replace the mask plate, and without multiple photolithography mask plates, to complete, simplify Processing technology to save costs.
  • Ar + ions are used for etching. Since the mechanism of Ar + ion etching is the etching caused by the physical bombardment of particles, the etching rate of the mask material layer of the polymer and the substrate is basically the same. Under the same etching time, and ensure that the Ar + etching can etch the remaining high polymer in several mask grooves, and can etch the corresponding grooves on the substrate.
  • the imprint template is formed by using quartz material through an ion milling process.
  • the imprint template can be reused, and the height of the stamper can be adjusted according to the size of the resonance frequency required by the resonator to further reduce the manufacturing cost.
  • the materials of the bottom electrode layer and the top electrode layer include but are not limited to metals such as molybdenum, tungsten, aluminum and the like.
  • the material of the piezoelectric layer includes but is not limited to aluminum nitride, lithium niobate and the like.
  • the masking material layer is pressed toward the substrate by using the imprint template, and the plurality of stampers are stamped on the masking material layer into a plurality of depths and a height of the stamping film
  • the uniform mask groove so that the step of forming the mask pattern layer by the mask material layer after removing the imprint template specifically includes:
  • the embossing template After heating the substrate pressed with the embossing template, the embossing template is removed to form a mask pattern layer including a plurality of mask grooves, and the mask grooves are used to remove the mask from the stamper The pattern formed after the film material layer.
  • the imprinting technology is used to make an imprint template that can be reused to define the position and thickness of the resonator, and the piezoelectrics with different thicknesses are directly formed by the photolithography process
  • the layer or top electrode layer several BAW resonators with different frequencies are formed on the same substrate to achieve the requirements of multiple frequency bands and small sizes, and the manufacturing process is simple and the cost is low.
  • FIG. 1 is a flowchart of steps of a method for manufacturing a monolithic integrated BAW resonator of the present application
  • FIG. 2 is a schematic cross-sectional view of an imprint template formed by the monolithic integrated BAW resonator pressing method shown in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of a substrate formed by a monolithic integrated BAW resonator pressing method shown in FIG. 1;
  • FIG. 4a is a schematic cross-sectional view of an imprint template imprinted on a substrate in the monolithic integrated BAW resonator pressing method shown in FIG. 1;
  • FIG. 4b is a schematic cross-sectional view of the substrate after the stamping template in FIG. 4a is removed;
  • FIG. 5 is a schematic cross-sectional view of the substrate including the mask pattern layer after etching in FIG. 4b;
  • FIG. 6 is a schematic cross-sectional view of the monolithic integrated BAW resonator formed in the first embodiment of the monolithic integrated BAW resonator pressing method shown in FIG. 1;
  • FIG. 7 is a schematic cross-sectional view of the monolithic integrated BAW resonator formed in the second embodiment of the monolithic integrated BAW resonator pressing method shown in FIG. 1;
  • 8a, 8b and 9a, 9b are cross-sectional schematic diagrams of the formation process of the monolithic integrated BAW resonator shown in FIG. 6;
  • 10a, 10b, 11a, and 11b are schematic cross-sectional views of layers during the formation of the monolithic integrated BAW resonator shown in FIG.
  • the present application provides a method for manufacturing a monolithic integrated BAW resonator, and a monolithic integrated multi-band BAW resonator capable of miniaturization and a device having the same sandwich sandwich structure as the BAW resonator are used in this embodiment.
  • the BAW resonator is used as an example for illustration.
  • the BAW resonator is suitable for use in filters of terminals such as mobile phones.
  • FIG. 1 is a flowchart of steps of a method for manufacturing a monolithic integrated BAW resonator.
  • the method includes:
  • Step S1 is a schematic cross-sectional view of an imprinting template, providing an imprinting template 10, including a pressing plate 11 and a plurality of stampers protruding on the surface of the stamping plate 11, at least at least There are two stampers with different heights compared to the surface of the pressing plate 11.
  • the pressing plate 11 is in the shape of a flat plate, and the plurality of pressing dies are at least two, and the heights of the two pressing dies are different; in this embodiment, there are two pressing dies, which are the pressing die 121 and the pressing die 122, that is, the following
  • the steps are described by taking two resonators with different frequency bands as examples.
  • the imprint template 10 is formed by using quartz material through an ion milling process.
  • the embossing template 10 can be reused, and the height of the stamper 12 can be adjusted according to the size of the resonance frequency required by the resonator (reducing the large-sized stamper to a smaller thickness) to further reduce the manufacturing cost .
  • a mask material layer 21 is formed on the substrate 20.
  • the material of the mask material layer 21 is a polymer
  • the substrate 20 is flat
  • the material is insulating, including but not limited to silicon dioxide or silicon.
  • the mask material layer 21 is formed by spin coating, specifically on the surface of the substrate 20.
  • the layered polymer is not completely cured and can be shaped.
  • FIG. 4a is a schematic view after pressing the imprint template 10 and the mask material layer 21, and FIG. 4b is a schematic cross-sectional view of the substrate 20 with the imprint template 10 removed.
  • the imprint template press the mask material layer toward the substrate to imprint a plurality of mask grooves with a depth consistent with the height of the imprint film on the mask material layer.
  • the imprint template 10 is used to press the mask material layer 21 toward the substrate 20 to form a mask pattern layer 22, and the plurality of stampers are imprinted on the mask material layer 21 A plurality of mask grooves having a depth consistent with the height of the stamper are formed, and the mask pattern layer 22 includes a mask groove after the stamper is removed.
  • the stamper 121 and the stamper 122 are embossed on the mask material layer 21 into a plurality of mask grooves 211 and mask grooves 212 having a depth consistent with the height of the stamper,
  • the mask groove 211 and the mask groove 212 may be a through groove penetrating the mask material layer 21 according to different depths, or may be a groove shape with a bottom that does not penetrate.
  • This step specifically includes: applying a certain external force to press the mask material layer 21 in the direction of the substrate 20 of the imprint template 10; and inserting the stamper 121 and the stamper 122 from above the surface of the substrate 20 In the mask material layer 21, so that the mask material layer 21 can be better attached to each surface of the stamper 121 and the stamper 122 of the imprint template 10 to form a mask groove 211 and a mask groove of precise size 212.
  • the imprint template 10 After heating the substrate 20 pressed with the imprint template 10, the imprint template 10 is removed to form a mask pattern layer including a plurality of mask grooves, the mask grooves are The pattern formed after the mold leaves the mask material layer 21, that is, the mask material layer 21 forms the mask pattern layer 22.
  • the mask grooves include a mask groove 211 and a mask groove 212.
  • the heating temperature in this step may be a temperature that does not affect the shape of the mask material layer 21 to ensure the size of the mask groove.
  • the mask pattern layer 22 is a schematic diagram of etching the mask; to form the mask material layer of the mask groove, that is, the mask material layer is the mask to the liner
  • the bottom 20 is subjected to plasma etching, so that in the same etching time, grooves corresponding to the positions of the mask grooves 211 and 212 are formed on the surface of the substrate 20, the number At least two of the grooves have different depths, namely groove 23a and groove 23b.
  • the mask grooves 211, 212 and their corresponding grooves 23a and 23b penetrate through, and the depth of the groove 23a is smaller than the depth of the groove 23b.
  • Ar + ions are used for etching.
  • other high-precision physical etching methods may be used, such as He + ion etching. Since the mechanism of Ar + ion etching is etching caused by physical bombardment of particles, the etching rate of the mask material layer 21 and the substrate 20 of the polymer is basically the same. Under the same etching time, the etching depth is guaranteed to be Consistently, it can be ensured that Ar + etching can etch the remaining high polymer in several mask grooves 211 and etch corresponding grooves on the substrate 20; The depth of 212 is different.
  • the etching depth is the same.
  • the grooves 23a and 23b formed on the substrate 20 have different depths.
  • the groove 23a and the groove 23b are defined areas of the position and thickness of the BAW resonator.
  • Step S5 forming a bottom electrode layer, a piezoelectric layer, and a top electrode layer that are sequentially stacked in the several grooves; thereby forming resonators with different frequencies. That is to say, a resonator is formed in each groove, the resonator can protrude from the groove, or can be located inside the groove and flush with the surface where the slot is located, and it can also be located in the groove if the design requires it. Wherein, in a direction perpendicular to the substrate, the thicknesses of the bottom electrode layers are the same and both are smaller than the depth of the groove; at least two of the several resonators have different piezoelectric layer thicknesses, or At least two resonators have different top electrode layer thicknesses.
  • a bottom electrode layer 241, a piezoelectric layer 242, and a top electrode layer 243 that are sequentially stacked are formed in the groove 23a and the groove 23b; further, resonators 24A and resonators of different frequencies are formed at the positions of the groove 23a and the groove 23b 24B; wherein, in the direction perpendicular to the substrate 20, the bottom electrode layer 241 in the groove 23a and the groove 23b has the same thickness and is less than the depth of the groove 23a and the groove 23b; as shown in FIG. 6 As shown; the thickness of the piezoelectric layer 242 of the two resonators 24A and 24B is different, or the top electrode layer 243 of the two resonators 24A and 24B is different as shown in FIG. 7.
  • the imprint template 10 and the mask pattern layer 22 are used to form a mask, and a plurality of grooves forming the resonator are defined on the substrate 20, and the number At least two grooves 23a and 23b have different depths according to the depths of the grooves, and the grooves are used as the thickness-limiting regions of the resonator, and are patterned in the grooves
  • the formed piezoelectric layers with different thicknesses or top electrode layers with different thicknesses realize different center frequencies of the resonators, and then form multi-band resonators on the same substrate 20 to achieve miniaturization.
  • the imprinting technique is used to directly define the thickness-defining region and the lateral region (the length and width of the resonator) of the resonators of different depths (grooves) on the substrate 20, and through the grooves
  • the length and width of the bottom electrode layer, piezoelectric layer, and top electrode layer of the resonator can be determined at once, without the need for multiple photolithography processes to define the length and width of each electrode, and the use of multiple photolithography processes can be avoided, while In the subsequent formation process of the bottom electrode layer, the piezoelectric layer and the top electrode layer, according to different vibration frequencies, the same functional layers of several resonators can be realized by only one photolithography process, and each resonator does not need to be separated
  • the use of one photolithography to achieve different thickness of the piezoelectric layer greatly simplifies the manufacturing process and greatly reduces the manufacturing cost.
  • step S5 it specifically includes:
  • a bottom electrode layer is formed in each groove by using the same photolithography process, specifically, the surface of the mask pattern layer 22 is formed by metal deposition Metals are vapor-deposited in the grooves 23a and 23b, and a bottom electrode layer 241 of metal is formed in the grooves 23a and 23b. As shown in Figure 8a or 10a.
  • a piezoelectric layer is formed on the bottom electrode layers by using the same photolithography process, so that the bottom electrode layer and the piezoelectric layer in each of the grooves The sum of the thicknesses of the layers is equal to or less than the depth of the groove.
  • FIGS. 8b and 9a, 9b an embodiment is shown in FIGS. 8b and 9a, 9b,
  • a photolithographic process is used to form a piezoelectric material layer a1 and a piezoelectric material layer a2 on the bottom electrode layer 241 in the groove 23a and the groove 23b, respectively,
  • the piezoelectric material layer a1 and the piezoelectric material layer a2 protrude from the surface of the substrate 20 where the groove is provided, that is, the piezoelectric material layer a1 and the piezoelectric material layer a2 will extend into the mask groove.
  • the mask pattern layer 22 is removed to expose the portions of the piezoelectric material layer a1 and the piezoelectric material layer a2 that protrude from the surface of the substrate; in this step, the organic solvent will be used to mask the pattern layer 22 Removal, organic solvents such as acetone.
  • the portions of the piezoelectric material layer a1 and the piezoelectric material layer a2 protruding from the substrate surface are polished until the surfaces of the piezoelectric material layer a1 and the piezoelectric material layer a2 and the substrate 20 The surface is flush to shape the piezoelectric layer 242.
  • the thickness of the piezoelectric material layers a1 and a2 filling the groove 23 is naturally different, and then the surface of the substrate 20 provided with the groove is used as a reference to polish
  • the piezoelectric material layers a1, a2, and finally the piezoelectric layers 242 with different thicknesses in the grooves 23a and 23b are formed, and the thickness of the piezoelectric layer 242 can be realized without reducing the thickness of each piezoelectric layer 242 one by one.
  • Different frequency bands the production process is simple.
  • the formation of the underlying electrode layer and the piezoelectric layer can be achieved by using one layer of the mask pattern layer 22, which reduces the process steps of manufacturing the mask, the number of times and the cost of repeating photolithography.
  • a top electrode material layer covering the plurality of piezoelectric layers 242 is deposited on the surface of the substrate 20, specifically, the top electrode material layer is formed by deposition and covered The surface of the substrate 20 and the plurality of piezoelectric layers 242 expose the surface of the groove 23;
  • the top electrode material layer is processed by the same process patterning process to form a top electrode layer 243 on the piezoelectric layer 242 of the groove 23a and the groove 23b, and the two top electrode layers 243 have the same thickness, and the top electrode layer 243 One surface is connected to the surface of the substrate 20, and the other surface is located on a plane parallel to the substrate 20.
  • the lateral width of the top electrode layer 243 perpendicular to the thickness direction is the same as the lateral width of the piezoelectric layer 242.
  • the patterning process includes coating a material layer and making a pattern by etching and developing photolithography.
  • FIGS. 10a and 10b and FIGS. 11a and 11b Another embodiment, as shown in FIGS. 10a and 10b and FIGS. 11a and 11b,
  • the first step is to use the mask pattern layer as a mask to form a bottom layer in the groove 23a and the groove 23b of the substrate 20 shown in FIG. 10a using the same patterning process
  • the electrode layer 241 and the piezoelectric layer 242 are formed on the bottom electrode layer 241 so that the piezoelectric layer 242 in the groove 23a and groove 23b is lower than the surface of the substrate 20, which is the piezoelectric layer Inside the groove, the surface away from the bottom electrode layer is lower than the surface of the substrate 20.
  • the piezoelectric layer 242 in the groove 23a and the groove 23b have the same thickness, and the surface facing the outside of the groove is a horizontal plane to ensure the flatness of the top electrode layer.
  • the second step is to deposit a top electrode material base layer covering the several piezoelectric layers 242 on the surface of the substrate 20 using the mask pattern layer 22 as a mask, specifically by depositing a metal layer Deposit a layer on the surface of the mask pattern layer and the grooves 23a and 23b to cover the surface of the substrate 20 and the top layers of the piezoelectric layers 242 in the grooves 23a and 23b
  • the portion of the electrode material base layer located in the groove 23a and the groove 23b fills the groove 23a and the groove 23b.
  • the thicknesses of several piezoelectric layers 242 are the same, and the thickness of the bottom electrode layer 241 is the same, the thickness of the base layer of the top electrode material in the groove 23a and the groove 23b is different.
  • the mask pattern layer 22 is removed to form the top electrode material layer b protruding from the groove 23a and the groove 23b from the surface of the substrate 20; the thickness of the top electrode material layer b is different.
  • the top electrode material layer b protruding from the surface of the substrate 20 is polished until the surface of the top electrode material layer b is flush with the surface of the substrate 20 to form The top electrode layer 243 is formed. At this time, the outer surface of the top electrode layer 243 is flush with the surface of the substrate 20.
  • the thickness of the bottom electrode layers 241 is the same.
  • the material layer of the piezoelectric layer 242 is formed.
  • the thickness is consistent, and the overall thickness can be increased or decreased to achieve the piezoelectric layer 242 located in the groove, that is, several piezoelectric layers 242 have the same thickness; the piezoelectric layer 242 protruding from the groove can also be formed to achieve Different thickness piezoelectric layers 242.
  • BAW resonators of different frequencies are realized by top electrode layers 243 of different thicknesses and piezoelectric layers 242 of different thicknesses, respectively.
  • the center frequency of the resonator can be changed in two ways by changing the thickness of the piezoelectric layer 242 or the thickness of the top electrode layer 243, thereby improving the flexibility of manufacturing.
  • the materials of the bottom electrode layer 241 and the top electrode layer 243 include but are not limited to metals such as molybdenum, tungsten, aluminum and the like.
  • the material of the piezoelectric layer 242 includes but is not limited to aluminum nitride, lithium niobate, and the like.

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Abstract

一种单片集成BAW谐振器制作方法，包括：准备一压印模板（S1）；在衬底上形成掩膜材料层（S2）；采用所述压印模板向所述衬底方向按压所述掩膜材料层以形成掩膜凹槽（S3）；以形成掩膜凹槽的所述掩膜材料层为掩膜对所述衬底进行等离子刻蚀（S4），在衬底形成与数个掩膜凹槽位置一一对应的凹槽；在所述数个凹槽内形成依次层叠的底层电极层、压电层以及顶层电极层，进而形成不同频率的谐振器（S5）；其中数个底层电极层厚度相同且均小于凹槽的深度，数个谐振器中至少有两个谐振器的压电层厚度不同，或者至少有两个谐振器的顶层电极层厚度不同。

Description

单片集成BAW谐振器制作方法 技术领域
本申请涉及谐振器件技术领域，尤其涉及一种单片集成BAW谐振器及其制作方法、滤波器以及终端。
背景技术
在终端设备尺寸和成本的限制下，射频前端元件的发展趋势必然是小型化和集成化。射频滤波器是射频前端中最重要的元件之一，其主要的功能是通过具有特定频率范围的电磁波。这种对于电磁波频率选择性可以通过各种技术实现，而现在应用于手机等终端中一般是由压电谐振器来完成这一任务，常见的压电谐振器如(Bulk Acoustic Wave，BAW)谐振器，其中，BAW的频率是由压电材料的厚度决定，且中心频率体现了该谐振器的工作频率的不同。而为了能够同时满足多频段、小尺寸、低成本等要求，在单片上能够实现多频率BAW谐振器成为必要的发展趋势。
发明内容
本申请实施例提供一种可以实现多频段、小尺寸、制作工艺简单的单片集成BAW谐振器的制作方法。
本申请实施例提供一种单片集成BAW谐振器制作方法，所述方法包括：
步骤一，准备一压印模板，包括压板及凸设于所述压板表面的多个压模，所述多个压模中至少有两个压模的相较于所述压板表面的凸出的高度不同。
步骤二，在衬底上形成掩膜材料层。本实施例中的掩膜材料层材料为高聚物，所述衬底为绝缘材料包括但不限于二氧化硅/硅。
步骤三，采用所述压印模板，向所述衬底方向按压所述掩膜材料层，以在所述掩膜材料层上压印成多个深度与所述压膜的高度一致的掩膜凹槽。所述掩膜凹槽根据深度不同，可以是贯通掩膜材料层的通槽，也可以是未贯通的有底部的凹槽形态。
步骤四，以所述掩膜材料层为掩膜，对所述衬底进行等离子刻蚀，在所述衬底表面上形成与所述数个掩膜凹槽位置一一对应的凹槽，所述数个凹槽中至少有两个凹槽的深度不同。本步骤中，所述掩膜凹槽与其对应的凹槽贯通。
步骤五，在所述数个凹槽内形成依次层叠的底层电极层、压电层以及顶层电极层；进而使而去除所述掩膜图案层后在每个凹槽位置形成不同频率的谐振器；其中，在垂直于所述衬底方向上，所述数个底层电极层厚度相同且均小于所述凹槽的深度；数个谐振器中至少有两个谐振器的压电层厚度不同，或者至少有两个谐振器的顶层电极层厚度不同。
本申请实施例所述的单片集成BAW谐振器制作方法中，采用压印模板与掩膜图案层形成掩膜，在衬底上定义出形成谐振器的数个凹槽，并且数个凹槽中至少有两个凹槽的深度不同，根据所述凹槽的深度不同，且以所述凹槽为谐振器的厚度限定区，通过图案化工艺在凹槽内形成的厚度不同的压电层或厚度不同的顶层电极层，实现谐振器的不同中心频率，进而在同一个衬底上形成多频段的谐振器，实现小型化；进一步的，本申请的方法中， 采用压印技术在衬底上直接定义出不同深度的(凹槽)谐振器的厚度限定区，可以避免使用光刻工艺，同时在后续的底层电极层、压电层以及顶层电极层形成过程中，根据不同振动频率，数个谐振器的相同功能层只需要一次光刻工艺即可实现，不需要每个谐振器都单独去通过一次光刻来实现压电层厚度不同，大大简化了制作工艺，大幅度降低制造成本。
进一步的，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤，包括：
以所述掩膜图案层为掩膜采用同一道光刻工艺在所述每个凹槽内形成底层电极层，
以所述掩膜图案层为掩膜采用同一道光刻工艺在所述数个底层电极层上形成压电层，使每一所述凹槽内的所述底层电极层和压电层的厚度之和等于或者小于该凹槽的深度。
本步骤中，由于所述数个凹槽中至少有两个凹槽的深度不同，所述数个底层电极层厚度相同，在形成压电层时，形成压电层的材料层的厚度一致，并且可以通过整体厚度的增加或者减少，以实现位于凹槽内的压电层，即数个压电层厚度相同；也可以形成凸出凹槽的压电层以实现不同厚度的压电层。通过这两种方式分别实现通过不同厚度的顶层电极层和通过不同厚度的压电层实现不同频率的BAW谐振器。以使本申请的方法中，可以通过改变压电层的厚度或者顶层电极层的厚度两种方式来改变谐振器的中心频率，提高制作的灵活性。
一实施例中，采用同一道图案化工艺在所述数个底层电极层上形成压电层，使每一所述凹槽内的所述底层电极层和压电层的厚度之和等于或者小于该凹槽的深度的步骤中，包括，
以所述掩膜图案层为掩膜在所述数个底层电极层上形成压电材料层，每一所述压电材料层凸出所述衬底设有凹槽的表面；
去除所述掩膜图案层；
对所述压电材料层进行抛光直至所述压电材料层的表面与所述衬底表面平齐，以形所述成压电层。本实施例中，压电层厚度可以做得较薄和平整，可以提高谐振器的谐振频率。而且本方法中，由于数个凹槽的深度不同，同样厚度的压电材料层在凹槽内形成的厚度就自然不同，再以所述衬底的表面为基准去抛光压电材料层，最后形成不同厚度的压电层，不需要对每个压电层逐个的去光刻减少厚度尺寸，制作工艺简单。
在本实施例基础上，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤，包括步骤中，包括，
在所述衬底的表面上沉积覆盖所述数个压电层的顶层电极材料层，
通过图案化工艺所述顶层电极材料层，以在每一个压电层上形成顶层电极层，且数个顶层电极层厚度相同。所述顶层电极层的与厚度方向垂直的横向宽度与所述压电层的横向宽度相同。本实施例中的数个BAW谐振器是通过压电层的厚度不同来实现谐振频率的不同。
另一种实施方式中，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤中，包括：以所述掩膜图案层为掩膜在所述数个凹槽内底层电极层上形成压电层，使所述底层电极层和压电层的厚度之和小于该凹槽的深度，且所述数个凹槽内的压电层厚度相同；通过制作顶层电极层来实现谐振频率的不同。
以所述掩膜图案层为掩膜在所述数个凹槽内底层电极层上形成压电层，步骤之后还包括：以所述掩膜图案层为掩膜沉积覆盖所述数个凹槽内的压电层的顶层电极材料层，图案化顶层电极材料层后去除所述掩膜图案层，形成由所述凹槽内凸出所述衬底的表面的顶层电极材料层；具体通过沉积金属层的方式在所述掩膜图案层的表面上及凹槽内沉积一层覆盖衬底表面和凹槽内的所述数个压电层顶层电极材料基层，位于凹槽内的部分把凹槽填满。然后光刻工艺将加工顶层电极材料基层，形成覆盖且与数个压电层一一对应的顶层电极材料层，此时由于凹槽的深度不同，数个压电层厚度相同，底层电极层厚度相同，所以顶层电极材料层厚度是不同的。
对所述顶层电极材料层凸出的部分进行抛光直至所述顶层电极材料层的表面与所述衬底表面平齐，以形所述成顶层电极层。本实施例中，制作底层电极层、压电层以及顶层电极层均采用所述掩膜图案层为掩膜，不需要更换掩膜板，不需要多次光刻掩膜板即可完成，简化加工工艺，节省成本。
一种实施方式中，以所述掩膜图案层为掩膜对所述衬底进行等离子刻蚀时，是采用Ar+离子进行刻蚀。由于Ar+离子刻蚀的机理是粒子物理轰击引起的刻蚀，因此对于高聚物的掩膜材料层和衬底的刻蚀速率基本相同。在相同刻蚀时间下，且确保Ar+刻蚀能够将数个掩膜凹槽中残余的高聚物都刻蚀完，并能在衬底上刻蚀出相应的凹槽。
进一步的，所述压印模板采用石英材料通过离子磨冼工艺形成。本申请方法中，所述的压印模板可以重复利用，并且压模的高度可以根据谐振器需要的谐振频率的大小来调整厚度，进一步降低制作成本。
进一步的，所述底层电极层和顶层电极层的材料包括但不限于钼、钨、铝等金属。所述压电层的材料包括但不限于氮化铝、铌酸锂等。
进一步的，采用所述压印模板向所述衬底方向按压所述掩膜材料层，所述多个压模在所述掩膜材料层上压印成多个深度与所述压膜的高度一致的掩膜凹槽，以使去除所述压印模板后所述掩膜材料层形成掩膜图案层的步骤中，具体包括，
施加一定外力给所述压印模板所述衬底方向按压所述掩膜材料层；以使掩膜材料层能够较好地贴附在压印模板的压模各个表面，形成精准尺寸的掩膜凹槽。
将压有所述压印模板的所述衬底进行加热后，去除所述压印模板，以形成包括数个掩膜凹槽的掩膜图案层，所述掩膜凹槽为压模脱离掩膜材料层后形成的图案。
本申请实施例提供的单片集成BAW谐振器制作方法中，采用压印技术，制作可以再重复利用的压印模板对谐振器位置和厚度进行定义，直接通过光刻工艺形成厚度不同的压电层或者顶层电极层，在同一个衬底上形成数个不同频率的BAW谐振器，实现多频段、小尺寸的要求并且制作工艺简单，成本较低。
附图说明
图1是本申请的单片集成BAW谐振器制作方法的步骤流程图；
图2是图1所示单片集成BAW谐振器压方法形成的压印模板的截面示意图；
图3是图1所示单片集成BAW谐振器压方法形成的衬底的截面示意图；
图4a是图1所示单片集成BAW谐振器压方法中压印模板压印在衬底的截面示意图；
图4b是图4a中的压印模板压去除后的衬底的截面示意图；
图5是图4b刻蚀后的包括掩膜图案层的衬底的截面示意图；
图6是图1所示单片集成BAW谐振器压方法第一实施例形成的单片集成BAW谐振器截面示意图；
图7是图1所示单片集成BAW谐振器压方法第二实施例形成的单片集成BAW谐振器截面示意图；
图8a、图8b和图9a、图9b是图6所示单片集成BAW谐振器形成过程的各层截面示意图；
图10a、图10b和图11a、图11b是图7所示单片集成BAW谐振器形成过程的各层截面示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本申请提供一种单片集成BAW谐振器制作方法，制作一种单片集成可以实现小型化的多频段BAW谐振器以及具有与BAW谐振器由相同的三明治夹层结构的器件，本实施例中以BAW谐振器为例进行说明，该BAW谐振器适用于手机等终端的滤波器中。
本实施例中，请参阅图1，为本单片集成BAW谐振器制作方法的步骤流程图，所述方法包括：
步骤S1，一并参阅图2，为压印模板的截面示意图，提供一压印模板10，包括压板11及凸设于所述压板11表面的多个压模，所述多个压模中至少有两个压模的相较于所述压板11表面的凸出的高度不同。所述压板11为平板状，所述多个压模至少为两个，且为两个时高度不同；本实施例中压模为两个，分别为压模121和压模122，也就是以下步骤均以制作两个不同频段的谐振器为例进行说明。
进一步的，所述压印模板10采用石英材料通过离子磨冼工艺形成。本申请方法中，所述的压印模板10可以重复利用，并且压模12的高度可以根据谐振器需要的谐振频率的大小来调整(将大尺寸的压模改小)厚度，进一步降低制作成本。
步骤S2，参阅图3，在衬底20上形成掩膜材料层21。本实施例中的掩膜材料层21材料为高聚物，所述衬底20为平板状且材料为绝缘包括但不限于二氧化硅或硅。所述掩膜材料层21是采用旋涂方式形成，具体是形成在衬底20的表面上，形成层状的高聚物并非完全固化，可以进行形态定型。
步骤S3，如图4a和图4b，图4a为压印模板10与所述掩膜材料层21按压后的示意图，图4b为去除压印模板10的衬底20的截面示意图。采用所述压印模板，向所述衬底方向按压所述掩膜材料层，以在所述掩膜材料层上压印成多个深度与所述压膜的高度一致的掩膜凹槽。具体的，采用所述压印模板10向所述衬底20方向按压所述掩膜材料层21以形成掩膜图案层22，所述多个压模在所述掩膜材料层21上压印成多个深度与所述压模的高度一致的掩膜凹槽，掩膜图案层22包括去除所述压模后的掩膜凹槽。本实施例中，所述压模121和压模122在所述掩膜材料层21上压印成多个深度与所述压模的高度一致的掩膜凹槽211和掩膜凹槽212，掩膜凹槽211和掩膜凹槽212根据深度不同，可以是贯通掩膜材料层 21的通槽，也可以是未贯通的有底部的凹槽形态。
本步骤中，具体包括：施加一定外力给所述压印模板10所述衬底20方向按压所述掩膜材料层21；使压模121和压模122从衬底20的表面上方插入所述掩膜材料层21内，以使掩膜材料层21能够较好地贴附在压印模板10的压模121和压模122各个表面，形成精准尺寸的掩膜凹槽211和掩膜凹槽212。
将压有所述压印模板10的所述衬底20进行加热后，去除所述压印模板10，以形成包括数个掩膜凹槽的掩膜图案层，所述掩膜凹槽为压模脱离掩膜材料层21后形成的图案，即所述掩膜材料层21形成掩膜图案层22。本实施例中，数个掩膜凹槽包括掩膜凹槽211和掩膜凹槽212。本步骤中的加热温度为不影响掩膜材料层21形态的温度即可，以保证掩膜凹槽的尺寸。
步骤S4，请参阅图4b，所述掩膜图案层22为掩膜进行刻蚀的示意图；以形成掩膜凹槽的所述掩膜材料层，即掩膜材料层为掩膜对所述衬底20进行等离子刻蚀，以使在相同的刻蚀时间内，在所述衬底20表面上形成与所述数个与掩膜凹槽211、212位置一一对应的凹槽，所述数个凹槽中至少有两个凹槽的深度不同，为凹槽23a和凹槽23b。本步骤中，所述掩膜凹槽211、212与其对应的凹槽23a和凹槽23b贯通，凹槽23a的深度小于凹槽23b的深度。
参阅图5，本实施例中，以所述掩膜图案层22为掩膜对所述衬底20进行等离子刻蚀时，是采用Ar+离子进行刻蚀。在其他实施方式中，可以采用其他高精度物理刻蚀方法，例如He+离子刻蚀等。由于Ar+离子刻蚀的机理是粒子物理轰击引起的刻蚀，因此对于高聚物的掩膜材料层21和衬底20的刻蚀速率基本相同，在相同刻蚀时间下，保证蚀刻的深度是一致的，可以确保Ar+刻蚀能够将数个掩膜凹槽211中残余的高聚物都刻蚀完并能在衬底20上刻蚀出相应的凹槽；又因为掩膜凹槽211、212的深度不同，在同一个刻蚀步骤中，蚀刻的深度相同，刻蚀贯穿掩膜凹槽211、212后，在所述衬底20上形成的凹槽23a和凹槽23b具有不同深度。所述凹槽23a和凹槽23b即为BAW谐振器的位置及厚度的定义区域。
步骤S5，在所述数个凹槽内形成依次层叠的底层电极层、压电层以及顶层电极层；进而形成不同频率的谐振器。也即是说在每个凹槽内形成谐振器，谐振器可以突出凹槽，也可以位于凹槽内部与槽口所在表面平齐，在设计需要的情况下位于凹槽内也是可以的。其中，在垂直于所述衬底方向上，所述数个底层电极层厚度相同且均小于所述凹槽的深度；数个谐振器中至少有两个谐振器的压电层厚度不同，或者至少有两个谐振器的顶层电极层厚度不同。
具体参阅图6和图7，为本方法制作的单片集成BAW谐振器的两个实施例的截面示意图，
在所述凹槽23a和凹槽23b内形成依次层叠的底层电极层241、压电层242以及顶层电极层243；进而在凹槽23a和凹槽23b位置形成不同频率的谐振器24A和谐振器24B；其中，在垂直于所述衬底20方向上，所述凹槽23a和凹槽23b内的底层电极层241厚度相同且均小于所述凹槽23a和凹槽23b的深度；如图6所示；两个谐振器24A和谐振器24B的压电层242厚度不同，或者如图7所示两个谐振器24A和谐振器24B的顶层电极层243厚 度不同。
本申请实施例所述的单片集成BAW谐振器制作方法中，采用压印模板10与掩膜图案层22形成掩膜，在衬底20上定义出形成谐振器的数个凹槽，并且数个凹槽中至少有两个凹槽23a和凹槽23b的深度不同，根据所述凹槽的深度不同，且以所述凹槽为谐振器的厚度限定区，通过图案化工艺在凹槽内形成的厚度不同的压电层或厚度不同的顶层电极层，实现谐振器的不同中心频率，进而在同一个衬底20上形成多频段的谐振器，实现小型化。进一步的，本申请的方法中，采用压印技术在衬底20上直接定义出不同深度的(凹槽)谐振器的厚度限定区以及横向区域(谐振器的长度和宽度)，并且通过凹槽可以一次性确定谐振器的底层电极层、压电层以及顶层电极层的长度和的宽度，无需多次光刻工艺去定义每一电极的长度和宽度，可以避免使用多次光刻工艺，同时在后续的底层电极层、压电层以及顶层电极层形成过程中，根据不同振动频率，数个谐振器的形同功能层只需要一次光刻工艺即可实现，不需要每个谐振器都单独去通过一次光刻来实现压电层厚度不同，大大简化了制作工艺，大幅度降低制造成本。
进一步的，在所述步骤S5中，具体包括：
第一步，以所述掩膜图案层22为掩膜采用同一道光刻工艺在所述每个凹槽内形成底层电极层，具体是采用蒸镀金属的方式在掩膜图案层22的表面和凹槽23a和凹槽23b内蒸镀金属，进而在凹槽23a和凹槽23b内形成金属的底层电极层241。如图8a或10a所示。
第二步，以所述掩膜图案层为掩膜采用同一光刻工艺在所述数个底层电极层上形成压电层，使每一所述凹槽内的所述底层电极层和压电层的厚度之和等于或者小于该凹槽的深度。本步骤包括两种实施方式
然后去除所述掩膜图案层22，衬底20上形成凹槽23a和凹槽23b，
具体的，一种实施方式，如图8b和图9a、图9b所示，
如图8b，以所述掩膜图案层为掩膜采用图光刻工艺在所述凹槽23a和凹槽23b内的底层电极层241上分别形成压电材料层a1和压电材料层a2，压电材料层a1和压电材料层a2凸出所述衬底20设有凹槽的表面，即压电材料层a1和压电材料层a2会伸入掩膜凹槽内。
如图9a，去除所述掩膜图案层22，露出所述压电材料层a1和压电材料层a2凸出所述衬底表面的部分；本步骤中，将使用机溶剂将掩膜图案层22去除，有机溶剂如丙酮。
如图9b，对所述压电材料层a1和压电材料层a2凸出所述衬底表面的部分进行抛光直至所述压电材料层a1和压电材料层a2的表面与所述衬底20表面平齐，以形所述压电层242。由于凹槽23a和凹槽23b的深度不同，同样厚度的压电材料层a1、a2填满凹槽23的厚度就自然不同，再以所述衬底20设有凹槽的表面为基准去抛光压电材料层a1、a2，最后形成凹槽23a和凹槽23b内的不同厚度的压电层242，不需要对每个压电层242逐个的去光刻减少厚度尺寸就可以实现谐振器的不同频段，制作工艺简单。而且本方法中，采用一层所述掩膜图案层22就可以实现底层电极层和压电层的形成，减少制作掩膜的工艺步骤、重复光刻的次数时间及成本。
如图6所示，本实施例中，在所述衬底20的表面上沉积覆盖所述数个压电层242的顶层电极材料层，具体是通过沉积方式形成所述顶层电极材料层并覆盖所述衬底20的表面和所述数个压电层242露出凹槽23的表面；
通过同一工艺图案化工艺加工所述顶层电极材料层，以在凹槽23a和凹槽23b的压电层242上形成顶层电极层243，且两个顶层电极层243厚度相同，并且顶层电极层243的一个表面与所述衬底20表面连接，另一个表面位于与衬底20平行的平面上。所述顶层电极层243的与厚度方向垂直的横向宽度与所述压电层242的横向宽度相同。本实施例中的数个BAW谐振器是通过压电层242的厚度不同来实现谐振频率的不同。所述图案化工艺包括涂布材料层，通过蚀刻显影光刻等工艺制作图案。
另一种实施方式，如图10a、图10b和图11a、图11b所示，
如图10a、图10b，第一步，以所述掩膜图案层为掩膜采用同一道图案化工艺在图10a所示的衬底20的所述凹槽23a和凹槽23b的内形成底层电极层241，以及在底层电极层241上形成压电层242，使所述位于所述凹槽23a和凹槽23b内的压电层242低于所述衬底20的表面，就是压电层位于凹槽内部，远离底层电极层的表面低于衬底20的表面。其中，所述凹槽23a和凹槽23b内的压电层242厚度相同，朝向凹槽外部的表面为水平面，以保证顶层电极层的平整性。
如图11a，第二步，以所述掩膜图案层22为掩膜在所述衬底20的表面上沉积覆盖所述数个压电层242的顶层电极材料基层，具体通过沉积金属层的方式在所述以所述掩膜图案层表面上以及凹槽23a和凹槽23b内沉积一层覆盖衬底20表面和凹槽23a和凹槽23b内内的所述数个压电层242顶层电极材料基层，位于凹槽23a和凹槽23b内内的部分把凹槽23a和凹槽23b内填满。此时由于凹槽23的深度不同，数个压电层242厚度相同，底层电极层241厚度相同，所以顶层电极材料基层在凹槽23a和凹槽23b内厚度是不同的。
如图11b，第三步，去除掩膜图案层22，形成由所述凹槽23a和凹槽23b内凸出所述衬底20的表面的顶层电极材料层b；顶层电极材料层b厚度是不同的。
如图7，第四步，对凸出所述衬底20的表面的所述顶层电极材料层b进行抛光直至所述顶层电极材料层b的表面与所述衬底20表面平齐，以形所述成顶层电极层243，此时顶层电极层243的外表面与衬底20表面平齐。
本步骤中，由于所述数个凹槽中至少有两个凹槽的深度不同，所述数个底层电极层241厚度相同，在形成压电层242时，形成压电层242的材料层的厚度一致，并且可以通过整体厚度的增加或者减少，以实现位于凹槽内的压电层242，即数个压电层242厚度相同；也可以形成凸出凹槽的的压电层242以实现不同厚度的压电层242。通过这两种方式分别实现通过不同厚度的顶层电极层243和通过不同厚度的压电层242实现不同频率的BAW谐振器。以使本申请的方法中，可以通过改变压电层242的厚度或者顶层电极层243的厚度两种方式来改变谐振器的中心频率，提高制作的灵活性。
进一步的，所述底层电极层241和顶层电极层243的材料包括但不限于钼、钨、铝等金属。所述压电层242的材料包括但不限于氮化铝、铌酸锂等。
以上是本发明实施例的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明实施例的保护范围。

Claims (10)

  1. 一种单片集成BAW谐振器制作方法，其特征在于，所述方法包括：
    准备一压印模板，包括压板及凸设于所述压板表面的多个压模，所述多个压模中至少有两个压模的相较于所述压板表面的凸出的高度不同；
    在衬底上形成掩膜材料层；
    采用所述压印模板，向所述衬底方向按压所述掩膜材料层，以在所述掩膜材料层上压印成多个深度与所述压膜的高度一致的掩膜凹槽；
    以所述掩模材料层为掩膜，对所述衬底进行等离子刻蚀，在所述衬底表面上形成与所述数个掩膜凹槽位置一一对应的凹槽，所述数个凹槽中至少有两个凹槽的深度不同；
    在所述数个凹槽内形成依次层叠的底层电极层、压电层以及顶层电极层；其中，在垂直于所述衬底方向上，所述数个底层电极层厚度相同且均小于所述凹槽的深度；数个谐振器中至少有两个谐振器的压电层厚度不同，或者至少有两个谐振器的顶层电极层厚度不同。
  2. 如权利要求1所述的单片集成BAW谐振器制作方法，其特征在于，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤，包括，
    以所述掩膜图案层为掩膜采用同一光刻工艺在所述每个凹槽内形成底层电极层，
    以所述掩膜图案层为掩膜采用同一光刻工艺在所述数个底层电极层上形成压电层，使每一所述凹槽内的所述底层电极层和压电层的厚度之和等于或者小于该凹槽的深度。
  3. 如权利要求2所述的单片集成BAW谐振器制作方法，其特征在于，以所述掩膜图案层为掩膜采用同一光刻工艺在所述数个底层电极层上形成压电层，使每一所述凹槽内的所述底层电极层和压电层的厚度之和等于或者小于该凹槽的深度的步骤中，包括，
    以所述掩膜图案层为掩膜在所述数个底层电极层上形成压电材料层，每一所述压电材料层凸出所述衬底设有凹槽的表面；
    去除所述掩膜图案层；
    对所述压电材料层进行抛光直至所述压电材料层的表面与所述衬底表面平齐，以形所述成压电层。
  4. 如权利要求3所述的单片集成BAW谐振器制作方法，其特征在于，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤，包括步骤中，包括
    在所述衬底的表面上沉积覆盖所述数个压电层的顶层电极材料层，
    通过图案化工艺所述顶层电极材料层，以在每一个压电层上形成顶层电极层，且数个顶层电极层厚度相同。
  5. 如权利要求2所述的单片集成BAW谐振器制作方法，其特征在于，在所述数个凹槽内沉积形成依次层叠的底层电极层、压电层以及顶层电极层的步骤中，包括，
    以所述掩膜图案层为掩膜在所述数个凹槽内底层电极层上形成压电层，使所述底层电 极层和压电层的厚度之和小于该凹槽的深度，其中所述数个凹槽内的压电层厚度相同。
  6. 如权利要求5所述的单片集成BAW谐振器制作方法，其特征在于，以所述掩膜图案层为掩膜在所述数个凹槽内底层电极层上形成压电层，步骤之后还包括，
    以所述掩膜图案层为掩膜沉积覆盖所述数个凹槽内的压电层的顶层电极材料层，
    图案化顶层电极材料层后去除所述掩膜图案层，形成由所述凹槽内凸出所述衬底的表面的顶层电极材料层；
    对所述顶层电极材料层凸出的部分进行抛光直至所述顶层电极材料层的表面与所述衬底表面平齐，以形所述成顶层电极层。
  7. 如权利要求1-6任一项所述的单片集成BAW谐振器制作方法，其特征在于，以所述掩膜图案层为掩膜对所述衬底进行等离子刻蚀时，是采用Ar+离子或者He+离子进行刻蚀。
  8. 如权利要求1-7任一项所述的单片集成BAW谐振器制作方法，其特征在于，所述掩膜材料层由高聚物材料制成，所述衬底为绝缘材料制成。
  9. 如权利要求1-8任一项所述的单片集成BAW谐振器制作方法，其特征在于，所述压印模板采用石英材料通过离子磨冼工艺形成。
  10. 如权利要求1-9任一项所述的单片集成BAW谐振器制作方法，其特征在于，采用所述压印模板向所述衬底方向按压所述掩膜材料层，所述多个压模在所述掩膜材料层上压印成多个深度与所述压膜的高度一致的掩膜凹槽，以使去除所述压印模板后所述掩膜材料层形成掩膜图案层的步骤中，包括，
    施加一定外力给所述压印模板向所述衬底方向按压所述掩膜材料层；
    将压有所述压印模板的所述衬底进行加热后，去除所述压印模板，以形成包括数个掩膜凹槽的掩膜图案层。
PCT/CN2018/111496 2018-10-23 2018-10-23 单片集成baw谐振器制作方法 WO2020082245A1 (zh)

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