WO2020063089A1 - 一种栅极驱动电路和显示装置 - Google Patents

一种栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020063089A1
WO2020063089A1 PCT/CN2019/098254 CN2019098254W WO2020063089A1 WO 2020063089 A1 WO2020063089 A1 WO 2020063089A1 CN 2019098254 W CN2019098254 W CN 2019098254W WO 2020063089 A1 WO2020063089 A1 WO 2020063089A1
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Prior art keywords
thin film
film transistor
circuit unit
stage
module
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PCT/CN2019/098254
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English (en)
French (fr)
Inventor
黄洪涛
戴超
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Publication of WO2020063089A1 publication Critical patent/WO2020063089A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of liquid crystal display, and in particular, to a gate driving circuit and a display device for an embedded touch screen.
  • the frame rate of the existing display device is usually 60 Hz, and the touch data report point rate of the touch screen usually needs to reach 120 Hz in order to perform the touch operation more accurately, and to ensure that the fast-moving touch operation does not experience a delay and freeze.
  • an embedded touch screen divides a frame in the display process into multiple periods, and alternates Display and Touch scanning.
  • touch scan display scan is paused.
  • the gate driving circuit is temporarily suspended during the progressive scanning process.
  • some of its internal nodes will maintain the potential before the pause to ensure that the gate drive circuit can return to the state before the pause after the pause and continue to perform progressive scanning from the pause position.
  • Figure 2 shows a circuit unit of a gate driving circuit in an existing embedded touch screen.
  • the pull-up control module (M1, M1A), the output module (M10, Cb), and the pull-up control node maintenance module (M8) , M13), the maintenance node generation module (M5, M6), the output node maintenance module (M11), and the empty module (M2, M14) are composed;
  • the gate driving circuit is composed of a plurality of the circuit units by cascading up and down.
  • the thin film transistor M10 works under a forward bias for a long time, and the threshold voltage Vth will drift forward, causing its on-state current to decrease, which causes a relatively large delay in the gate scan signal output by the circuit unit, so the display area at the corresponding position is therefore And horizontal stripes appear. Pause horizontal stripes is a display anomaly common to embedded touch screens.
  • the present invention provides a gate driving circuit and a display device, which can avoid the horizontal stripes caused by the threshold voltage drift of the thin film transistor and improve the reliability of the circuit.
  • the invention discloses a gate driving circuit, which includes N (N> 4, and N is a positive integer) stage circuit unit, and the nth (1 ⁇ n ⁇ N, and n is a positive integer) stage circuit unit includes a forward and reverse sweep.
  • the control module, output module, level transmission signal generating module, low-potential maintaining module, output maintaining module, and clearing module; the forward and reverse scanning control module, output module, low-potential maintaining module, and clearing module of the n-th circuit unit are connected to it.
  • the constant-voltage low level is input to the signal transmission module, low-potential maintenance module, output maintenance module, and empty module of the n-th circuit unit; the output module, output maintenance module, and empty module of the n-th circuit unit A gate scan signal line connected to the n-th circuit unit; the gate scan signal line outputs a gate scan signal;
  • the output module of the nth stage circuit unit receives the first clock signal and outputs the gate scan signal to the gate scan signal line;
  • the stage signal generation module of the nth stage circuit unit receives the fourth clock signal, and outputs the stage signal of the n stage circuit unit to the forward and reverse sweep control module of the previous stage circuit unit and the drive circuit of the latter stage. Forward and reverse scanning control module;
  • the forward and reverse scanning control module of the nth stage circuit unit includes two control terminals and two input terminals, and the two control terminals respectively input the stage transmission signal of the former stage circuit unit and the stage transmission signal of the latter stage circuit unit.
  • the two input terminals respectively input a second clock signal and a third clock signal;
  • the stage-transmission signal generating module receives the fourth clock signal and outputs the stage-transmission signal of the n-th circuit unit to the forward and reverse scanning control of the driving circuit of the subsequent stage.
  • the two control terminals of the forward and reverse scan control module respectively input the first auxiliary signal and the stage transmission signal of the latter-stage circuit unit, and the two input terminals respectively input the second clock signal and the third clock signal;
  • the stage-transmission signal generating module receives the fourth clock signal, and outputs the stage-transmission signal of the n-th circuit unit to the forward and reverse scans of the driving circuit of the previous stage.
  • the stage signal generation module of the n-th circuit unit includes a thirteenth thin film transistor and a fourteenth thin film transistor;
  • the control terminal of the thirteenth thin film transistor and the first path terminal of the thirteenth thin film transistor are short-circuited and connected to the gate scanning signal line of the n-th circuit unit, and the second path terminal of the thirteenth thin film transistor is connected to the fourteenth thin film.
  • the control terminal of the fourteenth thin film transistor inputs a fourth clock signal, the first path terminal of the fourteenth thin film transistor outputs a stage signal, and the second path terminal of the fourteenth thin film transistor inputs a constant voltage low level.
  • the forward and reverse scanning control module of the n-th circuit unit includes a first thin film transistor and a ninth thin film transistor;
  • the control terminal of the first thin film transistor inputs the level transmission signal of the previous circuit unit, the first path terminal of the first thin film transistor inputs the second clock signal, and the second path terminal of the first thin film transistor is connected to the pull-up control node;
  • the control terminal of the ninth thin film transistor receives the signal from the next stage circuit unit, the first path terminal of the ninth thin film transistor inputs the third clock signal, and the second path terminal of the ninth thin film transistor is connected to the pull-up control node;
  • the control terminal of the first thin film transistor and the control terminal of the ninth thin film transistor are used as two control terminals of the forward and reverse scanning control module, and the first path terminal of the first thin film transistor and the first path terminal of the ninth thin film transistor are used as positive and negative. Two inputs of the anti-sweep control module;
  • the control terminal of the first thin film transistor inputs a first auxiliary signal
  • the control terminal of the ninth thin film transistor inputs a second auxiliary signal.
  • the output maintenance module includes an eleventh thin film transistor, a control terminal of the eleventh thin film transistor inputs a fourth clock signal, and a first path end of the eleventh thin film transistor is connected to a gate scan signal of an n-th circuit unit. Line, the second path terminal of the eleventh thin film transistor outputs a constant voltage low level.
  • the stage transmission signal generating module of the n-th circuit unit outputs the stage transmission signal of the n-th circuit unit to the low-potential maintaining module of the previous-stage circuit unit and the low-potential maintaining module of the subsequent-stage driving circuit;
  • the low-potential maintenance module of the n-th circuit unit inputs the level-transfer signal of the previous-stage circuit unit and the level-transfer signal of the subsequent-stage circuit unit, and the low-potential maintenance module is used to maintain the low level of the pull-up control node;
  • the stage-transmission signal generating module When the n-th circuit unit is a first-stage circuit unit, the stage-transmission signal generating module outputs the stage-transmission signal of the n-th circuit unit to a low-potential maintaining module of a subsequent-stage driving circuit; the low-potential maintaining module inputs a first auxiliary signal. And the subsequent transmission signal of the subsequent circuit unit;
  • the stage transmission signal generating module outputs the stage transmission signal of the n stage circuit unit to the low-potential maintaining module of the previous-stage driving circuit; the low-potential maintaining module inputs the front-stage circuit.
  • the cascade signal and the second auxiliary signal of the unit are the cascade signal and the second auxiliary signal of the unit.
  • the low-potential maintaining module of the n-th circuit unit includes a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a fifteenth thin film transistor, and an eighth thin film transistor; the fourth thin film transistor, the fifth thin film transistor, The sixth thin film transistor, the fifteenth thin film transistor, and the eighth thin film transistor are connected to the sustaining node;
  • the control terminal of the fourth thin film transistor inputs the level transmission signal of the previous circuit unit, the first path terminal of the fourth thin film transistor is connected to the maintenance node, and the second path terminal of the fourth thin film transistor inputs the constant voltage low level;
  • the control terminal of the fifth thin film transistor and the first path terminal of the fifth thin film transistor are short-circuited and input a constant voltage high level, and the second path terminal of the fifth thin film transistor is connected to the maintenance node;
  • the control terminal of the sixth thin film transistor is connected to the pull-up control node, the first path terminal of the sixth thin film transistor is connected to the sustain node, and the second path terminal of the sixth thin film transistor is input with a constant low voltage level;
  • the control terminal of the fifteenth thin-film transistor inputs the level transmission signal of the subsequent circuit unit, the first path terminal of the fifteenth thin-film transistor is connected to the maintenance node, and the second path terminal of the fifteenth thin-film transistor inputs the constant voltage low level;
  • the control terminal of the eighth thin film transistor is connected to the maintenance node, the first path terminal of the eighth thin film transistor is connected to the pull-up control node, and the second path terminal of the eighth thin film transistor is input with a constant low voltage level;
  • n-th circuit unit is a first-stage circuit unit
  • a control terminal of the fourth thin film transistor inputs a first auxiliary signal
  • nth stage circuit unit is a tail stage circuit unit
  • a control terminal of the fifteenth thin film transistor inputs a second auxiliary signal.
  • the low-potential maintaining module of the n-th stage circuit unit includes a sustaining node and further includes two signal input terminals; the two signal input terminals are respectively connected to the sustaining node of the previous-stage circuit unit and the sustaining node of the subsequent-stage circuit unit;
  • the maintaining module is used to maintain the low level of the pull-up control node;
  • n-th stage circuit unit is a first-stage circuit unit
  • two of the signal input terminals respectively input a second clock signal and a maintenance node connected to a subsequent-stage driving circuit
  • the two signal input terminals are respectively connected to a maintenance node of a front-stage driving circuit and a third clock signal is input.
  • the low-potential maintaining module of the n-th circuit unit includes a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a sixteenth thin film transistor, and a seventeenth thin film transistor; a fifth thin film transistor and a sixth thin film transistor; Connected to the sustaining node with the seventh thin film transistor;
  • the control terminal of the fifth thin film transistor and the first path terminal of the fifth thin film transistor are short-circuited and a first clock signal is input, and the second path terminal of the fifth thin film transistor is connected to the maintenance node;
  • the control terminal of the sixth thin film transistor is connected to the pull-up control node, the first path terminal of the sixth thin film transistor is connected to the sustain node, and the second path terminal of the sixth thin film transistor is input with a constant low voltage level;
  • a control terminal of the seventh thin film transistor inputs a fourth clock signal, a first path terminal of the seventh thin film transistor is connected to a maintenance node, and a second path terminal of the seventh thin film transistor inputs a constant voltage low level;
  • the control terminal of the sixteenth thin film transistor is connected to the maintenance node of the previous circuit unit, the first path terminal of the sixteenth thin film transistor is connected to the pull-up control node, and the second path terminal of the sixteenth thin film transistor is input with a constant low voltage level;
  • the control terminal of the seventeenth thin film transistor is connected to the sustaining node of the subsequent circuit unit, the first path terminal of the seventeenth thin film transistor is connected to the pull-up control node, and the second path terminal of the seventeenth thin film transistor is input with a constant low voltage level. ;
  • control terminal of the sixteenth thin film transistor and the control terminal of the seventeenth thin film transistor are used as two signal input terminals of the low-potential maintaining module;
  • n-th circuit unit is a first-level circuit unit
  • a control terminal of the sixteenth thin film transistor inputs a second clock signal
  • nth stage circuit unit is a tail stage circuit unit
  • a control terminal of the seventeenth thin film transistor inputs a third clock signal.
  • the emptying module of the n-th circuit unit includes a second thin film transistor, a third thin film transistor, and a twelfth thin film transistor;
  • the control terminal of the second thin film transistor inputs a touch control signal
  • the first path terminal of the second thin film transistor is connected to a pull-up control node
  • the second path terminal of the second thin film transistor inputs a constant voltage low level
  • the control terminal of the third thin film transistor inputs a clear signal, the first path terminal of the third thin film transistor is connected to the maintenance node, and the second path terminal of the third thin film transistor inputs a constant voltage low level;
  • the control terminal of the twelfth thin film transistor inputs a touch control signal
  • the first path end of the twelfth thin film transistor is connected to the gate scanning signal line of the n-th circuit unit
  • the second path end of the twelfth thin film transistor receives a constant low voltage. Level.
  • the invention also discloses a display device, which comprises any one of the gate driving circuits described above.
  • the present invention can bring at least one of the following beneficial effects:
  • the cascade node in the cascade module stores the high-level cascade signal during the scan pause, and the forward and reverse scan control module of the next stage circuit unit after the scan pause is started;
  • the forward and reverse sweep control module has a bootstrap function.
  • the step-by-step signals of the previous and next-stage circuit units are subject to the capacitance of the second clock signal, the third clock signal, and the pull-up control node.
  • the coupling effect is raised to a potential much higher than the constant-voltage high-level VGH, which makes the pull-up control node charge faster and the potential is more stable.
  • FIG. 1 is a schematic diagram of a driving method of a gate driving circuit in an embedded touch screen
  • FIG. 2 is a schematic circuit diagram of a circuit unit of a conventional gate driving circuit
  • FIG. 3 is a schematic structural diagram of a circuit unit of a gate driving circuit according to the present invention.
  • FIG. 4 is a circuit diagram of a first embodiment of a gate driving circuit according to the present invention.
  • FIG. 5 is a waveform diagram of main signals in the circuit shown in FIG. 4;
  • FIG. 6 is a schematic circuit diagram of a second embodiment of a gate driving circuit according to the present invention.
  • FIG. 7 is a schematic structural diagram of a display device according to the present invention.
  • 01 positive and negative sweep control module, 02, output module, 03, level transmission signal generation module, 04, low potential maintenance module, 05, output maintenance module, 06, empty module, 06A, first empty module, 06B, second Empty the module,
  • M1 first thin film transistor, M2, second thin film transistor, M3, third thin film transistor, M6A, fourth thin film transistor, M5, fifth thin film transistor, M6, sixth thin film transistor, M7, seventh thin film transistor, M8 Eighth thin film transistor, M9, ninth thin film transistor, M10, tenth thin film transistor, M11, eleventh thin film transistor, M12, twelfth thin film transistor, M13, thirteenth thin film transistor, M14, fourteenth thin film Transistor, M6B, fifteenth thin film transistor, M8A, sixteenth thin film transistor, M8B, seventeenth thin film transistor, Cb, bootstrap capacitor;
  • Gn gate scan signal of n-th circuit unit, netAn, pull-up control node of n-th circuit unit, netBn, sustain node of n-th circuit unit, VGH, constant voltage high level, VSS, constant voltage low Level, CKa, first clock signal, CKb, second clock signal, CKc, third clock signal, CKd, fourth clock signal, Tn, stage transmission signal of the n-th circuit unit, Tn-1, n- Stage 1 signal of the circuit unit, Tn-2, stage 2 signal of the circuit unit, stage Tn + 1, n + 1 stage circuit signal, Tn + 2, n + 2 stage
  • each figure only schematically shows the parts related to the present invention, and they do not represent the actual structure as a product.
  • the first element when the first element is described as “electrically connected” to the second element, the first element may be directly connected to the second element or indirectly connected to the second element via one or more additional elements. Further, for the sake of clarity, certain elements that are not necessary for a full understanding of the present invention have been omitted concisely.
  • the gate driving circuit of the present invention includes N (N> 4, and N is a positive integer) stage circuit unit.
  • the nth stage (1 ⁇ n ⁇ N, and n is a positive integer) circuit unit includes a positive Anti-scan control module 01, output module 02, stage transmission signal generation module 03, low potential maintenance module 04, output maintenance module 05, and clear module 06; forward and reverse scan control module 01, output module 02, low
  • the potential maintaining module 04 and the clearing module 06 are connected to the pull-up control node netAn; the stage-level signal generation module 03, the low potential maintaining module 04, the output maintaining module 05, and the clearing module 06 of the n-th circuit unit all input constant voltage and low power.
  • Level VSS; the output module 02, the output maintaining module 05, and the clearing module 06 of the n-th circuit unit are connected to the gate scan signal line of the n-th circuit unit; the gate scan signal line outputs the gate scan signal Gn.
  • a frame in a display process is divided into multiple periods, and display scanning and touch scanning are alternately performed.
  • the gate drive circuit performs a scan pause during a touch scan.
  • the output module 02 receives the first clock signal CKa, and under the control of the pull-up control node netAn, outputs a certain pulse of the first clock signal CKa to the n-th gate scan signal line, and drives the display area as a gate scan signal.
  • the output module 02 further includes a bootstrap capacitor Cb, and the bootstrap capacitor Cb raises the potential of the pull-up control node netAn during the output of the gate scan signal of the current stage.
  • the cascade signal generation module 03 is connected between the n-th stage gate scan signal line and the constant voltage low level VSS.
  • the cascade signal generation module 03 receives the fourth clock signal CKd and outputs the cascade signal of the n-th circuit unit.
  • the forward and reverse scanning control module 01 includes two control terminals and two input terminals, and the two control terminals respectively input the stage transmission signal of the previous stage circuit unit and the stage transmission signal of the subsequent stage circuit unit, and the two input terminals are respectively The second clock signal CKb and the third clock signal CKc are input.
  • the forward and reverse scan control module 01 pulls up the pull-up control node netAn during the forward scan and reverse scan; at the moment when the pull-up control node netAn is pulled up, the forward and reverse scan control module 01 has a bootstrap ( bootstrap) function, the above-mentioned step-by-step signal of the previous stage circuit unit and the step-by-step signal of the latter stage circuit unit are subject to the capacitive coupling effect of the second clock signal CKb, the third clock signal CKc, and the pull-up control node netAn, and are Raising to a potential much higher than the constant-voltage high-level VGH makes the pull-up control node netAn charge faster and the potential is more stable.
  • bootstrap bootstrap
  • the clock signals CKa, CKb, CKc, and CKd will remain at a low potential VGL during the scan pause.
  • the stage transmission The node Tn will not be emptied, so that the stage node Tn is always at a high potential VGH during the scanning pause.
  • the pull-up control node netAn and the gate-scanning signal line of the current stage during the scanning pause will be cleared, which prevents the tenth thin film transistor M10 in the output module 02 from being in a positive biased working state during the scanning pause.
  • the waveform delay of the output gate scan signal Gn caused by the threshold voltage of the tenth thin film transistor M10 as the output TFT shifting forward is avoided, thereby avoiding the occurrence of pause horizontal stripes.
  • the step signal generation module 03 stores the step signal Tn at a high potential, and the forward and reverse scan control module 01 of the next stage circuit unit is started, so that the progressive scanning resumes the state before the pause and continues.
  • the low-potential maintenance module 04 includes a maintenance node netBn.
  • the low-potential maintenance module 04 maintains the pull-up control node netAn by charging and discharging the maintenance node netBn.
  • the circuit unit of this stage does not need to output a pulse of a gate scan signal, it will The pull-up control node netAn is maintained at a low potential.
  • the output sustaining module 05 receives the fourth clock signal, and maintains the gate scan signal line of the current stage at a low potential before or after the pulse output of the gate scan signal of the current stage ends.
  • the clearing module 06 clears the charge of the pull-up control node netAn and the gate scanning signal line during the scanning pause period and after the end of one frame scanning, and clears the maintenance node netBn after the end of one frame scanning.
  • each thin film transistor of the present invention includes a control terminal, a first via terminal, and a second via terminal.
  • the control terminal is a gate
  • one via terminal is a source and the other via
  • the terminal is the drain.
  • the control terminal is high, the source and drain are connected through the semiconductor layer. At this time, the thin film transistor is turned on.
  • circuit diagrams involved in the following embodiments are all gate driving circuits in a single-sided driving architecture, but the application of the gate driving circuit in the present invention is not limited to this method, and can be applied to any mode of driving architecture. Including non-left and right interleaved bilateral drive architecture, left and right interleaved bilateral drive architecture (interlace), etc.
  • the pre-stage circuit unit of the n-th stage circuit unit in the present invention refers to the (na) -stage circuit unit, where 1 ⁇ na ⁇ n
  • the pre-stage circuit unit of the n-th stage circuit unit refers to The (nb) th stage circuit unit, where 1 ⁇ nb ⁇ na
  • the so-called later stage circuit unit of the nth stage circuit unit refers to the (n + a) th stage circuit unit, where n ⁇ n + a ⁇ N
  • the latter stage circuit unit of the n-th stage circuit unit refers to the (n + b) stage circuit unit, where n + a ⁇ n + b ⁇ N.
  • the previous-stage circuit unit of the n-th stage circuit unit is an n-1th stage circuit unit, and the previous and previous stage circuit unit of the nth stage circuit unit is an n-2 stage circuit unit;
  • the next-stage circuit unit of the n-th stage circuit unit is an n + 1-stage circuit unit, and the next-stage circuit unit of the n-th stage circuit unit is an n + 2-stage circuit unit.
  • the first clock signal corresponding to the n-th circuit unit in the present invention refers to a clock signal input to the output module 02 of the n-th circuit unit.
  • the number of clock signals is M.
  • CKm 1, 2, ..., M.
  • the first clock signal is CKm
  • the corresponding second clock signal is CKm-1
  • the third clock signal is CKm + 1
  • the fourth clock signal is CKm + 2.
  • CCK0 is equivalent to CKM
  • CKM + 1 is equivalent to CK1
  • CKM + 2 is equivalent to CK2.
  • clock signal input mode is called clock signal positive sequence input, and the gate drive circuit is in the forward scanning state; when the waveforms of CK1, CK2, CK3, and CK4 are generated in reverse order, At this time, this clock signal input mode is called clock signal reverse order input, and the gate drive circuit is in the reverse scanning state.
  • this clock signal input mode is called clock signal reverse order input, and the gate drive circuit is in the reverse scanning state.
  • the first-stage circuit unit referred to in the following embodiments refers to: the first-stage circuit unit, and the first two-stage circuit unit refers to: the first-stage circuit unit and the second-stage circuit unit; the tail-stage circuit The unit refers to the Nth-level circuit unit, and the last two-level circuit units refer to the N-1th-level circuit unit and the Nth-level circuit unit.
  • each stage circuit unit is the same, and the difference is only that the signals input by some thin film transistors are different.
  • the nth (1 ⁇ n ⁇ N) stage circuit structure is mainly described in detail below.
  • FIG. 4 is a circuit diagram of a first embodiment of a gate driving circuit.
  • the nth stage circuit unit includes a forward and reverse scan control module 01, an output module 02, a level transmission signal generating module 03, a low potential maintaining module 04, and an output.
  • Maintenance module 05 and clear module 06; the forward and reverse sweep control module 01, output module 02, low potential maintenance module 04, and clear module 06 of the n-th circuit unit are connected to the pull-up control node netAn; the stage of the n-th circuit unit
  • the signal generation module 03, the low-potential maintenance module 04, the output maintenance module 05, and the clear module 06 all input a constant voltage low level; the output module 02, the output maintenance module 05, and the clear module 06 of the n-th circuit unit are connected to the first A gate scan signal line of the n-stage circuit unit; the gate scan signal line outputs a gate scan signal Gn.
  • the output module 02 includes a tenth thin film transistor M10; the control terminal of the tenth thin film transistor M10 is connected to the pull-up control node netAn, and the first path terminal of the tenth thin film transistor M10 receives the first clock signal CKm The second via terminal of the tenth thin film transistor M10 is connected to the gate scanning signal line of this stage.
  • the tenth thin film transistor M10 outputs a certain pulse of the clock signal CKm under the control of the pull-up control node netAn to drive the display area as a gate scan signal.
  • the output module 02 further includes a bootstrap capacitor Cb connected between the pull-up control node netAn and the gate scan signal line of the current stage.
  • the bootstrap capacitor Cb lifts the pull-up control node netAn during the output of the gate scan signal of the current stage. The potential.
  • the pass signal generating module 03 of the n-th circuit unit includes a thirteenth thin film transistor M13 and a fourteenth thin film transistor M14 connected to the pass node Tn.
  • the control terminal of the thirteenth thin film transistor M13 and the first path terminal of the thirteenth thin film transistor M13 are short-circuited and connected to the gate scan signal line of the n-th circuit unit, and the second path terminal of the thirteenth thin film transistor M13 is connected to the first The first via terminal of the fourteen thin film transistor M14; the thirteenth thin film transistor M13 is used to pull up the pass node Tn of the n-th circuit unit, and copy the potential of the gate scan signal of this stage to the pass node Tn.
  • the control terminal of the fourteenth thin film transistor M14 inputs a fourth clock signal CKm + 2, the first path terminal of the fourteenth thin film transistor M14 outputs a stage transmission signal, and the second path terminal of the fourteenth thin film transistor M14 inputs a constant voltage and low voltage.
  • the fourteenth thin film transistor M14 is used to clear the pass node Tn.
  • the forward and reverse scanning control module 01 of the n-th circuit unit includes a first thin film transistor M1 and a ninth thin film transistor M9.
  • the control terminal of the first thin film transistor M1 inputs the signal of the previous stage circuit unit, the first path terminal of the first thin film transistor M1 inputs the second clock signal CKm-1, and the second path terminal of the first thin film transistor M1 is connected.
  • the pull-up control node netAn preferably, the stage transmission signal of the previous stage circuit unit refers to the stage transmission signal Tn-2 of the n-2 stage circuit unit.
  • the control terminal of the ninth thin film transistor M9 inputs the signal of the next stage circuit unit, the first path terminal of the ninth thin film transistor M9 inputs the third clock signal CKm + 1, and the second path terminal of the ninth thin film transistor M9 is connected.
  • the pull-up control node netAn preferably, the stage transmission signal of the latter stage circuit unit refers to the stage transmission signal Tn + 2 of the n + 2 stage circuit unit.
  • the control terminal of the first thin film transistor M1 and the control terminal of the ninth thin film transistor M9 are used as two control terminals of the forward and reverse scanning control module 01, the first path terminal of the first thin film transistor M1 and the first of the ninth thin film transistor M9.
  • the path end is used as two input ends of the forward and reverse scan control module 01;
  • the control terminal of the first thin film transistor M1 inputs a first auxiliary signal
  • the control terminal of the ninth thin film transistor M9 inputs a second auxiliary signal.
  • the forward and reverse scan control module 01 pulls up the pull-up control node netAn during the forward scan and reverse scan; at the moment when the pull-up control node netAn is pulled up, the first thin film transistor M1 and the ninth thin film transistor M9 has a bootstrap function.
  • the above-mentioned step-by-step signal of the previous stage circuit unit and the step-by-step signal of the latter stage circuit unit are subject to the second clock signal CKm-1, the third clock signal CKm + 1, and pull-up.
  • the capacitive coupling effect of the control node netAn is raised to a potential much higher than the constant-voltage high-level VGH, so that the charge of the pull-up control node netAn is faster and the potential is more stable.
  • the clock signals CK1, CK2, CK3, and CK4 will always be at a low potential VGL during the scan pause.
  • the fourteenth thin film transistor M14 in the stage signal generation module 03 will always be Is off. After the output of the gate scanning signal Gn of this stage is completed, the stage transmission node Tn will not be cleared, so that the stage transmission node Tn is always at a high potential VGH during the scanning pause.
  • the pull-up control node netAn and the gate-scanning signal line of the current stage during the scanning pause will be cleared, which prevents the tenth thin film transistor M10 in the output module 02 from being in a positive biased working state during the scanning pause. Therefore, the threshold voltage of the tenth thin film transistor M10 is prevented from drifting forward and the waveform of the output gate scan signal Gn is delayed, thereby avoiding the occurrence of pause horizontal stripes.
  • the step signal generation module 03 stores the step signal Tn at a high potential, and the forward and reverse scan control module 01 of the next stage circuit unit is started, so that the progressive scanning resumes the state before the pause and continues.
  • the output maintaining module 05 of the n-th circuit unit includes an eleventh thin film transistor M11; a control terminal of the eleventh thin film transistor M11 inputs a fourth clock signal CKm + 2, and the eleventh thin film transistor
  • the first path end of M11 is connected to the gate scanning signal line of the n-th stage circuit unit, and the second path end of the eleventh thin film transistor M11 outputs a constant voltage low level;
  • the gate scan signal line of this stage is maintained at a low potential.
  • the stage-transmission signal generating module 03 of the n-th circuit unit outputs the stage-transmission signal Tn of the n-th circuit unit to the low-potential maintenance module 04 of the previous-stage circuit unit and the low-potential maintenance of the subsequent-stage driving circuit.
  • the low-potential maintenance module 04 of the nth-level circuit unit inputs the level-transmission signal of the previous-stage circuit unit and the level-transmission signal of the subsequent-stage circuit unit.
  • the low-potential maintenance module 04 maintains the pull-up control node when the circuit unit of this stage does not need to output. netAn is low.
  • the low-potential maintaining module 04 of the n-th circuit unit includes a fourth thin film transistor M6A, a fifth thin film transistor M5, a sixth thin film transistor M6, a fifteenth thin film transistor M6B, and an eighth thin film transistor M8; a fourth thin film transistor; M6A, the fifth thin film transistor M5, the sixth thin film transistor M6, the fifteenth thin film transistor M6B, and the eighth thin film transistor M8 are connected to the maintenance node netBn.
  • the control terminal of the fifth thin film transistor M5 and the first path terminal of the fifth thin film transistor M5 are short-circuited and input a constant voltage high level VGH, and the second path terminal of the fifth thin film transistor M5 is connected to the maintenance node netBn; the fifth thin film transistor M5 It is used to pull up to maintain the potential of the node netBn to a high potential VGH.
  • the control terminal of the sixth thin film transistor M6 is connected to the pull-up control node netAn, the first path terminal of the sixth thin film transistor M6 is connected to the maintenance node netBn, and the second path terminal of the sixth thin film transistor M6 is input with a constant low voltage level;
  • the transistor M6 is used to pull down the potential of the sustaining node netBn to a low potential when the circuit unit of this stage needs to output, so that the low-potential maintaining module 04 stops working to prevent it from affecting the output of the gate scan signal Gn of the stage.
  • the control terminal of the fourth thin film transistor M6A inputs the level transmission signal of the previous circuit unit, the first path terminal of the fourth thin film transistor M6A is connected to the maintenance node netBn, and the second path terminal of the fourth thin film transistor M6A inputs the constant voltage low level;
  • the stage transmission signal of the previous stage circuit unit refers to the stage transmission signal Tn-1 of the n-1th stage circuit unit;
  • the control terminal of the fifteenth thin film transistor M6B inputs the stage transmission signal of the subsequent circuit unit, the first path terminal of the fifteenth thin film transistor M6B is connected to the maintenance node netBn, and the second path terminal of the fifteenth thin film transistor M6B has a constant input low voltage.
  • Level preferably, the transmission signal of the subsequent circuit unit refers to the transmission signal Tn + 1 of the (n + 1) th circuit unit;
  • the fourth thin film transistor M6A and the fifteenth thin film transistor M6B are used to assist the sixth thin film transistor M6.
  • the node netBn will be kept clear.
  • the control terminal of the eighth thin film transistor M8 is connected to the maintenance node netBn, the first path terminal of the eighth thin film transistor M8 is connected to the pull-up control node netAn, and the second path terminal of the eighth thin film transistor M8 is input with a constant low voltage level; the eighth thin film The transistor M8 is controlled by the sustain node netBn, and is used to maintain the pull-up control node netAn at a low potential when the circuit unit of this stage does not need an output.
  • the control terminal of the fourth thin film transistor M6A inputs a first auxiliary signal
  • the control terminal of the fifteenth thin film transistor M6B inputs a second auxiliary signal.
  • the emptying module 06 of the n-th circuit unit includes a first emptying module 06A and a second emptying module 06B.
  • the first emptying module 06A includes a second thin film transistor M2, a third thin film transistor M3,
  • the second emptying module 06B includes a twelfth thin film transistor M12.
  • the control terminal of the second thin film transistor M2 inputs a touch control signal, the first path terminal of the second thin film transistor M2 is connected to the pull-up control node netAn, and the second path terminal of the second thin film transistor M2 inputs a constant voltage low level; the first thin film The transistor M1 is used to clear the pull-up control node netAn during the scan pause period and after the end of one frame scan.
  • the control terminal of the third thin film transistor M3 inputs a clear signal, the first path terminal of the third thin film transistor M3 is connected to the maintenance node netBn, and the second path terminal of the third thin film transistor M3 inputs a constant voltage low level; the third thin film transistor M3 is used for After one frame scan is completed, the maintenance node netBn is emptied.
  • the control terminal of the twelfth thin film transistor M12 inputs a touch control signal, the first path terminal of the twelfth thin film transistor M12 is connected to the gate scanning signal line of the n-th circuit unit, and the second path terminal of the twelfth thin film transistor M12 is input Constant voltage low level; the twelfth thin film transistor M12 is used to clear the gate scanning signal line of this stage during the scanning pause period and after the end of one frame scanning.
  • Fig. 5 is a schematic diagram of driving waveforms of the circuit shown in Fig. 4 during forward scanning, and the figure shows the waveforms of the circuit driving when four clock signals are used (the number of clock signals can be adjusted in actual application):
  • GSP1 is the first start signal, which is responsible for starting during forward scanning, and is input to the first two-stage circuit units as the first auxiliary signal;
  • GSP2 (not shown) is the second start signal, which is responsible for starting during reverse scanning and is input to the two-stage circuit unit as the second auxiliary signal;
  • CK1, CK2, CK3, and CK4 are clock signals. They are output in positive sequence during forward scanning. The duty cycle of CK1, CK2, CK3, and CK4 is 45%. During the scanning pause period, CK1, CK2, CK3, and CK4 all suspend output. Low potential state
  • TC is a touch control signal, which is at a high potential VGH during the scanning pause, and is responsible for maintaining the potentials of the gate scanning signal line, the pull-up control node netAn, and the maintenance node netBn during the scanning pause;
  • the other waveforms shown are the output waveforms of the internal nodes of the circuit.
  • G1, G3, Gn + 1, and Gn + 2 are the waveforms of the gate scan signals output by the circuit units at all levels.
  • T1, T3, Tn + 1, Tn + 2 are the waveforms of the cascaded signals output to your circuit unit.
  • FIG. 6 is a schematic circuit diagram of a second embodiment of a gate driving circuit according to the present invention.
  • the second embodiment is improved on the basis of the first embodiment.
  • the specific improvement points are as follows:
  • the low-potential maintenance module 04 of the n-th circuit unit includes a maintenance node netBn, and further includes two signal input terminals; the two signal input terminals are respectively connected to the maintenance node of the former circuit unit and the maintenance node of the subsequent circuit unit.
  • the low-potential maintaining module 04 of the n-th circuit unit includes a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, a sixteenth thin film transistor M8A, and a seventeenth thin film.
  • the transistor M8B; the fifth thin film transistor M5, the sixth thin film transistor M6, and the seventh thin film transistor M7 are connected to the maintenance node netBn.
  • the control terminal of the fifth thin film transistor M5 and the first path terminal of the fifth thin film transistor M5 are short-circuited and the first clock signal CKm is input.
  • the second path terminal of the fifth thin film transistor M5 is connected to the maintenance node netBn; the fifth thin film transistor M5 is used for Pull up the sustaining node netBn of this stage circuit unit.
  • the control terminal of the sixth thin film transistor M6 is connected to the pull-up control node netAn, the first path terminal of the sixth thin film transistor M6 is connected to the maintenance node netBn, and the second path terminal of the sixth thin film transistor M6 is input with a constant low voltage level;
  • the transistor M6 is used to pull the sustain node netBn to a low potential when the circuit unit of this stage needs to output a pulse of the gate scan signal.
  • the control terminal of the seventh thin film transistor M7 inputs a fourth clock signal CKm + 2, the first path terminal of the seventh thin film transistor M7 is connected to the maintenance node netBn, and the second path terminal of the seventh thin film transistor M7 inputs a constant voltage low level; Seven thin film transistors M7 are responsible for periodically pulling down and maintaining the node netBn.
  • the control terminal of the sixteenth thin film transistor M8A is connected to the sustain node of the previous circuit unit, the first path terminal of the sixteenth thin film transistor M8A is connected to the pull-up control node netAn, and the second path terminal of the sixteenth thin film transistor M8A is input with a constant voltage.
  • Low level preferably, the maintenance node of the previous-stage circuit unit refers to the maintenance node netBn-1 of the n-1th stage circuit unit.
  • the control terminal of the seventeenth thin film transistor M8B is connected to the sustaining node of the subsequent circuit unit, the first path terminal of the seventeenth thin film transistor M8B is connected to the pull-up control node netAn, and the second path terminal of the seventeenth thin film transistor M8B is input to constant Low level; preferably, the maintenance node of the subsequent-stage circuit unit refers to the maintenance node netBn + 1 of the (n + 1) -th stage circuit unit.
  • the control terminal of the sixteenth thin film transistor M8A and the control terminal of the seventeenth thin film transistor M8B are used as two signal input terminals of the low-potential maintaining module 04; the sixteenth thin film transistor M8A and the seventeenth thin film transistor M8B are used in the present
  • the stage circuit unit does not need to output a pulse
  • the pull-up control node netAn is alternately maintained at a low potential
  • the maintenance node netBn of the n-th stage circuit unit is shared by the adjacent front-stage circuit unit and the rear-stage circuit unit.
  • the control terminal of the sixteenth thin film transistor M8A inputs the second clock signal CKm-1;
  • the control terminal of the seventeenth thin film transistor M8B inputs the third clock signal CKm + 1.
  • the invention also discloses a display device including any of the above-mentioned gate driving circuits, which can be applied to an embedded touch screen, and supports a forward and reverse bidirectional scanning function and a reporting rate of 120 Hz and above. It should be noted that when the gate driving circuit of the present invention is used in a display device with a double-sided driving architecture as shown in FIG. 7, adaptive adjustment can be made.
  • the invention discloses a gate driving circuit, in which the two control ends of the forward and reverse scanning control module 01 respectively input the stage transmission signal of the previous stage circuit unit and the stage transmission signal of the subsequent stage circuit unit, two inputs Input the second clock signal CKb and the third clock signal CKc respectively, so that the forward and reverse scan control module 01 has a forward and reverse scan function and a bootstrap function; during the scan pause, the pull-up control node netAn and the gate scan signal line of this stage are cleared , To avoid the suspending stripes caused by the thin film transistor in the output module 02 during the scan pause; the cascade node in the cascade module 03 stores the high-level cascade signal during the scan pause. Tn, the forward and reverse scan control module 01 of the next stage circuit unit after the scan pause is started.

Abstract

一种栅极驱动电路，包括N级电路单元；第n(1≦n≦N，且n、N为正整数)级电路单元包括正反扫控制模块（01）、输出模块（02）和级传信号产生模块（03）；正反扫控制模块（01）的两个控制端分别输入前前一级电路单元的级传信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号（CKb）和第三时钟信号（CKc），使得正反扫控制模块（01）具有正反扫功能和自举功能；扫描暂停期间上拉控制节点（netAn）和本级栅极扫描信号线被清空，避免了输出模块（02）中的薄膜晶体管在扫描暂停期间一直处于正偏压状态所导致的暂停横纹；级传信号产生模块（03）中的级传节点（Tn）在扫描暂停的过程中储存高电平的级传信号，在扫描暂停结束后启动后后一级电路单元的正反扫控制模块（01）。

Description

一种栅极驱动电路和显示装置
本申请要求于2018年09月25日提交中国专利局、申请号为201811114461.6发明名称为“一种栅极驱动电路和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及液晶显示领域，尤其涉及一种用于内嵌式触摸屏的栅极驱动电路和显示装置。
背景技术
现有显示装置的帧率通常是60Hz，而触摸屏的触摸数据报点率通常需要达到120Hz，才能更准确地进行触摸操作，保证快速移动的触摸操作不出现延迟卡顿的情况。
为了实现120Hz以上的报点率，如图1所示，内嵌式触摸屏将显示过程中的一帧切分成多个时段，交替进行显示扫描(Display)和触摸扫描(Touch)。在进行触摸扫描的过程中，显示扫描被暂停。与其相应地，栅极驱动电路在进行逐行扫描的过程中，也会多次暂停。在栅极驱动电路扫描暂停的过程中，其部分内部节点会维持暂停前的电位，以保证暂停结束后栅极驱动电路能够恢复到暂停前的状态，从暂停位置继续进行逐行扫描。
图2所示为一种现有的内嵌式触摸屏中栅极驱动电路的电路单元，由上拉控制模块(M1、M1A)，输出模块(M10、Cb)，上拉控制节点维持模块(M8、M13)，维持节点产生模块(M5、M6)，输出节点维持模块(M11)，清空模块(M2、M14)组成；栅极驱动电路由多个该电路单元通过上下级联所组成。在进入暂停状态后，其相应位置电路单元的上拉控制节点netAn会一直维持高电位VGH，使得输出模块中的M10在暂停阶段一直工作在正向偏压状态下。薄膜晶体管M10长期工作在正向偏压下，阈值电压Vth会发生正向漂移，导致其开态电流下降，使得该电路单元输出的栅极扫描信号出现比较大的延迟，对应位置的显示区域因此而出现横纹。暂停横纹是内嵌式触摸屏常见的一种显示异常现象。
发明内容
为解决上述技术问题，本发明提供一种栅极驱动电路和显示装置，可以避免由薄膜晶体管的阈值电压漂移造成的暂停横纹，改善电路的可靠性。
本发明提供的技术方案如下：
本发明公开了一种栅极驱动电路，包括N(N>4，且N为正整数)级电路单元，第n(1≦n≦N，且n为正整数)级电路单元包括正反扫控制模块、输出模块、级传信号产生模块、低电位维持模块、输出维持模块以及清空模块；第n级电路单元的正反扫控制模块、输出模块、低电位维持模块以及清空模块相连接于上拉控制节点；第n级电路单元的级传信号产生模块、低电位维持模块、输出维持模块以及清空模块均输入恒压低电平；第n级电路单元的输出模块、输出维持模块以及清空模块相连接于第n级电路单元的栅极扫描信号线；栅极扫描信号线输出栅极扫描信号；
第n级电路单元的输出模块接收第一时钟信号，并将栅极扫描信号输出至栅极扫描信号线；
第n级电路单元的级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至前前一级电路单元的正反扫控制模块和后后一级驱动电路的正反扫控制模块；
第n级电路单元的正反扫控制模块包括两个控制端和两个输入端，两个控制端分别输入前前一级电路单元的级传信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号和第三时钟信号；
当所述第n级电路单元为首两级电路单元时，级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至后后一级驱动电路的正反扫控制模块；正反扫控制模块的两个控制端分别输入第一辅助信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号和第三时钟信号；
当所述第n级电路单元为尾两级电路单元时，级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至前前一级驱动电路的正反扫控制模块；正反扫控制模块的两个控制端分别输入前前一级电路单元的级传信号和第二辅助信号，两个输入端分别输入第二时钟信号和第三时钟信号。
优选地，第n级电路单元的级传信号产生模块包括第十三薄膜晶体管和第十四薄膜晶体管；
第十三薄膜晶体管的控制端和第十三薄膜晶体管的第一通路端短接并连接第n级电路单元的栅极扫描信号线，第十三薄膜晶体管的第二通路端连接第十四薄膜晶体管的第一通路端；
第十四薄膜晶体管的控制端输入第四时钟信号，第十四薄膜晶体管的第一通路端输出级传信号，第十四薄膜晶体管的第二通路端输入恒压低电平。
优选地，第n级电路单元的正反扫控制模块包括第一薄膜晶体管和第九薄膜晶体管；
第一薄膜晶体管的控制端输入前前一级电路单元的级传信号，第一薄膜晶体管的第一通路端输入第二时钟信号，第一薄膜晶体管的第二通路端连接上拉控制节点；
第九薄膜晶体管的控制端输入后后一级电路单元的级传信号，第九薄膜晶体管的第一通路端输入第三时钟信号，第九薄膜晶体管的第二通路端连接上拉控制节点；
第一薄膜晶体管的控制端和第九薄膜晶体管的控制端用作正反扫控制模块的两个控制端，第一薄膜晶体管的第一通路端和第九薄膜晶体管的第一通路端用作正反扫控制模块的两个输入端；
当所述第n级电路单元为首两级电路单元时，第一薄膜晶体管的控制端输入第一辅助信号；
当所述第n级电路单元为尾两级电路单元时，第九薄膜晶体管的控制端输入第二辅助信号。
优选地，所述输出维持模块包括第十一薄膜晶体管，第十一薄膜晶体管的控制端输入第四时钟信号，第十一薄膜晶体管的第一通路端连接第n级电路单元的栅极扫描信号线，第十一薄膜晶体管的第二通路端输出恒压低电平。
优选地，第n级电路单元的级传信号产生模块将第n级电路单元的级传信号输出至前级电路单元的低电位维持模块和后级驱动电路的低电位维持模块；
第n级电路单元的低电位维持模块输入前级电路单元的级传信号和后级电路单元的级传信号，低电位维持模块用于维持上拉控制节点的低电平；
当所述第n级电路单元为首级电路单元时，级传信号产生模块将第n级电路单元的级传信号输出至后级驱动电路的低电位维持模块；低电位维持模块输入第一辅助信号和后级电路单元的级传信号；
当所述第n级电路单元为尾级电路单元时，级传信号产生模块将第n级电路单元的级传信号输出至前级驱动电路的低电位维持模块；低电位维持模块输入前级电路单元的级传信号和第二辅助信号。
优选地，第n级电路单元的低电位维持模块包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第十五薄膜晶体管以及第八薄膜晶体管；第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第十五薄膜晶体管和第八薄膜晶体管相连接于维持节点；
第四薄膜晶体管的控制端输入前级电路单元的级传信号，第四薄膜晶体管的第一通路端连接维持节点，第四薄膜晶体管的第二通路端输入恒压低电平；
第五薄膜晶体管的控制端和第五薄膜晶体管的第一通路端短接并输入恒压高电平，第五薄膜晶体管的第二通路端连接维持节点；
第六薄膜晶体管的控制端连接上拉控制节点，第六薄膜晶体管的第一通路端连接维持节点，第六薄膜晶体管的第二通路端输入恒压低电平；
第十五薄膜晶体管的控制端输入后级电路单元的级传信号，第十五薄膜晶体管的第一通路端连接维持节点，第十五薄膜晶体管的第二通路端输入恒压低电平；
第八薄膜晶体管的控制端连接维持节点，第八薄膜晶体管的第一通路端连接上拉控制节点，第八薄膜晶体管的第二通路端输入恒压低电平；
当所述第n级电路单元为首级电路单元时，所述第四薄膜晶体管的控制端输入第一辅助信号；
当所述第n级电路单元为尾级电路单元时，所述第十五薄膜晶体管的控制端输入第二辅助信号。
优选地，第n级电路单元的低电位维持模块包括维持节点，还包括两个信号输入端；两个信号输入端分别连接前级电路单元的维持节点和后级电路单元的维持节点；低电位维持模块用于维持上拉控制节点的低电平；
当所述第n级电路单元为首级电路单元时，两个所述信号输入端分别输入第二时钟信号和连接后级驱动电路的维持节点；
当所述第n级电路单元为尾级电路单元时，两个所述信号输入端分别连接前级驱动电路的维持节点和输入第三时钟信号。
优选地，第n级电路单元的低电位维持模块包括第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第十六薄膜晶体管和第十七薄膜晶体管；第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管相连接于维持节点；
第五薄膜晶体管的控制端和第五薄膜晶体管的第一通路端短接并输入第一时钟信号，第五薄膜晶体管的第二通路端连接维持节点；
第六薄膜晶体管的控制端连接上拉控制节点，第六薄膜晶体管的第一通路端连接维持节点，第六薄膜晶体管的第二通路端输入恒压低电平；
第七薄膜晶体管的控制端输入第四时钟信号，第七薄膜晶体管的第一通路端连接维持节点，第七薄膜晶体管的第二通路端输入恒压低电平；
第十六薄膜晶体管的控制端连接前级电路单元的维持节点，第十六薄膜晶体管的第一通路端连接上拉控制节点，第十六薄膜晶体管的第二通路端输入恒压低电平；
第十七薄膜晶体管的控制端连接后级电路单元的维持节点，第十七薄膜晶体管的第一通路端连接上拉控制节点，第十七薄膜晶体管的第二通路端端输入恒压低电平；
第十六薄膜晶体管的控制端和第十七薄膜晶体管的控制端用作低电位维持模块的两个信号输入端；
当所述第n级电路单元为首级电路单元时，所述第十六薄膜晶体管的控制端输入第二时钟信号；
当所述第n级电路单元为尾级电路单元时，所述第十七薄膜晶体管的控制端输入第三时钟信号。
优选地，第n级电路单元的清空模块包括第二薄膜晶体管、第三薄膜晶体管以及第十二薄膜晶体管；
第二薄膜晶体管的控制端输入触摸控制信号，第二薄膜晶体管的第一通路端连接上拉控制节点，第二薄膜晶体管的第二通路端输入恒压低电平；
第三薄膜晶体管的控制端输入清空信号，第三薄膜晶体管的第一通路端连接维持节点，第三薄膜晶体管的第二通路端输入恒压低电平；
第十二薄膜晶体管的控制端输入触摸控制信号，第十二薄膜晶体管的第一通路端连接第n级电路单元的栅极扫描信号线，第十二薄膜晶体管的第二通路端输入恒压低电平。
本发明还公开了一种显示装置，该显示装置包括任一项上述的栅极驱动电路。
与现有技术相比，本发明能够带来以下至少一项有益效果：
1、扫描暂停期间上拉控制节点和本级栅极扫描信号线被清空，避免了输出模块中的薄膜晶体管在扫描暂停期间一直处于正偏压状态所导致的暂停横纹；
2、级传模块中的级传节点在扫描暂停的过程中储存高电平的级传信号，在扫描暂停结束后启动后后一级电路单元的正反扫控制模块；
3、正反扫控制模块具有自举功能，前前一级电路单元的级传信号和后后一级电路单元的级传信号受到第二时钟信号、第三时钟信号和上拉控制节点的电容耦合作用，被抬升到远高于恒压高电平VGH的电位，使得上拉控制节点的充电更快，电位更加稳定。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1为内嵌式触摸屏中栅极驱动电路的驱动方式示意图；
图2为一种现有栅极驱动电路的电路单元的电路示意图；
图3为本发明栅极驱动电路的电路单元的架构示意图；
图4为本发明栅极驱动电路的实施例一的电路示意图；
图5为图4所示的电路中主要信号的波形示意图；
图6为本发明栅极驱动电路的实施例二的电路示意图；
图7为本发明显示装置的结构示意图。
附图标号说明：
01、正反扫控制模块，02、输出模块，03、级传信号产生模块，04、低电位维持模块，05、输出维持模块，06、清空模块，06A、第一清空模块，06B、第二清空模块，
M1、第一薄膜晶体管，M2、第二薄膜晶体管，M3、第三薄膜晶体管，M6A、第四薄膜晶体管，M5、第五薄膜晶体管，M6、第六薄膜晶体管，M7、第七薄膜晶体管、M8、第八薄膜晶体管，M9、第九薄膜晶体管，M10、第十薄膜晶体管，M11、第十一薄膜晶体管，M12、第十二薄膜晶体管，M13、第十三薄膜晶体管，M14、第十四薄膜晶体管，M6B、第十五薄膜晶体管，M8A、第十六薄膜晶体管，M8B、第十七薄膜晶体管，Cb、自举电容；
Gn、第n级电路单元的栅极扫描信号，netAn、第n级电路单元的上拉控制节点，netBn、第n级电路单元的维持节点，VGH、恒压高电平、VSS、恒压低电平，CKa、第一时钟信号，CKb、第二时钟信号，CKc、第三时钟信号，CKd、第四时钟信号，Tn、第n级电路单元的级传信号，Tn-1、第n-1级电路单元的级传信号，Tn-2、第n-2级电路单元的级传信号，Tn+1、第n+1级电路单元的级传信号，Tn+2、第n+2级电路单元的级传信号，CLR、清空信号，TC、触摸控制信号。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们 并不代表其作为产品的实际结构。这里，当将第一元件描述为“电连接”到第二元件时，第一元件可以直接连接至第二元件，或经过一个或多个附加元件间接连接至第二元件。进一步的，为了清楚起见，简明省略了对于充分理解本发明而言不是必须的某些元件。
本发明的栅极驱动电路包括N(N>4，且N为正整数)级电路单元，如图3所示，第n级(1≦n≦N，且n为正整数)电路单元包括正反扫控制模块01、输出模块02、级传信号产生模块03、低电位维持模块04、输出维持模块05以及清空模块06；第n级电路单元的正反扫控制模块01、输出模块02、低电位维持模块04以及清空模块06相连接于上拉控制节点netAn；第n级电路单元的级传信号产生模块03、低电位维持模块04、输出维持模块05以及清空模块06均输入恒压低电平VSS；第n级电路单元的输出模块02、输出维持模块05以及清空模块06相连接于第n级电路单元的栅极扫描信号线；栅极扫描信号线输出栅极扫描信号Gn。
如图1所示，显示过程中的一帧切分成多个时段，交替进行显示扫描(Display)和触摸扫描(Touch)。栅极驱动电路在触摸扫描(Touch)时进行扫描暂停。
其中，输出模块02接收第一时钟信号CKa，在上拉控制节点netAn的控制下，输出第一时钟信号CKa的某个脉冲至第n级栅极扫描信号线，作为栅极扫描信号驱动显示区。优选地，输出模块02还包括自举电容Cb，自举电容Cb在本级栅极扫描信号输出期间抬升上拉控制节点netAn的电位。
级传信号产生模块03连接在第n级栅极扫描信号线和恒压低电平VSS之间,级传信号产生模块03接收第四时钟信号CKd，将第n级电路单元的级传信号输出至前前一级电路单元的正反扫控制模块01和后后一级驱动电路的正反扫控制模块01。
正反扫控制模块01包括两个控制端和两个输入端，两个控制端分别输入前前一级电路单元的级传信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号CKb和第三时钟信号CKc。正反扫控制模块01在正向扫描和反向扫描的过程中对上拉控制节点netAn进行上拉；在对上拉控制节点 netAn进行上拉的瞬间，正反扫控制模块01具有自举(bootstrap)功能，上述前前一级电路单元的级传信号和后后一级电路单元的级传信号受到第二时钟信号CKb、第三时钟信号CKc和上拉控制节点netAn的电容耦合作用，被抬升到远高于恒压高电平VGH的电位，使得上拉控制节点netAn的充电更快，电位更加稳定。
当栅极驱动电路需要在本级电路进行扫描暂停时，时钟信号CKa、CKb、CKc、CKd会在扫描暂停期间一直处于低电位VGL，在完成本级栅极扫描信号Gn的输出之后，级传节点Tn不会被清空，从而使级传节点Tn在扫描暂停的过程中一直处于高电位VGH。与此同时，扫描暂停期间的上拉控制节点netAn和本级栅极扫描信号线将被清空，避免了输出模块02中的第十薄膜晶体管M10在扫描暂停期间一直处于正偏压的工作状态，从而避免了作为输出TFT的第十薄膜晶体管M10的阈值电压发生正向漂移而导致的输出栅极扫描信号Gn的波形延迟，从而避免了暂停横纹的产生。
在扫描暂停结束之后，时钟信号CKa、CKb、CKc、CKd将恢复。级传信号产生模块03内保存了处于高电位的级传信号Tn，将启动后后一级电路单元的正反扫控制模块01，从而使逐行扫描恢复暂停前的状态，继续进行下去。
低电位维持模块04包括维持节点netBn，低电位维持模块04通过向维持节点netBn进行充电和放电对上拉控制节点netAn进行维持，在本级电路单元不需要输出栅极扫描信号的脉冲时，将上拉控制节点netAn维持在低电位。
输出维持模块05接收第四时钟信号，在本级栅极扫描信号的脉冲输出前或输出结束后，将本级栅极扫描信号线维持在低电位。
清空模块06在扫描暂停期间和一帧扫描结束后对上拉控制节点netAn和栅极扫描信号线进行电荷清空，在一帧扫描结束后对维持节点netBn进行清空。
需要说明的是，本发明每个薄膜晶体管均包括控制端、第一通路端和第二通路端，在以下的实施例中，控制端为栅极，其中一个通路端为源极、另一个通路端为漏极。当给控制端高电平时，源极和漏极通过半导体层连接，此时薄膜晶体管处于开启状态。
需要说明的是，以下实施例所涉及的电路图均为单边驱动架构下的栅极驱动电路，但本发明所述栅极驱动电路的应用不仅限于该方式，可以适用于任意模式的驱动架构，包括非左右交错式双边驱动架构、左右交错式双边驱动架构(interlace)等。
本发明中所称的第n级电路单元的前级电路单元是指第(n-a)级电路单元，其中1≤n-a<n，所称的第n级电路单元的前前一级电路单元是指第(n-b)级电路单元，其中1≤n-b<n-a；所称的第n级电路单元的后级电路单元是指第(n+a)级电路单元，其中n<n+a≤N,所称的第n级电路单元的后后一级电路单元是指第(n+b)级电路单元，其中n+a<n+b≤N。在单边驱动架构下，优选地，第n级电路单元的前级电路单元为第n-1级电路单元，第n级电路单元的前前一级电路单元为第n-2级电路单元；第n级电路单元的后级电路单元为第n+1级电路单元，第n级电路单元的后后一级电路单元为第n+2级电路单元。
本发明中所称的对应第n级电路单元的第一时钟信号是指输入第n级电路单元的输出模块02的时钟信号。时钟信号数量为M个，在单边驱动架构下，相邻M个电路单元的时钟信号表示为CKm(m＝1、2、……、M)。当第一时钟信号为CKm时，对应的第二时钟信号为CKm-1，第三时钟信号为CKm+1，第四时钟信号为CKm+2。特别地，CK0等同于CKM，CKM+1等同于CK1，CKM+2等同于CK2。
以下的实施例中选用4个时钟信号CK1、CK2、CK3、CK4，CK1、CK2、CK3、CK4的占空比为45％。当CK1、CK2、CK3、CK4波形依序产生时，这一时钟信号输入模式称之为时钟信号正序输入，栅极驱动电路处于正向扫描状态；当CK1、CK2、CK3、CK4波形逆序产生时，这一时钟信号输入模式称之为时钟信号逆序输入，栅极驱动电路处于反向扫描状态。应当说明的是，在本发明的基础上选用其他数量和波形的时钟信号及其他时钟信号输入模式的常规功能改进均应落入本发明的保护范围。
在单边驱动架构下，以下实施例中所称的首级电路单元是指：第1级电路单元，首两级电路单元是指：第1级电路单元和第2级电路单元；尾级电路单元是指：第N级电路单元，尾两级电路单元是指：第N-1级电路单元和第N级 电路单元。
本发明中每级电路单元的电路结构相同，区别仅在于部分薄膜晶体管输入的信号不同，下面主要对第n(1≦n≦N)级电路结构作详细介绍。
下面以具体实施例详细介绍本发明。
实施例一：
如图4所示为一种栅极驱动电路的实施例一的电路图，第n级电路单元包括正反扫控制模块01、输出模块02、级传信号产生模块03、低电位维持模块04、输出维持模块05以及清空模块06；第n级电路单元的正反扫控制模块01、输出模块02、低电位维持模块04以及清空模块06相连接于上拉控制节点netAn；第n级电路单元的级传信号产生模块03、低电位维持模块04、输出维持模块05以及清空模块06均输入恒压低电平；第n级电路单元的输出模块02、输出维持模块05以及清空模块06相连接于第n级电路单元的栅极扫描信号线；栅极扫描信号线输出栅极扫描信号Gn。
如图4所示，具体的，输出模块02包括第十薄膜晶体管M10；第十薄膜晶体管M10的控制端连接上拉控制节点netAn，第十薄膜晶体管M10的第一通路端接收第一时钟信号CKm，第十薄膜晶体管M10的第二通路端连接本级栅极扫描信号线。第十薄膜晶体管M10在上拉控制节点netAn的控制下，输出时钟信号CKm的某个脉冲，作为栅极扫描信号驱动显示区。
优选地，输出模块02还包括连接在上拉控制节点netAn和本级栅极扫描信号线之间的自举电容Cb，自举电容Cb在本级栅极扫描信号输出期间抬升上拉控制节点netAn的电位。
如图4所示，具体地，第n级电路单元的级传信号产生模块03包括相连接于级传节点Tn的第十三薄膜晶体管M13和第十四薄膜晶体管M14。
第十三薄膜晶体管M13的控制端和第十三薄膜晶体管M13的第一通路端短接并连接第n级电路单元的栅极扫描信号线，第十三薄膜晶体管M13的第二通路端连接第十四薄膜晶体管M14的第一通路端；第十三薄膜晶体管M13用于上拉第n级电路单元的级传节点Tn，将本级栅极扫描信号的电位复制到级传 节点Tn中。
第十四薄膜晶体管M14的控制端输入第四时钟信号CKm+2，第十四薄膜晶体管M14的第一通路端输出级传信号，第十四薄膜晶体管M14的第二通路端输入恒压低电平；第十四薄膜晶体管M14用于清空级传节点Tn。
如图4所示，具体地，第n级电路单元的正反扫控制模块01包括第一薄膜晶体管M1和第九薄膜晶体管M9。
第一薄膜晶体管M1的控制端输入前前一级电路单元的级传信号，第一薄膜晶体管M1的第一通路端输入第二时钟信号CKm-1，第一薄膜晶体管M1的第二通路端连接上拉控制节点netAn；优选地，前前一级电路单元的级传信号是指第n-2级电路单元的级传信号Tn-2。
第九薄膜晶体管M9的控制端输入后后一级电路单元的级传信号，第九薄膜晶体管M9的第一通路端输入第三时钟信号CKm+1，第九薄膜晶体管M9的第二通路端连接上拉控制节点netAn；优选地，后后一级电路单元的级传信号是指第n+2级电路单元的级传信号Tn+2。
第一薄膜晶体管M1的控制端和第九薄膜晶体管M9的控制端用作正反扫控制模块01的两个控制端，第一薄膜晶体管M1的第一通路端和第九薄膜晶体管M9的第一通路端用作正反扫控制模块01的两个输入端；
特别地，当所述第n级电路单元为首两级电路单元时，第一薄膜晶体管M1的控制端输入第一辅助信号；
特别地，当所述第n级电路单元为尾两级电路单元时，第九薄膜晶体管M9的控制端输入第二辅助信号。
正反扫控制模块01在正向扫描、反向扫描的过程中对上拉控制节点netAn进行上拉；在对上拉控制节点netAn进行上拉的瞬间，第一薄膜晶体管M1和第九薄膜晶体管M9具有自举(bootstrap)功能，上述前前一级电路单元的级传信号和后后一级电路单元的级传信号受到第二时钟信号CKm-1、第三时钟信号CKm+1和上拉控制节点netAn的电容耦合作用，被抬升到远高于恒压高电平VGH的电位，使得上拉控制节点netAn的充电更快，电位更加稳定。
当栅极驱动电路需要在本级电路进行扫描暂停时，时钟信号CK1、CK2、 CK3、CK4会在扫描暂停期间一直处于低电位VGL，级传信号产生模块03中第十四薄膜晶体管M14将一直处于关闭状态。在完成本级栅极扫描信号Gn的输出之后，级传节点Tn不会被清空，从而使级传节点Tn在扫描暂停的过程中一直处于高电位VGH。与此同时，扫描暂停期间的上拉控制节点netAn和本级栅极扫描信号线将被清空，避免了输出模块02中的第十薄膜晶体管M10在扫描暂停期间一直处于正偏压的工作状态，从而避免了第十薄膜晶体管M10的阈值电压发生正向漂移和输出栅极扫描信号Gn的波形延迟，从而避免了暂停横纹的产生。
在扫描暂停结束之后，时钟信号CK1、CK2、CK3、CK4将恢复。级传信号产生模块03内保存了处于高电位的级传信号Tn，将启动后后一级电路单元的正反扫控制模块01，从而使逐行扫描恢复暂停前的状态，继续进行下去。
如图4所示，具体地，第n级电路单元的输出维持模块05包括第十一薄膜晶体管M11；第十一薄膜晶体管M11的控制端输入第四时钟信号CKm+2，第十一薄膜晶体管M11的第一通路端连接第n级电路单元的栅极扫描信号线，第十一薄膜晶体管M11的第二通路端输出恒压低电平；用于在本级电路单元不需要输出时，将本级栅极扫描信号线维持在低电位。
如图4所示，第n级电路单元的级传信号产生模块03将第n级电路单元的级传信号Tn输出至前级电路单元的低电位维持模块04和后级驱动电路的低电位维持模块04。
第n级电路单元的低电位维持模块04输入前级电路单元的级传信号和后级电路单元的级传信号，低电位维持模块04在本级电路单元不需要输出时，维持上拉控制节点netAn的低电平。
具体地，第n级电路单元的低电位维持模块04包括第四薄膜晶体管M6A、第五薄膜晶体管M5、第六薄膜晶体管M6、第十五薄膜晶体管M6B以及第八薄膜晶体管M8；第四薄膜晶体管M6A、第五薄膜晶体管M5、第六薄膜晶体管M6、第十五薄膜晶体管M6B和第八薄膜晶体管M8相连接于维持节点netBn。
第五薄膜晶体管M5的控制端和第五薄膜晶体管M5的第一通路端短接并输入恒压高电平VGH，第五薄膜晶体管M5的第二通路端连接维持节点netBn； 第五薄膜晶体管M5用于上拉维持节点netBn的电位至高电位VGH。
第六薄膜晶体管M6的控制端连接上拉控制节点netAn，第六薄膜晶体管M6的第一通路端连接维持节点netBn，第六薄膜晶体管M6的第二通路端输入恒压低电平；第六薄膜晶体管M6用于在本级电路单元需要输出的时候，将维持节点netBn的电位拉低至低电位，使低电位维持模块04停止工作，防止其影响本级栅极扫描信号Gn输出。
第四薄膜晶体管M6A的控制端输入前级电路单元的级传信号，第四薄膜晶体管M6A的第一通路端连接维持节点netBn，第四薄膜晶体管M6A的第二通路端输入恒压低电平；优选地，前级电路单元的级传信号是指第n-1级电路单元的级传信号Tn-1；
第十五薄膜晶体管M6B的控制端输入后级电路单元的级传信号，第十五薄膜晶体管M6B的第一通路端连接维持节点netBn，第十五薄膜晶体管M6B的第二通路端输入恒压低电平；优选地，后级电路单元的级传信号是指第n+1级电路单元的级传信号Tn+1；
第四薄膜晶体管M6A和第十五薄膜晶体管M6B用于辅助第六薄膜晶体管M6，在本级电路单元不需要输出信号时，将维持节点netBn清空。
第八薄膜晶体管M8的控制端连接维持节点netBn，第八薄膜晶体管M8的第一通路端连接上拉控制节点netAn，第八薄膜晶体管M8的第二通路端输入恒压低电平；第八薄膜晶体管M8受维持节点netBn控制，用于在本级电路单元不需要输出时，将上拉控制节点netAn维持在低电位。
特别地，当第n级电路单元为首级电路单元时，第四薄膜晶体管M6A的控制端输入第一辅助信号；
特别地，当第n级电路单元为尾级电路单元时，第十五薄膜晶体管M6B的控制端输入第二辅助信号。
如图4所示，具体地，第n级电路单元的清空模块06包括第一清空模块06A和第二清空模块06B，第一清空模块06A包括第二薄膜晶体管M2、第三薄膜晶体管M3，第二清空模块06B包括第十二薄膜晶体管M12。
第二薄膜晶体管M2的控制端输入触摸控制信号，第二薄膜晶体管M2的 第一通路端连接上拉控制节点netAn，第二薄膜晶体管M2的第二通路端输入恒压低电平；第一薄膜晶体管M1用于在扫描暂停期间和一帧扫描结束后对上拉控制节点netAn进行清空。
第三薄膜晶体管M3的控制端输入清空信号，第三薄膜晶体管M3的第一通路端连接维持节点netBn，第三薄膜晶体管M3的第二通路端输入恒压低电平；第三薄膜晶体管M3用于在一帧扫描结束后对维持节点netBn进行清空。
第十二薄膜晶体管M12的控制端输入触摸控制信号，第十二薄膜晶体管M12的第一通路端连接第n级电路单元的栅极扫描信号线，第十二薄膜晶体管M12的第二通路端输入恒压低电平；第十二薄膜晶体管M12用于在扫描暂停期间和一帧扫描结束后对本级栅极扫描信号线进行清空。
图5为图4所示的电路在正向扫描时的驱动波形示意图，该图示意了电路驱动采用4个时钟讯号时的波形(实际应用时的时钟讯号数量可调整)：
GSP1是第一启动信号，负责在正向扫描时进行启动，并作为第一辅助信号输入首两级电路单元；
GSP2(图未示)是第二启动信号，负责在反向扫描时进行启动，并作为第二辅助信号输入尾两级电路单元；
CK1、CK2、CK3、CK4是时钟信号，正向扫描时正序输出，CK1、CK2、CK3、CK4的占空比为45％，在扫描暂停期间CK1、CK2、CK3、CK4均暂停输出，处于低电位状态；
TC是触摸控制信号，在扫描暂停期间处于高电位VGH，负责在扫描暂停期间维持本级栅极扫描信号线、上拉控制节点netAn和维持节点netBn的电位；
其他所示波形如netA1、netA3、netAn+1、netAn+2是电路内部节点的输出波形，G1、G3、Gn+1、Gn+2分别为各级电路单元输出的栅极扫描信号的波形，T1、T3、Tn+1、Tn+2分别为给你电路单元输出的级传信号的波形。
实施例二：
图6为本发明栅极驱动电路的实施例二的电路示意图。实施例二是在实施例一的基础上进行改进，具体改进点在于：
1、第n级电路单元的低电位维持模块04包括维持节点netBn，还包括两个 信号输入端；两个信号输入端分别连接前级电路单元的维持节点和后级电路单元的维持节点。
如图6所示，具体地，第n级电路单元的低电位维持模块04包括第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第十六薄膜晶体管M8A和第十七薄膜晶体管M8B；第五薄膜晶体管M5、第六薄膜晶体管M6和第七薄膜晶体管M7相连接于维持节点netBn。
第五薄膜晶体管M5的控制端和第五薄膜晶体管M5的第一通路端短接并输入第一时钟信号CKm，第五薄膜晶体管M5的第二通路端连接维持节点netBn；第五薄膜晶体管M5用于上拉本级电路单元的维持节点netBn。
第六薄膜晶体管M6的控制端连接上拉控制节点netAn，第六薄膜晶体管M6的第一通路端连接维持节点netBn，第六薄膜晶体管M6的第二通路端输入恒压低电平；第六薄膜晶体管M6用于在本级电路单元需要输出栅极扫描信号的脉冲时将维持节点netBn拉低至低电位。
第七薄膜晶体管M7的控制端输入第四时钟信号CKm+2，第七薄膜晶体管M7的第一通路端连接维持节点netBn，第七薄膜晶体管M7的第二通路端输入恒压低电平；第七薄膜晶体管M7负责周期性下拉维持节点netBn。
第十六薄膜晶体管M8A的控制端连接前级电路单元的维持节点，第十六薄膜晶体管M8A的第一通路端连接上拉控制节点netAn，第十六薄膜晶体管M8A的第二通路端输入恒压低电平；优选地，前级电路单元的维持节点是指第n-1级电路单元的维持节点netBn-1。
第十七薄膜晶体管M8B的控制端连接后级电路单元的维持节点，第十七薄膜晶体管M8B的第一通路端连接上拉控制节点netAn，第十七薄膜晶体管M8B的第二通路端端输入恒压低电平；优选地，后级电路单元的维持节点是指第n+1级电路单元的维持节点netBn+1。
第十六薄膜晶体管M8A的控制端和第十七薄膜晶体管M8B的控制端用作低电位维持模块04的两个信号输入端；第十六薄膜晶体管M8A和第十七薄膜晶体管M8B用于在本级电路单元不需要输出脉冲时，交替对上拉控制节点netAn进行低电位维持，第n级电路单元的维持节点netBn为相邻的前级电路单 元和后级电路单元所共享。
特别地，当第n级电路单元为首级电路单元时，第十六薄膜晶体管M8A的控制端输入第二时钟信号CKm-1；
特别地，当第n级电路单元为尾级电路单元时，第十七薄膜晶体管M8B的控制端输入第三时钟信号CKm+1。
本发明还公开了一种显示装置，包括上述任一种栅极驱动电路，可适用于内嵌式触摸屏，支持正反双向扫描功能和120Hz及以上的报点率。需要说明的是，当本发明的栅极驱动电路用于如图7所示的双边驱动架构的显示装置时，可以作出适应性调整。
本发明公开了一种栅极驱动电路，其中正反扫控制模块01的两个控制端分别输入前前一级电路单元的级传信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号CKb和第三时钟信号CKc，使得正反扫控制模块01具有正反扫功能和自举功能；扫描暂停期间上拉控制节点netAn和本级栅极扫描信号线被清空，避免了输出模块02中的薄膜晶体管在扫描暂停期间一直处于正偏压状态所导致的暂停横纹；级传模块03中的级传节点在扫描暂停的过程中储存高电平的级传信号Tn，在扫描暂停结束后启动后后一级电路单元的正反扫控制模块01。
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种栅极驱动电路，包括N(N>4，且N为正整数)级电路单元，其特征在于：
    第n(1≦n≦N，且n为正整数)级电路单元包括正反扫控制模块、输出模块、级传信号产生模块、低电位维持模块、输出维持模块以及清空模块；第n级电路单元的正反扫控制模块、输出模块、低电位维持模块以及清空模块相连接于上拉控制节点；第n级电路单元的级传信号产生模块、低电位维持模块、输出维持模块以及清空模块均输入恒压低电平；第n级电路单元的输出模块、输出维持模块以及清空模块相连接于第n级电路单元的栅极扫描信号线；栅极扫描信号线输出栅极扫描信号；
    第n级电路单元的输出模块接收第一时钟信号，并将栅极扫描信号输出至栅极扫描信号线；
    第n级电路单元的级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至前前一级电路单元的正反扫控制模块和后后一级驱动电路的正反扫控制模块；
    第n级电路单元的正反扫控制模块包括两个控制端和两个输入端，两个控制端分别输入前前一级电路单元的级传信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号和第三时钟信号；
    当所述第n级电路单元为首两级电路单元时，级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至后后一级驱动电路的正反扫控制模块；正反扫控制模块的两个控制端分别输入第一辅助信号和后后一级电路单元的级传信号，两个输入端分别输入第二时钟信号和第三时钟信号；
    当所述第n级电路单元为尾两级电路单元时，级传信号产生模块接收第四时钟信号，并将第n级电路单元的级传信号输出至前前一级驱动电路的正反扫控制模块；正反扫控制模块的两个控制端分别输入前前一级电路单元的级传信号和第二辅助信号，两个输入端分别输入第二时钟信号和第三时钟信号。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于：
    第n级电路单元的级传信号产生模块包括第十三薄膜晶体管和第十四薄 膜晶体管；
    第十三薄膜晶体管的控制端和第十三薄膜晶体管的第一通路端短接并连接第n级电路单元的栅极扫描信号线，第十三薄膜晶体管的第二通路端连接第十四薄膜晶体管的第一通路端；
    第十四薄膜晶体管的控制端输入第四时钟信号，第十四薄膜晶体管的第一通路端输出级传信号，第十四薄膜晶体管的第二通路端输入恒压低电平。
  3. 根据权利要求1所述的栅极驱动电路，其特征在于：
    第n级电路单元的正反扫控制模块包括第一薄膜晶体管和第九薄膜晶体管；
    第一薄膜晶体管的控制端输入前前一级电路单元的级传信号，第一薄膜晶体管的第一通路端输入第二时钟信号，第一薄膜晶体管的第二通路端连接上拉控制节点；
    第九薄膜晶体管的控制端输入后后一级电路单元的级传信号，第九薄膜晶体管的第一通路端输入第三时钟信号，第九薄膜晶体管的第二通路端连接上拉控制节点；
    第一薄膜晶体管的控制端和第九薄膜晶体管的控制端用作正反扫控制模块的两个控制端，第一薄膜晶体管的第一通路端和第九薄膜晶体管的第一通路端用作正反扫控制模块的两个输入端；
    当所述第n级电路单元为首两级电路单元时，第一薄膜晶体管的控制端输入第一辅助信号；
    当所述第n级电路单元为尾两级电路单元时，第九薄膜晶体管的控制端输入第二辅助信号。
  4. 根据权利要求1所述的栅极驱动电路，其特征在于：
    所述输出维持模块包括第十一薄膜晶体管，第十一薄膜晶体管的控制端输入第四时钟信号，第十一薄膜晶体管的第一通路端连接第n级电路单元的栅极扫描信号线，第十一薄膜晶体管的第二通路端输出恒压低电平。
  5. 根据权利要求1所述的栅极驱动电路，其特征在于：
    第n级电路单元的级传信号产生模块将第n级电路单元的级传信号输出至 前级电路单元的低电位维持模块和后级驱动电路的低电位维持模块；
    第n级电路单元的低电位维持模块输入前级电路单元的级传信号和后级电路单元的级传信号，低电位维持模块用于维持上拉控制节点的低电平；
    当所述第n级电路单元为首级电路单元时，级传信号产生模块将第n级电路单元的级传信号输出至后级驱动电路的低电位维持模块；低电位维持模块输入第一辅助信号和后级电路单元的级传信号；
    当所述第n级电路单元为尾级电路单元时，级传信号产生模块将第n级电路单元的级传信号输出至前级驱动电路的低电位维持模块；低电位维持模块输入前级电路单元的级传信号和第二辅助信号。
  6. 根据权利要求5所述的栅极驱动电路，其特征在于：
    第n级电路单元的低电位维持模块包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第十五薄膜晶体管以及第八薄膜晶体管；第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第十五薄膜晶体管和第八薄膜晶体管相连接于维持节点；
    第四薄膜晶体管的控制端输入前级电路单元的级传信号，第四薄膜晶体管的第一通路端连接维持节点，第四薄膜晶体管的第二通路端输入恒压低电平；
    第五薄膜晶体管的控制端和第五薄膜晶体管的第一通路端短接并输入恒压高电平，第五薄膜晶体管的第二通路端连接维持节点；
    第六薄膜晶体管的控制端连接上拉控制节点，第六薄膜晶体管的第一通路端连接维持节点，第六薄膜晶体管的第二通路端输入恒压低电平；
    第十五薄膜晶体管的控制端输入后级电路单元的级传信号，第十五薄膜晶体管的第一通路端连接维持节点，第十五薄膜晶体管的第二通路端输入恒压低电平；
    第八薄膜晶体管的控制端连接维持节点，第八薄膜晶体管的第一通路端连接上拉控制节点，第八薄膜晶体管的第二通路端输入恒压低电平；
    当所述第n级电路单元为首级电路单元时，所述第四薄膜晶体管的控制端输入第一辅助信号；
    当所述第n级电路单元为尾级电路单元时，所述第十五薄膜晶体管的控制端输入第二辅助信号。
  7. 根据权利要求1所述的栅极驱动电路，其特征在于：
    第n级电路单元的低电位维持模块包括维持节点，还包括两个信号输入端；两个信号输入端分别连接前级电路单元的维持节点和后级电路单元的维持节点；低电位维持模块用于维持上拉控制节点的低电平；
    当所述第n级电路单元为首级电路单元时，两个所述信号输入端分别输入第二时钟信号和连接后级驱动电路的维持节点；
    当所述第n级电路单元为尾级电路单元时，两个所述信号输入端分别连接前级驱动电路的维持节点和输入第三时钟信号。
  8. 根据权利要求7所述的栅极驱动电路，其特征在于：
    第n级电路单元的低电位维持模块包括第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第十六薄膜晶体管和第十七薄膜晶体管；第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管相连接于维持节点；
    第五薄膜晶体管的控制端和第五薄膜晶体管的第一通路端短接并输入第一时钟信号，第五薄膜晶体管的第二通路端连接维持节点；
    第六薄膜晶体管的控制端连接上拉控制节点，第六薄膜晶体管的第一通路端连接维持节点，第六薄膜晶体管的第二通路端输入恒压低电平；
    第七薄膜晶体管的控制端输入第四时钟信号，第七薄膜晶体管的第一通路端连接维持节点，第七薄膜晶体管的第二通路端输入恒压低电平；
    第十六薄膜晶体管的控制端连接前级电路单元的维持节点，第十六薄膜晶体管的第一通路端连接上拉控制节点，第十六薄膜晶体管的第二通路端输入恒压低电平；
    第十七薄膜晶体管的控制端连接后级电路单元的维持节点，第十七薄膜晶体管的第一通路端连接上拉控制节点，第十七薄膜晶体管的第二通路端端输入恒压低电平；
    第十六薄膜晶体管的控制端和第十七薄膜晶体管的控制端用作低电位维持模块的两个信号输入端；
    当所述第n级电路单元为首级电路单元时，所述第十六薄膜晶体管的控制端输入第二时钟信号；
    当所述第n级电路单元为尾级电路单元时，所述第十七薄膜晶体管的控制端输入第三时钟信号。
  9. 根据权利要求6或8所述的栅极驱动电路，其特征在于：
    第n级电路单元的清空模块包括第二薄膜晶体管、第三薄膜晶体管以及第十二薄膜晶体管；
    第二薄膜晶体管的控制端输入触摸控制信号，第二薄膜晶体管的第一通路端连接上拉控制节点，第二薄膜晶体管的第二通路端输入恒压低电平；
    第三薄膜晶体管的控制端输入清空信号，第三薄膜晶体管的第一通路端连接维持节点，第三薄膜晶体管的第二通路端输入恒压低电平；
    第十二薄膜晶体管的控制端输入触摸控制信号，第十二薄膜晶体管的第一通路端连接第n级电路单元的栅极扫描信号线，第十二薄膜晶体管的第二通路端输入恒压低电平。
  10. 一种显示装置，其特征在于：包括权利要求1-9任一项所述的栅极驱动电路。
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