WO2020062676A1 - 像素驱动电路和显示装置 - Google Patents

像素驱动电路和显示装置 Download PDF

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Publication number
WO2020062676A1
WO2020062676A1 PCT/CN2018/124267 CN2018124267W WO2020062676A1 WO 2020062676 A1 WO2020062676 A1 WO 2020062676A1 CN 2018124267 W CN2018124267 W CN 2018124267W WO 2020062676 A1 WO2020062676 A1 WO 2020062676A1
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Prior art keywords
transistor
capacitor
electrically connected
drain
gate
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PCT/CN2018/124267
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English (en)
French (fr)
Inventor
马伟欣
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/349,992 priority Critical patent/US10699619B1/en
Publication of WO2020062676A1 publication Critical patent/WO2020062676A1/zh
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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Definitions

  • the present invention relates to the technical field of liquid crystal display, and particularly to a pixel driving circuit and a display device.
  • AMOLED display devices are composed of AMOLED pixels with multiple rows and columns.
  • AMOLED pixels usually use a thin film transistor (TFT) to build a pixel driving circuit to provide corresponding current for Organic Light-Emitting Diode (OLED) devices.
  • TFT thin film transistor
  • OLED Organic Light-Emitting Diode
  • the basic pixel driving circuit of AMOLED is shown as 1, specifically 7T1C circuit.
  • the 7T1C circuit includes seven transistors and a capacitor.
  • t1 is the preparation stage. In this stage, the second scan signal scan [n-1] is at a low potential, so the fourth transistor T4 is turned on, and the potential of the reference point A becomes Low potential, the first capacitor C1 is charged; t2 is the compensation stage of the threshold voltage Vth of the first transistor T1. In this stage, the first scan signal scan [n] is a low potential, so the second transistor T2, the third transistor T3 and seventh transistor T7 are turned on.
  • the gate of the first transistor T1 has a negative voltage
  • the source and drain of the first transistor T1 are shorted, and the potential at the reference point A is
  • the gray-scale data voltage Vdata charges the reference point A through the first transistor T1 until the voltage at the reference point A becomes Vdata-
  • the device OLED is reset; t3 is the display phase.
  • the source-drain current through the first transistor T1 K Cox ⁇ W / L, current flows through the light emitting device OLED.
  • the light-emitting device OLED works, for example, a display panel with a resolution of (1440 * 296018.5: 9).
  • t3 1 / 60-t1-t2
  • its driving time is 16.7ms.
  • this time is for the TFTs that are turned on at t3 (the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on) because the enable signal EM is at a low level for a long time, which makes the two TFTs T5 and T6 long. It is in an on state, and at the same time, the gate of the first transistor T1 is at a low level for a long time in the light emitting stage due to the first capacitor C1, and is very long.
  • the TFT device If the TFT is turned on for a long time, the TFT device will be in a bias stress state for a long time, which will cause the electrical characteristics of the device such as the turn-on voltage and electron mobility to drift, thereby affecting the display effect of the entire screen and shortening the life of the TFT device. In view of this, it is urgent to provide a solution to solve the above problems.
  • An object of the present invention is to provide a pixel driving circuit.
  • the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are partly turned off during a display period, thereby preventing the device from being turned on for a long time. The damage is caused, and the life of the TFT device is increased.
  • the present invention provides a pixel driving circuit
  • the pixel driving circuit includes: a light emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first Five transistors, a sixth transistor, a seventh transistor, and a first capacitor; wherein the first end of the light-emitting device is electrically connected to the drain of the sixth transistor and the drain of the seventh transistor, respectively, so A second terminal of the light emitting device is grounded, a positive terminal of the first capacitor receives a power supply voltage signal, and a negative terminal of the first capacitor is electrically connected to a source of the fourth transistor and a drain of the third transistor,
  • the gate of the fourth transistor receives a second scan signal, the drain of the fourth transistor receives a working voltage signal, the drain of the second transistor receives a gray-scale data voltage signal, and the second crystal
  • the source of is electrically connected to the source of the first transistor and the drain of the fifth transistor, respectively, and the drain of the first transistor is electrically connected
  • the drain of the eighth transistor is electrically connected to the gate of the first transistor.
  • the gate of the eighth transistor receives the enable signal.
  • the source of the eighth transistor is electrically connected to the negative terminal of the first capacitor; during the first time period, when the second scan signal is at a low level, the fourth transistor is in an on state and is located at the First parameter of the negative terminal of the first capacitor Point becomes low level, the first capacitor is in a charging state, wherein a start time of the first time period is when the first capacitor starts to charge, and an end time of the first time period is the first time Capacitance charging is completed; when the first scanning signal is at a low level in the second time period, the second transistor, the third transistor, and the seventh transistor are in an on state, and the second time
  • the start time of the segment is the end of the charging of the first capacitor
  • the end time of the second period is the potential of the first reference point located at the negative terminal of the first capacitor becomes a gray data voltage and a first transistor
  • the difference in threshold voltage causes the first
  • the present invention provides a pixel driving circuit
  • the pixel driving circuit includes: a light emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a A fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; wherein the first end of the light emitting device is electrically connected to the drain of the sixth transistor and the drain of the seventh transistor, A second terminal of the light emitting device is grounded, a positive terminal of the first capacitor receives a power voltage signal, and a negative terminal of the first capacitor is electrically connected to a source of the fourth transistor and a drain of the third transistor, respectively.
  • the gate of the fourth transistor receives a second scan signal
  • the drain of the fourth transistor receives a working voltage signal
  • the drain of the second transistor receives a gray-scale data voltage signal
  • the first The sources of the two crystals are electrically connected to the source of the first transistor and the drain of the fifth transistor, respectively, and the drain of the first transistor is electrically connected to the source of the sixth transistor, and the A gate of a transistor is electrically connected to a negative terminal of the first capacitor
  • a source of the sixth transistor is electrically connected to a source of the third transistor
  • the gate of the transistor receives an enable signal
  • the gate of the third transistor receives a first scan signal
  • the drain of the third transistor is electrically connected to the negative terminal of the first capacitor
  • the fifth transistor The source of is electrically connected to the positive terminal of the first capacitor
  • the source of the seventh transistor is electrically connected to the drain of the fourth transistor
  • the gate of the seventh transistor receives the first scan signal
  • the fourth transistor is in an on state, and the first transistor is located at the first end of the negative terminal of the first capacitor.
  • the reference point becomes low, and the first capacitor is in a charging state, wherein a start time of the first time period is when the first capacitor starts to be charged, and an end time of the first time period is the first time period. A capacitor is charged.
  • the second transistor, the third transistor, and the seventh transistor are in an on state.
  • the start time of the second time period is the end of charging of the first capacitor, and the end time of the second time period is that the potential of the first reference point located at the negative terminal of the first capacitor becomes gray
  • the difference between the degree data voltage and the threshold voltage of the first transistor causes the first transistor to be turned off.
  • the first transistor when the gate voltage of the first transistor is greater than a threshold voltage of the first transistor, the first transistor is in an on state, and the gray-scale data voltage signal is located at the The first reference point of the negative terminal of the first capacitor is charged until the potential of the first reference point becomes a difference between a grayscale data voltage and a threshold voltage of the first transistor, and the first transistor is turned off.
  • the first transistor, the eighth transistor, the fifth transistor, and the sixth transistor are at Off state, wherein the start time of the third time period is the difference between the potential of the first reference point and the gray-scale data voltage and the threshold voltage of the first transistor, and the first transistor is turned off, and The end time of the third time period is the end time of a timing cycle of the pixel driving circuit.
  • the third time period includes a plurality of first high-level sustaining times during which the enable signals maintain a high level.
  • a first high-level maintaining time of the enable signal maintaining a high level is greater than or equal to a sum of the first time period and the second time period.
  • the first transistor, the eighth transistor, the fifth transistor, and the sixth transistor are at On state.
  • the current flowing through the first transistor is Where K is the conductivity parameter.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor And the eighth transistor is a P-type transistor.
  • the present invention further provides a display device including the pixel driving circuit described above.
  • An advantage of the present invention is that the pixel driving circuit adds a TFT driven by an enable signal (EM signal) to the gate of the first transistor in the original pixel drive circuit, and enables the enable signal at the display stage. Send out a regular square wave signal, so that the fifth transistor, the sixth transistor, and the first transistor are turned off for a part of the display period. At the same time, the input frequency of the enable signal needs to make the pixels blink in the human eye recognition ability. In addition, the fifth transistor, the sixth transistor, and the first transistor will be turned off for a part of the display period, thereby avoiding damage to the device caused by the device being turned on for a long time, and increasing the life of the TFT device. Extends the life of the entire circuit.
  • EM signal enable signal
  • FIG. 1 is an equivalent circuit diagram of a conventional pixel driving circuit.
  • FIG. 2 is a driving timing chart of the pixel driving circuit described in FIG. 1.
  • FIG. 3 is a circuit diagram of a pixel driving circuit in an embodiment of the present invention.
  • FIG. 4 is a driving timing diagram of the pixel driving circuit described in FIG. 3, wherein an enabling signal timing is a high-level signal.
  • FIG. 5 is a driving timing chart of pixels in the n-th row of the conventional 7T1C.
  • a pixel driving circuit is provided.
  • the pixel driving circuit includes a light emitting device OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
  • the first end of the light-emitting device OLED is electrically connected to the drain of the sixth transistor T6 and the drain of the seventh transistor T7, the second end of the light-emitting device OLED is grounded, and the first capacitor
  • the positive terminal of C1 receives the power supply voltage signal Vdd
  • the negative terminal of the first capacitor C1 is electrically connected to the source of the fourth transistor T4 and the drain of the third transistor T3, and the gate of the fourth transistor T4.
  • the drain of the fourth transistor T4 receives the operating voltage signal Vi
  • the drain of the second transistor T2 receives the gray-scale data voltage signal Vdata
  • the A source is electrically connected to a source of the first transistor T1 and a drain of the fifth transistor T5
  • a drain of the first transistor T1 is electrically connected to a source of the sixth transistor T6.
  • the gate of the first transistor T1 is electrically connected to the negative terminal of the first capacitor C1
  • the source of the sixth transistor T6 is electrically connected to the source of the third transistor T3, and the gate of the sixth transistor T6 and
  • the gate of the fifth transistor T5 receives an enable signal EM
  • the third crystal The gate of the body tube T3 receives the first scan signal scan [n]
  • the drain of the third transistor T3 is electrically connected to the negative terminal of the first capacitor C1
  • the source of the fifth transistor T5 is electrically connected to The positive terminal of the first capacitor C1
  • the source of the seventh transistor T7 is electrically connected to the drain of the fourth transistor T4, and the gate of the seventh transistor T7 receives the first scan signal scan [n]
  • the pixel driving circuit further includes an eighth transistor T8, the drain of the eighth transistor T8 is electrically connected to the gate of the first transistor T1, and the gate of the eighth transistor T8 receives the enable signal EM
  • a source of the eighth transistor T8 is electrically connected to a negative
  • the seventh transistor T7 and the eighth transistor T8 are P-type transistors. Therefore, the gates of these transistors meet the conditions of being turned on by a low level and turned off by a high level.
  • the fourth transistor T4 in the first period of time, since the gate of the fourth transistor T4 is controlled by the second scan signal scan [n-1], when the second scan signal scan [n-1] When it is at a low level, the fourth transistor T4 is in an on state, a first reference point located at a negative terminal of the first capacitor C1 becomes a low level, and the first capacitor C1 is in a charging state, wherein the The first time period starts when the first capacitor C1 is charged, and the first time period ends when the first capacitor C1 is charged.
  • the second transistor T2, the third transistor T3, and the seventh transistor T7 are controlled by a first scan signal scan [n], when the first transistor When the scan signal scan [n] is at a low level, the second transistor T2, the third transistor T3, and the seventh transistor T7 are in an on state, wherein a start time of the second time period is The charging of the first capacitor C1 is completed, and the end time of the second period is that the potential of the first reference point located at the negative terminal of the first capacitor C1 becomes the gray-scale data voltage Vdata and the threshold voltage of the first transistor T1 The difference in Vth causes the first transistor T1 to be turned off.
  • the first transistor T1 In the second period, when the gate voltage of the first transistor T1 is greater than the threshold voltage Vth of the first transistor T1, the first transistor T1 is in an on state, so the first transistor T1 can be turned on.
  • the transistor T1 is regarded as a conducting diode, and the gray-scale data voltage signal Vdata charges a first reference point located at the negative terminal of the first capacitor C1 until the potential of the first reference point becomes gray-scale.
  • the first transistor T1 When the difference between the data voltage Vdata and the threshold voltage Vth of the first transistor T1, the first transistor T1 is turned off. That is, when the potential of the first reference point A is equal to Vdata-
  • the gate of the seventh transistor T7 is controlled by the first scan signal (scan [n] or Xscan [n]). Therefore, when the first scan signal Xscan [n] is At a low level, the seventh transistor T7 is in an on state, so the light emitting device OLED connected to the seventh transistor T7 is reset.
  • scan [n-1] is the n-1th scan signal
  • scan [n] is the nth scan signal
  • Xscan [n] is a signal related to scan [n], which can be related to scan [n] n]
  • EM is an enable signal or a light emission control signal.
  • the third period since the gates of the first transistor T1, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are controlled by the enable signal EM, when the enable signal EM is a high voltage Usually, the first transistor T1, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are in an off state, and the start time of the third period is the first reference point
  • the potential becomes the difference between the gray-scale data voltage Vdata and the threshold voltage Vth of the first transistor T1, the first transistor T1 is turned off, and the end time of the third period is a timing of the pixel driving circuit The end time of the cycle.
  • a plurality of first high-level sustaining times in which the enable signal EM maintains a high level are included, as shown in a1, a2,... In FIG. 4.
  • these first high-level sustaining times may be represented by X2, which may be the same or different from each other.
  • the enable signal EM is at a low level
  • the first transistor T1, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are in an on state. On state.
  • the gate-source voltage Vgs Vdd- (Vdata-
  • Vdd represents a power supply voltage
  • Vdata represents a gray-scale data voltage
  • Vth represents a threshold voltage of the first transistor T1.
  • K is the conductivity parameter.
  • the power supply voltage Vdd may be 4.6 volts, and the working voltage Vi is -2.5 volts.
  • the scanning frequency of the pixel driving circuit is 60 Hz, that is, the gate driving time t1 or t2 is equal to 1/60 / (1440 + blank) is about 6 ⁇ s.
  • 1440 is the scanning line amount
  • blank is the displacement amount.
  • the third time period t3 1 / 60-t1-t2, so the driving time is approximately 16.7 ms.
  • the gate of the eighth transistor T8 is controlled by the enable signal EM, and at the same time, the third transistor
  • the enable signal EM sends a regular square wave signal, so that the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are turned off for a part of the display period.
  • the input frequency of the enable signal EM needs to make the pixels flicker beyond the recognition ability of the human eye (that is, greater than 60 Hz), so that the fifth transistor T5, the sixth transistor T6, and the first transistor T1 will have a part of the time during the display stage. Being in the off state can not only avoid the problem that the TFT device is in the on state for a long time or cause damage to the TFT device, but also can increase the life of the TFT device and the life of the entire pixel driving circuit.
  • the light-emitting device described above may be an LED lamp, an OLED, or other light-emitting devices, which are not specifically limited in the embodiments of the present invention.
  • a display device is further provided.
  • the display device includes the pixel driving circuit described above.
  • the specific structure of the pixel driving circuit is not repeated here.
  • the display device includes, but is not limited to, a display.

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Abstract

一种像素驱动电路及显示装置，像素驱动电路通过在原有像素驱动电路中的第一晶体管（T1）的栅极新增一由使能信号（EM）驱动栅极的晶体管（T8），同时在显示阶段使使能信号（EM）发出一有规律的方波信号，使得第五晶体管（T5）、第六晶体管（T6）、第一晶体管（T1）在显示阶段中的一部分时间处于关断状态，同时使能信号（EM）的输入频率需使像素闪烁在人眼识别能力之外，这样第五晶体管（T5）、第六晶体管（T6）、第一晶体管（T1）就会在显示阶段有一部分时间处于关断状态，从而避免器件长时间处于开启状态给器件造成的损伤，并且增加了晶体管器件的寿命，以延长了整个电路的寿命。

Description

像素驱动电路和显示装置 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种像素驱动电路和显示装置。
背景技术
目前，主动矩阵有机发光二极体面板(Active-matrix Organic Light Emitting Diode，简称AMOLED)显示装置广泛应用于各类产品中，AMOLED显示装置由多行、多列的AMOLED像素组成。AMOLED像素通常由薄膜晶体管(Thin Film Transistor，简称TFT)构建像素驱动电路为有机发光二极管(Organic Light-Emitting Diode，简称OLED)器件提供相应的电流。以AMOLED的基本像素驱动电路为例，AMOLED的基本像素驱动电路如1所示，具体为7T1C电路。所述7T1C电路包括七个晶体管和一个电容。
传统的7T1C像素驱动电路等效如图1所示，驱动时序图如图2所示。所述7T1C像素驱动电路的工作原理如下：t1为准备阶段，在此阶段中，第二扫描信号scan[n-1]为低电位，于是第四晶体管T4开启，将参考点A的电位变为低电位，第一电容C1进行充电；t2为第一晶体管T1的阈值电压Vth的补偿阶段，在此阶段中，第一扫描信号scan[n]为低电位，于是第二晶体管T2、第三晶体管T3和第七晶体管T7开启。由于第一晶体管T1的栅极上有负电压，于是第一晶体管T1的源漏短接，参考点A的电位|V A|>|Vth|，即此时第一晶体管T1变为二极管，T1为开启，灰度数据电压Vdata通过第一晶体管T1给参考点A充电，直至参考点A的电压变为Vdata-|Vth|时,第一晶体管T1截止，另外由于第七晶体管T7开启，因此发光器件OLED被复位；t3为显示阶段，在此阶段中，使能信号EM为低电位，第五晶体管T5和第六晶体管T6开启，其中第一晶体管T1的Vgs＝Vdd‐(Vdata‐|Vth|)，经过第一晶体管T1的源漏极电流
Figure PCTCN2018124267-appb-000001
K＝CoxμW/L，电流流过发光器件OLED。在t3显示阶段，发光器件OLED工作，例如解析度为(1440*296018.5:9)的显示面板，栅极扫描的驱动电路的扫描频率是60HZ，也就是栅极驱动时间t1或t2＝1/60/(1440+blank)大约6us时间，其中blank为位移量，可忽略。由于一帧的时间为1/60s，t1+t2+t3为一帧，因此，t3＝1/60-t1-t2，其驱动时间16.7ms。然而，这个时间对于t3阶段打开的TFT(第一晶体管T1、第五晶体管T5、第六晶体管T6为开启的原因是使能信号EM长时间处于低电平，使得T5、T6两个TFT长时间处于开启状态，同时第一晶体管T1的栅极由于第一电容C1的原因，在发光阶段也是长时间处于低电平，并处于开启状态)是非常长的。
技术问题
TFT长时间处于开启状态会导致TFT器件长时间处于偏压stress状态，导致器件的开启电压、电子迁移率等电学特性发生漂移，从而影响整个屏幕的显示效果及缩短TFT器件的寿命。有鉴于此，亟需提供一种方案以解决上述问题。
技术解决方案
本发明的目的在于，提供一种像素驱动电路，第五晶体管T5、第六晶体管T6、第一晶体管T1就会在显示阶段有一部分时间处于关断状态，从而避免器件长时间处于开启状态给器件造成的损伤，并且增加了TFT器件的寿命。
根据本发明的一方面，本发明提供了一种像素驱动电路，所述像素驱动电路包括：一发光器 件、一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管和一第一电容；其中所述发光器件的第一端分别与所述第六晶体管的漏极和所述第七晶体管的漏极电连接，所述发光器件的第二端接地，所述第一电容的正极端接收电源电压信号，所述第一电容的负极端分别电连接至所述第四晶体管的源极和第三晶体管的漏极，所述第四晶体管的栅极接收一第二扫描信号，所述第四晶体管的漏极接收一工作电压信号，所述第二晶体管的漏极接收一灰度数据电压信号，所述第二晶体的源极分别电连接至所述第一晶体管的源极和所述第五晶体管的漏极，所述第一晶体管的漏极电连接至所述第六晶体管的源极，所述第一晶体管的栅极电连接至所述第一电容的负极端，所述第六晶体管的源极电连接至所述第三晶体管的源极，所述第六晶体管的栅极和所述第五晶体管的栅极接收一使能信号，所述第三晶体管的栅极接收一第一扫描信号，所述第三晶体管的漏极电连接至所述第一电容的负极端，所述第五晶体管的源极电连接至所述第一电容的正极端，所述第七晶体管的源极电连接至所述第四晶体管的漏极，所述第七晶体管的栅极接收所述第一扫描信号，其中所述像素驱动电路还包括一第八晶体管，所述第八晶体管的漏极电连接至所述第一晶体管的栅极，所述第八晶体管的栅极接收所述使能信号，所述第八晶体管的源极电连接至所述第一电容的负极端；在第一时间段内，当所述第二扫描信号为低电平时，所述第四晶体管处于导通状态，位于所述第一电容的负极端的第一参考点变为低电平，所述第一电容处于充电状态，其中所述第一时间段的起始时间为所述第一电容开始充电，所述第一时间段的结束时间为所述第一电容充电结束；在第二时间段内，当所述第一扫描信号为低电平时，所述第二晶体管、所述第三晶体管和所述第七晶体管处于导通状态，所述第二时间段的起始时间为所述第一电容充电结束，所述第二时间段的结束时间为位于所述第一电容的负极端的第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，使第一晶体管为截止状态。
根据本发明的另一方面，本发明提供了一种像素驱动电路，所述像素驱动电路包括：一发光器件、一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管和一第一电容；其中所述发光器件的第一端分别与所述第六晶体管的漏极和所述第七晶体管的漏极电连接，所述发光器件的第二端接地，所述第一电容的正极端接收一电源电压信号，所述第一电容的负极端分别电连接至所述第四晶体管的源极和第三晶体管的漏极，所述第四晶体管的栅极接收一第二扫描信号，所述第四晶体管的漏极接收一工作电压信号，所述第二晶体管的漏极接收一灰度数据电压信号，所述第二晶体的源极分别电连接至所述第一晶体管的源极和所述第五晶体管的漏极，所述第一晶体管的漏极电连接至所述第六晶体管的源极，所述第一晶体管的栅极电连接至所述第一电容的负极端，所述第六晶体管的源极电连接至所述第三晶体管的源极，所述第六晶体管的栅极和所述第五晶体管的栅极接收一使能信号，所述第三晶体管的栅极接收一第一扫描信号，所述第三晶体管的漏极电连接至所述第一电容的负极端，所述第五晶体管的源极电连接至所述第一电容的正极端，所述第七晶体管的源极电连接至所述第四晶体管的漏极，所述第七晶体管的栅极接收所述第一扫描信号；所述像素驱动电路还包括一第八晶体管，所述第八晶体管的漏极电连接至所述第一晶体管的栅极，所述第八晶体管的栅极接收使能信号，所述第八晶体管的源极电连接至所述第一电容的负极端。
在本发明的一实施例中，在第一时间段内，当所述第二扫描信号为低电平时，所述第四晶体管处于导通状态，位于所述第一电容的负极端的第一参考点变为低电平，所述第一电容处于充电状态，其中所述第一时间段的起始时间为所述第一电容开始充电，所述第一时间段的结束时间为所述第一电容充电结束。
在本发明的一实施例中，在第二时间段内，当所述第一扫描信号为低电平时，所述第二晶体管、所述第三晶体管和所述第七晶体管处于导通状态，其中，所述第二时间段的起始时间为 所述第一电容充电结束，所述第二时间段的结束时间为位于所述第一电容的负极端的第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，使第一晶体管为截止状态。
在本发明的一实施例中，当所述第一晶体管的栅极电压大于所述第一晶体管的阈值电压时，所述第一晶体管处于导通状态，所述灰度数据电压信号向位于所述第一电容的负极端的第一参考点充电，直至所述第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差时，所述第一晶体管转为截止状态。
在本发明的一实施例中，在第三时间段内且所述使能信号为高电平时，所述第一晶体管、所述第八晶体管、所述第五晶体管和所述第六晶体管处于截止状态，其中所述第三时间段的开始时间为所述第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，所述第一晶体管转为截止状态，所述第三时间段的结束时间为所述像素驱动电路的一时序周期的结束时间。
在本发明的一实施例中，所述第三时间段包括多个所述使能信号维持高电平的第一高电平维持时间。
在本发明的一实施例中，所述使能信号维持高电平的第一高电平维持时间大于或等于第一时间段和第二时间段之和。
在本发明的一实施例中，在第三时间段内且所述使能信号为低电平时，所述第一晶体管、所述第八晶体管、所述第五晶体管和所述第六晶体管处于导通状态。
在本发明的一实施例中，流经所述第一晶体管的电流为
Figure PCTCN2018124267-appb-000002
其中K为导电参数。
在本发明的一实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管为P型晶体管。根据本发明的另一方面，本发明还提供一种显示装置，所述显示装置包括上述的像素驱动电路。
有益效果
本发明的优点在于，所述像素驱动电路通过在原有像素驱动电路中的第一晶体管的栅极新增一由使能信号(EM信号)驱动栅极的TFT，同时在显示阶段使使能信号发出一有规律的方波信号，使得第五晶体管、第六晶体管、第一晶体管在显示阶段中的一部分时间处于关断状态，同时使能信号的输入频率需使像素闪烁在人眼识别能力之外，以至第五晶体管、第六晶体管、第一晶体管就会在显示阶段有一部分时间处于关断状态，从而避免器件长时间处于开启状态给器件造成的损伤，并且增加了TFT器件的寿命，以延长了整个电路的寿命。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有的像素驱动电路的等效电路图。
图2是图1所述的像素驱动电路的驱动时序图。
图3是本发明一实施例中的像素驱动电路的电路图。
图4是图3所述的像素驱动电路的驱动时序图，其中使能信号时序为高位信号。
图5是传统7T1C的第n行像素的驱动时序图。
本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本发明公开的原理的各实施例仅用于说明，而不应解释为限制本发明公开的范围。所属领域的技术人员将理解，本发明的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本发明说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本发明的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本发明说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本发明说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。本发明实施例提供一种像素驱动电路及显示装置。以下将分别进行详细说明。
参见图3至图4所示，在本发明的一实施例中，提供一种像素驱动电路。
所述像素驱动电路包括：发光器件OLED、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第一电容C1。其中所述发光器件OLED的第一端分别与所述第六晶体管T6的漏极和所述第七晶体管T7的漏极电连接，所述发光器件OLED的第二端接地，所述第一电容C1的正极端接收电源电压信号Vdd，所述第一电容C1的负极端分别电连接至所述第四晶体管T4的源极和第三晶体管T3的漏极，所述第四晶体管T4的栅极接收第二扫描信号scan[n-1]，所述第四晶体管T4的漏极接收工作电压信号Vi，所述第二晶体管T2的漏极接收灰度数据电压信号Vdata，所述第二晶体的源极分别电连接至所述第一晶体管T1的源极和所述第五晶体管T5的漏极，所述第一晶体管T1的漏极电连接至所述第六晶体管T6的源极，所述第一晶体管T1的栅极电连接至所述第一电容C1的负极端，所述第六晶体管T6的源极电连接至第三晶体管T3的源极，所述第六晶体管T6的栅极和所述第五晶体管T5的栅极接收一使能信号EM，所述第三晶体管T3的栅极接收第一扫描信号scan[n]，所述第三晶体管T3的漏极电连接至所述第一电容C1的负极端，所述第五晶体管T5的源极电连接至所述第一电容C1的正极端，所述第七晶体管T7的源极电连接至所述第四晶体管T4的漏极，所述第七晶体管T7的栅极接收第一扫描信号scan[n]；所述像素驱动电路还包括一第八晶体管T8，所述第八晶体管T8的漏极电连接至所述第一晶体管T1的栅极，所述第八晶体管T8的栅极接收使能信号EM，所述第八晶体管T8的源极电连接至所述第一电容C1的负极端。
在本实施例中，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7和所述第八晶体管T8为P型晶体管。因此，该些晶体管的栅极满足受低电平使其导通，高电平使其截止条件。在本实施例中，在第一时间段内，由于第四晶体管T4的栅极受到第二扫描信号scan[n-1]的控制，因此，当所述第二扫描信号scan[n-1]为低电平时，所述第四晶体管T4处于导通状态，位于所述第一电容C1的负极端的第一参考点变为低电平，所述第一电容C1处于充电状态， 其中所述第一时间段的起始时间为所述第一电容C1开始充电，所述第一时间段的结束时间为所述第一电容C1充电结束。
在第二时间段内，由于所述第二晶体管T2、所述第三晶体管T3和所述第七晶体管T7的栅极受到第一扫描信号scan[n]的控制，因此，当所述第一扫描信号scan[n]为低电平时，所述第二晶体管T2、所述第三晶体管T3和所述第七晶体管T7处于导通状态，其中，所述第二时间段的起始时间为所述第一电容C1充电结束，所述第二时间段的结束时间为位于所述第一电容C1的负极端的第一参考点的电位变为灰度数据电压Vdata与第一晶体管T1的阈值电压Vth之差，使第一晶体管T1为截止状态。
在第二时间段内，由于当所述第一晶体管T1的栅极电压大于第一晶体管T1的阈值电压Vth时，因此，所述第一晶体管T1处于导通状态，于是可以将所述第一晶体管T1视为一导通的二极管，所述灰度数据电压信号Vdata向位于所述第一电容C1的负极端的第一参考点进行充电，直至所述第一参考点的电位变为灰度数据电压Vdata与第一晶体管T1的阈值电压Vth之差时，所述第一晶体管T1转为截止状态。也就是说，第一参考点A的电位等于Vdata-|Vth|时，所述第一晶体管T1为截止，Vdata表示灰度数据电压，Vth表示第一晶体管T1的阈值电压。
另外，在此第二时间段内，第七晶体管T7的栅极受到第一扫描信号(scan[n]或Xscan[n])的控制，因此，当所述第一扫描信号Xscan[n]为低电平时，所述第七晶体管T7为导通状态，于是，与所述第七晶体管T7相连的发光器件OLED进行复位。需说明的是,scan[n-1]为第n-1个扫描信号，scan[n]为第n个扫描信号，Xscan[n]为与scan[n]相关的信号，可以是与scan[n]相同的信号，EM为使能信号或称发光控制信号。
在第三时间段内，由于第一晶体管T1、第八晶体管T8、第五晶体管T5和第六晶体管T6的栅极受到使能信号EM的控制，因此，当所述使能信号EM为高电平时，所述第一晶体管T1、所述第八晶体管T8、所述第五晶体管T5和所述第六晶体管T6处于截止状态，其中所述第三时间段的开始时间为所述第一参考点的电位变为灰度数据电压Vdata与第一晶体管T1的阈值电压Vth之差，所述第一晶体管T1转为截止状态，所述第三时间段的结束时间为所述像素驱动电路的一时序周期的结束时间。
在本实施例中，在所述第三时间段内，包括多个所述使能信号EM维持高电平的第一高电平维持时间，如图4所示的a1,a2…。当然这些第一高电平维持时间可以用X2表示，其可以是彼此相同或不同。与图5所示的传统7T1C的第n行像素的驱动时序图相比，在图4所示的本发明像素驱动电路的驱动时序图中，在所述第三时间段内，有多个使能信号EM维持高电平。另外，在本实施例中，将所述使能信号EM维持高电平的第一高电平维持时间X2设置为大于或等于第一时间段和第二时间段之和(X1＝t1+t2)。这样，在整个第三时间段内，有一定的时间，使得第一晶体管T1、第五晶体管T5和第六晶体管T6处于关断状态，从而避免TFT器件长时间处于开启状态。
当然，在第三时间段内，如果所述使能信号EM为低电平时，所述第一晶体管T1、所述第八晶体管T8、所述第五晶体管T5和所述第六晶体管T6处于导通状态。
由于所述第一晶体管T1和第八晶体管T8为开启状态，因此，所述第一晶体管T1的栅极-源极电压Vgs＝Vdd-(Vdata-|Vth|)，其中，Vdd表示电源电压，Vdata表示灰度数据电压，Vth表示第一晶体管T1的阈值电压。此时，流经所述第一晶体管T1的电流为
Figure PCTCN2018124267-appb-000003
其中K为导电参数。
在本实施例中，电源电压Vdd可以为4.6伏，工作电压Vi为-2.5伏。
在第三时间段内为发光器件OLED的工作阶段，假设像素驱动电路的扫描频率为60赫兹， 也就是栅极驱动时间t1或t2等于1/60/(1440+blank)大约为6μs。其中，1440为扫描线量,blank为位移量。
第三时间段t3＝1/60-t1-t2，因此，驱动时间大致为16.7ms。在此时间内，通过在第一参考点和第一晶体管T1之间设置第八晶体管T8，第八晶体管T8的栅极由使能信号EM控制，同时在第三时间段(即显示阶段)使使能信号EM发出一有规律的方波信号，于是使得第五晶体管T5、第六晶体管T6和第一晶体管T1在显示阶段的一部分时间内处于关断状态。另外，使能信号EM的输入频率需使像素闪烁在人眼识别能力之外(即大于60赫兹)，这样第五晶体管T5、第六晶体管T6和第一晶体管T1就会在显示阶段有一部分时间处于关断状态，从而不仅能够避免TFT器件长时间处于开启状态以至TFT器件造成损伤的问题，而且能够增加了TFT器件的寿命以及整个像素驱动电路的寿命。
另外，上述的发光器件可以为LED灯，也可以为OLED，还可以为其他的发光器件，本发明实施例不作具体限定。
另外，本发明的一实施例中，还提供一种显示装置，所述显示装置包括上述的像素驱动电路。所述像素驱动电路的具体结构在此不再赘述。可选的，所述显示装置包括但不限于显示器。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
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  1. 一种像素驱动电路，所述像素驱动电路包括：一发光器件、一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管和一第一电容；其中所述发光器件的第一端分别与所述第六晶体管的漏极和所述第七晶体管的漏极电连接，所述发光器件的第二端接地，所述第一电容的正极端接收一电源电压信号，所述第一电容的负极端分别电连接至所述第四晶体管的源极和第三晶体管的漏极，所述第四晶体管的栅极接收一第二扫描信号，所述第四晶体管的漏极接收一工作电压信号，所述第二晶体管的漏极接收一灰度数据电压信号，所述第二晶体的源极分别电连接至所述第一晶体管的源极和所述第五晶体管的漏极，所述第一晶体管的漏极电连接至所述第六晶体管的源极，所述第一晶体管的栅极电连接至所述第一电容的负极端，所述第六晶体管的源极电连接至所述第三晶体管的源极，所述第六晶体管的栅极和所述第五晶体管的栅极接收一使能信号，所述第三晶体管的栅极接收一第一扫描信号，所述第三晶体管的漏极电连接至所述第一电容的负极端，所述第五晶体管的源极电连接至所述第一电容的正极端，所述第七晶体管的源极电连接至所述第四晶体管的漏极，所述第七晶体管的栅极接收所述第一扫描信号，其中所述像素驱动电路还包括一第八晶体管，所述第八晶体管的漏极电连接至所述第一晶体管的栅极，所述第八晶 体管的栅极接收所述使能信号，所述第八晶体管的源极电连接至所述第一电容的负极端；在第一时间段内，当所述第二扫描信号为低电平时，所述第四晶体管处于导通状态，位于所述第一电容的负极端的第一参考点变为低电平，所述第一电容处于充电状态，其中所述第一时间段的起始时间为所述第一电容开始充电，所述第一时间段的结束时间为所述第一电容充电结束；在第二时间段内，当所述第一扫描信号为低电平时，所述第二晶体管、所述第三晶体管和所述第七晶体管处于导通状态，所述第二时间段的起始时间为所述第一电容充电结束，所述第二时间段的结束时间为位于所述第一电容的负极端的第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，使所述第一晶体管为截止状态。
  2. 一种像素驱动电路，所述像素驱动电路包括：一发光器件、一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管和一第一电容；其中所述发光器件的第一端分别与所述第六晶体管的漏极和所述第七晶体管的漏极电连接，所述发光器件的第二端接地，所述第一电容的正极端接收电源电压信号，所述第一电容的负极端分别电连接至所述第四晶体管的源极和第三晶体管的漏极，所述第四晶体管的栅极接收第二扫描信号，所述第四晶体管的漏极接收一工作电压信号，所述第二晶体管的漏极接收一灰度数据电压信号，所述第二晶体的源极分别电连接至所述第一晶体管的源极和所述第五晶体管的漏极，所述第一晶体管的漏极电连接至所述第六晶体管 的源极，所述第一晶体管的栅极电连接至所述第一电容的负极端，所述第六晶体管的源极电连接至第三晶体管的源极，所述第六晶体管的栅极和所述第五晶体管的栅极接收一使能信号，所述第三晶体管的栅极接收一第一扫描信号，所述第三晶体管的漏极电连接至所述第一电容的负极端，所述第五晶体管的源极电连接至所述第一电容的正极端，所述第七晶体管的源极电连接至所述第四晶体管的漏极，所述第七晶体管的栅极接收所述第一扫描信号，其中所述像素驱动电路还包括一第八晶体管，所述第八晶体管的漏极电连接至所述第一晶体管的栅极，所述第八晶体管的栅极接收所述使能信号，所述第八晶体管的源极电连接至所述第一电容的负极端。
  3. 根据权利要求2所述的像素驱动电路，其中在第一时间段内，当所述第二扫描信号为低电平时，所述第四晶体管处于导通状态，位于所述第一电容的负极端的第一参考点变为低电平，所述第一电容处于充电状态，所述第一时间段的起始时间为所述第一电容开始充电，所述第一时间段的结束时间为所述第一电容充电结束。
  4. 根据权利要求2所述的像素驱动电路，其中在第二时间段内，当所述第一扫描信号为低电平时，所述第二晶体管、所述第三晶体管和所述第七晶体管处于导通状态，所述第二时间段的起始时间为所述第一电容充电结束，所述第二时间段的结束时间为位于所述第一电容的负极端的第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，使第一晶体管为截止状态。
  5. 根据权利要求4所述的像素驱动电路，其中当所述第一晶体管的栅极电压大于所述第一晶体管的阈值电压时，所述第一晶体管处于导通状态，所述灰度数据电压信号向位于所述第一电容的负极端的第一参考点充电，直至所述第一参考点的电位变为灰度数据电压与所述第一晶体管的阈值电压之差时，所述第一晶体管转为截止状态。
  6. 根据权利要求2所述的像素驱动电路，其中在第三时间段内且所述使能信号为高电平时，所述第一晶体管、所述第八晶体管、所述第五晶体管和所述第六晶体管处于截止状态，其中所述第三时间段的开始时间为所述第一参考点的电位变为灰度数据电压与第一晶体管的阈值电压之差，所述第一晶体管转为截止状态，所述第三时间段的结束时间为所述像素驱动电路的一时序周期的结束时间。
  7. 根据权利要求6所述的像素驱动电路，其中所述第三时间段包括多个所述使能信号维持高电平的第一高电平维持时间。
  8. 根据权利要求6所述的像素驱动电路，其中所述使能信号维持高电平的第一高电平维持时间大于或等于第一时间段和第二时间段之和。
  9. 根据权利要求2所述的像素驱动电路，其中在第三时间段内且所述使能信号为低电平时，所述第一晶体管、所述第八晶体管、所述第五晶体管和所述第六晶体管处于导通状态。
  10. 根据权利要求9所述的像素驱动电路，其中流经所述第一晶体管的电流为
    Figure PCTCN2018124267-appb-100001
    其中K为导电参数。
  11. 根据权利要求2所述的像素驱动电路，其中所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管为P型晶体管。
  12. 一种显示装置，其中所述显示装置包括如权利要求2至11中任一项所述的像素驱动电路。
PCT/CN2018/124267 2018-09-27 2018-12-27 像素驱动电路和显示装置 Ceased WO2020062676A1 (zh)

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