WO2020062551A1 - 显示面板驱动电路及显示装置 - Google Patents

显示面板驱动电路及显示装置 Download PDF

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Publication number
WO2020062551A1
WO2020062551A1 PCT/CN2018/119047 CN2018119047W WO2020062551A1 WO 2020062551 A1 WO2020062551 A1 WO 2020062551A1 CN 2018119047 W CN2018119047 W CN 2018119047W WO 2020062551 A1 WO2020062551 A1 WO 2020062551A1
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WO
WIPO (PCT)
Prior art keywords
signal
communication
terminal
input terminal
output
Prior art date
Application number
PCT/CN2018/119047
Other languages
English (en)
French (fr)
Inventor
黄笑宇
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Publication date
Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/317,036 priority Critical patent/US10991296B2/en
Publication of WO2020062551A1 publication Critical patent/WO2020062551A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/042—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller for monitor identification

Definitions

  • the present application relates to the field of display driving technology, and in particular, to a display panel driving circuit and a display device.
  • the timing controller TCON The data in the internal static read-only memory (SROM) of the IC cannot generally be saved after power failure, and the EEPROM (Electrically Erasable Programmable read only memory, erasable memory) or data stored in the flash memory can be saved even after power failure, so the control program of the timing controller will be stored in the external memory EEPROM or Flash. After power-on, the timing controller will initialize, read timing control data from the internal memory through the bus, and then connect to the external control chip through the bus.
  • SROM static read-only memory
  • EEPROM Electrical Erasable Programmable read only memory, erasable memory
  • the memory and the timing controller are connected to the timing controller through the communication bus, when the timing control data is read from the external memory through the bus, the control signal of the control chip may interfere with the timing controller and the memory. Data read, resulting in data read failure.
  • the main purpose of this application is to propose a display panel driving circuit and a display device, which aim to solve the problem of reading errors of the timing controller software and improve the reliability of the display device.
  • the display panel driving circuit includes:
  • the connector is configured to access the serial communication bus and drive power
  • the communication switch circuit includes a reference voltage input terminal, a driving signal input terminal, a communication signal input terminal, and a communication signal output terminal, and the communication signal input terminal is communicatively connected to the serial communication bus through the connector;
  • the timing controller includes a data transmission terminal and a control terminal.
  • the data transmission terminal is connected to a communication signal output terminal of the communication control circuit and a data output terminal of the memory.
  • the control terminal is driven by the communication switch circuit.
  • a signal input terminal is connected, and the reference voltage input terminal is connected to the driving power source through the connector;
  • the timing controller is configured to output a driving signal to a driving signal input terminal of the communication switch circuit
  • the communication switch circuit is configured to be turned on or off according to a driving signal and a signal input from the reference voltage input terminal;
  • the timing controller is further configured to receive a communication signal connected to the serial communication bus when the communication switch circuit is turned on, and read software data of the memory when the communication switch circuit is turned off.
  • the communication switch circuit includes a signal comparison unit, a signal trigger unit, and a communication signal output unit.
  • a first input terminal of the signal comparison unit is the reference voltage input terminal, and a second input of the signal comparison unit.
  • the terminal is a driving signal input terminal.
  • the output terminal of the signal comparison unit is connected to the input terminal of the signal trigger unit.
  • the output terminal of the signal trigger unit is connected to the controlled terminal of the communication signal output unit.
  • An input end of the signal output unit is connected to the connector, and an output end of the communication signal output unit is a communication signal output end of the communication switch circuit.
  • the signal comparison unit includes a first comparator, a non-inverting input terminal of the first comparator is a second input terminal of the signal comparison unit, and an inverting input terminal of the first comparator is A first output terminal of the signal comparison unit, and an output terminal of the first comparator is an output terminal of the signal comparison unit.
  • the display panel driving circuit further includes a first DC power source;
  • the signal trigger unit includes a trigger, and a clock signal input terminal of the trigger is an input terminal of the signal trigger unit, and the trigger The signal output terminal of is the output terminal of the signal triggering unit, and the signal input terminal of the trigger is connected to the first DC power source.
  • the signal triggering unit further includes a first resistor, a first terminal of the first resistor is connected to an output terminal of the signal comparison unit, and a second terminal of the first resistor is grounded.
  • the communication signal output unit includes a first electronic switch and a second resistor, the controlled end of the first electronic switch is the controlled end of the communication signal output unit, and the input of the first electronic switch Terminal is the input terminal of the communication signal output unit, and the output terminal of the first electronic switch is the output terminal of the communication signal output unit; the first terminal of the second resistor and the receiving end of the first electronic switch The control terminal is connected, and the second terminal of the second resistor is connected to the input terminal of the first electronic switch.
  • the display panel driving circuit further includes a unidirectional conduction element, an input end of the unidirectional conduction element is connected to the memory, and an output end of the unidirectional conduction element is connected to the timing controller.
  • the display panel driving circuit further includes a gate driving circuit and a source driving circuit, and the controlled ends of the gate driving circuit and the source driving circuit are respectively connected to the output terminal of the timing controller.
  • the present application also proposes a display device including a display panel and the display panel driving circuit as described above.
  • the display panel driving circuit includes:
  • the connector is configured to access the serial communication bus and drive power
  • the communication switch circuit includes a reference voltage input terminal, a driving signal input terminal, a communication signal input terminal, and a communication signal output terminal, and the communication signal input terminal is communicatively connected to the serial communication bus through the connector;
  • the timing controller includes a data transmission terminal and a control terminal.
  • the data transmission terminal is connected to a communication signal output terminal of the communication control circuit and a data output terminal of the memory.
  • the control terminal is driven by the communication switch circuit.
  • a signal input terminal is connected, and the reference voltage input terminal is connected to the driving power source through the connector;
  • the timing controller is configured to output a driving signal to a driving signal input terminal of the communication switch circuit
  • the communication switch circuit is configured to be turned on or off according to a driving signal and a signal input from the reference voltage input terminal;
  • the timing controller is further configured to receive a communication signal connected to the serial communication bus when the communication switch circuit is turned on, and read software data of the memory when the communication switch circuit is turned off;
  • a gate driving circuit and a source driving circuit of the display panel driving circuit are electrically connected to the display panel, respectively.
  • the display device further includes a power management circuit, and an input end of the power management circuit is connected to a driving power source through a connector of the display panel driving circuit, and an output end of the power management circuit is connected to the The electrode driving circuit, the source driving circuit and the display panel driving circuit timing controller are connected.
  • the communication switch circuit includes a signal comparison unit, a signal trigger unit, and a communication signal output unit.
  • a first input terminal of the signal comparison unit is the reference voltage input terminal, and a second input of the signal comparison unit.
  • the terminal is a driving signal input terminal.
  • the output terminal of the signal comparison unit is connected to the input terminal of the signal trigger unit.
  • the output terminal of the signal trigger unit is connected to the controlled terminal of the communication signal output unit.
  • An input end of the signal output unit is connected to the connector, and an output end of the communication signal output unit is a communication signal output end of the communication switch circuit.
  • the signal comparison unit includes a first comparator, a non-inverting input terminal of the first comparator is a second input terminal of the signal comparison unit, and an inverting input terminal of the first comparator is A first output terminal of the signal comparison unit, and an output terminal of the first comparator is an output terminal of the signal comparison unit.
  • the display device further includes a first DC power source;
  • the signal trigger unit includes a trigger, and a clock signal input terminal of the trigger is an input terminal of the signal trigger unit, and a signal of the trigger
  • the output terminal is the output terminal of the signal triggering unit, and the signal input terminal of the trigger is connected to the first DC power source.
  • the signal triggering unit further includes a first resistor, a first terminal of the first resistor is connected to an output terminal of the signal comparison unit, and a second terminal of the first resistor is grounded.
  • the communication signal output unit includes a first electronic switch and a second resistor, the controlled end of the first electronic switch is the controlled end of the communication signal output unit, and the input of the first electronic switch Terminal is the input terminal of the communication signal output unit, and the output terminal of the first electronic switch is the output terminal of the communication signal output unit; the first terminal of the second resistor and the receiving end of the first electronic switch The control terminal is connected, and the second terminal of the second resistor is connected to the input terminal of the first electronic switch.
  • the display device further includes a unidirectional conduction element, an input end of the unidirectional conduction element is connected to the memory, and an output end of the unidirectional conduction element is connected to the timing controller.
  • the display panel driving circuit further includes a gate driving circuit and
  • the source driving circuit, the gate driving circuit and the controlled ends of the source driving circuit are respectively connected to the output terminal of the timing controller.
  • the display panel is a liquid crystal display or an organic light emitting diode display.
  • a timing controller and a memory are provided, and a communication connection is performed through a serial communication bus, and a communication switch circuit is arranged in series between a connector for connecting an external control chip and the timing controller.
  • the communication switch circuit is based on the timing control.
  • the driving signal of the circuit is controlled, and when the timing controller outputs a low-level driving signal to control the communication switch circuit to be closed, the timing controller and the memory are communicably connected, so that the timing controller reads the software data of the memory to complete the timing The initial settings of the controller.
  • the timing controller When the timing controller outputs a high-level driving signal to control the communication switch circuit to open, the timing controller and the external control chip are communicatively connected to receive the control signal output from the external control chip and convert it to the corresponding driving signal and output.
  • the image display of the display panel is completed.
  • This application solves that when the timing controller reads the data in the memory, the data in the memory may enter the external control chip, which causes the work of the external control chip to be disordered, or the data signals of the external control chip are output to the timing controller or the memory. As a result, the timing controller fails to read the memory data. This application effectively solves the problem of reading errors of the timing controller software and improves the reliability of the display device.
  • FIG. 1 is a schematic diagram of functional modules of an embodiment of a display panel driving circuit of the present application
  • FIG. 2 is a schematic circuit structure diagram of an embodiment of a display panel driving circuit of the present application.
  • FIG. 3 is a schematic circuit structure diagram of an embodiment of a display device of the present application.
  • the directional indication is only used to explain in a specific posture (as shown in the drawings) (Shown) the relative positional relationship, movement, etc. of the various components, if the specific posture changes, the directional indicator will change accordingly.
  • the present application proposes a display panel driving circuit.
  • the display panel driving circuit includes:
  • the connector 20 is configured to access a serial communication bus and a driving power source
  • the communication switch circuit 30 includes a reference voltage input terminal, a driving signal input terminal, a communication signal input terminal, and a communication signal output terminal, and the communication signal input terminal is communicatively connected to the serial communication bus through the connector 20;
  • the timing controller 40 includes a data transmission end and a control end.
  • the data transmission end is connected to a communication signal output end of the communication control circuit and a data output end of the memory 10.
  • the control end is connected to the communication switch circuit.
  • the driving signal input terminal is connected, and the reference voltage input terminal is connected to the driving power source through the connector 20; wherein,
  • the timing controller 40 is configured to output a driving signal to a driving signal input terminal of the communication switch circuit 30;
  • the communication switch circuit 30 is configured to be turned on or off according to a driving signal and a signal input from the reference voltage input terminal;
  • the timing controller 40 is further configured to receive a communication signal connected to the serial communication bus when the communication switch circuit 30 is turned on, and read the memory 10 of the memory 10 when the communication switch circuit is turned off. Software data.
  • the display panel driving circuit further includes a gate driving circuit 100, a source driving circuit 500, and a power management integrated circuit 400.
  • the gate driving circuit 100 and controlled terminals of the source driving circuit 500 Respectively connected to the output terminal of the timing controller 40, the input terminal of the power management integrated circuit is connected to the driving power via the connector 20, and the output terminal is connected to the timing controller 40, the gate driving circuit 100 and the source driving circuit 500 connection.
  • Both the memory 10 and the timing controller 40 can be set in timing control (Timing Controller (TCON) PCB, timing control (Timing Controller (TCON) PCB is also provided with a power management integrated circuit.
  • the power management integrated circuit uses the connector 20 and the driving power in the display device to convert the driving power to the timing controller 40 and the gate driving circuit 100.
  • the source driving circuit 500 provides an operating voltage.
  • the memory 10 can store control signals for driving the gate driving circuit 100 and the source driving circuit 500 to work, and is communicatively connected to the timing controller 40 through a serial communication bus.
  • the timing controller 40 When the display device is powered on, the timing controller 40 reads The control signals in the memory 10 and other setting data are taken for initial setting to generate corresponding timing control signals, thereby driving the source driving circuit 500 and the gate driving circuit 100 in the display device to work.
  • the data in the memory 10 cannot be modified during the normal operation of the display device. Once modified, the setting data is wrong, which will cause the display device to display abnormally. Therefore, most of the memory 10 is provided with a write protection pin (WP pin), and when the high level is input, the memory 10 can be controlled to write data, and at the low level, data cannot be written. At this time, the memory 10 can only read data from the timing controller 40.
  • WP pin write protection pin
  • a power management integrated circuit is also provided on the timing control board, and the output terminals of the power management integrated circuit are respectively connected to the memory 10 and the timing controller 40.
  • the serial communication bus may use (I2Cnter-Integrated Circuit) communication bus, of course, other communication lines can also be used to implement it, and there is no limitation here.
  • the connector 20 can be connected to a control chip such as a main controller of a display device or a video processing chip through a communication bus.
  • a control chip such as a main controller of a display device or a video processing chip
  • each external control chip is connected to a timing controller through a serial communication bus. 40 connections.
  • the timing controller 40 can receive R / G / B compression signals and control signals via the serial communication bus.
  • the driving power is connected to the power management integrated circuit through the power cord.
  • the power management integrated circuit converts the received power into corresponding driving power and outputs it to the circuit module on the timing control board.
  • the timing controller 40 converts the received R / G / B compression signals and control signals into data signals and control signals suitable for the source driving circuit 500 and the gate driving circuit 100 in the display device. And the clock signal to realize the image display of the display panel 200.
  • the external control chip, the timing controller 40, and the memory 10 are all connected through a serial communication bus, and the timing controller 40 needs to read the data of the memory 10 and the external control chip to implement the display panel 200. drive. Therefore, when the timing controller 40 reads data, it may affect other chips. For example, when the timing controller 40 reads the data of the memory 10, the data of the memory 10 may enter the external control chip through the communication bus. As a result, the work of the external control chip is disordered, or when the timing controller 40 reads the data of the memory 10, the data signal of the external control chip is output to the timing controller 40 or the memory 10, which causes the timing controller 40 to read the data of the memory 10. failure.
  • the display panel driving circuit of this embodiment may be provided with a communication switch circuit 30 to implement switching of the communication circuit.
  • the reference voltage input terminal and the driving signal input terminal of the communication switch circuit 30 are respectively connected to the driving power source and the control terminal of the timing controller 40, and are turned on / off by receiving a control signal output by the timing controller 40.
  • the timing controller 40 When the display device is powered on, the timing controller 40 outputs a low-level driving signal to the driving signal input terminal. At this time, the voltage value of the driving signal is less than the driving power source voltage, and the communication switch circuit 30 is in an off state.
  • the timing controller 40 is communicatively connected to the memory 10 through a serial communication bus, so as to read software data of the memory 10 and realize the initial setting of the timing controller 40.
  • the communication switch circuit 30 is in an off state, so the data of the external control chip will not be output to the memory 10 or the timing controller 40 via the serial communication bus, and it will interfere with the timing controller 40 reading the data of the memory 10,
  • the data of the memory 10 will not enter into the external control chip, and the function of the external control chip will be disordered.
  • the timing controller 40 outputs a high-level driving signal to the driving signal input terminal, thereby driving the communication switch circuit 30 to turn on.
  • the timing controller 40 communicates with the outside through the serial communication bus.
  • the control chip is communicatively connected, so as to receive control signals, data signals and clock signals output by the external control chip, and convert them into corresponding driving signals and output them, thereby completing the image display of the display panel 200.
  • the timing controller 40 and the memory 10 are provided, and communication connection is performed through a serial communication bus, and the communication switch circuit 30 is arranged in series between the connector 20 for connecting an external control chip and the timing controller 40 to communicate with each other.
  • the switch circuit 30 is controlled based on the driving signal of the timing control circuit, and when the timing controller 40 outputs a low-level driving signal to control the communication switch circuit 30 to close, the timing controller 40 and the memory 10 are communicatively connected to enable the timing controller 40 reads the software data of the memory 10 to complete the initial setting of the timing controller 40.
  • the timing controller 40 When the timing controller 40 outputs a high-level driving signal to control the communication switch circuit 30 to be turned on, the timing controller 40 is communicably connected to an external control chip, so as to receive the control signal output by the external control chip and convert it into a corresponding driving signal. After output, the image display of the display panel 200 is completed.
  • the present application solves that when the timing controller 40 reads the data of the memory 10, the data of the memory 10 may enter the external control chip, which causes the work of the external control chip to be disordered, or the data signals of the external control chip are output to the timing controller. 40 or the memory 10, which causes the timing controller 40 to fail to read the data of the memory 10. This application effectively solves the problem of software read errors of the timing controller 40 and improves the reliability of the display device.
  • the communication switch circuit 30 includes a signal comparison unit 31, a signal trigger unit 32, and a communication signal output unit 33.
  • the first input end of the signal comparison unit 31 is The reference voltage input terminal
  • the second input terminal of the signal comparison unit 31 is a drive signal input terminal
  • the output terminal of the signal comparison unit 31 is connected to the input terminal of the signal trigger unit 32
  • the signal trigger unit The output of 32 is connected to the controlled end of the communication signal output unit 33
  • the input of the communication signal output unit 33 is connected to the connector 20, and the output of the communication signal output unit 33 is the communication A communication signal output terminal of the switch circuit 30.
  • the first input terminal and the second input terminal of the signal comparison unit 31 are respectively connected to the control terminal and the driving power of the timing controller 40, and receive the control signal output by the timing controller 40 to be turned on / off.
  • the controller 40 outputs a low-level driving signal to the second input terminal
  • the voltage signal value of the second input terminal is smaller than the power supply voltage value of the first input terminal at this time, thereby outputting a low-level trigger signal.
  • the timing controller 40 outputs a high-level driving signal to the second input terminal, the voltage signal value of the second input terminal is greater than the power supply voltage value of the first input terminal, and a high-level trigger signal is output.
  • the signal trigger unit 32 operates when the signal comparison unit 31 outputs a high-level trigger signal, thereby controlling the communication signal output unit 33 to turn on, so as to implement the timing controller 40 to communicate with the external control chip through the connector 20 and the communication bus.
  • the signal comparison unit 31 outputs a low-level trigger signal, it does not operate, so that the communication signal output unit 33 is controlled to be closed, so that the timing controller 40 is disconnected from the communication connection with the external control chip.
  • the signal comparison unit 31 further includes a first comparator U1, and a non-inverting input terminal of the first comparator U1 is a second input terminal of the signal comparison unit 31.
  • the inverting input terminal of the first comparator U1 is the first output terminal of the signal comparison unit 31, and the output terminal of the first comparator U1 is the output terminal of the signal comparison unit 31.
  • the non-inverting input terminal of the first comparator U1 is connected to the timing controller 40, and the inverting input terminal is connected to the external driving power source through the connector 20. It can be understood that the high level output by the timing controller 40 The driving signal voltage value VGH voltage is greater than the power supply voltage value Vin, that is, when the high-level driving signal voltage value output by the timing controller 40 reaches the non-inverting input terminal, the first comparator U1 outputs a high-level trigger signal to the signal trigger.
  • the unit 32 outputs a low-level trigger signal to the signal trigger unit 32 when the low-level driving signal voltage value output by the timing controller 40 reaches the non-inverting input terminal.
  • the display panel 200 driving circuit further includes a first DC power source VDD;
  • the signal triggering unit 32 includes a trigger U2, and a clock signal input terminal C of the trigger U2 is The input terminal of the signal trigger unit 32, the signal output terminal Q of the trigger U2 is the output terminal of the signal trigger unit 32, and the signal input terminal D of the trigger U2 is connected to the first DC power source VDD. .
  • the flip-flop U2 may be selected as the D flip-flop U2.
  • the first DC power source VDD may be the power supply of the timing controller 40, that is, the first DC power source VDD voltage output by the power management integrated circuit.
  • a DC power supply VDD voltage is triggered by the D flip-flop U2
  • a high-level trigger signal is output to the N-MOS tube to trigger the N-MOS tube to be turned on.
  • the D flip-flop U2 operates based on the trigger signal output from the signal comparison unit 31.
  • the first comparator U1 outputs a high-level trigger signal to the clock signal input terminal C
  • the D flip-flop U2 triggers and outputs a high-level trigger.
  • the first comparator U1 outputs a low-level trigger signal to the clock signal input terminal C
  • the D flip-flop U2 does not operate.
  • the signal triggering unit 32 further includes a first resistor R1.
  • a first terminal of the first resistor R1 is connected to an output terminal of the signal comparison unit 31.
  • the first The second terminal of the resistor R1 is grounded.
  • the first resistor R1 is a pull-down resistor, and is used to output a low-level trigger signal to a clock signal input terminal of the D flip-flop U2, so that the D flip-flop U2 does not operate, thereby effectively ensuring that the N-MOS tube remains in an off state.
  • the communication signal output unit 33 includes a first electronic switch Q1 and a second resistor R2, and a controlled end of the first electronic switch Q1 is a receiver of the communication signal output unit 33.
  • the control terminal, the input terminal of the first electronic switch Q1 is the input terminal of the communication signal output unit 33, and the output terminal of the first electronic switch Q1 is the output terminal of the communication signal output unit 33;
  • a first terminal of the two resistors R2 is connected to a controlled terminal of the first electronic switch Q1, and a second terminal of the second resistor R2 is connected to an input terminal of the first electronic switch Q1.
  • the first electronic switch Q1 may be implemented by using a switching transistor such as a triode or a MOS transistor, and this embodiment may optionally be implemented by using an N-MOS transistor.
  • the second resistor R2 is a bias resistor and is used to ensure that the N-MOS tube is reliably turned on.
  • the timing controller 40 When the display device is powered on, the timing controller 40 outputs a low-level driving signal to the first comparator U1, the first comparator U1 outputs a low-level trigger signal, and the clock input terminal of the D flip-flop U2 is the clock falling No action is taken along the edges to keep the N-MOS tube in the off state.
  • the timing controller 40 is communicatively connected to the memory 10 to realize the initial setting of the timing controller 40.
  • the timing controller 40 After the initialization is completed and the display device enters a normal working state, the timing controller 40 outputs a high-level driving signal, thereby triggering the D flip-flop U233 to output the high-level control signal output from the first DC power source VDD to the N-MOS tube. In order to control the N-MOS tube to be turned on, the timing controller 40 is controlled to communicate with the external control chip through the connector 20 to realize data transmission and complete the image display of the display panel.
  • the display panel driving circuit further includes a unidirectional conduction element (not shown), and an input terminal of the unidirectional conduction element is connected to the memory 10. An output terminal of the unidirectional conducting element is connected to the timing controller 40.
  • the data in the memory 10 cannot be modified during the normal operation of the display device. Once the data is modified, the setting data is wrong, which will cause the display device to display abnormally. Therefore, most of the memory 10 is provided with a write protection pin (WP pin), and when the high level is input, the memory 10 can be controlled to write data, while at the low level, data cannot be written, and the memory 10 is write protected.
  • WP pin write protection pin
  • the parasitic capacitance and impedance existing on the timing control board and the external serial communication bus may easily cause a clutter on the serial communication bus to the write protection pin, and a high level may appear, thereby causing the memory 10 to enter the write protection. State, at this time, if the communication switch circuit 30 is turned on after receiving the control signal output from the timing controller 40, the control signal will enter the memory 10, causing the data in the memory 10 to be rewritten.
  • the unidirectional conduction element may be implemented by using a unidirectional diode with isolation characteristics such as a photocoupler and a diode.
  • a diode may be optionally implemented.
  • the unidirectional conduction element is used to prevent the data of the external control chip from entering the memory 10 when the timing controller 40 reads the data of the external control chip, and the data of the memory 10 is rewritten.
  • the present application also proposes a display device including a display panel and the display panel driving circuit as described above.
  • the gate driving circuit 100 and the source driving circuit 500 of the display panel driving circuit are electrically connected to the display panel, respectively.
  • the display panel may be a liquid crystal display (Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED), etc. to configure the display panel.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the present application also provides a display device including a display panel and the display panel driving circuit as described above.
  • the gate driving circuit 100 and the source driving circuit 500 of the display panel are electrically connected to the display panel, respectively.
  • the display panel driving circuit is used in the display device of the present application, embodiments of the display device of the present application include All the technical solutions of all the embodiments of the display panel driving circuit described above, and the technical effects achieved are also completely the same, and will not be repeated here.
  • the display device may be a display device with a display panel, such as a television, a tablet computer, or a mobile phone.

Abstract

一种显示面板驱动电路及显示装置，电路包括：存储器（10）；通讯开关电路（30）；时序控制器（40），包括数据传输端及控制端，数据传输端与通讯开关电路（30）的通讯信号输出端及存储器（10）的数据输出端连接，控制端与通讯开关电路（30）的驱动信号输入端连接，参考电压输入端经连接器与驱动电源连接；其中，时序控制器（40），被配置为在通讯开关电路（30）开启时，接收串行通讯总线接入的通讯信号，在通讯开关电路（30）关闭时，读取存储器（10）的软体数据。

Description

显示面板驱动电路及显示装置
相关专利
本申请要求2018年09月30日，申请号为201821620918.6，申请名称为“显示面板驱动电路及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示驱动技术领域，特别涉及一种显示面板驱动电路及显示装置。
背景技术
显示装置中，时序控制器TCON IC内部静态只读存储器SROM里的数据一般在掉电之后不能保存，而EEPROM(Electrically Erasable Programmable read only memory，可擦除存储器）或闪存器Flash里存储的数据即使掉电之后也能保存，所以会将时序控制器的控制程序储存在外部存储器EEPROM或Flash中。上电之后，时序控制器会进行初始化，通过总线从内部存储器中读取时序控制数据，随后再通过总线与外部控制芯片连接。
由于存储器和时序控制器均是通过通讯总线与时序控制器连接的，因此，在通过总线从外部存储器中读取时序控制数据时，控制芯片的控制信号可能会干扰时序控制器与存储器之间的数据读取，导致数据读取失败。
申请内容
本申请的主要目的是提出一种显示面板驱动电路及显示装置，旨在解决时序控制器软件读取错误的问题，提高了显示装置的可靠性。
为实现上述目的，本申请提出一种显示面板驱动电路，所述显示面板驱动电路包括：
存储器；
连接器，被配置为接入串行通讯总线及驱动电源；
通讯开关电路，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器与所述串行通讯总线通讯连接；
时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器与所述驱动电源连接；其中，
所述时序控制器，被配置为输出驱动信号至通讯开关电路的驱动信号输入端；
所述通讯开关电路，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
所述时序控制器，还被配置为在所述通讯开关电路开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器的软体数据。
可选地，所述通讯开关电路包括信号比较单元、信号触发单元及通讯信号输出单元，所述信号比较单元的第一输入端为所述参考电压输入端，所述信号比较单元的第二输入端为驱动信号输入端，所述信号比较单元的输出端与所述信号触发单元的输入端连接，所述信号触发单元的输出端与所述通讯信号输出单元的受控端连接，所述通讯信号输出单元的输入端与所述连接器连接，所述通讯信号输出单元的输出端为所述通讯开关电路的通讯信号输出端。
可选地，所述信号比较单元包括第一比较器，所述第一比较器的正相输入端为所述信号比较单元的第二输入端，所述第一比较器的反相输入端为所述信号比较单元的第一输出端，所述第一比较器的输出端为所述信号比较单元的输出端。
可选地，所述显示面板驱动电路还包括第一直流电源；所述信号触发单元包括触发器，所述触发器的时钟信号输入端为所述信号触发单元的输入端，所述触发器的信号输出端为所述信号触发单元的输出端，所述触发器的信号输入端与所述第一直流电源连接。
可选地，所述信号触发单元包括还包括第一电阻，所述第一电阻的第一端与所述信号比较单元的输出端连接，所述第一电阻的第二端接地。
可选地，所述通讯信号输出单元包括第一电子开关、第二电阻，所述第一电子开关的受控端为所述通讯信号输出单元的受控端，所述第一电子开关的输入端为所述通讯信号输出单元的输入端，所述第一电子开关的输出端为所述通讯信号输出单元的输出端；所述第二电阻的第一端与所述第一电子开关的受控端连接，所述第二电阻的第二端与所述第一电子开关的输入端连接。
可选地，所述显示面板驱动电路还包括单向导通元件，所述单向导通元件的输入端与所述存储器连接，所述单向导通元件的输出端与所述时序控制器连接。
可选地，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
本申请还提出一种显示装置，包括显示面板及如上所述的显示面板驱动电路，所述显示面板驱动电路包括：
存储器；
连接器，被配置为接入串行通讯总线及驱动电源；
通讯开关电路，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器与所述串行通讯总线通讯连接；
时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器与所述驱动电源连接；其中，
所述时序控制器，被配置为输出驱动信号至通讯开关电路的驱动信号输入端；
所述通讯开关电路，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
所述时序控制器，还被配置为在所述通讯开关电路开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器的软体数据；
所述显示面板驱动电路的栅极驱动电路和源极驱动电路分别与所述显示面板电连接。
可选地，所述显示装置还包括电源管理电路，所述电源管理电路的输入端经所述显示面板驱动电路的连接器接入驱动电源，所述电源管理电路的输出端分别与所述栅极驱动电路、所述源极驱动电路和所述显示面板驱动电路时序控制器连接。
可选地，所述通讯开关电路包括信号比较单元、信号触发单元及通讯信号输出单元，所述信号比较单元的第一输入端为所述参考电压输入端，所述信号比较单元的第二输入端为驱动信号输入端，所述信号比较单元的输出端与所述信号触发单元的输入端连接，所述信号触发单元的输出端与所述通讯信号输出单元的受控端连接，所述通讯信号输出单元的输入端与所述连接器连接，所述通讯信号输出单元的输出端为所述通讯开关电路的通讯信号输出端。
可选地，所述信号比较单元包括第一比较器，所述第一比较器的正相输入端为所述信号比较单元的第二输入端，所述第一比较器的反相输入端为所述信号比较单元的第一输出端，所述第一比较器的输出端为所述信号比较单元的输出端。
可选地，所述显示装置还包括第一直流电源；所述信号触发单元包括触发器，所述触发器的时钟信号输入端为所述信号触发单元的输入端，所述触发器的信号输出端为所述信号触发单元的输出端，所述触发器的信号输入端与所述第一直流电源连接。
可选地，所述信号触发单元包括还包括第一电阻，所述第一电阻的第一端与所述信号比较单元的输出端连接，所述第一电阻的第二端接地。
可选地，所述通讯信号输出单元包括第一电子开关、第二电阻，所述第一电子开关的受控端为所述通讯信号输出单元的受控端，所述第一电子开关的输入端为所述通讯信号输出单元的输入端，所述第一电子开关的输出端为所述通讯信号输出单元的输出端；所述第二电阻的第一端与所述第一电子开关的受控端连接，所述第二电阻的第二端与所述第一电子开关的输入端连接。
可选地，所述显示装置还包括单向导通元件，所述单向导通元件的输入端与所述存储器连接，所述单向导通元件的输出端与所述时序控制器连接。
可选地，所述显示面板驱动电路还包括栅极驱动电路及
源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
可选地，所述显示面板为液晶显示器或者有机发光二极管显示器。
本申请通过设置时序控制器及存储器，并通过串行通讯总线进行通讯连接，以及将通讯开关电路串联设置于用于连接外部控制芯片的连接器与时序控制器之间，通讯开关电路基于时序控制电路的驱动信号控制，并在时序控制器输出低电平的驱动信号而控制通讯开关电路关闭时，实现时序控制器与存储器通讯连接，以使时序控制器读取存储器的软体数据，进而完成时序控制器的初始设置。而在时序控制器输出高电平的驱动信号控制通讯开关电路开启时，实现时序控制器与外部控制芯片通讯连接，从而接收外部控制芯片输出的控制信号，并转换为对应的驱动信号后输出，完成显示面板的图像显示。本申请解决了在时序控制器读取存储器的数据时，存储器的数据可能窜入至外部控制芯片，而导致外部控制芯片的工作紊乱，或者外部控制芯片的数据信号输出至时序控制器或者存储器，而导致时序控制器读取存储器数据失败的问题。本申请有效的解决了时序控制器软件读取错误的问题，提高了显示装置的可靠性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板驱动电路一实施例的功能模块示意图；
图2为本申请显示面板驱动电路一实施例的电路结构示意图；
图3为本申请显示装置一实施例的电路结构示意图。
附图标号说明：
标号 名称 标号 名称
10 存储器 R1 第一电阻
20 连接器 R2 第二电阻
30 通讯开关电路 Q1 第一电子开关
40 时序控制器 VDD 第一直流电源
31 信号比较单元 C 时钟信号输入端
32 信号触发单元 D 数据输入端
33 通讯信号输出单元 Q 数据输出端
U1 第一比较器 U2 D触发器
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种显示面板驱动电路。
参照图1至图3，在本申请一实施例中，该显示面板驱动电路包括：
存储器10；
连接器20，被配置为接入串行通讯总线及驱动电源；
通讯开关电路30，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器20与所述串行通讯总线通讯连接；
时序控制器40，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器10的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器20与所述驱动电源连接；其中，
所述时序控制器40，被配置为输出驱动信号至通讯开关电路30的驱动信号输入端；
所述通讯开关电路30，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
所述时序控制器40，还被配置为在所述通讯开关电路30开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器10的软体数据。
本实施例中，所述显示面板驱动电路还包括栅极驱动电路100、源极驱动电路500及电源管理集成电路400，所述栅极驱动电路100和所述源极驱动电路500的受控端分别与所述时序控制器40的输出端连接，电源管理集成电路的输入端经连接器20与驱动电源连接，输出端与时序控制器40、栅极驱动电路100和所述源极驱动电路500连接。
存储器10和时序控制器40均可以设置于时序控制（Timing Controller，TCON）PCB板上，时序控制（Timing Controller，TCON）PCB板上还设置有电源管理集成电路，电源管理集成电路通过连接器20与显示装置中的驱动电源，以将驱动电源进行转换，从而为时序控制器40、栅极驱动电路100、源极驱动电路500提供工作电压。存储器10可以存储用于驱动栅极驱动电路100和源极驱动电路500工作的控制信号，并通过串行通讯总线与时序控制器40通讯连接，在显示装置上电工作时，时序控制器40读取存储器10里的控制信号，及其他设定数据进行初始设置，以产生对应的时序控制信号，从而驱动显示装置中的源极驱动电路500及栅极驱动电路100工作。存储器10的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。因此，存储器10大多设置写保护引脚（WP pin），并在输入高电平时，可以控制存储器10写入数据，而在低电平时，不能写入数据，此时存储器10仅供时序控制器40读取数据。时序控制板上还设置有电源管理集成电路，电源管理集成电路的输出端分别与存储器10及时序控制器40连接。上述实施例中，串行通讯总线可以采用（I2Cnter-Integrated Circuit）通讯总线，当然也可以采用其他的通讯线路来实现，此处不做限制。
该连接器20通过通讯总线可以连接显示装置的主控制器或者视频处理芯片等控制芯片连接，当外部控制芯片的数量设置为多个时每一外部控制芯片均通过串行通讯总线与时序控制器40连接。在显示装置工作时，时序控制器40可以经串行通讯总线接收R/G/B压缩信号、控制信号。驱动电源则通过电源线连接电源管理集成电路。电源管理集成电路将接收到的电源转换成对应的驱动电源后输出至时序控制板上的电路模块。在显示装置正常工作后，时序控制器40将接收到的R/G/B压缩信号、控制信号转换成适于显示装置中的源极驱动电路500和栅极驱动电路100的数据信号、控制信号及时钟信号，实现显示面板200的图像显示。
需要说明的是，外部控制芯片、时序控制器40及存储器10之间均通过串行通讯总线进行通讯连接，并且时序控制器40需要读取存储器10及外部控制芯片的数据来实现显示面板200的驱动。因此，在时序控制器40读取数据的过程中，可能对其他芯片产生影响，例如在时序控制器40读取存储器10的数据时，存储器10的数据可能通过通讯总线窜入至外部控制芯片，而导致外部控制芯片的工作紊乱，或者在时序控制器40读取存储器10的数据时，外部控制芯片的数据信号输出至时序控制器40或者存储器10，而导致时序控制器40读取存储器10数据失败。
为了解决上述问题，本实施例显示面板驱动电路可以设置通讯开关电路30来实现通讯电路的切换。具体地，通讯开关电路30的参考电压输入端和驱动信号输入端分别与驱动电源和时序控制器40的控制端连接，并接收时序控制器40输出的控制信号而开启/关闭。在显示装置上电时，时序控制器40输出低电平的驱动信号至驱动信号输入端，此时驱动信号的电压值小于驱动电源电压值，通讯开关电路30处于关闭状态。时序控制器40通过串行通讯总线与存储器10通讯连接，以读取所述存储器10的软体数据，实现对时序控制器40的初始设置。在这个过程中，通讯开关电路30处于关闭状态，因此外部控制芯片的数据不会经串行通讯总线输出至存储器10或者时序控制器40，而对时序控制器40读取存储器10数据产生干扰，同时，存储器10的数据也不会窜入至外部控制芯片，而导致外部控制芯片的功能紊乱。在初始化结束，显示装置进入正常工作状态时，时序控制器40输出高电平的驱动信号至驱动信号输入端，从而驱动通讯开关电路30开启，此时时序控制器40通过串行通讯总线与外部控制芯片通讯连接，从而接收外部控制芯片输出的控制信号、数据信号及时钟信号，并转换为对应的驱动信号后输出，完成显示面板200的图像显示。
本申请通过设置时序控制器40及存储器10，并通过串行通讯总线进行通讯连接，以及将通讯开关电路30串联设置于用于连接外部控制芯片的连接器20与时序控制器40之间，通讯开关电路30基于时序控制电路的驱动信号控制，并在时序控制器40输出低电平的驱动信号而控制通讯开关电路30关闭时，实现时序控制器40与存储器10通讯连接，以使时序控制器40读取存储器10的软体数据，进而完成时序控制器40的初始设置。而在时序控制器40输出高电平的驱动信号控制通讯开关电路30开启时，实现时序控制器40与外部控制芯片通讯连接，从而接收外部控制芯片输出的控制信号，并转换为对应的驱动信号后输出，完成显示面板200的图像显示。本申请解决了在时序控制器40读取存储器10的数据时，存储器10的数据可能窜入至外部控制芯片，而导致外部控制芯片的工作紊乱，或者外部控制芯片的数据信号输出至时序控制器40或者存储器10，而导致时序控制器40读取存储器10数据失败的问题。本申请有效的解决了时序控制器40软件读取错误的问题，提高了显示装置的可靠性。
参照图1至图3，在一可选实施例中，所述通讯开关电路30包括信号比较单元31、信号触发单元32及通讯信号输出单元33，所述信号比较单元31的第一输入端为所述参考电压输入端，所述信号比较单元31的第二输入端为驱动信号输入端，所述信号比较单元31的输出端与所述信号触发单元32的输入端连接，所述信号触发单元32的输出端与所述通讯信号输出单元33的受控端连接，所述通讯信号输出单元33的输入端与所述连接器20连接，所述通讯信号输出单元33的输出端为所述通讯开关电路30的通讯信号输出端。
本实施例中，信号比较单元31的第一输入端和第二输入端分别与时序控制器40的控制端和驱动电源连接，并接收时序控制器40输出的控制信号而开启/关闭，在时序控制器40输出低电平的驱动信号至第二输入端时，此时第二输入端的电压信号值小于第一输入端的电源电压值，从而输出低电平的触发信号。在时序控制器40输出高电平的驱动信号至第二输入端时，此时第二输入端的电压信号值大于第一输入端的电源电压值，从而输出高电平的触发信号。信号触发单元32在信号比较单元31输出高电平的触发信号时动作，从而控制通讯信号输出单元33开启，以实现时序控制器40通过连接器20及通讯总线与外部控制芯片通讯连接。在信号比较单元31输出低电平的触发信号时不动作，从而控制通讯信号输出单元33关闭，以使时序控制器40断开与外部控制芯片通讯连接。
参照图1至图3，进一步地，所述信号比较单元31包括第一比较器U1，所述第一比较器U1的正相输入端为所述信号比较单元31的第二输入端，所述第一比较器U1的反相输入端为所述信号比较单元31的第一输出端，所述第一比较器U1的输出端为所述信号比较单元31的输出端。
本实施例中，第一比较器U1的正相输入端与时序控制器40连接，反相输入端经连接器20与外部驱动电源连接，可以理解的是，时序控制器40输出的高电平驱动信号电压值VGH电压大于电源电压值Vin，也即在时序控制器40输出的高电平驱动信号电压值至正相输入端时，第一比较器U1输出高电平的触发信号至信号触发单元32，在时序控制器40输出的低电平驱动信号电压值至正相输入端时，第一比较器U1输出低电平的触发信号至信号触发单元32。
参照图1至图3，进一步地，所述显示面板200驱动电路还包括第一直流电源VDD；所述信号触发单元32包括触发器U2，所述触发器U2的时钟信号输入端C为所述信号触发单元32的输入端，所述触发器U2的信号输出端Q为所述信号触发单元32的输出端，所述触发器U2的信号输入端D与所述第一直流电源VDD连接。
本实施例中，触发器U2可选为D触发器U2，第一直流电源VDD可以是时序控制器40的供电电源，也即由电源管理集成电路输出的第一直流电源VDD电压，第一直流电源VDD电压在D触发器U2触发时，输出高电平的触发信号至N-MOS管，以触发N-MOS管导通。D触发器U2基于信号比较单元31输出的触发信号动作，并在第一比较器U1输出高电平的触发信号至时钟信号输入端C时，D触发器U2触发时，输出高电平的触发信号至N-MOS管，而在第一比较器U1输出低电平的触发信号至时钟信号输入端C时，D触发器U2不动作。
参照图1至图3，进一步地，所述信号触发单元32包括还包括第一电阻R1，所述第一电阻R1的第一端与所述信号比较单元31的输出端连接，所述第一电阻R1的第二端接地。
第一电阻R1为下拉电阻，用于输出低电平的触发信号至D触发器U2的时钟信号输入端，以使D触发器U2不动作，从而有效保证N-MOS管保持截止状态。
参照图1至图3，进一步地，所述通讯信号输出单元33包括第一电子开关Q1、第二电阻R2，所述第一电子开关Q1的受控端为所述通讯信号输出单元33的受控端，所述第一电子开关Q1的输入端为所述通讯信号输出单元33的输入端，所述第一电子开关Q1的输出端为所述通讯信号输出单元33的输出端；所述第二电阻R2的第一端与所述第一电子开关Q1的受控端连接，所述第二电阻R2的第二端与所述第一电子开关Q1的输入端连接。
本实施例中，第一电子开关Q1可以采用三极管、MOS管等开关管来实现，本实施例可选采用N-MOS管来实现。第二电阻R2为偏置电阻，用于保证N-MOS管可靠导通。在显示装置上电时，时序控制器40输出低电平的驱动信号至第一比较器U1，第一比较器U1则输出低电平的触发信号，D触发器U2的时钟输入端为时钟下降沿而不动作，从而使N-MOS管保持截止状态，此时时序控制器40与存储器10通讯连接，实现对时序控制器40的初始设置。在初始化结束，显示装置进入正常工作状态时，时序控制器40输出高电平的驱动信号，从而触发D触发器U233将第一直流电源VDD输出的高电平控制信号输出至N-MOS管，以控制N-MOS管导通，从而控制时序控制器40通过连接器20与外部控制芯片通讯连接，实现数据传输，完成显示面板的图像显示。
参照图1至图3，在一可选实施例中，所述显示面板驱动电路还包括单向导通元件（图未示出），所述单向导通元件的输入端与所述存储器10连接，所述单向导通元件的输出端与所述时序控制器40连接。
需要说明的是，存储器10的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。因此，存储器10大多设置写保护引脚（WP pin），并在输入高电平时，可以控制存储器10写入数据，而在低电平时，不能写入数据，而对存储器10进行写保护。而在时序控制板与外部的串行通讯总线上存在的寄生电容及阻抗，这样容易导致串行通讯总线上产生杂波串到写保护脚，而出现高电平，从而使存储器10进入写保护状态，此时，若通讯开关电路30接收时序控制器40输出的控制信号而开启，该控制信号将进入至存储器10，导致存储器10的数据被改写。
为了解决上述问题，单向导通元件可以采用光耦、二极管等具有隔离特性的单向二极管来实现，本实施例可选采用二极管实现。单向导通元件用于防止时序控制器40读取外部控制芯片的数据时，外部控制芯片的数据窜入至存储器10，而导致存储器10的数据被改写。
本申请还提出一种显示装置，包括显示面板及如上所述的显示面板驱动电路，所述显示面板驱动电路的栅极驱动电路100和源极驱动电路500分别与所述显示面板电连接。
本实施例中，显示面板可以是可以采用液晶显示器（Liquid Crystal Display，LCD）、有机发光二极管显示器（Organic Light-Emitting Diode, OLED）等形式来配置显示面板。
本申请还提出一种显示装置，包括显示面板及如上所述的显示面板驱动电路，所述显示面板的栅极驱动电路100和所述源极驱动电路500分别与所述显示面板电连接。该显示面板驱动电路的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请显示装置中使用了上述显示面板驱动电路，因此，本申请显示装置的实施例包括上述显示面板驱动电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
本实施例中，显示装置可以是电视机、平板电脑、手机等具有显示面板的显示装置。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板驱动电路，其中，所述显示面板驱动电路包括：
    存储器；
    连接器，被配置为接入串行通讯总线及驱动电源；
    通讯开关电路，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器与所述串行通讯总线通讯连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器与所述驱动电源连接；其中，
    所述时序控制器，被配置为输出驱动信号至通讯开关电路的驱动信号输入端；
    所述通讯开关电路，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
    所述时序控制器，还被配置为在所述通讯开关电路开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器的软体数据。
  2. 如权利要求1所述的显示面板驱动电路，其中，所述通讯开关电路包括信号比较单元、信号触发单元及通讯信号输出单元，所述信号比较单元的第一输入端为所述参考电压输入端，所述信号比较单元的第二输入端为驱动信号输入端，所述信号比较单元的输出端与所述信号触发单元的输入端连接，所述信号触发单元的输出端与所述通讯信号输出单元的受控端连接，所述通讯信号输出单元的输入端与所述连接器连接，所述通讯信号输出单元的输出端为所述通讯开关电路的通讯信号输出端。
  3. 如权利要求2所述的显示面板驱动电路，其中，所述信号比较单元包括第一比较器，所述第一比较器的正相输入端为所述信号比较单元的第二输入端，所述第一比较器的反相输入端为所述信号比较单元的第一输出端，所述第一比较器的输出端为所述信号比较单元的输出端。
  4. 如权利要求2所述的显示面板驱动电路，其中，所述显示面板驱动电路还包括第一直流电源；所述信号触发单元包括触发器，所述触发器的时钟信号输入端为所述信号触发单元的输入端，所述触发器的信号输出端为所述信号触发单元的输出端，所述触发器的信号输入端与所述第一直流电源连接。
  5. 如权利要求2所述的显示面板驱动电路，其中，所述信号触发单元包括还包括第一电阻，所述第一电阻的第一端与所述信号比较单元的输出端连接，所述第一电阻的第二端接地。
  6. 如权利要求2所述的显示面板驱动电路，其中，所述通讯信号输出单元包括第一电子开关、第二电阻，所述第一电子开关的受控端为所述通讯信号输出单元的受控端，所述第一电子开关的输入端为所述通讯信号输出单元的输入端，所述第一电子开关的输出端为所述通讯信号输出单元的输出端；所述第二电阻的第一端与所述第一电子开关的受控端连接，所述第二电阻的第二端与所述第一电子开关的输入端连接。
  7. 如权利要求1所述的显示面板驱动电路，其中，所述显示面板驱动电路还包括单向导通元件，所述单向导通元件的输入端与所述存储器连接，所述单向导通元件的输出端与所述时序控制器连接。
  8. 如权利要求7所述的显示面板驱动电路，其中，所述单向导通元件为光耦或者二极管。
  9. 如权利要求1所述的显示面板驱动电路，其中，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
  10. 一种显示面板驱动电路，其中，所述显示面板驱动电路包括：
    存储器；
    连接器，被配置为接入串行通讯总线及驱动电源；
    通讯开关电路，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器与所述串行通讯总线通讯连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器与所述驱动电源连接；其中，
    所述时序控制器，被配置为输出驱动信号至通讯开关电路的驱动信号输入端；
    所述通讯开关电路，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
    所述时序控制器，还被配置为在所述通讯开关电路开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器的软体数据。
  11. 一种显示装置，其中，包括显示面板及显示面板驱动电路，
    所述显示面板驱动电路包括：
    存储器，所述存储器设置写保护引脚，所述存储器在所述写保护脚输入高电平时，写入数据，在低电平时，存储器供时序控制器读取数据；
    连接器，被配置为接入串行通讯总线及驱动电源；
    通讯开关电路，包括参考电压输入端、驱动信号输入端、通讯信号输入端及通讯信号输出端，所述通讯信号输入端经所述连接器与所述串行通讯总线通讯连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯控制电路的通讯信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯开关电路的驱动信号输入端连接，所述参考电压输入端经所述连接器与所述驱动电源连接；其中，
    所述时序控制器，被配置为输出驱动信号至通讯开关电路的驱动信号输入端；
    所述通讯开关电路，被配置为根据驱动信号与所述参考电压输入端输入的信号开启或关闭；
    所述时序控制器，还被配置为在所述通讯开关电路开启时，接收所述串行通讯总线接入的通讯信号，在所述通讯开关电路关闭时，读取所述存储器的软体数据；
    所述显示面板驱动电路的栅极驱动电路和源极驱动电路分别与所述显示面板电连接。
  12. 如权利要求11所述的显示装置，其中，所述显示装置还包括电源管理电路，所述电源管理电路的输入端经所述显示面板驱动电路的连接器接入驱动电源，所述电源管理电路的输出端分别与所述栅极驱动电路、所述源极驱动电路和所述显示面板驱动电路时序控制器连接。
  13. 如权利要求11所述的显示装置，其中，所述通讯开关电路包括信号比较单元、信号触发单元及通讯信号输出单元，所述信号比较单元的第一输入端为所述参考电压输入端，所述信号比较单元的第二输入端为驱动信号输入端，所述信号比较单元的输出端与所述信号触发单元的输入端连接，所述信号触发单元的输出端与所述通讯信号输出单元的受控端连接，所述通讯信号输出单元的输入端与所述连接器连接，所述通讯信号输出单元的输出端为所述通讯开关电路的通讯信号输出端。
  14. 如权利要求13所述的显示装置，其中，所述信号比较单元包括第一比较器，所述第一比较器的正相输入端为所述信号比较单元的第二输入端，所述第一比较器的反相输入端为所述信号比较单元的第一输出端，所述第一比较器的输出端为所述信号比较单元的输出端。
  15. 如权利要求13所述的显示装置，其中，所述显示装置还包括第一直流电源；所述信号触发单元包括触发器，所述触发器的时钟信号输入端为所述信号触发单元的输入端，所述触发器的信号输出端为所述信号触发单元的输出端，所述触发器的信号输入端与所述第一直流电源连接。
  16. 如权利要求13所述的显示装置，其中，所述信号触发单元包括还包括第一电阻，所述第一电阻的第一端与所述信号比较单元的输出端连接，所述第一电阻的第二端接地。
  17. 如权利要求13所述的显示装置，其中，所述通讯信号输出单元包括第一电子开关、第二电阻，所述第一电子开关的受控端为所述通讯信号输出单元的受控端，所述第一电子开关的输入端为所述通讯信号输出单元的输入端，所述第一电子开关的输出端为所述通讯信号输出单元的输出端；所述第二电阻的第一端与所述第一电子开关的受控端连接，所述第二电阻的第二端与所述第一电子开关的输入端连接。
  18. 如权利要求11所述的显示装置，其中，所述显示装置还包括单向导通元件，所述单向导通元件的输入端与所述存储器连接，所述单向导通元件的输出端与所述时序控制器连接。
  19. 如权利要求11所述的显示装置，其中，所述显示面板驱动电路还包括栅极驱动电路及
    源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
  20. 如权利要求11所述的显示装置，其中，所述显示面板为液晶显示器或者有机发光二极管显示器。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114187858A (zh) * 2021-12-09 2022-03-15 京东方科技集团股份有限公司 显示设备及显示设备的检测方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109634892B (zh) * 2018-11-09 2022-05-17 惠科股份有限公司 显示装置的数据保护系统及保护方法
WO2020124703A1 (zh) * 2018-12-18 2020-06-25 惠科股份有限公司 一种驱动电路、驱动装置及显示装置
CN110910848A (zh) 2019-11-28 2020-03-24 Tcl华星光电技术有限公司 液晶显示器的驱动电路及驱动方法
CN111179800B (zh) * 2020-01-06 2022-09-09 Tcl华星光电技术有限公司 显示装置驱动系统及电子设备
CN111477154B (zh) * 2020-05-08 2022-09-09 Tcl华星光电技术有限公司 显示面板的通信架构与显示面板
CN111681585B (zh) * 2020-06-05 2023-10-13 Tcl华星光电技术有限公司 一种显示面板的驱动电路及显示装置
CN113763884A (zh) * 2021-09-18 2021-12-07 京东方科技集团股份有限公司 数据连接器、数据提供模组、方法和显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110066735A (ko) * 2009-12-11 2011-06-17 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN102237037A (zh) * 2010-05-07 2011-11-09 普诚科技股份有限公司 控制电泳显示集成电路的控制模块与方法
CN202134195U (zh) * 2011-07-20 2012-02-01 深圳创维－Rgb电子有限公司 一种液晶电视机及其edid存储与lvds转接装置
CN102968960A (zh) * 2011-08-30 2013-03-13 美格纳半导体有限公司 Led驱动器装置、lcd和驱动led背光单元的方法
CN203466798U (zh) * 2013-08-26 2014-03-05 上海斐讯数据通信技术有限公司 一种基于电子开关的串口切换装置
CN105427822A (zh) * 2015-12-29 2016-03-23 深圳市华星光电技术有限公司 灰阶补偿数据重置装置及方法
CN107144989A (zh) * 2017-06-06 2017-09-08 昆山龙腾光电有限公司 一种宽窄视角切换模块及液晶显示装置
CN107610664A (zh) * 2017-09-25 2018-01-19 惠科股份有限公司 一种电路板以及显示器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160128538A (ko) * 2015-04-28 2016-11-08 삼성디스플레이 주식회사 표시 장치
KR102531409B1 (ko) * 2018-07-31 2023-05-15 삼성디스플레이 주식회사 표시 장치

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110066735A (ko) * 2009-12-11 2011-06-17 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN102237037A (zh) * 2010-05-07 2011-11-09 普诚科技股份有限公司 控制电泳显示集成电路的控制模块与方法
CN202134195U (zh) * 2011-07-20 2012-02-01 深圳创维－Rgb电子有限公司 一种液晶电视机及其edid存储与lvds转接装置
CN102968960A (zh) * 2011-08-30 2013-03-13 美格纳半导体有限公司 Led驱动器装置、lcd和驱动led背光单元的方法
CN203466798U (zh) * 2013-08-26 2014-03-05 上海斐讯数据通信技术有限公司 一种基于电子开关的串口切换装置
CN105427822A (zh) * 2015-12-29 2016-03-23 深圳市华星光电技术有限公司 灰阶补偿数据重置装置及方法
CN107144989A (zh) * 2017-06-06 2017-09-08 昆山龙腾光电有限公司 一种宽窄视角切换模块及液晶显示装置
CN107610664A (zh) * 2017-09-25 2018-01-19 惠科股份有限公司 一种电路板以及显示器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114187858A (zh) * 2021-12-09 2022-03-15 京东方科技集团股份有限公司 显示设备及显示设备的检测方法
CN114187858B (zh) * 2021-12-09 2023-12-22 京东方科技集团股份有限公司 显示设备及显示设备的检测方法

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