WO2019206040A1 - 电源使能电路 - Google Patents

电源使能电路 Download PDF

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Publication number
WO2019206040A1
WO2019206040A1 PCT/CN2019/083447 CN2019083447W WO2019206040A1 WO 2019206040 A1 WO2019206040 A1 WO 2019206040A1 CN 2019083447 W CN2019083447 W CN 2019083447W WO 2019206040 A1 WO2019206040 A1 WO 2019206040A1
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WO
WIPO (PCT)
Prior art keywords
circuit
power
input
output
enable
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PCT/CN2019/083447
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English (en)
French (fr)
Inventor
韩璧丞
王天河
周承邦
黄柏维
梁茂星
Original Assignee
深圳市心流科技有限公司
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Application filed by 深圳市心流科技有限公司 filed Critical 深圳市心流科技有限公司
Publication of WO2019206040A1 publication Critical patent/WO2019206040A1/zh
Priority to US17/038,380 priority Critical patent/US11467640B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Definitions

  • the present application relates to the field of power supply technologies, and in particular, to a power supply enabling circuit.
  • power supply circuits have been widely used as devices for supplementing electrical energy in electronic devices in learning and living production.
  • the power supply circuit is usually turned off, for example, the input signal of the enable terminal (active high) of the power supply circuit is switched to a low level.
  • the electronic device Since the electronic device needs to activate the main system when accessing the external power source to enter the charging state, in order to display the charging effect or the communication requirement, etc., and the equivalent cannot be displayed by the battery or the power management module, and then the power supply circuit needs to be inserted when the external power source is inserted. Activation status. However, the existing power supply circuit cannot activate the main system of the electronic device when the external power source is connected.
  • the main purpose of the present application is to provide a power supply enabling circuit, which aims to solve the technical problem that the existing power supply circuit cannot activate the main system of the electronic device when accessing the external power source.
  • the present application provides a power supply enabling circuit, and the power supply enabling circuit includes:
  • a multi-input NAND gate wherein the input terminals of the multi-input NAND gate are respectively connected to the multi-channel activation signal source;
  • a delay circuit wherein an input end of the delay circuit is electrically connected to a shared active signal source of one of the plurality of activated signal sources;
  • the output of the delay circuit is logically coupled to the output of the multi-input NAND gate and is electrically coupled to the enable input of the power supply circuit.
  • the activation signal source is logic 0 active.
  • the activation signal source includes an off-system activation signal source
  • the power supply enable circuit further includes:
  • the non-gate input is electrically connected to an external activation signal source, and the output of the NOT gate is electrically connected to one input of the multi-input NAND gate.
  • system external activation signal source is logic 1 active.
  • the power enable circuit further includes: an AND gate, wherein an input end of the AND gate is electrically connected to an output end of the delay circuit and an output end of the multiple input NAND gate The output end of the AND gate is electrically connected to the enable input terminal;
  • the output of the delay circuit is electrically connected to the enable input of the power supply circuit after being connected to the output terminal of the multiple input NAND gate.
  • the multiple input NAND gate includes a three-input NAND gate.
  • the activation signal source includes an output end of the switch circuit and an external power supply output end of the battery management chip, and the input end of the three-input NAND gate and the output end of the switch circuit respectively The external power supply output end of the battery management chip and the output end of the non-gate are electrically connected.
  • the power enable circuit further includes:
  • first resistor one end of the first resistor is electrically connected to an output end of the NOT gate, and the other end is electrically connected to an output end of the power circuit.
  • the power enable circuit further includes:
  • a second resistor one end of the second resistor is electrically connected to the output end of the three-input NAND gate, and the other end is logically connected to the output end of the delay circuit, and is electrically connected to the enable input terminal.
  • the switch circuit is provided with a touch switch, and when the touch switch is pressed, the signal outputted by the switch circuit to the three-input NAND gate is logic 0. .
  • the power circuit when any one of the multiple activation signals is logic 0, the power circuit can be activated by the circuit, thereby activating the main system of the corresponding electronic device; and the activation signal connected to the delay circuit activates the signal.
  • the main system of the electronic device corresponding to the power circuit keeps the main system in an active state, thereby avoiding the problem that the main system of the electronic device cannot be activated when the external power source is inserted, thereby improving the use efficiency of the power circuit, and
  • the circuit controls the power circuit reset.
  • the signal connected to the NAND gate and the delay reset circuit is at the same time, and the rest include, but are not limited to, a power lock signal output by the single chip microcomputer, and an external power supply effective lock signal.
  • the system can provide flexible single-button power start and reset functions, simple structure and easy integration, and improve system power efficiency.
  • FIG. 1 is a schematic structural diagram of an embodiment of a power supply enabling circuit of the present application.
  • first”, “second”, and the like in this application are used for the purpose of description only, and are not to be construed as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
  • the application proposes a power supply enabling circuit.
  • FIG. 1 is a schematic structural diagram of an embodiment of a power supply enabling circuit of the present application.
  • the power enable circuit includes a multi-input NAND gate A and a delay circuit C.
  • the power enable circuit is applied to an electronic device having a power supply circuit.
  • the input terminals of the multi-input NAND gate A are respectively connected to the multi-channel activation signal source.
  • the input end of the delay circuit C is electrically connected to a shared active signal source in the multi-channel active signal source; that is, there is a shared active signal source in the multi-channel active signal source, and the shared active signal source is simultaneously connected to the input terminal of the delay circuit C and
  • the multi-input is electrically connected to one input of the non-gate.
  • the multi-channel activation signal source can be logic 0 valid.
  • the output of the delay circuit C is logically coupled to the output of the multi-input NAND gate A, and is electrically coupled to the enable input of the power supply circuit.
  • the power supply enabling circuit further comprises: an AND gate B, wherein the input end of the AND gate B is electrically connected to the output end of the delay circuit C and the output end of the multi-input NAND gate A, respectively, and the output end of the AND gate B
  • the enable input is electrically connected; or the output of the delay circuit C and the output terminal of the multi-input NAND gate A are electrically connected to the enable input of the power supply circuit.
  • the delay circuit C described above is a programmable reset chip.
  • the power enable circuit further includes a power module electrically coupled to the programmable reset chip, the power module configured to power the programmable reset chip such that the programmable reset chip is in a permanently powered state .
  • the programmable reset chip has a programmable delay time.
  • the programmable reset chip When the input signal of the shared active signal source is logic 0 or low level, if the duration of the logic 0 continuously exceeds the programming time (preset duration), the programmable reset chip
  • the output logic 0 is a low level '0' and is held for a period of time.
  • the programmable reset chip continuously outputs a logic 0, that is, a low level, for a preset period of time.
  • the programmable reset chip can continue to output logic continuously. 0 is low until the input signal of the shared active signal source switches to logic 1 or high level '1'.
  • the programmable reset chip is an open collector output.
  • the activation signal source includes an external system activation signal source
  • the power supply enable circuit further includes: a non-gate D, and the input end of the non-gate D is electrically connected to an external activation signal source, and the non-gate The output of D is electrically connected to one input of the multi-input NAND gate. That is, the output of the NOT gate D serves as a source of activation signals in the multi-channel activation signal source.
  • the external activation signal source of the system is logic 1 valid.
  • the multiple input NAND gate A includes a three-input NAND gate.
  • the activation signal source includes an output end of the switch circuit and an external power supply output end of the battery management chip, and the input end of the three-input NAND gate and the output end of the switch circuit, the external power supply output end of the battery management chip, and the non-gate The output of the door D is electrically connected.
  • the control output end of the single chip microcomputer is an output pin of the single chip microcomputer, and when the single chip microcomputer is in a power-on state, the output pin of the single chip outputs a high level.
  • the output pin of the single chip outputs a low level.
  • the output pin of the microcontroller outputs a low level.
  • the MCU is powered off, its output pin is not easy to be high.
  • Some MCUs directly pull the output pin to the high level.
  • the pin status is unstable.
  • a large current leakage that is, after the microcontroller is powered down, its output pin is generally low. Therefore, in this embodiment, a non-gate D is set between the output pin of the single chip and the three-input NAND gate, and then the This output pin controls the enable input of the power supply circuit.
  • the power circuit is provided with an interface electrically connected to an external power source.
  • the battery management chip is a chip that can switch the effective input power to its output. For example, when only the battery exists in the power circuit, the battery power is output; when there is an external power source in the power circuit, the power of the external power source is output, and of course, the battery can be charged at the same time, and the battery management chip is provided with an indication indicating that the external power source is valid.
  • the port is the external power indicator output. Wherein, when the interface is connected to the external power source, the external power source of the battery management chip instructs the output terminal to output a logic 0, that is, a low level '0'.
  • the switch circuit is provided with a light touch switch.
  • the signal output from the switch circuit to the three-input NAND gate is logic 0, that is, low level '0'.
  • the switch circuit can use a switch that can be locked, but the switch can be locked for a shorter service life.
  • the touch switch therefore, in this embodiment, the switch circuit uses a light touch switch.
  • the use of the light touch switch can provide additional input functions for the electronic device after the main system is successfully activated, so that the whole system can perform multiple functions with only one tact switch, without having to prepare an additional switch for the power supply.
  • the power supply enabling circuit further includes: a first resistor, one end of the first resistor is electrically connected to an output end of the NOT gate D, and the other end is electrically connected to an output end of the power circuit.
  • the power supply enabling circuit further includes: a second resistor, one end of the second resistor is electrically connected to the output end of the three-input NAND gate, and the other end is logically coupled with the output end of the delay circuit C, It is electrically connected to the enable input of the power circuit.
  • the power-enable circuit is protected by the second resistor, and when the electronic device is in normal operation, if the power-off (reset) function of the main system is implemented by the switch circuit, specifically, when the user presses the switch circuit After the touch switch is over a period of time, the output end of the switch circuit outputs a logic 0 to the delay circuit C, that is, a low level '0', and the delay circuit C forcibly outputs a logic 0, that is, a low level '0'.
  • the presence of the two resistors, whether the output of the three-input NAND gate is low or high, enables the power-enable circuit to operate normally, thereby protecting the power-enable circuit.
  • the output end of the single-chip microcomputer and the power supply circuit are electrically connected, and the power supply circuit supplies power to the single-chip microcomputer.
  • the control output terminal of the single-chip microcomputer outputs logic 0, that is, a low level.
  • the control output of the MCU outputs a logic 1 or a high level.
  • the activation signal source includes an output end of the switch circuit, an external power supply output end of the battery management chip, and a control output end of the single chip microcomputer, and can pass through an output end of the switch circuit and an external part of the battery management chip.
  • the power indication output terminal and the control output end of the single chip microcomputer jointly adjust the input signal of the enable input end of the power supply circuit, and only the output end of the switch circuit, the external power supply output end of the battery management chip, and the control output end of the single chip microcomputer are all logic 1
  • the high level '1', the input signal of the enable input is logic 0 or low level '0', in order to control the power supply circuit to prohibit power supply to the electronic device, thereby powering down the system.
  • the switch of the switch circuit In the normal operation of the electronic device, the switch of the switch circuit is not pressed, the output signal of the switch circuit is logic 1 or high level '1', and the battery management chip is connected to an external power source, that is, the battery management chip.
  • the output signal of the external power supply indication output is high level '1', and only the control output of the single-chip microcomputer outputs a low level '0'. Therefore, if the main system of the electronic device is activated, if it is desired to turn off the main system, Control the output of the microcontroller to output a high level '1', that is, only need to set the control output to a high level '1', the main system will be powered down and turned off.
  • the power-off (reset) function of the main system can be realized by the switch circuit. Specifically, when the user presses the touch switch of the switch circuit for more than a period of time, the output end of the switch circuit is delayed. The circuit C outputs a low level '0', and the delay circuit C forcibly outputs a low level '0', so that the enable input terminal of the power supply circuit can be set to a low level '0', and the power supply circuit stops working.
  • the switch circuit After the touch switch is bounced, the switch circuit outputs a low level '1' to the delay circuit C, and the delay circuit C forcibly outputs a low level '1', so that the power supply circuit continues to supply power to its corresponding electronic device, thereby reaching the main system. Power off (reset) function.
  • the power supply circuit can be powered by the output end of the switch circuit, the external power supply output end of the battery management chip, and the control output end of the single chip microcomputer to activate the power supply circuit, thereby activating the main system.
  • the power circuit when any one of the multiple activation signals is logic 0, the power circuit can be activated by the circuit, thereby activating the main system of the corresponding electronic device; and the activation signal connected to the delay circuit is activated.
  • the power system corresponds to the main system of the electronic device, and the main system is kept in an active state, thereby avoiding the problem that the main system of the electronic device cannot be activated when the external power source is inserted, thereby improving the use efficiency of the power circuit and passing the This circuit controls the power circuit reset.
  • the signal connected to the NAND gate and the delay reset circuit is at the same time, and the rest include, but are not limited to, a power lock signal output by the single chip microcomputer, and an external power supply effective lock signal.
  • the system can provide flexible single-button power start and reset functions, simple structure and easy integration, and improve system power efficiency.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
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Abstract

本申请公开一种电源使能电路，包括：多输入与非门，其输入端分别与多路激活信号相连接；延迟电路，其输入端连接到激活信号中的一路，其输出端与所述多输入与非门的输出端"线与"后连接到被控电源电路的使能输入端。本申请在多路激活信号中有任意一路为逻辑"0"时可以通过该电路激活电源电路，进而激活该对应的电子设备的主系统；而连接到延迟电路的那一路激活信号，又可以通过该电路控制电源电路复位。一般的，同时连接到与非门和延迟复位电路的为按键信号，其余的包括但不限于：单片机输出的电源锁定信号，外部电源有效锁定信号。该系统可以提供灵活的单按键电源启动和复位功能，结构简单便于集成，提高系统电源效率。

Description

电源使能电路
本申请要求于2018年4月23日提交中国专利局、申请号为201810365870.7、发明名称为“电源使能电路”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本申请涉及电源技术领域，特别涉及一种电源使能电路。
背景技术
目前，电源电路作为电子设备补充电能的装置已经广泛应用在学习及生活生产中。在电子设备的主系统关闭时，为尽量减少耗电电流，通常将电源电路关闭，例如，将电源电路的使能端（高电平有效）的输入信号切换为低电平。
由于电子设备在接入外部电源进入充电状态时需要激活主系统，以便于显示充电灯效或通信需求等，并且这个等效无法使用电池或电源管理模块显示，进而需要插入外部电源时保持电源电路的激活状态。但是，现有电源电路在在接入外部电源时无法激活电子设备的主系统。
上述内容仅用于辅助理解本申请的技术方案，并不代表承认上述内容是现有技术。
发明内容
本申请的主要目的是提供一种电源使能电路，旨在解决现有电源电路在在接入外部电源时无法激活电子设备的主系统的技术问题。
为实现上述目的，本申请提供一种电源使能电路，所述电源使能电路包括：
多输入与非门，所述多输入与非门的输入端分别连接多路激活信号源；
延迟电路，所述延迟电路的输入端与多路所述激活信号源中的一路共享激活信号源电连接；
所述延迟电路的输出端与所述多输入与非门的输出端进行逻辑与后，与电源电路的使能输入端电连接。
进一步地，在一实施方式中，所述激活信号源为逻辑0有效。
进一步地，在一实施方式中，所述激活信号源包括系统外激活信号源，所述电源使能电路还包括：
非门，所述非门的输入端与系统外激活信号源电连接，所述非门的输出端与多输入与非门的一路输入端电连接。
进一步地，在一实施方式中，所述系统外激活信号源为逻辑1有效。
进一步地，在一实施方式中，所述电源使能电路还包括：与门，所述与门的输入端分别与所述延迟电路的输出端与所述多输入与非门的输出端电连接，所述与门的输出端与所述使能输入端电连接；
或者，所述延迟电路的输出端与所述多输入与非门的输出端线与后，与电源电路的使能输入端电连接。
进一步地，在一实施方式中，所述多输入与非门包括三输入与非门。
进一步地，在一实施方式中，所述激活信号源包括开关电路的输出端及电池管理芯片的外部电源指示输出端，所述三输入与非门的输入端分别与所述开关电路的输出端、电池管理芯片的外部电源指示输出端、所述非门的输出端电连接。
进一步地，在一实施方式中，所述电源使能电路还包括：
第一电阻，所述第一电阻的一端与所述非门的输出端电连接，另一端与所述电源电路的输出端电连接。
进一步地，在一实施方式中，所述电源使能电路还包括：
第二电阻，所述第二电阻的一端与所述三输入与非门的输出端电连接，另一端与所述延迟电路的输出端进行逻辑与后，与所述使能输入端电连接。
进一步地，在一实施方式中，所述开关电路设有轻触式开关，在所述轻触式开关被按下时，所述开关电路输出至所述三输入与非门的信号为逻辑0。
本申请技术方案在多路激活信号中有任意一路为逻辑0时可以通过该电路激活电源电路，进而激活该对应的电子设备的主系统；而连接到延迟电路的那一路激活信号，进而激活该电源电路对应的电子设备的主系统，并将该主系统保持在激活状态，避免了在插入外部电源时无法激活电子设备的主系统的问题，进而提高了电源电路的使用效率，又可以通过该电路控制电源电路复位。一般的，同时连接到与非门和延迟复位电路的为按键信号，其余的包括但不限于：单片机输出的电源锁定信号，外部电源有效锁定信号。该系统可以提供灵活的单按键电源启动和复位功能，结构简单便于集成，提高系统电源效率。
附图说明
图1为本申请电源使能电路一实施例的结构示意图。
附图标号说明：
多输入与非门 A 与门 B
延迟电路 C 非门 D
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种电源使能电路。
参照图1，图1为本申请电源使能电路一实施例的结构示意图。
在本申请实施例中，该电源使能电路包括多输入与非门A以及延迟电路C。
该电源使能电路应用于设有电源电路的电子设备中。多输入与非门A的输入端分别连接多路激活信号源。
与开关电路、电池管理芯片的外部电源指示输出端、单片机的控制输出端电连接；
延迟电路C的输入端与多路激活信号源中的一路共享激活信号源电连接；即多路激活信号源中存在一路共享激活信号源，该共享激活信号源同时与延迟电路C的输入端及多输入与非门的一路输入端电连接。其中，该多路激活信号源均可为逻辑0有效。
延迟电路C的输出端与多输入与非门A的输出端进行逻辑与后，与电源电路的使能输入端电连接。优选地，电源使能电路还包括：与门B，与门B的输入端分别与延迟电路C的输出端与多输入与非门A的输出端电连接，与门B的输出端与所述使能输入端电连接；或者，延迟电路C的输出端与多输入与非门A的输出端线与后，与电源电路的使能输入端电连接。
上述延迟电路C为可编程复位芯片。在其他实施例中，电源使能电路还包括与可编程复位芯片电连接的电源模块，该电源模块用于为所述可编程复位芯片供电，以使得该可编程复位芯片处于永久上电的状态。
该可编程复位芯片可编程延时时间，当共享激活信号源的输入信号为逻辑0即低电平时，若该逻辑0的持续时长连续超过编程时间（预设时长），则该可编程复位芯片输出逻辑0即低电平‘0’并保持一段时间，例如，该可编程复位芯片在预设时长内持续输出逻辑0即低电平，优选地，该可编程复位芯片还可以一直持续输出逻辑0即低电平，直至共享激活信号源的输入信号切换为逻辑1即高电平‘1’。其中，该可编程复位芯片为集电极开路输出。
进一步地，在一实时方式中，激活信号源包括系统外激活信号源，该电源使能电路还包括：非门D，该非门D的输入端与系统外激活信号源电连接，该非门D的输出端与多输入与非门的一路输入端电连接。即该非门D的输出端作为多路激活信号源中的一路激活信号源。其中，该系统外激活信号源为逻辑1有效。
进一步地，在一实施例中，该多输入与非门A包括三输入与非门。
激活信号源包括开关电路的输出端及电池管理芯片的外部电源指示输出端，该三输入与非门的输入端分别与开关电路的输出端、电池管理芯片的外部电源指示输出端、所述非门D的输出端电连接。
其中，单片机的控制输出端为该单片机的输出引脚，在单片机处于上电状态时，单片机的输出引脚输出高电平。当然，在单片机处于掉电状态时，单片机的输出引脚输出低电平。在单片机掉电后，其输出引脚保持高电平不易，部分单片机直接将输出引脚使用电阻上拉到高电平，而电源引脚无电能输入时，引脚状态不稳定，有时甚至有很大电流泄漏，即单片机掉电后，其输出引脚一般为低电平，因此，本实施例中，在单片机的输出引脚与三输入与非门之间设置非门D，进而可通过该输出引脚控制电源电路的使能输入。
该电源电路设有与外部电源电连接的接口。电池管理芯片是一种可以切换有效输入电源到其输出的芯片。例：当电源电路中只有电池存在时，输出电池电能；当电源电路中存在外接电源时，输出外界电源的电能，当然还可以同时对电池进行充电，电池管理芯片设有指示外接电源有效的指示端口即外部电源指示输出端。其中，在接口连接外部电源时，电池管理芯片的外部电源指示输出端输出逻辑0即低电平‘0’。
开关电路设有轻触式开关，在轻触式开关被按下时，开关电路输出至三输入与非门的信号为逻辑0即低电平‘0’。一般情况下，在电子设备处于关机状态（电子设备的主系统关闭）时，需要一个额外的方式触发主系统工作，该开关电路可采用可以锁定的开关，但该可以锁定的开关的使用寿命不如轻触式开关，因此，本实施例中，该开关电路采用轻触式开关。同时，使用轻触式开关可以在主系统成功激活后，为电子设备提供额外的输入功能，使得全系统只需要一个轻触开关就可以完成多种功能，无需为电源额外准备一个开关。
优选地，该电源使能电路还包括：第一电阻，所述第一电阻的一端与所述非门D的输出端电连接，另一端与所述电源电路的输出端电连接。
进一步地，该电源使能电路还包括：第二电阻，所述第二电阻的一端与该三输入与非门的输出端电连接，另一端与该延迟电路C的输出端进行逻辑与后，与电源电路的使能输入端电连接。
本实施例中，通过该第二电阻保护该电源使能电路，在电子设备正常运行情况下，若通过开关电路实现主系统的断电（复位）功能，具体地，当用户按下开关电路的轻触式开关超过一段时间后，开关电路的输出端向延迟电路C输出逻辑0即低电平‘0’，延迟电路C强制将输出逻辑0即低电平‘0’，此时，因第二电阻的存在，无论三输入与非门的输出端输出低电平还是高电平，均能使该电源使能电路正常工作，进而起到保护该电源使能电路的作用。
需要说明的是，单片机与电源电路的输出端电连接，电源电路为单片机供电，在单片机处于上电状态时，单片机的控制输出端输出逻辑0即低电平。当然，在单片机处于掉电状态时，单片机的控制输出端输出逻辑1即高电平。
本实施例中的电源使能电路，可激活信号源包括开关电路的输出端、电池管理芯片的外部电源指示输出端、单片机的控制输出端，可通过开关电路的输出端、电池管理芯片的外部电源指示输出端、单片机的控制输出端共同调节电源电路的使能输入端的输入信号，仅在开关电路的输出端、电池管理芯片的外部电源指示输出端、单片机的控制输出端全部为逻辑1即高电平‘1’，该使能输入端的输入信号为逻辑0即低电平‘0’，才能控制电源电路禁止向电子设备供电，进而使系统掉电。
在电子设备正常运行情况下，该开关电路的开关未被按下，该开关电路的输出信号为逻辑1即高电平‘1’，该电池管理芯片为接入外部电源，即电池管理芯片的外部电源指示输出端的输出信号为高电平‘1’，仅有单片机的控制输出端输出低电平‘0’，因此，在电子设备的主系统激活后，若希望关闭该主系统，则可控制单片机的控制输出端输出高电平‘1’，即只需要将控制输出设置为高电平‘1’，该主系统便掉电而关闭。并且在电子设备正常运行情况下，可通过开关电路实现主系统的断电（复位）功能，具体地，当用户按下开关电路的轻触式开关超过一段时间后，开关电路的输出端向延迟电路C输出低电平‘0’，延迟电路C强制将输出低电平‘0’，进而使电源电路的使能输入端能置为低电平‘0’，电源电路停止工作，在该轻触式开关弹起后，开关电路向延迟电路C输出低电平‘1’，延迟电路C强制将输出低电平‘1’，使电源电路继续为其对应的电子设备供电，进而达到主系统断电（复位）功能。
在主系统掉电而关闭时，可通过开关电路的输出端、电池管理芯片的外部电源指示输出端、单片机的控制输出端调节电源电路使电源电路为其对应的电子设备供电，进而激活该主系统。
本申请技术方案，在多路激活信号中有任意一路为逻辑0时可以通过该电路激活电源电路，进而激活该对应的电子设备的主系统；而连接到延迟电路的那一路激活信号，进而激活该电源电路对应的电子设备的主系统，并将该主系统保持在激活状态，避免了在插入外部电源时无法激活电子设备的主系统的问题，进而提高了电源电路的使用效率，又可以通过该电路控制电源电路复位。一般的，同时连接到与非门和延迟复位电路的为按键信号，其余的包括但不限于：单片机输出的电源锁定信号，外部电源有效锁定信号。该系统可以提供灵活的单按键电源启动和复位功能，结构简单便于集成，提高系统电源效率。
应当说明的是，本申请的各个实施例的技术方案可以相互结合，但是必须是以本领域的技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当人认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种电源使能电路，其特征在于，所述电源使能电路包括：
    多输入与非门，所述多输入与非门的输入端分别连接多路激活信号源；
    延迟电路，所述延迟电路的输入端与多路所述激活信号源中的一路共享激活信号源电连接；
    所述延迟电路的输出端与所述多输入与非门的输出端进行逻辑与后，与电源电路的使能输入端电连接。
  2. 如权利要求1所述的电源使能电路，其特征在于，所述激活信号源为逻辑0有效。
  3. 如权利要求1所述的电源使能电路，其特征在于，所述激活信号源包括系统外激活信号源，所述电源使能电路还包括：
    非门，所述非门的输入端与系统外激活信号源电连接，所述非门的输出端与多输入与非门的一路输入端电连接。
  4. 如权利要求3所述的电源使能电路，其特征在于，所述系统外激活信号源为逻辑1有效。
  5. 如权利要求1所述的电源使能电路，其特征在于，所述电源使能电路还包括：与门，所述与门的输入端分别与所述延迟电路的输出端与所述多输入与非门的输出端电连接，所述与门的输出端与所述使能输入端电连接；
    或者，所述延迟电路的输出端与所述多输入与非门的输出端线与后，与电源电路的使能输入端电连接。
  6. 如权利要求3所述的电源使能电路，其特征在于，所述多输入与非门包括三输入与非门。
  7. 如权利要求6所述的电源使能电路，其特征在于，所述激活信号源包括开关电路的输出端及电池管理芯片的外部电源指示输出端，所述三输入与非门的输入端分别与所述开关电路的输出端、电池管理芯片的外部电源指示输出端、所述非门的输出端电连接。
  8. 如权利要求7所述的电源使能电路，其特征在于，所述电源使能电路还包括：
    第一电阻，所述第一电阻的一端与所述非门的输出端电连接，另一端与所述电源电路的输出端电连接。
  9. 如权利要求7所述的电源使能电路，其特征在于，所述电源使能电路还包括：
    第二电阻，所述第二电阻的一端与所述三输入与非门的输出端电连接，另一端与所述延迟电路的输出端进行逻辑与后，与所述使能输入端电连接。
  10. 如权利要求7所述的电源使能电路，其特征在于，所述开关电路设有轻触式开关，在所述轻触式开关被按下时，所述开关电路输出至所述三输入与非门的信号为逻辑0。
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