WO2018201684A1 - 电视机待机电源控制电路及电视机 - Google Patents

电视机待机电源控制电路及电视机 Download PDF

Info

Publication number
WO2018201684A1
WO2018201684A1 PCT/CN2017/110353 CN2017110353W WO2018201684A1 WO 2018201684 A1 WO2018201684 A1 WO 2018201684A1 CN 2017110353 W CN2017110353 W CN 2017110353W WO 2018201684 A1 WO2018201684 A1 WO 2018201684A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
resistor
circuit
standby
trigger circuit
Prior art date
Application number
PCT/CN2017/110353
Other languages
English (en)
French (fr)
Inventor
王安伟
毕军辉
Original Assignee
深圳Tcl数字技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳Tcl数字技术有限公司 filed Critical 深圳Tcl数字技术有限公司
Publication of WO2018201684A1 publication Critical patent/WO2018201684A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/63—Generation or supply of power specially adapted for television receivers

Definitions

  • the present application relates to the field of circuit control, and more particularly to a television standby power control circuit and a television.
  • the main purpose of the present application is to provide a television standby power control circuit and a television, aiming at solving the problem that the CPU needs to consume power when the television is in standby.
  • the present application provides a television standby power control circuit, including a CPU power supply, a standby trigger circuit, a bistable trigger circuit, and a switch circuit, and an input end of the switch circuit and an output of the CPU power supply. End connection, an output end of the switch circuit is connected to a power end of a CPU of the television; the standby trigger circuit is connected to a power control end of the CPU, and the standby trigger circuit is further connected to the bistable trigger circuit An input terminal is connected, and an output end of the bistable trigger circuit is connected to a controlled end of the switch circuit;
  • the standby trigger circuit is configured to control the bistable trigger circuit to trigger and output a first level signal when detecting a low level standby signal sent by the CPU;
  • the switch circuit is configured to turn off when the first level signal is received, and cut off an output of the CPU power supply.
  • the television standby power control circuit further includes a button power-on trigger circuit for triggering and outputting a high-level power-on signal of the television, the button power-on trigger circuit and the input end of the bistable trigger circuit connection;
  • the button power-on trigger circuit is configured to control a level of the first level signal output by the bistable trigger circuit when the high-level power-on signal of the television is triggered and output;
  • the switching circuit is further configured to be turned on when receiving the first level signal of level inversion, and controlling the CPU power supply output.
  • the television standby power control circuit further includes a current limiting resistor, and the button power-on trigger circuit is connected to the input end of the bistable trigger circuit through the current limiting resistor.
  • the bistable trigger circuit includes a first triode, a second triode, a first resistor, a second resistor, a third resistor, and a fourth resistor; and an emitter of the first triode Grounded, the collector of the first transistor is connected to the CPU power supply through the first resistor, and the base of the first transistor passes through the second resistor and the second transistor a collector connection; a base of the second transistor is connected to a collector of the first transistor through the third resistor, an emitter of the second transistor is grounded, the second a collector of the triode is further connected to the CPU power supply through the fourth resistor; a collector of the first triode is an output end of the bistable trigger circuit; and the second triode The base is the input of the bistable trigger circuit.
  • the first triode and the second triode are both NPN transistors.
  • the switch circuit includes a third transistor, a fifth resistor, a sixth resistor, and a MOS transistor; a base of the third transistor is connected to one end of the fifth resistor, and the fifth The other end of the resistor is a controlled end of the switch circuit; the emitter of the third transistor is grounded, and the collector of the third transistor is connected to the CPU power supply through the sixth resistor.
  • the collector of the third transistor is also connected to the gate of the MOS transistor; the source of the MOS transistor is connected to the CPU power supply, and the drain of the MOS transistor is the output of the switch circuit .
  • the MOS transistor is a PMOS transistor
  • the third triode is an NPN transistor
  • the standby trigger circuit includes a capacitor, a seventh resistor, an eighth resistor, a ninth resistor, and a fourth transistor; a first end of the capacitor is connected to an input end of the bistable trigger circuit, a second end of the capacitor is connected to an emitter of the fourth transistor through the seventh resistor; one end of the eighth resistor is connected to a common end of the capacitor and the seventh resistor, The other end of the eighth resistor is grounded; the base of the fourth transistor is connected to one end of the ninth resistor, and the other end of the ninth resistor is a detection input of the standby trigger circuit, the fourth three The collector of the pole tube is connected to the power control terminal of the CPU.
  • the fourth triode is a PNP triode.
  • the present application further provides a television set including a CPU and a television standby power supply control circuit, wherein the television standby power supply control circuit is a television standby device according to any one of the above-mentioned items.
  • a power control circuit the CPU has a power terminal and a standby signal output end, and an output end of the switch circuit of the standby power control circuit of the television is connected to a power end of the CPU, and the standby trigger of the standby power control circuit of the television The circuit is coupled to the standby signal output of the CPU.
  • the standby trigger circuit detects the low-level standby signal, and controls the bistable trigger circuit to trigger and output the first A level signal, the switch circuit cutting off an output of the CPU power supply. Since the output of the CPU power supply is cut off in the standby mode, the power consumption is reduced, and the circuit structure is simple and green.
  • FIG. 1 is a block diagram showing the circuit structure of an embodiment of a standby power control circuit for a television of the present application
  • FIG. 2 is a schematic structural view of an embodiment of a standby power control circuit for a television of the present application.
  • first”, “second”, and the like in this application are used for the purpose of description only, and are not to be construed as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
  • the application provides a television standby power control circuit.
  • the television standby power control circuit includes a CPU power supply VCC, a bistable trigger circuit 10, a switch circuit 20, and a standby trigger circuit 30, and the input end of the switch circuit 20 is An output end of the CPU power supply VCC is connected, an output end of the switch circuit 20 is connected to a power end of the CPU 40 of the television; the standby trigger circuit 30 is connected to a power control end of the CPU 40, and the standby trigger circuit 30 is further connected.
  • the output end of the bistable trigger circuit 10 is connected to the controlled end of the switch circuit 20; wherein the standby trigger circuit 30 is used for detecting Controlling the bistable trigger circuit 10 to trigger and output a first level signal when the low level standby signal is sent by the CPU 40; the switch circuit 20 is configured to receive the first level signal Turn off and cut off the output of the CPU power supply VCC.
  • the television standby power control circuit is suitable for use in television standby control.
  • the television In the initial state, the television can be controlled by a remote control or a button to turn on the switch circuit 20 to control the output of the CPU power supply VCC to realize AC power-on.
  • the CPU issues a low-level standby signal.
  • the standby trigger circuit 30 detects the low-level standby signal sent by the CPU 40, the bistable trigger circuit 10 is triggered at this time.
  • the first level signal is output. It can be understood that the first level signal output by the bistable trigger circuit 10 can be set according to actual needs.
  • the bistable state The trigger circuit 10 outputs a first level as a low level signal.
  • the switch circuit 20 is turned off, thereby cutting off the output of the CPU power supply VCC. Since the CPU power supply VCC output power is cut off to the CPU 40 in the standby state of the television, the power consumption during the standby control is reduced, energy is saved, and the environment is green.
  • the television standby power control circuit further includes a button power-on trigger circuit 50 for triggering and outputting a high-level power-on signal of the television, the button power-on trigger circuit 50 and the bistable trigger circuit 10
  • the input terminal is connected; the button power-on trigger circuit 50 is configured to control the level of the first level signal output by the bistable trigger circuit 10 when the high-level power-on signal of the television is triggered and output
  • the switch circuit 20 is further configured to be turned on when receiving the first level signal of level inversion, and control the CPU power supply VCC output.
  • the television standby power control circuit may further include a current limiting resistor R0, and the button power-on trigger circuit 50 passes through the current limiting resistor R0 and the bistable trigger circuit 10 The input is connected. By setting the current limiting resistor R0, it acts to limit the current.
  • the structure of the button power-on trigger circuit 50 can be set according to actual needs, but in the normal implementation process of the circuit, the button power-on trigger circuit 50 needs to have a button circuit compatible with the normal key value to implement, and the button is turned on. Trigger circuit 50 defaults to high impedance.
  • the above-mentioned button power-on trigger circuit 50 is mainly used to control the CPU power supply VCC to be turned on when the television is in standby and the CPU power supply VCC is turned off.
  • the button power-on trigger circuit 50 since the CPU power supply VCC is turned off, the TV cannot control the TV to be turned on by the wireless signal, for example, by remotely turning on the power, so the button power-on trigger circuit 50 is set, and when the button is turned on, the trigger circuit 50 triggers and outputs the high of the TV.
  • the button start-up trigger circuit 50 controls the bistable trigger circuit 10 to output a first level signal inversion, and the output first level signal is converted from an output low level to an output high level.
  • the switch circuit 20 is turned on to control the CPU power supply VCC output, thereby making up for the situation that the standby power cannot be turned on by the remote control when the CPU power supply VCC is turned off.
  • the bistable trigger circuit 10 includes a first transistor Q1 and a second transistor Q2. a resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; an emitter of the first transistor Q1 is grounded, and a collector of the first transistor Q1 passes through the first resistor R1 Connected to the CPU power supply VCC, the base of the first transistor Q1 is connected to the collector of the second transistor Q2 through the second resistor R2, and the second transistor Q2 The base is connected to the collector of the first transistor Q1 through the third resistor R3, the emitter of the second transistor Q2 is grounded, and the collector of the second transistor Q2 is also passed through The fourth resistor R4 is connected to the CPU power supply VCC; the collector of the first transistor Q1 is the output end of the bistable trigger circuit 10; the base of the second transistor Q2 is extremely The input of the flip-flop circuit 10 is described.
  • the bistable trigger circuit 10 includes a resistor R1, a second resistor R2, a third resistor R3,
  • the switch circuit 20 includes a third transistor Q3, a fifth resistor R5, a sixth resistor R6, and a MOS transistor Q5; a base of the third transistor Q3 and the fifth resistor R5 Connected at one end, the other end of the fifth resistor R5 is a controlled end of the switch circuit 20; the emitter of the third transistor Q3 is grounded, and the collector of the third transistor Q3 passes the
  • the sixth resistor R6 is connected to the CPU power supply VCC, the collector of the third transistor Q3 is also connected to the gate of the MOS transistor Q5, the source of the MOS transistor Q5 and the CPU power supply The VCC is connected, and the drain of the MOS transistor Q5 is the output terminal of the switching circuit 20.
  • the MOS transistor Q5 is a PMOS transistor
  • the third transistor Q3 is an NPN transistor.
  • the standby trigger circuit 30 includes a capacitor C, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a fourth transistor Q4; the first end of the capacitor C and the bistable trigger
  • the input end of the circuit 10 is connected, the second end of the capacitor C is connected to the emitter of the fourth transistor Q4 through the seventh resistor R7; one end of the eighth resistor R8 is opposite to the capacitor C
  • the common end of the seventh resistor R7 is connected, the other end of the eighth resistor R8 is grounded; the base of the fourth transistor Q4 is connected to one end of the ninth resistor R9, and the ninth resistor R9
  • the other end is the detection input terminal OFF_CTR of the standby trigger circuit 30, and the collector of the fourth transistor Q4 is connected to the power supply control terminal POWEROFF of the CPU 40.
  • the power supply control terminal of the CPU 40 when the television is AC powered on, the power supply control terminal of the CPU 40 is powered OFF by default, and the detection input terminal OFF_CTR is at a low level.
  • the first transistor Q1 is saturated and turned on.
  • the two transistor Q2 is cut off, the collector of the first transistor Q1 outputs a high level, the collector of the third transistor Q3 outputs a low level, and the MOS transistor Q5 is turned on to control the CPU power supply VCC output power to The CPU 40.
  • the detection input terminal OFF_CTR of the standby trigger circuit 30 detects the input high level, the fourth transistor Q4 is turned off, and since no voltage change occurs at both ends of the capacitor C, the bistable trigger circuit 10 The trigger signal is not received, the MOS tube remains on, and the CPU power supply VCC continuously outputs power to the CPU 40. At this time, the TV can still realize normal remote power-on or button-on. If the detection input terminal OFF_CTR of the standby trigger circuit 30 detects an input low level, the fourth transistor Q4 is turned on, so that the collector of the fourth transistor Q4 detects the low-level standby signal of the CPU 40.
  • the emitter side of the fourth transistor Q4 is also at a low level, and a voltage drop change occurs at both ends of the capacitor C.
  • the second transistor Q2 in the bistable trigger circuit 10 is turned off, and the first transistor Q1 is turned on.
  • the bistable trigger circuit 10 triggers and outputs a first level signal.
  • the collector of the third transistor Q3 outputs a high level, and the MOS transistor Q5 is turned off to control the CPU power supply VCC to stop outputting power.
  • the CPU power supply VCC is cut off in the standby state of the TV, and the CPU 40 is continuously powered by the CPU power supply VCC compared to the current standby condition, which saves energy and is environmentally friendly.
  • the base of the second transistor Q2 is at a low level
  • the button trigger circuit 50 triggers and outputs a high-level power-on signal of the television.
  • the base voltage of the second transistor Q2 increases, the second transistor Q2 is turned on, the first transistor Q1 is turned off, and the output of the first level signal of the bistable trigger circuit 10 Flip, flipped from the output low level to the output high level, the collector of the first transistor Q1 outputs a high level, the collector of the third transistor Q3 outputs a low level, and the MOS transistor Q5 conducts the control
  • the CPU power supply VCC output enables the button to be turned on.
  • the capacitor C functions to turn off the CPU power supply VCC and reset the flip-flop circuit 10 according to the output of the power supply control terminal POWEROFF of the CPU 40.
  • the bistable trigger circuit 10 is characterized in that the circuit is always in the original stable state without the external trigger signal. After the application of the input trigger signal, the bistable trigger circuit 10 flips from one stable state to another.
  • the bistable trigger circuit 10 by introducing the bistable trigger circuit 10, the standby power supply standby trigger circuit of the television is stable, and is not easily affected by external factors and self factors, and the control is accurate.
  • the bistable trigger circuit 10 is not triggered when the power detecting terminal OFF_CTR detects a high level, the fourth transistor Q4 is turned on when a low level is detected, thereby triggering the bistable trigger circuit 10 to output the first
  • the present application further provides a television set including a CPU and a television standby power control circuit.
  • the structure of the standby power control circuit of the television can refer to the above embodiment, wherein the CPU has a power terminal and a standby signal output terminal.
  • the output end of the switch circuit of the standby power control circuit of the television is connected to the power end of the CPU, and the standby trigger circuit of the standby power control circuit of the television is connected to the standby signal output end of the CPU, and the other is here. No longer.
  • the television set of the embodiment adopts the technical solution of the above-mentioned television standby power supply control circuit, the television set has all the beneficial effects of the above-described television standby power supply control circuit.

Abstract

本申请公开了一种电视机待机电源控制电路，包括CPU供电电源、待机触发电路、双稳态触发电路和开关电路，开关电路的输入端与CPU供电电源的输出端连接，开关电路的输出端与电视机的CPU的电源端连接；待机触发电路与CPU的电源控制端连接，待机触发电路还与双稳态触发电路的输入端连接，双稳态触发电路的输出端与开关电路的受控端连接；其中，待机触发电路，用于在检测到CPU发出的低电平待机信号时，控制双稳态触发电路触发并输出第一电平信号；开关电路，用于在接收到第一电平信号时关断，切断CPU供电电源的输出。本申请还公开了一种电视机。

Description

电视机待机电源控制电路及电视机
技术领域
本申请涉及电路控制领域，尤其涉及电视机待机电源控制电路及电视机。
背景技术
目前，电视机在日常生活中普及率非常高，而现有的电视机都是依靠CPU实现待机控制的，这种待机控制方式需要CPU供电电源在电视机待机时，持续输出电能至电视机的CPU，因此这种待机控制方式会造成如下缺陷：CPU待机控制需要消耗一定的电能。
申请内容
本申请的主要目的在于提供一种电视机待机电源控制电路及电视机，旨在解决电视机待机时CPU需要消耗电能的问题。
为了实现上述目的，本申请提供一种电视机待机电源控制电路，包括CPU供电电源、待机触发电路、双稳态触发电路和开关电路，所述开关电路的输入端与所述CPU供电电源的输出端连接，所述开关电路的输出端与电视机的CPU的电源端连接；所述待机触发电路与所述CPU的电源控制端连接，所述待机触发电路还与所述双稳态触发电路的输入端连接，所述双稳态触发电路的输出端与所述开关电路的受控端连接；其中，
所述待机触发电路，用于在检测到所述CPU发出的低电平待机信号时，控制所述双稳态触发电路触发并输出第一电平信号；
所述开关电路，用于在接收到所述第一电平信号时关断，切断所述CPU供电电源的输出。
可选地，所述电视机待机电源控制电路还包括用于触发并输出电视机的高电平开机信号的按键开机触发电路，所述按键开机触发电路与所述双稳态触发电路的输入端连接；
所述按键开机触发电路，用于在触发并输出所述电视机的高电平开机信号时，控制所述双稳态触发电路输出的第一电平信号的电平翻转；
所述开关电路，还用于在接收到电平翻转的所述第一电平信号时开启，控制所述CPU供电电源输出。
可选地，所述电视机待机电源控制电路还包括限流电阻，所述按键开机触发电路通过所述限流电阻与所述双稳态触发电路的输入端连接。
可选地，所述双稳态触发电路包括第一三极管、第二三极管、第一电阻、第二电阻、第三电阻及第四电阻；所述第一三极管的发射极接地，所述第一三极管的集电极通过所述第一电阻与所述CPU供电电源连接，所述第一三极管的基极通过所述第二电阻与所述第二三极管的集电极连接；所述第二三极管的基极通过所述第三电阻与所述第一三极管的集电极连接，所述第二三极管的发射极接地，所述第二三极管的集电极还通过所述第四电阻与所述CPU供电电源连接；所述第一三极管的集电极为所述双稳态触发电路的输出端；所述第二三极管的基极为所述双稳态触发电路的输入端。
可选地，所述第一三极管和所述第二三极管均为NPN三极管。
可选地，所述开关电路包括第三三极管、第五电阻、第六电阻和MOS管；所述第三三极管的基极与所述第五电阻的一端连接，所述第五电阻的另一端为所述开关电路的受控端；所述第三三极管的发射极接地，所述第三三极管的集电极通过所述第六电阻与所述CPU供电电源连接，所述第三三极管的集电极还与所述MOS管的栅极连接；所述MOS管的源极与所述CPU供电电源连接，所述MOS管的漏极为所述开关电路的输出端。
可选地，所述MOS管为PMOS管，所述第三三极管为NPN三极管。
可选地，所述待机触发电路包括电容、第七电阻、第八电阻、第九电阻和第四三极管；所述电容的第一端与所述双稳态触发电路的输入端连接，所述电容的第二端通过所述第七电阻与所述第四三极管的发射极连接；所述第八电阻的一端与所述电容和所述第七电阻的公共端连接，所述第八电阻的另一端接地；所述第四三极管的基极与所述第九电阻的一端连接，所述第九电阻的另一端为待机触发电路的检测输入端，所述第四三极管的集电极与所述CPU的电源控制端连接。
可选地，所述第四三极管为PNP三极管。
此外，为实现上述目的，本申请还提供一种电视机，所述电视机包括CPU和电视机待机电源控制电路，所述电视机待机电源控制电路是如上述任一项所述的电视机待机电源控制电路，所述CPU具有电源端及待机信号输出端，所述电视机待机电源控制电路的开关电路的输出端与所述CPU的电源端连接，所述电视机待机电源控制电路的待机触发电路与所述CPU的待机信号输出端连接。
本申请的技术方案中，电视机从开机状态进入待机状态时，CPU发出低电平待机信号，所述待机触发电路检测到该低电平待机信号，控制双稳态触发电路触发并输出第一电平信号，所述开关电路切断所述CPU供电电源的输出。由于在待机情况下，切断了CPU供电电源的输出，因此减少了电能的消耗，这种电路结构简单，绿色环保。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请电视机待机电源控制电路一实施例的电路结构框图；
图2为本申请电视机待机电源控制电路一实施例的结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
附图标号说明：
标号 名称 标号 名称
VCC CPU供电电源 OFF_CTR 检测输入端
10 双稳态触发电路 R1 第一电阻
20 开关电路 R2 第二电阻
30 待机触发电路 R3 第三电阻
40 CPU R4 第四电阻
50 按键开机触发电路 R5 第五电阻
Q1 第一三极管 R6 第六电阻
Q2 第二三极管 R7 第七电阻
Q3 第三三极管 R8 第八电阻
Q4 第四三极管 R9 第九电阻
Q5 MOS管 C 电容
POWEROFF 电源控制端 R0 限流电阻
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提供一种电视机待机电源控制电路。
参照图1，在一实施例中，该电视机待机电源控制电路包括CPU供电电源VCC、双稳态触发电路10、开关电路20和待机触发电路30，所述开关电路20的输入端与所述CPU供电电源VCC的输出端连接，所述开关电路20的输出端与电视机的CPU40的电源端连接；所述待机触发电路30与所述CPU40的电源控制端连接，所述待机触发电路30还与所述双稳态触发电路10的输入端连接，所述双稳态触发电路10的输出端与所述开关电路20的受控端连接；其中，所述待机触发电路30，用于在检测到所述CPU40发出的低电平待机信号时，控制所述双稳态触发电路10触发并输出第一电平信号；所述开关电路20，用于在接收到所述第一电平信号时关断，切断所述CPU供电电源VCC的输出。
在本实施例中，该电视机待机电源控制电路适用于电视机待机控制中。初始状态下，电视机可以通过遥控或按键控制，使开关电路20开启，以控制所述CPU供电电源VCC输出，实现交流开机。在电视机从开机状态进入待机状态时，CPU发出低电平待机信号，当所述待机触发电路30检测到所述CPU40发出的低电平待机信号时，此时双稳态触发电路10触发并输出第一电平信号。可以理解的是，所述双稳态触发电路10输出的第一电平信号可以根据实际需要进行设置，在本实施例中，当待机触发电路20接收到低电平待机信号时，双稳态触发电路10输出第一电平为低电平信号。所述开关电路20的受控端在接收到所述第一电平信号时，所述开关电路20关断，从而切断了所述CPU供电电源VCC的输出。由于在电视机待机情况下切断了CPU供电电源VCC输出电能至CPU40，因此减少了待机控制时电能的消耗，节约了能源，绿色环保。
可选地，上述电视机待机电源控制电路还包括用于触发并输出电视机的高电平开机信号的按键开机触发电路50，所述按键开机触发电路50与所述双稳态触发电路10的输入端连接；所述按键开机触发电路50，用于在触发并输出所述电视机的高电平开机信号时，控制所述双稳态触发电路10输出的第一电平信号的电平翻转；所述开关电路20，还用于在接收到电平翻转的所述第一电平信号时开启，控制所述CPU供电电源VCC输出。
请一并参照图2，可选地，上述电视机待机电源控制电路还可以包括限流电阻R0，所述按键开机触发电路50通过所述限流电阻R0与所述双稳态触发电路10的输入端连接。通过设置限流电阻R0，起到了限制电流的作用。
需要说明的是，按键开机触发电路50的结构可以根据实际需要进行设置，但在电路正常实现过程中，所述按键开机触发电路50需要有和正常键值相兼容的按键电路来实现，按键开机触发电路50默认高阻。上述按键开机触发电路50主要用于在电视机待机且CPU供电电源VCC关闭的情况下，控制CPU供电电源VCC打开。可以理解的是，由于CPU供电电源VCC关闭，电视机无法通过无线信号控制电视机开机，例如通过遥控开机，因此设置了按键开机触发电路50，当按键开机触发电路50触发并输出电视机的高电平开机信号时，所述按键开机触发电路50控制所述双稳态触发电路10输出第一电平信号翻转，所述输出第一电平信号由输出低电平转为输出高电平，所述开关电路20开启，控制CPU供电电源VCC输出，从而弥补了在待机且CPU供电电源VCC关闭时，无法通过遥控开机的情况。
需要说明的是，上述双稳态触发电路10的结构可以根据实际需要进行设置，在本实施例中，上述双稳态触发电路10包括第一三极管Q1、第二三极管Q2、第一电阻R1、第二电阻R2、第三电阻R3及第四电阻R4；所述第一三极管Q1的发射极接地，所述第一三极管Q1的集电极通过所述第一电阻R1与所述CPU供电电源VCC连接，所述第一三极管Q1的基极通过所述第二电阻R2与所述第二三极管Q2的集电极连接，所述第二三极管Q2的基极通过所述第三电阻R3与所述第一三极管Q1的集电极连接，所述第二三极管Q2的发射极接地，所述第二三极管Q2的集电极还通过所述第四电阻R4与所述CPU供电电源VCC连接；所述第一三极管Q1的集电极为所述双稳态触发电路10的输出端；所述第二三极管Q2的基极为所述双稳态触发电路10的输入端。可选地，所述第一三极管Q1和所述第二三极管Q2均为NPN三极管。
可选地，所述开关电路20包括第三三极管Q3、第五电阻R5、第六电阻R6和MOS管Q5；所述第三三极管Q3的基极与所述第五电阻R5的一端连接，所述第五电阻R5的另一端为所述开关电路20的受控端；所述第三三极管Q3的发射极接地，所述第三三极管Q3的集电极通过所述第六电阻R6与所述CPU供电电源VCC连接，所述第三三极管Q3的集电极还与所述MOS管Q5的栅极连接，所述MOS管Q5的源极与所述CPU供电电源VCC连接，所述MOS管Q5的漏极为所述开关电路20的输出端。可选地，所述MOS管Q5为PMOS管，所述第三三极管Q3为NPN三极管。
可选地，上述待机触发电路30包括电容C、第七电阻R7、第八电阻R8、第九电阻R9和第四三极管Q4；所述电容C的第一端与所述双稳态触发电路10的输入端连接，所述电容C的第二端通过所述第七电阻R7与所述第四三极管Q4的发射极连接；所述第八电阻R8的一端与所述电容C和所述第七电阻R7的公共端连接，所述第八电阻R8的另一端接地；所述第四三极管Q4的基极与所述第九电阻R9的一端连接，所述第九电阻R9的另一端为待机触发电路30的检测输入端OFF_CTR，所述第四三极管Q4的集电极与CPU40的电源控制端POWEROFF连接。
需要说明的是，在本实施例中，电视机交流开机时，CPU40的电源控制端POWEROFF默认高电平，检测输入端OFF_CTR默认低电平，此时第一三极管Q1饱和导通，第二三极管Q2截止，所述第一三极管Q1的集电极输出高电平，第三三极管Q3的集电极输出低电平，MOS管Q5导通控制CPU供电电源VCC输出电能至所述CPU40。在电视机交流开机后，若所述待机触发电路30的检测输入端OFF_CTR检测到输入高电平，第四三极管Q4截止，由于电容C两端未产生电压变化，双稳态触发电路10未接收到触发信号，MOS管保持导通，CPU供电电源VCC持续输出电能至CPU40，此时电视机依然能实现正常的遥控开机或按键开机。若所述待机触发电路30的检测输入端OFF_CTR检测到输入低电平，则第四三极管Q4导通，使第四三极管Q4的集电极检测到所述CPU40的低电平待机信号，第四三极管Q4的发射极侧也为低电平，电容C两端由此产生压降变化，双稳态触发电路10中第二三极管Q2截止，第一三极管Q1导通，双稳态触发电路10触发并输出第一电平信号，此时第三三极管Q3的集电极输出高电平，MOS管Q5关断，以控制所述CPU供电电源VCC停止输出电能至所述CPU40，从而实现了在电视机待机情况下，切断CPU供电电源VCC，相比目前待机情况下持续通过CPU供电电源VCC为CPU40供电，节约了能源，绿色环保。
可选地，在电视机待机且CPU供电电源VCC停止输出时，所述第二三极管Q2的基极为低电平，当所述按键触发电路50触发并输出电视机的高电平开机信号时，所述第二三极管Q2的基极电压增大，使第二三极管Q2导通，第一三极管Q1截止，所述双稳态触发电路10的输出第一电平信号翻转，由输出低电平翻转为输出高电平，第一三极管Q1的集电极输出高电平，第三三极管Q3的集电极输出低电平，MOS管Q5导通控制所述CPU供电电源VCC输出，从而实现了按键开机。
需要说明的是，电容C在上述实施例中起到了根据CPU40的电源控制端POWEROFF的输出关断CPU供电电源VCC及使双稳态触发电路10复位的作用。而在电子电路中，双稳态触发电路10的特点是在没有外来触发信号的作用下，电路始终处于原来的稳定状态。在外加输入触发信号作用后，所述双稳态触发电路10从一个稳定状态翻转到另一个稳定状态。在本实施例中，通过引入双稳态触发电路10使该电视机待机电源待机触发电路运行稳定，不容易受外界因素和自身因素影响，控制准确。
此外，为了保证在电源检测端OFF_CTR检测到高电平时不触发双稳态触发电路10，在检测到低电平才导通第四三极管Q4，从而触发双稳态触发电路10输出第一电平翻转的效果，需要将电容C的取值设置的相对较小，第七电阻R7和第八电阻R8分压适当。
本申请还提供一种电视机，该电视机包括CPU和电视机待机电源控制电路，该电视机待机电源控制电路的结构可参照上述实施例，其中，所述CPU具有电源端及待机信号输出端，所述电视机待机电源控制电路的开关电路的输出端与所述CPU的电源端连接，所述电视机待机电源控制电路的待机触发电路与所述CPU的待机信号输出端连接，其他在此不再赘述。理所应当地，由于本实施例的电视机采用了上述电视机待机电源控制电路的技术方案，因此该电视机具有上述电视机待机电源控制电路所有的有益效果。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种电视机待机电源控制电路，其中，包括CPU供电电源、待机触发电路、双稳态触发电路和开关电路，所述开关电路的输入端与所述CPU供电电源的输出端连接，所述开关电路的输出端与电视机的CPU的电源端连接；所述待机触发电路与所述CPU的电源控制端连接，所述待机触发电路还与所述双稳态触发电路的输入端连接，所述双稳态触发电路的输出端与所述开关电路的受控端连接；其中，
    所述待机触发电路，用于在检测到所述CPU发出的低电平待机信号时，控制所述双稳态触发电路触发并输出第一电平信号；
    所述开关电路，用于在接收到所述第一电平信号时关断，切断所述CPU供电电源的输出。
  2. 如权利要求1所述的电视机待机电源控制电路，其中，所述电视机待机电源控制电路还包括用于触发并输出电视机的高电平开机信号的按键开机触发电路，所述按键开机触发电路与所述双稳态触发电路的输入端连接；
    所述按键开机触发电路，用于在触发并输出所述电视机的高电平开机信号时，控制所述双稳态触发电路输出的第一电平信号的电平翻转；
    所述开关电路，还用于在接收到电平翻转的所述第一电平信号时开启，控制所述CPU供电电源输出。
  3. 如权利要求2所述的电视机待机电源控制电路，其中，所述电视机待机电源控制电路还包括限流电阻，所述按键开机触发电路通过所述限流电阻与所述双稳态触发电路的输入端连接。
  4. 如权利要求3所述的电视机待机电源控制电路，其中，所述双稳态触发电路包括第一三极管、第二三极管、第一电阻、第二电阻、第三电阻及第四电阻；所述第一三极管的发射极接地，所述第一三极管的集电极通过所述第一电阻与所述CPU供电电源连接，所述第一三极管的基极通过所述第二电阻与所述第二三极管的集电极连接；所述第二三极管的基极通过所述第三电阻与所述第一三极管的集电极连接，所述第二三极管的发射极接地，所述第二三极管的集电极还通过所述第四电阻与所述CPU供电电源连接；所述第一三极管的集电极为所述双稳态触发电路的输出端；所述第二三极管的基极为所述双稳态触发电路的输入端。
  5. 如权利要求4所述的电视机待机电源控制电路，其中，所述开关电路包括第三三极管、第五电阻、第六电阻和MOS管；所述第三三极管的基极与所述第五电阻的一端连接，所述第五电阻的另一端为所述开关电路的受控端；所述第三三极管的发射极接地，所述第三三极管的集电极通过所述第六电阻与所述CPU供电电源连接，所述第三三极管的集电极还与所述MOS管的栅极连接；所述MOS管的源极与所述CPU供电电源连接，所述MOS管的漏极为所述开关电路的输出端。
  6. 如权利要求5所述的电视机待机电源控制电路，其中，所述待机触发电路包括电容、第七电阻、第八电阻、第九电阻和第四三极管；所述电容的第一端与所述双稳态触发电路的输入端连接，所述电容的第二端通过所述第七电阻与所述第四三极管的发射极连接；所述第八电阻的一端与所述电容和所述第七电阻的公共端连接，所述第八电阻的另一端接地；所述第四三极管的基极与所述第九电阻的一端连接，所述第九电阻的另一端为待机触发电路的检测输入端，所述第四三极管的集电极与所述CPU的电源控制端连接。
  7. 如权利要求1所述的电视机待机电源控制电路，其中，所述双稳态触发电路包括第一三极管、第二三极管、第一电阻、第二电阻、第三电阻及第四电阻；所述第一三极管的发射极接地，所述第一三极管的集电极通过所述第一电阻与所述CPU供电电源连接，所述第一三极管的基极通过所述第二电阻与所述第二三极管的集电极连接；所述第二三极管的基极通过所述第三电阻与所述第一三极管的集电极连接，所述第二三极管的发射极接地，所述第二三极管的集电极还通过所述第四电阻与所述CPU供电电源连接；所述第一三极管的集电极为所述双稳态触发电路的输出端；所述第二三极管的基极为所述双稳态触发电路的输入端。
  8. 如权利要求7所述的电视机待机电源控制电路，其中，所述第一三极管和所述第二三极管均为NPN三极管。
  9. 如权利要求1所述的电视机待机电源控制电路，其中，所述开关电路包括第三三极管、第五电阻、第六电阻和MOS管；所述第三三极管的基极与所述第五电阻的一端连接，所述第五电阻的另一端为所述开关电路的受控端；所述第三三极管的发射极接地，所述第三三极管的集电极通过所述第六电阻与所述CPU供电电源连接，所述第三三极管的集电极还与所述MOS管的栅极连接；所述MOS管的源极与所述CPU供电电源连接，所述MOS管的漏极为所述开关电路的输出端。
  10. 如权利要求9所述的电视机待机电源控制电路，其中，所述MOS管为PMOS管，所述第三三极管为NPN三极管。
  11. 如权利要求1所述的电视机待机电源控制电路，其中，所述待机触发电路包括电容、第七电阻、第八电阻、第九电阻和第四三极管；所述电容的第一端与所述双稳态触发电路的输入端连接，所述电容的第二端通过所述第七电阻与所述第四三极管的发射极连接；所述第八电阻的一端与所述电容和所述第七电阻的公共端连接，所述第八电阻的另一端接地；所述第四三极管的基极与所述第九电阻的一端连接，所述第九电阻的另一端为待机触发电路的检测输入端，所述第四三极管的集电极与所述CPU的电源控制端连接。
  12. 如权利要求11所述的电视机待机电源控制电路，其中，所述第四三极管为PNP三极管。
  13. 一种电视机，其中，所述电视机包括CPU和电视机待机电源控制电路，所述CPU具有电源端及待机信号输出端，所述电视机待机电源控制电路的开关电路的输出端与所述CPU的电源端连接，所述电视机待机电源控制电路的待机触发电路与所述CPU的待机信号输出端连接；
    所述电视机待机电源控制电路包括CPU供电电源、待机触发电路、双稳态触发电路和开关电路，所述开关电路的输入端与所述CPU供电电源的输出端连接，所述开关电路的输出端与电视机的CPU的电源端连接；所述待机触发电路与所述CPU的电源控制端连接，所述待机触发电路还与所述双稳态触发电路的输入端连接，所述双稳态触发电路的输出端与所述开关电路的受控端连接；其中，
    所述待机触发电路，用于在检测到所述CPU发出的低电平待机信号时，控制所述双稳态触发电路触发并输出第一电平信号；
    所述开关电路，用于在接收到所述第一电平信号时关断，切断所述CPU供电电源的输出。
  14. 如权利要求13所述的电视机，其中，所述电视机待机电源控制电路还包括用于触发并输出电视机的高电平开机信号的按键开机触发电路，所述按键开机触发电路与所述双稳态触发电路的输入端连接；
    所述按键开机触发电路，用于在触发并输出所述电视机的高电平开机信号时，控制所述双稳态触发电路输出的第一电平信号的电平翻转；
    所述开关电路，还用于在接收到电平翻转的所述第一电平信号时开启，控制所述CPU供电电源输出。
  15. 如权利要求14所述的电视机，其中，所述电视机待机电源控制电路还包括限流电阻，所述按键开机触发电路通过所述限流电阻与所述双稳态触发电路的输入端连接。
  16. 如权利要求13所述的电视机，其中，所述双稳态触发电路包括第一三极管、第二三极管、第一电阻、第二电阻、第三电阻及第四电阻；所述第一三极管的发射极接地，所述第一三极管的集电极通过所述第一电阻与所述CPU供电电源连接，所述第一三极管的基极通过所述第二电阻与所述第二三极管的集电极连接；所述第二三极管的基极通过所述第三电阻与所述第一三极管的集电极连接，所述第二三极管的发射极接地，所述第二三极管的集电极还通过所述第四电阻与所述CPU供电电源连接；所述第一三极管的集电极为所述双稳态触发电路的输出端；所述第二三极管的基极为所述双稳态触发电路的输入端。
  17. 如权利要求16所述的电视机，其中，所述第一三极管和所述第二三极管均为NPN三极管。
  18. 如权利要求13所述的电视机，其中，所述开关电路包括第三三极管、第五电阻、第六电阻和MOS管；所述第三三极管的基极与所述第五电阻的一端连接，所述第五电阻的另一端为所述开关电路的受控端；所述第三三极管的发射极接地，所述第三三极管的集电极通过所述第六电阻与所述CPU供电电源连接，所述第三三极管的集电极还与所述MOS管的栅极连接；所述MOS管的源极与所述CPU供电电源连接，所述MOS管的漏极为所述开关电路的输出端。
  19. 如权利要求13所述的电视机，其中，所述MOS管为PMOS管，所述第三三极管为NPN三极管。
  20. 如权利要求13所述的电视机，其中，所述待机触发电路包括电容、第七电阻、第八电阻、第九电阻和第四三极管；所述电容的第一端与所述双稳态触发电路的输入端连接，所述电容的第二端通过所述第七电阻与所述第四三极管的发射极连接；所述第八电阻的一端与所述电容和所述第七电阻的公共端连接，所述第八电阻的另一端接地；所述第四三极管的基极与所述第九电阻的一端连接，所述第九电阻的另一端为待机触发电路的检测输入端，所述第四三极管的集电极与所述CPU的电源控制端连接。
PCT/CN2017/110353 2017-05-03 2017-11-10 电视机待机电源控制电路及电视机 WO2018201684A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201720483254.2U CN206743411U (zh) 2017-05-03 2017-05-03 电视机待机电源控制电路及电视机
CN201720483254.2 2017-05-03

Publications (1)

Publication Number Publication Date
WO2018201684A1 true WO2018201684A1 (zh) 2018-11-08

Family

ID=60562608

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/110353 WO2018201684A1 (zh) 2017-05-03 2017-11-10 电视机待机电源控制电路及电视机

Country Status (2)

Country Link
CN (1) CN206743411U (zh)
WO (1) WO2018201684A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110299122A (zh) * 2019-07-05 2019-10-01 福州京东方光电科技有限公司 显示器模式控制电路及其驱动方法、显示器模式控制系统
CN112230756B (zh) * 2020-08-28 2022-07-08 苏州浪潮智能科技有限公司 一种电源装置、电源控制方法及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003324667A (ja) * 2002-05-08 2003-11-14 Sanyo Electric Co Ltd データ伝送回路及び放送受信装置
CN101013859A (zh) * 2006-02-05 2007-08-08 王海 具有微功耗待机功能的容开电源
CN101197979A (zh) * 2007-12-05 2008-06-11 深圳创维数字技术股份有限公司 一种数字电视接收机的节能待机系统
CN101419434A (zh) * 2007-10-26 2009-04-29 王海 具有微功耗待机功能的容开电源
CN201345697Y (zh) * 2008-12-24 2009-11-11 深圳创维－Rgb电子有限公司 一种电源待机控制系统及液晶电视
CN203734748U (zh) * 2013-12-19 2014-07-23 深圳Tcl新技术有限公司 电视机的待机电路及电视机

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003324667A (ja) * 2002-05-08 2003-11-14 Sanyo Electric Co Ltd データ伝送回路及び放送受信装置
CN101013859A (zh) * 2006-02-05 2007-08-08 王海 具有微功耗待机功能的容开电源
CN101419434A (zh) * 2007-10-26 2009-04-29 王海 具有微功耗待机功能的容开电源
CN101197979A (zh) * 2007-12-05 2008-06-11 深圳创维数字技术股份有限公司 一种数字电视接收机的节能待机系统
CN201345697Y (zh) * 2008-12-24 2009-11-11 深圳创维－Rgb电子有限公司 一种电源待机控制系统及液晶电视
CN203734748U (zh) * 2013-12-19 2014-07-23 深圳Tcl新技术有限公司 电视机的待机电路及电视机

Also Published As

Publication number Publication date
CN206743411U (zh) 2017-12-12

Similar Documents

Publication Publication Date Title
WO2015172584A1 (zh) 一种电子设备及其辅助开关机装置
CN102332898B (zh) 零待机功耗开关机电路
WO2018201684A1 (zh) 电视机待机电源控制电路及电视机
WO2014114033A1 (zh) 一种耳机和实现耳机自动识别切换控制的方法
WO2020113709A1 (zh) 驱动保护电路、显示装置及驱动保护方法
CN105511540A (zh) 一种具有极低泄露电流的带隙基准启动电路
WO2014040421A1 (zh) 一种电平跳变复位ic设计电路
WO2022105433A1 (zh) 看门狗芯片供电电路、看门狗电路及看门狗装置
CN201995065U (zh) 一种唤醒电路及数字电视接收终端
WO2019206040A1 (zh) 电源使能电路
CN214204980U (zh) 一种通讯激活电路
US3090039A (en) Bistable indicator circuit
US20200366303A1 (en) Circuit having analog-to-digital conversion function and electronic device
WO2019020085A1 (zh) 采样电流处理电路、功率检测电路以及电磁烹饪器具
CN111046395A (zh) Ec更新固件保护电路以及电子设备
WO2018040049A1 (zh) 信号传输电路及通信设备
WO2016026244A1 (zh) 电视机控制电路及电视机
CN212305482U (zh) 一种用于可视对讲门铃的音频信号激活电路
CN217010837U (zh) 声光开关控制电路及装置
CN206849250U (zh) 一种遥控器
CN210925880U (zh) 大功率精密继电器
CN210609113U (zh) 一种一键开关机电路
CN213903636U (zh) 数据采集电路及装置
JPH0346594Y2 (zh)
CN206211962U (zh) 电源开关控制电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17908742

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09.03.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17908742

Country of ref document: EP

Kind code of ref document: A1