WO2020052055A1 - 存储器写保护电路及显示装置 - Google Patents

存储器写保护电路及显示装置 Download PDF

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Publication number
WO2020052055A1
WO2020052055A1 PCT/CN2018/115778 CN2018115778W WO2020052055A1 WO 2020052055 A1 WO2020052055 A1 WO 2020052055A1 CN 2018115778 W CN2018115778 W CN 2018115778W WO 2020052055 A1 WO2020052055 A1 WO 2020052055A1
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WO
WIPO (PCT)
Prior art keywords
memory
write
write protection
resistor
terminal
Prior art date
Application number
PCT/CN2018/115778
Other languages
English (en)
French (fr)
Inventor
黄北洲
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2020052055A1 publication Critical patent/WO2020052055A1/zh
Priority to US17/035,755 priority Critical patent/US11386943B2/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/22—Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source

Definitions

  • the present application relates to the technical field of electronic circuits, and in particular, to a memory write protection circuit and a display device.
  • the timing controller TCON IC Timing Controller Integrated Circuit
  • SROM Internal Static Read Only Memory
  • EEPROM Electrically Erasable Programmable read only The data stored in memory
  • flash memory can be saved even after the power is turned off, so the control program of the timing controller is stored in the external memory EEPROM or flash.
  • the data in the memory cannot be modified during the normal operation of the display device. Once it is modified, the setting data is wrong, which will cause the display device to display abnormally.
  • the write protection pin of the memory is connected to the communication bus. Interference signals on the communication bus may cause the write protection pin signal of the memory to be pulled up, and the data in the memory may be rewritten.
  • the main purpose of the present application is to provide a memory write protection circuit and a display device, which are intended to prevent software data of the memory from being rewritten.
  • the present application proposes a memory write protection circuit.
  • the memory write protection circuit includes:
  • a data write trigger terminal which is connected to a write protection pin of the memory and is configured to receive a first level signal that controls the memory to enter a write state
  • the write-protection control circuit is connected to the write-protect pin of the memory and is configured to provide a second-level signal that restricts data to be written to the memory to the write-protect pin of the memory; the second-level signal and the first-level signal are Opposite polarity
  • the interference signal absorption circuit is connected to the data write trigger terminal and is configured to detect a level signal received by the data write trigger terminal when the memory is normally operating, and receive the signal when the data write trigger terminal is detected. When the signal reaches the first level, the first level signal is absorbed.
  • the interference signal absorption circuit is specifically configured to detect a level signal received by the data write trigger when receiving a first control signal characterizing the normal operation of the memory, and detect the data write When the in trigger terminal receives the first level signal, it absorbs the first level signal.
  • the interference signal absorption circuit includes a first switch tube and a first resistor, and an input terminal of the first switch tube is interconnected with the data write trigger terminal and the first terminal of the first resistor, The second end of the first resistor is connected to the controlled end of the first electronic switch, and the output end of the first switch tube is grounded.
  • the first switching transistor is an N-MOS transistor.
  • the memory write protection circuit further includes a power input terminal
  • the interference signal absorption circuit includes a second switch tube and a second resistor, and an input terminal of the second switch tube is connected to the data write trigger terminal A controlled end of the second switch tube is connected to the power input terminal via the second resistor, and an output terminal of the second switch tube is grounded.
  • the power input terminal VCC is connected in parallel with the power input terminal of the memory to access the power supply of the memory.
  • the second switching transistor is an N-MOS transistor.
  • the memory write protection circuit further includes a current limiting element, and the current limiting element is disposed in series between the data write trigger terminal and a write protection pin of the memory.
  • the current limiting element is a third resistor, and the third resistor is disposed in series between the data write trigger terminal and a write protection pin of the memory.
  • the write protection control circuit includes a fourth resistor, and the fourth resistor is disposed in series between the write protection pin of the memory and the ground.
  • the third resistor and the fourth resistor are arranged in series.
  • the third resistor and the fourth resistor are set to be connected to a host computer through an I2C communication bus and an electrical connector at the data write trigger terminal, and a high-level write protection trigger signal is connected.
  • a high-level signal is controlled to be output to the write protection pin to trigger the memory to enter a writable state.
  • a ratio of resistance values of the third resistor and the fourth resistor is 1:12 to 1: 6.
  • a ratio of resistance values of the third resistor and the fourth resistor is set to 1:10.
  • the present application also proposes a memory write protection circuit.
  • the memory write protection circuit includes:
  • the first resistor is connected to the write protection pin of the memory and is configured to input a low-level write control signal to the write protection pin of the memory when the memory is normally operating;
  • the data write trigger terminal is connected to the write protection pin of the memory and is configured to output a high-level write protection trigger signal to the write protection pin of the memory when the memory is performing data update;
  • An interference signal absorption circuit connected to the data write trigger terminal,
  • the present application also proposes a display device including the memory write protection circuit as described above; the memory write protection circuit includes:
  • a data write trigger terminal which is connected to a write protection pin of the memory and is configured to receive a first level signal that controls the memory to enter a write state
  • the write-protection control circuit is connected to the write-protect pin of the memory and is configured to provide a second-level signal that restricts data to be written to the memory to the write-protect pin of the memory; the second-level signal and the first-level signal Opposite polarity
  • the interference signal absorption circuit is connected to the data write trigger terminal and is configured to detect a level signal received by the data write trigger terminal when the memory is normally operating, and receive the signal when the data write trigger terminal is detected. When the signal reaches the first level, the first level signal is absorbed.
  • the display device further includes an I 2 C (Inter-Integrated Circuit) communication bus and a timing controller, and the memory is connected to the timing controller through an I 2 C communication bus.
  • I 2 C Inter-Integrated Circuit
  • the display device further includes a display panel, a source driving integrated circuit, and a gate driving integrated circuit.
  • the timing controller is connected to the source driving integrated circuit and the gate driving integrated circuit, respectively.
  • the source driving integrated circuit and the gate driving integrated circuit are also connected to the display panel.
  • the interference signal absorption circuit is specifically configured to detect a level signal received by the data write trigger when receiving a first control signal characterizing the normal operation of the memory, and detect the data write When the input trigger receives the first level signal, it absorbs the first level signal.
  • the memory write protection circuit further includes a power input terminal
  • the interference signal absorption circuit includes a second switch tube and a second resistor, and an input terminal of the second switch tube is connected to the data write trigger terminal A controlled end of the second switch tube is connected to the power input terminal via the second resistor, and an output terminal of the second switch tube is grounded.
  • the memory write protection circuit of the present application is provided with a write protection control circuit and connected to the write protection pin of the memory, so that when the memory works normally, a write control signal is input to the write protection pin of the memory; and a data write trigger terminal and a write protection trigger The signal output end is respectively connected to the electrical connector and the write protection pin of the memory, so that when the memory performs data update, the write protection trigger signal that is accessed is output to the write protection pin of the memory; the application also provides that the interference signal is absorbed A circuit whose input end is connected to the data writing trigger end, so as to absorb the interference signal that enters the data writing trigger end on the I 2 C (Inter-Integrated Circuit) communication bus when the display device is powered on and works normally.
  • I 2 C Inter-Integrated Circuit
  • the application solves that the level of the write protection pin of the memory pin is pulled up by the interference signal, which causes the interference signal on the I 2 C communication bus to access the data transmission pin (clock pin and data pin) of the memory through the I 2 C communication bus.
  • the problem of rewriting the software data in the memory This application can effectively prevent software data in the memory from being rewritten.
  • FIG. 1 is a functional structure diagram of an embodiment of a memory write protection circuit of the present application
  • FIG. 2 is a schematic structural diagram of an embodiment of a memory write protection circuit of the present application.
  • FIG. 3 is a schematic structural diagram of another embodiment of a memory write protection circuit of the present application.
  • Label name Label name WP-I Data write trigger R1 ⁇ R4 First resistance to fourth resistance 100 Memory WP Write protect foot 10 Write protection control circuit Q1 First switch tube 20 Interference signal absorption circuit Q2 Second switch tube
  • the directional indication is only used to explain in a specific posture (as shown in the drawings) (Shown) the relative positional relationship, movement, etc. of the various components, if the specific posture changes, the directional indicator will change accordingly.
  • This application proposes a memory write-protection circuit, which is suitable for a display device with a display panel, such as a television, a mobile phone, or a computer.
  • the memory write protection circuit includes:
  • a data write trigger terminal WP-I which is connected to the write protection pin WP of the memory 100 and is configured to receive a first level signal that controls the memory 100 to enter a write state;
  • the write protection control circuit 10 is connected to the write protection pin WP of the memory 100 and is configured to provide a second level signal that restricts data to be written to the memory 100 to the write protection pin WP of the memory 100; the second level signal and The polarity of the first level signal is opposite;
  • the interference signal absorption circuit 20 is connected to the data write trigger terminal WP-I, and is configured to detect a level signal received by the data write trigger terminal WP-I when the memory 100 works normally, and detects When the data write trigger terminal WP-I receives the first level signal, it absorbs the first level signal.
  • the first level signal may be high level, the second level signal is configured as low level, or the first level signal is configured as low level, and the second level signal is configured Is high.
  • the memory 100 may be provided on a timing controller (TCON) PCB.
  • the memory 100 may store a control signal for driving the gate driving integrated circuit and the source driving integrated circuit, and pass the I 2 C (Inter-Integrated Circuit) )
  • the communication bus is communicatively connected to the timing controller.
  • the timing controller reads the control signals in the memory 100 and other setting data to perform initial settings to generate corresponding timing control signals to drive the display.
  • the source driving integrated circuit and the gate driving integrated circuit of the display panel in the device work.
  • the data in the memory 100 cannot be modified during the normal operation of the display device. Once modified, the setting data is wrong, which will cause the display device to display abnormally.
  • a write protection pin WP pin
  • the memory 100 can be controlled to write data, and at the low level, data cannot be written, and the memory 100 is write protected. Therefore, in this embodiment, during the normal operation of the memory 100, a second-level signal that restricts data to be written to the memory 100 is provided to the write protection pin WP of the memory 100 to write-protect the memory 100.
  • the write protection is generally performed by connecting a resistor in series between the write protection and the ground, so that the data of the memory 100 will not be rewritten when the display device works normally.
  • the write protection pin WP, clock pin and data pin of the memory 100 are connected to the upper computer through the I2C communication bus and electrical connector, and the input of the upper computer is received at the write protection pin WP.
  • noise high-level surge
  • the interference signal will The memory 100 malfunctions, and the data of the interference signal is written, causing the software data code stored in the memory 100 to be rewritten.
  • the memory write protection circuit of this embodiment may be provided on the main control board of the display device, and write-protect the memory 100 in the display device to prevent the programs stored in the memory 100, that is, the software data code from being changed. tamper.
  • the data writing trigger terminal WP-I is connected to the electrical connector in the display device through the I2C communication bus.
  • the data writing trigger terminal WP-I passes the I2C communication bus and power.
  • the connector is connected to the upper computer to access the high-level write protection trigger signal to the write protection pin WP of the memory 100.
  • the upper computer can communicate with the memory 100 through the electrical connector in the display device and the I2C communication bus. Thereby, the software data of the memory 100 is rewritten.
  • the write protection control circuit 10 is connected to the write protection pin WP of the memory 100, that is, in parallel with the write protection trigger signal output terminal, so as to output the low-level second-level signal to the write protection of the memory 100 when the display device works normally.
  • the pin WP that is, the level of the write protection pin WP of the memory 100 is pulled down by the write protection control circuit 10 to ensure that the software data in the memory 100 is not rewritten when the display device is powered on and works normally, so that The memory 100 is write protected.
  • the input terminal of the interference signal absorption circuit 20 is connected to the data write trigger terminal WP-I.
  • the write protection pin WP of the memory 100 is clamped at a low level for write protection. If the interference signal absorption circuit 20 detects that the data write trigger terminal WP-I receives a high-level first-level signal during the normal operation of the memory 100, it can be determined that the first-level signal is high-voltage Level interference signal, and absorbs the interference signal flowing from the I 2 C communication bus to the data writing trigger terminal WP-I, so as to avoid the level of the write protection pin WP of the 100-pin memory being pulled up by the interference signal, leading to I
  • the interference signal on the 2 C communication bus is connected to the data transmission pins (clock pin and data pin) of the memory 100 through the I2C communication bus, and the software data of the memory 100 is rewritten. When the display device needs to update the program, the interference signal absorption circuit 20 does not work, the host computer communicates with the memory 100 normally, and the
  • the memory write protection circuit of the present application is provided with a write protection control circuit 10 and connected to the write protection pin WP of the memory 100, so that when the memory 100 works normally, a write control signal is input to the write protection pin WP of the memory 100; and data write
  • the trigger terminal WP-I and the write protection trigger signal output terminal are respectively connected to the electrical connector and the write protection pin WP of the memory 100, so that when the data is updated in the memory 100, the accessed write protection trigger signal is output to the memory 100.
  • Write protection pin WP This application is also provided with an interference signal absorption circuit 20, and the input terminal of the interference signal absorption circuit 20 is connected to the data write trigger terminal WP-I to absorb I2C communication when the display device is powered on and works normally.
  • Interfering signals flowing into the bus to the data writing trigger terminal WP-I The present application addresses the write protection pin WP 100 foot level of the interference signal is pulled high memory, resulting in an interference signal on the I 2 C communication bus via I 2 C communication bus to a memory access data transfer pin (clock pin 100 And data pins), and rewriting the software data of the memory 100. It is possible to effectively prevent software data of the memory 100 from being rewritten.
  • the interference signal absorption circuit 20 is specifically configured to detect the data write trigger when receiving a first control signal indicating that the memory 100 works normally.
  • the WP-I receives the level signal, and when it is detected that the data write trigger terminal WP-I receives the first level signal, it absorbs the first level signal.
  • the circuit structure of the interference signal absorption circuit 20 may be specifically set according to the type of the signal to which the first control signal is connected.
  • the first control signal may be a low-level second-level signal, or may be a power signal.
  • the write protection control circuit 10 when the first control signal is a low-level second-level signal, the memory 100 is powered on to work, or during normal operation, the write protection control circuit 10 outputs a low-level second electric power. Tie the signal to the write-protect pin WP to keep the memory 100 in a write-protected state. At the same time, the second level signal will be output to the interference signal absorption circuit 20 to control the interference absorption circuit from operating.
  • the interference signal absorption circuit 20 includes a first switching transistor Q1 and a first resistor R1. An input terminal of the first switching transistor Q1 and the data writing trigger terminal WP-I and a first of the first resistor R1. Terminals are interconnected, a second terminal of the first resistor R1 is connected to a controlled terminal of the first electronic switch, and an output terminal of the first switch Q1 is grounded.
  • the first switching transistor Q1 may be implemented by using a switching transistor such as a triode or a MOS transistor. This embodiment may optionally be implemented by using an N-MOS transistor.
  • the resistance of the first resistor R1 can be set to 0 ohms, and the first resistor R1 is used to provide a bias voltage for the N-MOS tube.
  • a noise signal such as a high-level surge signal, enters from the data write trigger terminal WP-I
  • the first resistor R1 provides a bias voltage for the N-MOS tube, and the N-MOS tube turns on.
  • VCS VVS>0
  • the interference signal is output to the ground through the N-MOS tube without causing the write protection pin WP of the memory 100 to be in a high state, and at this time, the write protection control circuit 10 maintains a low level output, The write protection pin WP of the memory 100 is maintained at a low level, that is, the write protection state is maintained, so that the memory 100 cannot write code.
  • the memory write protection circuit when the first control signal is a high-level power signal, the memory write protection circuit further includes a power input terminal VCC, and the controlled terminal of the interference signal absorption circuit 20 is connected to the power input terminal VCC.
  • the power input VCC can be connected to the power supply of the memory 100, such as 3.
  • the interference signal absorption circuit 20 receives the power supply and starts to work, and absorbs the high-level first-level signal received by its input end.
  • the interference signal absorption circuit 20 includes a second switch Q2 and a second resistor R2. An input terminal of the second switch Q2 is connected to the data write trigger terminal WP-I. The controlled terminal is connected to the power input terminal VCC through the second resistor R2, and the output terminal of the second switching tube Q2 is grounded.
  • the second switching transistor Q2 may be implemented by using a switching transistor such as a triode or a MOS transistor. This embodiment may optionally be implemented by using an N-MOS transistor.
  • the second resistor R2 is a current-limiting resistor, and is used to prevent the controlled terminal current output to the second switch Q2 from being too large and damaging the switch.
  • the power input terminal VCC is used to access a control signal to control the second switch Q2 to be turned on.
  • the power input terminal VCC can be connected in parallel with the power input terminal VCC of the memory 100 to access the power supply of the memory 100, such as 3.
  • the second switching tube Q2 With a 3V DC power supply, the second switching tube Q2 is turned on after the display device is powered on, thereby short-circuiting the data writing trigger terminal WP-I to ground. This is set so that when an interference signal enters from the data write trigger terminal WP-I, it can be output to the ground through the N-MOS tube without causing the write protection pin WP of the memory 100 to be in a high state, and, At this time, the write protection control circuit 10 maintains a low-level output to maintain the write-protection pin WP of the memory 100 at a low level, that is, to maintain a write-protected state, so that the memory 100 cannot write code.
  • the memory write protection circuit further includes a current limiting element (not shown in the figure), and the current limiting element is disposed in series at the data write trigger terminal WP-I. And the write protection pin WP of the memory 100.
  • the current limiting element may be implemented by using an element that can limit current, such as an inductor or a resistor.
  • This embodiment may be selected as a third resistor R3, and the third resistor R3 is arranged in series on the data write trigger.
  • the terminal WP-I is between the write protection pin WP of the memory 100.
  • the third resistor R3 is a pull-up resistor, which is used to connect to the host computer through the I2C communication bus and electrical connector at the data write trigger terminal WP-I, and access a high-level write protection trigger signal to When the write protection pin WP of the memory 100 is ensured, a high-level signal can be output to the write protection pin WP to trigger the memory 100 to enter a writable state.
  • the write protection control circuit 10 includes a fourth resistor R4, and the fourth resistor R4 is connected in series between the write protection pin WP of the memory 100 and the ground.
  • the ratio of the resistance values of the third resistor R3 and the fourth resistor R4 is 1:12 to 1: 6.
  • the third resistor R3 and the fourth resistor R4 divide the voltage in series, so that the data write trigger terminal WP-I is connected to the upper computer through the I 2 C communication bus and electrical connector, and is connected in parallel.
  • the write protection pin WP of the memory 100 needs to be guaranteed to be high, and the power supply voltage of the memory 100 is generally 3.3 V, so the write protection trigger signal generally needs to be set to 2.7-3.6V.
  • the memory 100 reads the voltage signal as a high-level signal.
  • the voltage of the electrical connector is generally 3.3V. After this voltage is divided in series by the third resistor R3 and the fourth resistor R4, it is necessary to ensure that the write protection pin WP of the memory 100 is maintained at a voltage of 2.7-3.6V.
  • the third resistor R3 and the fourth resistor R4 can be divided to write the protection pin after voltage division.
  • the actual WP voltage is still high.
  • the ratio of the resistance values of the third resistor R3 and the fourth resistor R4 in this embodiment may be 1:10.
  • the present application also proposes a display device including the memory write protection circuit as described above.
  • the memory write protection circuit For the detailed structure of the memory write protection circuit, reference may be made to the foregoing embodiment, and details are not described herein again. It can be understood that, because the memory write protection circuit is used in the display device of the present application, embodiments of the display device of the present application include All the technical solutions of all the embodiments of the memory write protection circuit described above, and the technical effects achieved are also completely the same, and are not repeated here.

Abstract

一种存储器写保护电路及显示装置，包括干扰信号吸收电路（20），与数据写入触发端（WP-I）连接，在检测到数据写入触发端（WP-I）接收到第一电平信号时，将第一电平信号进行吸收。

Description

存储器写保护电路及显示装置
技术领域
本申请涉及电子电路技术领域，特别涉及一种存储器写保护电路及显示装置。
背景技术
显示装置中，时序控制器TCON IC（Timing Controller Integrated Circuit）内部静态只读存储器SROM（Static Read Only Memory）里的数据一般在掉电之后不能保存，而可擦除存储器EEPROM（Electrically Erasable Programmable read only memory）或闪存存储器Flash里存储的数据即使掉电之后也能保存，所以会将时序控制器的控制程序储存在外部存储器EEPROM或Flash中。
存储器的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。然而，存储器的写保护脚是与通讯总线连接的，通讯总线上的干扰信号可能会导致存储器的写保护脚信号被拉高，而使存储器的数据被改写。
申请内容
本申请的主要目的是提出一种存储器写保护电路及显示装置，旨在防止存储器的软体数据被改写。
为实现上述目的，本申请提出一种存储器写保护电路，所述存储器写保护电路包括：
数据写入触发端，所述数据写入触发端与存储器的写保护脚连接，被配置为接收控制存储器进入写入状态的第一电平信号；
写保护控制电路，与存储器的写保护脚连接，被设置为提供限制存储器被写入数据的第二电平信号至存储器的写保护脚；所述第二电平信号与第一电平信号的极性相反；
干扰信号吸收电路，与所述数据写入触发端连接，被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
可选地，所述干扰信号吸收电路，具体设置为在接收到表征存储器正常工作的第一控制信号时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
可选地，所述干扰信号吸收电路包括第一开关管及第一电阻，所述第一开关管的输入端与所述数据写入触发端及所述第一电阻的第一端互连，所述第一电阻的第二端与所述第一电子开关的受控端连接，所述第一开关管的输出端接地。
可选地，所述第一开关管为N-MOS管。
可选地，所述存储器写保护电路还包括电源输入端，所述干扰信号吸收电路包括第二开关管及第二电阻，所述第二开关管的输入端与所述数据写入触发端连接，所述第二开关管的受控端经所述第二电阻与所述电源输入端连接，所述第二开关管的输出端接地。
可选地，所述电源输入端VCC与所述存储器的电源输入端并联，以接入所述存储器的供电电源。
可选地，所述第二开关管为N-MOS管。
可选地，所述存储器写保护电路还包括限流元件，所述限流元件串联设置于所述数据写入触发端与存储器的写保护脚之间。
可选地，所述限流元件为第三电阻，所述第三电阻串联设置于所述数据写入触发端与存储器的写保护脚之间。
可选地，所述写保护控制电路包括第四电阻，所述第四电阻串联设置于存储器的写保护脚与地之间。
可选地，所述第三电阻和第四电阻串联设置。
可选地，所述第三电阻和所述第四电阻，设置为在所述数据写入触发端通过I2C通讯总线及电连接器与上位机连接，并接入高电平的写保护触发信号至所述存储器的写保护脚时，控制高电平信号输出至写保护脚而触发所述存储器进入可写入状态。
可选地，所述第三电阻和所述第四电阻的阻值之比为1:12~1:6。
可选地，所述第三电阻和所述第四电阻的阻值之比设置为1:10。
本申请还提出一种存储器写保护电路，所述存储器写保护电路包括：
第一电阻，与存储器的写保护脚连接，被设置为在存储器正常工作时，输入低电平的写控制信号至存储器的写保护脚；
数据写入触发端，与存储器的写保护脚连接，被设置为在存储器进行数据更新时，将接入的高电平的写保护触发信号输出至存储器的写保护脚；
干扰信号吸收电路，与所述数据写入触发端连接，
被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
本申请还提出一种显示装置，包括如上项所述的存储器写保护电路；所述存储器写保护电路包括：
数据写入触发端，所述数据写入触发端与存储器的写保护脚连接，被配置为接收控制存储器进入写入状态的第一电平信号；
写保护控制电路，与存储器的写保护脚连接，被设置为提供限制存储器被写入数据的第二电平信号至存储器的写保护脚；所述第二电平信号与第一电平信号的极性相反；
干扰信号吸收电路，与所述数据写入触发端连接，被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
可选地，所述显示装置还包括I2C（Inter-Integrated Circuit）通讯总线及时序控制器，所述存储器通过I2 C通讯总线与时序控制器连接。
可选地，所述显示装置还包括显示面板、源极驱动集成电路及栅极驱动集成电路，所述时序控制器分别与所述源极驱动集成电路及所述栅极驱动集成电路连接，所述所述源极驱动集成电路及所述栅极驱动集成电路还与所述显示面板。
可选地，所述干扰信号吸收电路，具体设置为在接收到表征存储器正常工作的第一控制信号时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收.
可选地，所述存储器写保护电路还包括电源输入端，所述干扰信号吸收电路包括第二开关管及第二电阻，所述第二开关管的输入端与所述数据写入触发端连接，所述第二开关管的受控端经所述第二电阻与所述电源输入端连接，所述第二开关管的输出端接地。
本申请存储器写保护电路通过设置写保护控制电路，并与存储器的写保护脚连接，以为在存储器正常工作时，输入写控制信号至存储器的写保护脚；以及数据写入触发端及写保护触发信号输出端，分别与电连接器和存储器的写保护脚连接，从而在存储器进行数据更新时，将接入的写保护触发信号输出至存储器的写保护脚；本申请还设置有，干扰信号吸收电路，其的入端与数据写入触发端连接，以在显示装置上电以及正常工作时，吸收I2 C（Inter-Integrated Circuit）通讯总线上窜入至数据写入触发端的干扰信号。本申请解决了存储器脚的写保护脚的电平被干扰信号拉高，导致I2 C通讯总线上的干扰信号通过I2C通讯总线的接入至存储器的数据传输脚（时钟脚及数据脚），并对存储器的软体数据进行改写的问题。本申请可以有效地防止存储器的软体数据被改写。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请存储器写保护电路一实施例的功能结构示意图；
图2为本申请存储器写保护电路一实施例的结构示意图；
图3为本申请存储器写保护电路另一实施例的结构示意图。
附图标号说明：
标号 名称 标号 名称
WP-I 数据写入触发端 R1~R4 第一电阻~第四电阻
100 存储器 WP 写保护脚
10 写保护控制电路 Q1 第一开关管
20 干扰信号吸收电路 Q2 第二开关管
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种存储器写保护电路，适用于电视机、手机、电脑等具有显示面板的显示装置中。
参照图1至图3，在本申请一实施例中，该存储器写保护电路包括：
数据写入触发端WP-I，所述数据写入触发端WP-I与存储器100的写保护脚WP连接，被配置为接收控制存储器100进入写入状态的第一电平信号；
写保护控制电路10，与存储器100的写保护脚WP连接，被设置为提供限制存储器100被写入数据的第二电平信号至存储器100的写保护脚WP；所述第二电平信号与第一电平信号的极性相反；
干扰信号吸收电路20，与所述数据写入触发端WP-I连接，被设置为在存储器100正常工作时，检测所述数据写入触发端WP-I接收的电平信号，并在检测到所述数据写入触发端WP-I接收到第一电平信号时，将第一电平信号进行吸收。
本实施例中，第一电平信号可以是高电平，第二电平信号则被配置为低电平，或者第一电平信号被配置为低电平，第二电平信号则被配置为高电平。
存储器100可以设置于时序控制（Timing Controller，TCON）PCB板上，存储器100可以存储用于驱动栅极驱动集成电路和源极驱动集成电路工作的控制信号，并通过I2C（Inter-Integrated Circuit）通讯总线与时序控制器通讯连接，在显示装置上电工作时，时序控制器读取存储器100里的控制信号，及其他设定数据进行初始设置，以产生对应的时序控制信号，从而驱动显示装置中的显示面板的源极驱动集成电路及栅极驱动集成电路工作。存储器100的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。因此，存储器100大多设置写保护引脚（WP pin），并在输入高电平时，可以控制存储器100写入数据，而在低电平时，不能写入数据，而对存储器100进行写保护。因此，本实施例中，在存储器100正常工作的过程中，提供限制存储器100被写入数据的第二电平信号至存储器100的写保护脚WP，以对存储器100进行写保护。
需要说明的是，写保护一般是通过在写保护与地之间串联一个电阻，以在显示装置正常工作的情况下，存储器100都不会被改写数据。在显示装置进行程序烧录或者程更新时，存储器100的写保护脚WP、时钟脚及数据脚均通过I2C通讯总线及电连接器与上位机连接，并在写保护脚WP接收到上位机输入的高电平信号，从而将数据信号写入至存储器100，直至更新结束。然而，在程序更新结束之后，往往会有杂讯（高电平突波）串到写保护脚WP，当这个杂讯为高电平时，并且I2C总线也存在干扰信号，此时该干扰信号将存储器100误动作，而写入该干扰信号的数据，导致存储器100存储的软体数据code被改写。
为了解决上述问题，本实施例存储器写保护电路可以设置于显示装置的主控板上，并对显示装置中的存储器100进行写保护，以防止存储器100中存储的程序，也即软体数据code被篡改。
其中，数据写入触发端WP-I通过I2C通讯总线与显示装置中的电连接器连接，在显示装置进行程序烧录或者程序更新时，数据写入触发端WP-I过I2C通讯总线及电连接器与上位机连接，以接入高电平的写保护触发信号至存储器100的写保护脚WP，此时上位机可以通过显示装置中的电连接器以及I2C通讯总线与存储器100通讯连接，从而对存储器100的软体数据进行改写。
写保护控制电路10与存储器100的写保护脚WP连接，也即与写保护触发信号输出端并联，以在显示装置正常工作时，输出低电平的第二电平信号至存储器100的写保护脚WP，也即，存储器100脚的写保护脚WP的电平被写保护控制电路10拉低，以保证在显示装置上电以及正常工作时，存储器100内的软体数据不被改写，从而对存储器100进行写保护。
干扰信号吸收电路20的输入端与数据写入触发端WP-I连接，在显示装置上电以及正常工作时，存储器100的写保护脚WP被低电平钳制，而进行写保护的。若干扰信号吸收电路20在存储器100正常工作的过程中，检测到数据写入触发端WP-I接收到高电平的第一电平信号时，则可以判定该第一电平信号为高电平的干扰信号，并吸收自I2C通讯总线上窜入至数据写入触发端WP-I的干扰信号，从而避免存储器100脚的写保护脚WP的电平被干扰信号拉高，导致I2 C通讯总线上的干扰信号通过I2C通讯总线的接入至存储器100的数据传输脚（时钟脚及数据脚），并对存储器100的软体数据进行改写。在显示装置需要进行程序更新时，干扰信号吸收电路20不工作，上位机与存储器100正常通讯，并完成存储器100的软体数据写入。
本申请存储器写保护电路通过设置写保护控制电路10，并与存储器100的写保护脚WP连接，以为在存储器100正常工作时，输入写控制信号至存储器100的写保护脚WP；以及数据写入触发端WP-I及写保护触发信号输出端，分别与电连接器和存储器100的写保护脚WP连接，从而在存储器100进行数据更新时，将接入的写保护触发信号输出至存储器100的写保护脚WP；本申请还设置有，干扰信号吸收电路20，干扰信号吸收电路20的输入端与数据写入触发端WP-I连接，以在显示装置上电以及正常工作时，吸收I2C通讯总线上窜入至数据写入触发端WP-I的干扰信号。本申请解决了存储器100脚的写保护脚WP的电平被干扰信号拉高，导致I2 C通讯总线上的干扰信号通过I2 C通讯总线的接入至存储器100的数据传输脚（时钟脚及数据脚），并对存储器100的软体数据进行改写的问题。可以有效地防止存储器100的软体数据被改写。
参照图1至图3，在一可选实施例中，在所述干扰信号吸收电路20具体配置为：在接收到表征存储器100正常工作的第一控制信号时，检测所述数据写入触发端WP-I接收的电平信号，并在检测到所述数据写入触发端WP-I接收到第一电平信号时，将第一电平信号进行吸收。
本实施例中，干扰信号吸收电路20的电路结构具体可以根据第一控制信号接入的信号类型进行设置。第一控制信号可以是低电平的第二电平信号，也可以是电源信号。
参照图1及图2，在第一控制信号为低电平的第二电平信号时，在存储器100上电工作，或者在正常工作时，写保护控制电路10输出低电平的第二电平信号至写保护脚WP，以使存储器100维持写保护状态。同时该第二电平信号将输出至干扰信号吸收电路20，以控制干扰吸收电路不动作。
所述干扰信号吸收电路20包括第一开关管Q1及第一电阻R1，所述第一开关管Q1的输入端与所述数据写入触发端WP-I及所述第一电阻R1的第一端互连，所述第一电阻R1的第二端与所述第一电子开关的受控端连接，所述第一开关管Q1的输出端接地。
本实施例中，第一开关管Q1可以采用三极管、MOS管等开关管来实现，本实施例可选采用N-MOS管来实现。第一电阻R1的阻值可设置为0欧姆，第一电阻R1用于为N-MOS管提供偏置电压。在显示装置正常工作时，电连接器以及I2 C通讯总线上是无电压输入的，也即数据写入触发端WP-I无信号输入，此时写保护控制电路10输出低电平的写保护信号至存储器100的写保护脚WP，以使存储器100维持写保护状态，该低电平的第二电平信号输出至N-MOS管的栅极，从而使N-MOS管处于截止状态（VGS=0）。当有杂讯杂波信号，例如高电平突波信号，从数据写入触发端WP-I窜入时，第一电阻R1为N-MOS管提供偏置电压，而使N-MOS管导通（VGS>0）；干扰信号经N-MOS管输出到地，而不会使存储器100的写保护脚WP处于高电平状态，并且，此时写保护控制电路10维持低电平输出，以将存储器100的写保护脚WP维持低电平，也即维持写保护状态，从而使存储器100无法写入code。
参照图1及图3，在第一控制信号为高电平的电源信号时，所述存储器写保护电路还包括电源输入端VCC，干扰信号吸收电路20的受控端与电源输入端VCC连接，该电源输入端VCC可以接入存储器100的供电电源，例如3. 3V的直流电源，并在存储器100上电工作时，干扰信号吸收电路20接收到该供电电源开始工作，并将其输入端接收到的高电平的第一电平信号，也即进行吸收。
所述干扰信号吸收电路20包括第二开关管Q2及第二电阻R2，所述第二开关管Q2的输入端与所述数据写入触发端WP-I连接，所述第二开关管Q2的受控端经所述第二电阻R2与所述电源输入端VCC连接，所述第二开关管Q2的输出端接地。
本实施例中，第二开关管Q2可以采用三极管、MOS管等开关管来实现，本实施例可选采用N-MOS管来实现。第二电阻R2为限流电阻，用于防止输出至第二开关管Q2的受控端电流过大而损坏开关管。电源输入端VCC用于接入控制信号，以控制第二开关管Q2开启，电源输入端VCC可以与存储器100的电源输入端VCC并联，从而接入存储器100的供电电源，例如3. 3V的直流电源，第二开关管Q2在显示装置上电工作后导通，从而将数据写入触发端WP-I与地短接。如此设置，使得当有干扰信号从数据写入触发端WP-I窜入时，可以经N-MOS管输出到地，而不会使存储器100的写保护脚WP处于高电平状态，并且，此时写保护控制电路10维持低电平输出，以将存储器100的写保护脚WP维持低电平，也即维持写保护状态，从而使存储器100无法写入code。
参照图1至图3，在一可选实施例中，所述存储器写保护电路还包括限流元件（图未标示），所述限流元件串联设置于所述数据写入触发端WP-I与存储器100的写保护脚WP之间。
上述实施例中，所述限流元件可以采用电感、电阻等可以限制电流的元件来实现，本实施例可选为第三电阻R3，所述第三电阻R3串联设置于所述数据写入触发端WP-I与存储器100的写保护脚WP之间。本实施例中，第三电阻R3为上拉电阻，用于在数据写入触发端WP-I过I2C通讯总线及电连接器与上位机连接，并接入高电平的写保护触发信号至存储器100的写保护脚WP时，保证高电平信号能够输出至写保护脚WP而触发存储器100进入可写入状态。
参照图1至图3，在一可选实施例中，所述写保护控制电路10包括第四电阻R4，所述第四电阻R4串联设置于存储器100的写保护脚WP与地之间。
进一步地，上述实施例中，所述第三电阻R3和所述第四电阻R4的阻值之比为1:12~1:6。本实施例中，可以理解的是，第三电阻R3和第四电阻R4串联分压，以使数据写入触发端WP-I过I2 C通讯总线及电连接器与上位机连接，并接入高电平的写保护触发信号至存储器100的写保护脚WP时，保证高电平信号能够输出至写保护脚WP而触发存储器100进入可写入状态。
需要说明的是，当需要对存储器100的程序进行更新时，也即需要将code写入存储器100使，存储器100的写保护脚WP需要保证为高电平，而存储器100的供电电压一般为3.3V，因此写保护触发信号一般需要设置为2.7-3.6V，此时存储器100才读取该电压信号为高电平信号。电连接器接入的电压一般为3.3V，该电压经第三电阻R3和第四电阻R4串联分压后需要保证存储器100的写保护脚WP接入的维持在电压2.7-3.6V，本实施例中，根据分压原理，当第三电阻R3和第四电阻R4的阻值之比设置为1:12~1:6时，可以第三电阻R3和第四电阻R4分压后写保护脚WP实际电压还是为高电平。本实施例第三电阻R3和第四电阻R4的阻值之比可选为1:10。
本申请还提出一种显示装置，其中，包括如上所述的存储器写保护电路。该存储器写保护电路的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请显示装置中使用了上述存储器写保护电路，因此，本申请显示装置的实施例包括上述存储器写保护电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种存储器写保护电路，其中，所述存储器写保护电路包括：
    数据写入触发端，所述数据写入触发端与存储器的写保护脚连接，被配置为接收控制存储器进入写入状态的第一电平信号；
    写保护控制电路，与存储器的写保护脚连接，被设置为提供限制存储器被写入数据的第二电平信号至存储器的写保护脚；所述第二电平信号与第一电平信号的极性相反；
    干扰信号吸收电路，与所述数据写入触发端连接，被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
  2. 如权利要求1所述的存储器写保护电路，其中，所述干扰信号吸收电路，具体设置为在接收到表征存储器正常工作的第一控制信号时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
  3. 如权利要求2所述的存储器写保护电路，其中，所述干扰信号吸收电路包括第一开关管及第一电阻，所述第一开关管的输入端与所述数据写入触发端及所述第一电阻的第一端互连，所述第一电阻的第二端与所述第一电子开关的受控端连接，所述第一开关管的输出端接地。
  4. 如权利要求3所述的存储器写保护电路，其中，所述第一开关管为N-MOS管。
  5. 如权利要求2所述的存储器写保护电路，其中，所述存储器写保护电路还包括电源输入端，所述干扰信号吸收电路包括第二开关管及第二电阻，所述第二开关管的输入端与所述数据写入触发端连接，所述第二开关管的受控端经所述第二电阻与所述电源输入端连接，所述第二开关管的输出端接地。
  6. 如权利要求5所述的存储器写保护电路，其中，所述电源输入端VCC与所述存储器的电源输入端并联，以接入所述存储器的供电电源。
  7. 如权利要求5所述的存储器写保护电路，其中，所述第二开关管为N-MOS管。
  8. 如权利要求1所述的存储器写保护电路，其中，所述存储器写保护电路还包括限流元件，所述限流元件串联设置于所述数据写入触发端与存储器的写保护脚之间。
  9. 如权利要求8所述的存储器写保护电路，其中，所述限流元件为第三电阻，所述第三电阻串联设置于所述数据写入触发端与存储器的写保护脚之间。
  10. 如权利要求9所述的存储器写保护电路，其中，所述写保护控制电路包括第四电阻，所述第四电阻串联设置于存储器的写保护脚与地之间。
  11. 如权利要求10所述的存储器写保护电路，其中，所述第三电阻和第四电阻串联设置。
  12. 如权利要求10所述的存储器写保护电路，其中，所述第三电阻和所述第四电阻，设置为在所述数据写入触发端通过I2 C通讯总线及电连接器与上位机连接，并接入高电平的写保护触发信号至所述存储器的写保护脚时，控制高电平信号输出至写保护脚而触发所述存储器进入可写入状态。
  13. 如权利要求10所述的存储器写保护电路，其中，所述第三电阻和所述第四电阻的阻值之比为1:12~1:6。
  14. 如权利要求11所述的存储器写保护电路，其中，所述第三电阻和所述第四电阻的阻值之比设置为1:10。
  15. 一种存储器写保护电路，其中，所述存储器写保护电路包括：
    第一电阻，与存储器的写保护脚连接，被设置为在存储器正常工作时，输入低电平的写控制信号至存储器的写保护脚；
    数据写入触发端，与存储器的写保护脚连接，被设置为在存储器进行数据更新时，将接入的高电平的写保护触发信号输出至存储器的写保护脚；
    干扰信号吸收电路，与所述数据写入触发端连接，
    被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
  16. 一种显示装置，其中，包括如权利要求1所述的存储器写保护电路；
    所述存储器写保护电路包括：
    数据写入触发端，所述数据写入触发端与存储器的写保护脚连接，被配置为接收控制存储器进入写入状态的第一电平信号；
    写保护控制电路，与存储器的写保护脚连接，被设置为提供限制存储器被写入数据的第二电平信号至存储器的写保护脚；所述第二电平信号与第一电平信号的极性相反；
    干扰信号吸收电路，与所述数据写入触发端连接，被设置为在存储器正常工作时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收。
  17. 如权利要求16所述的显示装置，其中，所述显示装置还包括I2 C（Inter-Integrated Circuit）通讯总线及时序控制器，所述存储器通过I2 C通讯总线与时序控制器连接。
  18. 如权利要求17所述的显示装置，其中，所述显示装置还包括显示面板、源极驱动集成电路及栅极驱动集成电路，所述时序控制器分别与所述源极驱动集成电路及所述栅极驱动集成电路连接，所述所述源极驱动集成电路及所述栅极驱动集成电路还与所述显示面板。
  19. 如权利要求16所述的显示装置，其中，所述干扰信号吸收电路，具体设置为在接收到表征存储器正常工作的第一控制信号时，检测所述数据写入触发端接收的电平信号，并在检测到所述数据写入触发端接收到第一电平信号时，将第一电平信号进行吸收.
  20. 如权利要求19所述的显示装置，其中，所述存储器写保护电路还包括电源输入端，所述干扰信号吸收电路包括第二开关管及第二电阻，所述第二开关管的输入端与所述数据写入触发端连接，所述第二开关管的受控端经所述第二电阻与所述电源输入端连接，所述第二开关管的输出端接地。
PCT/CN2018/115778 2018-09-14 2018-11-16 存储器写保护电路及显示装置 WO2020052055A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN113218042A (zh) * 2021-04-29 2021-08-06 Tcl空调器(中山)有限公司 空调外机参数修改方法、装置、存储介质及空调系统
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2678275Y (zh) * 2003-12-26 2005-02-09 深圳创维－Rgb电子有限公司 一种电视机存储器的写保护装置
CN201117293Y (zh) * 2007-11-16 2008-09-17 青岛海信电器股份有限公司 存储器写保护电路及具有所述电路的电视机
CN102446141A (zh) * 2011-09-14 2012-05-09 杭州华三通信技术有限公司 用于实现写保护控制的装置和方法
CN106463157A (zh) * 2016-06-15 2017-02-22 深圳市锐明技术股份有限公司 一种存储器的电磁干扰保护电路及车载电子设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101089997A (zh) * 2006-06-12 2007-12-19 景曙光 存储器电路
JP4706626B2 (ja) * 2006-11-30 2011-06-22 株式会社デンソー 電子制御装置
US9466385B1 (en) * 2012-10-17 2016-10-11 Google Inc. Methods and apparatus related to a write protect fastener
JP2018014050A (ja) * 2016-07-22 2018-01-25 東芝メモリ株式会社 メモリシステム
KR20180071675A (ko) * 2016-12-20 2018-06-28 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
CN106971108A (zh) * 2017-03-20 2017-07-21 郑州云海信息技术有限公司 一种在线更新bios的rom写保护的系统及方法
CN207182913U (zh) * 2017-07-06 2018-04-03 深圳市英蓓特科技有限公司 NAND Flash数据保护电路
TWI676993B (zh) * 2019-04-19 2019-11-11 宜鼎國際股份有限公司 寫入保護電路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2678275Y (zh) * 2003-12-26 2005-02-09 深圳创维－Rgb电子有限公司 一种电视机存储器的写保护装置
CN201117293Y (zh) * 2007-11-16 2008-09-17 青岛海信电器股份有限公司 存储器写保护电路及具有所述电路的电视机
CN102446141A (zh) * 2011-09-14 2012-05-09 杭州华三通信技术有限公司 用于实现写保护控制的装置和方法
CN106463157A (zh) * 2016-06-15 2017-02-22 深圳市锐明技术股份有限公司 一种存储器的电磁干扰保护电路及车载电子设备

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