WO2020093529A1 - 显示面板中存储器的保护电路及显示面板 - Google Patents

显示面板中存储器的保护电路及显示面板 Download PDF

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Publication number
WO2020093529A1
WO2020093529A1 PCT/CN2018/121831 CN2018121831W WO2020093529A1 WO 2020093529 A1 WO2020093529 A1 WO 2020093529A1 CN 2018121831 W CN2018121831 W CN 2018121831W WO 2020093529 A1 WO2020093529 A1 WO 2020093529A1
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WO
WIPO (PCT)
Prior art keywords
memory
circuit
display panel
switch
power supply
Prior art date
Application number
PCT/CN2018/121831
Other languages
English (en)
French (fr)
Inventor
何怀亮
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/398,307 priority Critical patent/US11322187B2/en
Publication of WO2020093529A1 publication Critical patent/WO2020093529A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers

Definitions

  • the present application relates to the technical field of display panels, and in particular to a protection circuit for a memory in a display panel and a display panel.
  • the timing controller and the memory are connected to each other through a serial communication unit, such as an I2C bus, for data transmission.
  • the timing controller will read the software data of the timing controller stored in the memory (such as output enable signal OE, latch signal TP, frame start signal STV, polarity) through the serial communication unit Reverse the signal POL) to complete the initial setting of the timing controller, and then control the display panel drive circuit to drive the display panel to work.
  • the read and write of the timing controller is controlled by the signal WP provided by the computer.
  • WP is the write protection signal of the memory. The read operation is performed when WP is high, and the read and write operation is performed when WP is low. Protection state, that is, WP has to be high level H in normal state.
  • the problem that is more likely to occur now is that the writing of software data into the memory is generally completed in the printing factory after the PCBA is printed. Then in the panel factory, after the binding point is completed, the power-on test is performed. At this time, because the WP is high, the read operation is performed, but once the WP is interfered and pulled down, the read and write operation will be performed. If the read-write bit on the SDA data line is encountered again because of line length and high frequency, etc., it is written during memory recognition, which will cause the software data in the memory to be rewritten. When the timing controller reads the rewritten software data, it may cause a reading error, fail to complete the initial setting of the timing controller, or even cause an abnormal display when driving the display panel.
  • the main purpose of the present application is to provide a protection circuit for memory in a display panel, which aims to reduce the chance of software data being rewritten in the display panel.
  • the protection circuit for memory in the display panel includes:
  • Timing controller with signal transmission end and write control signal output end
  • the memory has a signal transmission end and a write protection signal control end, the signal transmission end of the memory is connected to the signal transmission end of the timing controller; the memory is used to store software data of the timing controller;
  • a power supply circuit an output end of the power supply circuit is connected to the write protection signal control end, and the power supply circuit is used to output a write protection signal to the memory to limit the data of the memory to be rewritten;
  • a switch circuit the input end of the switch circuit is interconnected with the output end of the power supply circuit, the write protection signal control end, the output end of the switch circuit is grounded, the controlled end of the switch circuit and the write control Signal output connection;
  • the timing controller is used to control the switch circuit to be in a normally-off state, and to control the switch circuit to be turned on when receiving a data writing instruction to the memory.
  • the switch circuit includes a switch tube, the switch tube has a first connection terminal, a second connection terminal and a controlled terminal, and the first connection terminal of the switch tube is an input terminal of the switch circuit
  • the second connection terminal is the output terminal of the switch circuit
  • the controlled terminal of the switch tube is the controlled terminal of the switch circuit.
  • the switch tube is a P-type MOS tube
  • the source of the P-type MOS tube is the first connection end of the switch tube
  • the drain of the P-type MOS tube is the first Two connection ends
  • the gate of the P-type MOS tube is the controlled end of the switch tube.
  • the switch tube is an N-type MOS tube
  • the drain of the N-type MOS tube is the first connection end of the switch tube
  • the source of the N-type MOS tube is the first Two connection ends
  • the gate of the N-type MOS tube is the controlled end of the switch tube.
  • the protection circuit of the memory in the display panel further includes a first resistor, a first end of the first resistor is connected to an output end of the power supply circuit, and a second end of the first resistor is The input terminal of the switch circuit is connected to the common terminal of the write protection signal control terminal.
  • the timing controller is further configured to control the switch circuit to be turned off when receiving the feedback signal after the memory has finished writing data.
  • the memory is an electrically erasable programmable read-only memory.
  • the present application also provides a protection circuit for memory in a display panel.
  • the protection circuit for memory in the display panel includes:
  • Timing controller with signal transmission end and write control signal output end
  • the memory has a power supply terminal, a signal transmission terminal and a write protection signal control terminal, the signal transmission terminal of the memory is connected to the signal transmission terminal of the timing controller; the memory is used to store software data of the timing controller ;
  • a power supply circuit the output end of the power supply circuit is connected to the write protection signal control end, the power supply circuit is also connected to the power supply end of the memory; the power supply circuit is used to output a write protection signal to the memory, To limit the data in the memory to be rewritten;
  • a switch circuit the input end of the switch circuit is interconnected with the output end of the power supply circuit, the write protection signal control end, the output end of the switch circuit is grounded, the controlled end of the switch circuit and the write control Signal output connection;
  • the timing controller is used to control the switch circuit to be in a normally-off state, and to control the switch circuit to be turned on when receiving a data writing instruction to the memory.
  • the present application also proposes a display panel including the protection circuit of the memory in the above display panel, and the protection circuit of the memory in the above display panel includes:
  • Timing controller with signal transmission end and write control signal output end
  • the memory has a signal transmission end and a write protection signal control end, the signal transmission end of the memory is connected to the signal transmission end of the timing controller; the memory is used to store software data of the timing controller;
  • a power supply circuit an output end of the power supply circuit is connected to the write protection signal control end, and the power supply circuit is used to output a write protection signal to the memory to limit the data of the memory to be rewritten;
  • a switch circuit the input end of the switch circuit is interconnected with the output end of the power supply circuit, the write protection signal control end, the output end of the switch circuit is grounded, the controlled end of the switch circuit and the write control Signal output connection;
  • the timing controller is used to control the switch circuit to be in a normally-off state, and to control the switch circuit to be turned on when receiving a data writing instruction to the memory.
  • the memory further has a power terminal, and the power circuit is also connected to the power terminal of the memory.
  • the switch circuit includes a switch tube, the switch tube has a first connection terminal, a second connection terminal and a controlled terminal, and the first connection terminal of the switch tube is an input terminal of the switch circuit
  • the second connection terminal is the output terminal of the switch circuit
  • the controlled terminal of the switch tube is the controlled terminal of the switch circuit.
  • the switch tube is a P-type MOS tube
  • the source of the P-type MOS tube is the first connection end of the switch tube
  • the drain of the P-type MOS tube is the first Two connection ends
  • the gate of the P-type MOS tube is the controlled end of the switch tube.
  • the switch tube is an N-type MOS tube
  • the drain of the N-type MOS tube is the first connection end of the switch tube
  • the source of the N-type MOS tube is the first Two connection ends
  • the gate of the N-type MOS tube is the controlled end of the switch tube.
  • the protection circuit of the memory in the display panel further includes a first resistor, a first end of the first resistor is connected to an output end of the power supply circuit, and a second end of the first resistor is The input terminal of the switch circuit is connected to the common terminal of the write protection signal control terminal.
  • the timing controller is further configured to control the switch circuit to be turned off when receiving the feedback signal after the memory has finished writing data.
  • the memory is an electrically erasable programmable read-only memory.
  • the power supply circuit is a DC power supply.
  • the display panel is a liquid crystal display panel or an organic light emitting diode display panel or a field emission display panel or a plasma display panel or a curved type panel.
  • a protection circuit for the memory in the display panel is formed by setting a timing controller, a memory, a power circuit, and a switch circuit.
  • the original write protection signal WP is removed, and the power circuit outputs the write protection signal To the memory, to limit the data of the memory to be rewritten
  • the timing controller controls the switch circuit to be in a normally-off state, and only controls the switch circuit to be in a state of receiving a data write instruction to the memory In the on state, when the switch circuit is turned off, the power supply circuit is controlled to output a write protection signal to the write protection signal control terminal of the memory, and when the switch circuit is turned on, the write protection signal control terminal of the memory is connected to ground.
  • the write protection signal is output from the power circuit, it is stable and reliable, and is not easily affected by other circuits. Therefore, even if the read and write bits on the SDA data line are written during memory recognition due to line length and high frequency, it will not make the memory
  • the software data in is rewritten, that is to achieve the purpose of reducing the probability of the software data in the memory being rewritten.
  • FIG. 1 is a circuit functional block diagram of an embodiment of a protection circuit of a memory in a display panel of the present application
  • FIG. 2 is a schematic diagram of a circuit structure of an embodiment of a protection circuit of a memory in a display panel of the present application
  • FIG. 3 is a schematic diagram of a circuit structure of another embodiment of a protection circuit for a memory in a display panel of the present application.
  • first, second, etc. are for descriptive purposes only, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of those skilled in the art to realize. When the combination of technical solutions contradicts or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • the timing controller and the memory are connected to each other through a serial communication unit, such as an I2C bus (including SDA data lines and SCL clock lines), for data transmission.
  • a serial communication unit such as an I2C bus (including SDA data lines and SCL clock lines)
  • the timing controller will read the software data of the timing controller stored in the memory (such as output enable signal OE, latch signal TP, frame start signal STV, polarity) through the serial communication unit Reverse the signal POL) to complete the initial setting of the timing controller.
  • the reading and writing of the memory are controlled by the signal WP provided by the computer, WP is the write protection signal of the memory, the reading operation is performed when WP is high, and the reading and writing operation is performed when WP is low, and the memory should be in the write protection state in the normal state , That is, WP is always high level H under normal conditions.
  • WP is the write protection signal of the memory
  • the reading operation is performed when WP is high
  • the reading and writing operation is performed when WP is low
  • the memory should be in the write protection state in the normal state , That is, WP is always high level H under normal conditions.
  • the problem that is more likely to occur now is that the writing of software data into the memory is generally completed in the printing factory after the PCBA is printed. Then in the panel factory, after the binding point is completed, the power-on test is performed. At this time, because the WP is high, the read operation is performed, but once the WP is interfered and pulled down, the read and write operation will be performed.
  • the read-write bit on the SDA data line is encountered again because of line length and high frequency, etc., it is written during memory recognition, which will cause the software data in the memory to be rewritten.
  • the timing controller reads the rewritten software data, it may cause a reading error and the initialization setting of the timing controller cannot be completed.
  • various control signals used to drive the display panel cannot be output correctly, resulting in abnormal display screens and frequent errors.
  • the present application proposes a protection circuit for memory in a display panel.
  • the protection circuit for memory in a display panel includes a memory 100, a timing controller 200, a power circuit 300, and a switch Circuit 400.
  • the timing controller 200 has a signal transmission end and a write control signal output end, and the memory 100 has a signal transmission end and a write protection signal control end; the signal transmission end of the memory 100 is connected to the signal transmission end of the timing controller 200;
  • the output terminal of the power circuit 300 is connected to the write protection signal control terminal, the input terminal of the switch circuit 400 is connected to the output terminal of the power circuit 300 and the write protection signal control terminal, and the switch circuit 400 The output terminal is grounded, and the controlled terminal of the switch circuit 400 is connected to the write control signal output terminal.
  • the memory 100 may be an electrically erasable programmable read-only memory EEPROM, which can store data after power-off to prevent data loss.
  • the memory 100 is used to store the software data of the timing controller 200.
  • the timing controller 200 can read the software data of the memory 100 to complete the corresponding initial setting. After completing the corresponding initial setting, the timing controller 200 can output various control signals to drive the display panel to work.
  • the power supply circuit 300 may be a DC power supply or a DC power supply obtained by connecting an AC power supply and performing power conversion.
  • the power supply circuit 300 is used to output the write protection signal WP_O to the memory 100 to limit the data of the memory 100 to be rewritten.
  • the write protection signal WP_O is in principle a high level signal, so that the input signal of the write protection signal control terminal of the memory 100 is always high, which is equivalent to WP being always high, so that the memory 100 is always in the write protection state, The data is written so that the software data in the memory 100 can be prevented from being rewritten.
  • the switch circuit 400 has two states of off and on, which can be implemented by various transistors, such as MOS transistors, transistors, and other composite switch circuits 400 composed of multiple transistors.
  • the switch circuit 400 When the switch circuit 400 is turned off, the power supply circuit 300 outputs a write protection signal to the write protection signal control terminal of the memory 100, and when the switch circuit 400 is turned on, it connects the write protection signal control terminal of the memory 100 to ground.
  • the timing controller 200 is used to control the switch circuit 400 to be in a normally-off state, and to control the switch circuit 400 to be in an on state when receiving a data write instruction to the memory 100.
  • the power circuit 300 When the switch circuit 400 is in the normally-off state, the power circuit 300 outputs the write protection signal WP_O to the write protection signal control terminal of the memory 100 to restrict the memory 100 from being written with data, that is, the original write protection signal WP is removed, and this signal WP_O It is equivalent to the original write protection signal WP. Because this signal is output by the WP_O power circuit 300, it is stable and reliable, and is not easily affected by other signals or circuits. Therefore, even if the read and write bits on the SDA data line are due to line length and high frequency, etc.
  • the memory 100 is written when recognized, but due to the protection of the write protection signal WP_O, the software data in the memory 100 will not be rewritten, that is, the purpose of reducing the probability of the software data in the memory 100 being rewritten is achieved, and a switching circuit is adopted 400 to switch control, the circuit structure is simple and easy to implement.
  • the scrap rate is reduced, and further the production yield can be increased.
  • the memory 100 further has a power terminal, and the power circuit 300 is also connected to the power terminal of the memory 100.
  • the memory 100 is powered by the power supply circuit 300, and the operating voltage can be 3.3V.
  • the WP is high, it is also 3.3V, so that only one power supply can realize power supply and write protection control for the memory 100, so that even if the power supply fails.
  • the write protection signal WP_O output to the memory 100 becomes invalid, then the memory 100 also stops working due to the power failure. At this time, it is impossible to write data to the memory 100 regardless of the method used. Since the data of the memory 100 is rewritten, the anti-interference ability of the display panel is improved.
  • the switch circuit 400 is implemented with the following circuit structure.
  • the switch circuit 400 includes a switch tube, the switch tube has a first connection end, a second connection end, and a controlled end, and the first connection end of the switch tube It is the input end of the switch circuit 400, the second connection end is the output end of the switch circuit 400, and the controlled end of the switch tube is the controlled end of the switch circuit 400.
  • the on and off of the switch tube is controlled by the high and low signals output by the timing controller 200. If the switch is selected to be turned off when a high-level signal is received, and turned on when a low-level signal is received, then here, the timing controller 200 outputs a high-level signal in a normal state, so that the switch is in the off state, allowing The high level signal output by the power supply circuit 300 is given to the write protection signal control end of the memory 100, so that the memory 100 is in the write protection state, and when data is to be written to the memory 100, the timing controller 200 outputs a low level signal to control the switch When the tube is turned on, the signal at the control terminal of the write protection signal of the memory 100 is pulled down to release or release the write protection state of the memory 100.
  • the timing controller 200 If the switch is selected to be turned off when a low-level signal is received and turned on when a high-level signal is received, then here, the timing controller 200 outputs a low-level signal in a normal state so that the switch is in the off state, allowing The high level signal output by the power supply circuit 300 is given to the write protection signal control end of the memory 100, so that the memory 100 is in the write protection state, and when data is to be written to the memory 100, the timing controller 200 outputs a high level signal to control the switch When the tube is turned on, the signal at the control terminal of the write protection signal of the memory 100 is pulled down to release or release the write protection state of the memory 100.
  • the switch is used for switch control.
  • the response speed of the switch is fast, which can avoid response delay and cause protection failure.
  • the circuit structure is simple, and the implementation cost is lower than the cost of the composite switch.
  • the switch tube can be implemented by a triode or a MOS tube, which is not limited to specifics.
  • a MOS tube as an example to describe in detail.
  • the switch tube is a P-type MOS tube Q1
  • the source of the P-type MOS tube Q1 is the first connection end of the switch tube
  • the drain of the P-type MOS tube Q1 At the second connection end of the switch, the gate of the P-type MOS transistor Q1 is the controlled end of the switch.
  • the P-type MOS transistor Q1 is turned on when the gate receives a low-level signal (corresponding to the on state of the switch), and turned off when the high-level is received, that is, if the memory 100 is in the write-protected state, the timing
  • the signal TC output from the write control signal output terminal of the controller 200 needs to be set high to turn off the P-type MOS transistor Q1.
  • the signal TC output from the write control signal output terminal of the timing controller 200 needs to be set to low, so that the P-type MOS transistor Q1 is turned on.
  • the P-type MOS transistor Q1 is turned off, the high-level signal output by the power supply circuit 300 is given to the memory 100, so that the memory 100 is in a write-protected state, and when the P-type MOS transistor Q1 is turned on, the write-protected signal control terminal of the memory 100 WP_O is connected to ground, WP_O is low, the memory 100 can be written.
  • the switch is an N-type MOS transistor Q2
  • the drain of the N-type MOS transistor Q2 is the first connection end of the switch
  • the N-type MOS transistor Q2 The source electrode is the second connection end of the switch
  • the gate of the N-type MOS transistor Q2 is the controlled end of the switch.
  • the N-type MOS transistor Q2 is turned on when the gate receives a high level signal (corresponding to the on state of the switch), and turned off when the low level is received, that is to say, to make the memory 100 in the write protection state, the The signal TC output from the write control signal output terminal of the controller 200 needs to be set low to turn off the N-type MOS transistor Q2.
  • the signal TC output from the write control signal output terminal of the timing controller 200 is set to high, so that the N-type MOS transistor Q2 is turned on.
  • the N-type MOS transistor Q2 is turned off, the high-level signal output from the power supply circuit 300 is given to the memory 100, so that the memory 100 is in a write-protected state, and when the N-type MOS transistor Q2 is turned on, the write-protected signal control terminal of the memory 100 WP_O is connected to ground, WP_O is low, the memory 100 can be written.
  • the protection circuit of the memory in the display panel further includes a first resistor R1, a first end of the first resistor R1 is connected to the output end of the power supply circuit 300, and the first The second terminal of a resistor R1 is connected to the input terminal of the switch circuit 400 and the common terminal of the write protection signal control terminal.
  • the power supply circuit 300 is a DC power supply VDD
  • the first resistor R1 is a pull-up resistor of the memory 100, which can clamp the output signal to a high level even when the power supply signal output by the DC power supply VDD is abnormal.
  • the output is stable and reliable, avoiding the failure of the write protection signal WP_O.
  • the timing controller 200 is further configured to control the switch circuit 400 to be turned off when receiving a feedback signal after the memory 100 completes writing data. After the memory 100 finishes writing data, it will send a feedback or response signal to the timing controller 200. When the timing controller 200 receives the feedback or response signal, it will know that the memory 100 has finished writing data, and then control the switch The circuit 400 is turned off, which can not only put the memory 100 into a write-protected state but also prevent the first resistor R1 from consuming energy. It can be understood that, due to the existence of the first resistor R1, if the switch circuit 400 is still turned on after writing data to the memory 100, energy will be consumed through the first resistor R1, causing unnecessary losses. In the example, after writing data to the memory 100, the control switch circuit 400 is turned off, so this problem is well avoided.
  • the present application also provides a display panel including the above-mentioned protection circuit for the memory in the display panel. It can be understood that since the protection circuit for the memory in the display panel is used in the display panel, the display The embodiments of the panel include all the technical solutions of all the embodiments of the protection circuit of the memory in the display panel, and the technical effects achieved are also the same, which will not be repeated here.
  • the display panel includes but is not limited to a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, a curved panel, the liquid crystal panel includes a thin film transistor liquid crystal display panel, TN panel, VA type Panel, IPS panel, etc.
  • the present application also provides a display device including the above-mentioned display panel, and the display panel includes the above-mentioned protection circuit of the memory in the display panel, therefore, it also has all the embodiments of the above-mentioned display panel memory protection circuit All the technical solutions, and the technical effects achieved are also the same, which will not be repeated here.
  • the display device may be a general display or a flat-screen TV, and of course, it may also be a liquid crystal display or a liquid crystal TV.

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Abstract

本申请公开一种显示面板中存储器的保护电路及显示面板，该电路包括时序控制器、存储器、电源电路及开关电路，通过将原来由计算机提供的写保护信号被去除，由电源电路输出稳定、可靠地写保护信号至存储器，以限制存储器的数据被改写，时序控制器则仅在接收到对存储器进行数据写入的指令时，控制开关电路开启而将存储器的写保护信号控制端接到地。

Description

显示面板中存储器的保护电路及显示面板
相关申请
本申请要求2018年11月06日申请的，申请号为201811317750.6，名称为“显示面板中存储单元的保护电路、显示面板及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示面板技术领域，特别涉及一种显示面板中存储器的保护电路及显示面板。
背景技术
在显示面板中，时序控制器与存储器通过串行通信单元，例如I2C总线相互连接，以进行数据传输。在刚上电时，时序控制器内部会通过串行通信单元去读取存储器里面存储的时序控制器的软件数据（如输出使能信号OE、锁存信号TP、帧启始信号STV、极性反转信号POL），完成时序控制器的初始化设定，进而控制显示面板驱动电路驱动显示面板工作。其中，时序控制器的读写由计算机提供的信号WP进行控制，WP是存储器的写保护信号，WP为高时进行读操作，WP为低时进行读写操作，存储器正常状态下都要处于写保护状态，即正常状态下WP一直要为高电平H。
可是现在比较容易出现的问题是，软件数据写入存储器中一般是在电路板PCBA打件完成之后在打件厂内就已经完成。然后在面板厂内，在绑点完成之后，才进行上电测试，此时因为WP为高，进行的是读操作，但是一旦WP受到干扰而被拉低，就将进行读写操作，此时如果又遇到SDA数据线上的读写位由于线长和高频率等原因在存储器识别的时候为写，就会导致存储器中的软件数据被改写。当时序控制器读取被改写后的软件数据时，就可能会造成读取错误，不能完成时序控制器的初始化设定，甚至造成驱动显示面板时显示异常。
申请内容
本申请的主要目的是提供一种显示面板中存储器的保护电路，旨在降低显示面板中软件数据被改写的几率。
为实现上述目的，本申请提出一种显示面板中存储器的保护电路，该显示面板中存储器的保护电路包括：
时序控制器，具有信号传输端和写控制信号输出端；
存储器，具有信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
在一实施例中，所述开关电路包括开关管，所述开关管具有第一连接端、第二连接端及受控端，所述开关管的第一连接端为所述开关电路的输入端，所述第二连接端为所述开关电路的输出端，所述开关管的受控端为所述开关电路的受控端。
在一实施例中，所述开关管为P型MOS管，所述P型MOS管的源极为所述开关管的第一连接端，所述P型MOS管的漏极为所述开关管的第二连接端，所述P型MOS管的栅极为所述开关管的受控端。
在一实施例中，所述开关管为N型MOS管，所述N型MOS管的漏极为所述开关管的第一连接端，所述N型MOS管的源极为所述开关管的第二连接端，所述N型MOS管的栅极为所述开关管的受控端。
在一实施例中，所述显示面板中存储器的保护电路还包括第一电阻，所述第一电阻的第一端与所述电源电路的输出端连接，所述第一电阻的第二端与所述开关电路的输入端和所述写保护信号控制端的公共端连接。
在一实施例中，所述时序控制器还用于在接收到所述存储器完成数据写入后的反馈信号时，控制所述开关电路关断。
在一实施例中，所述存储器为电可擦可编程只读存储器。
为实现上述目的，本申请还提出一种显示面板中存储器的保护电路，所述显示面板中存储器的保护电路包括：
时序控制器，具有信号传输端和写控制信号输出端；
存储器，具有电源端、信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路还与所述存储器的电源端连接；所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
为实现上述目的，本申请还提出一种显示面板，所述显示面板包括上述显示面板中存储器的保护电路，上述显示面板中存储器的保护电路包括：
时序控制器，具有信号传输端和写控制信号输出端；
存储器，具有信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
在一实施例中，所述存储器还具有电源端，所述电源电路还与所述存储器的电源端连接。
在一实施例中，所述开关电路包括开关管，所述开关管具有第一连接端、第二连接端及受控端，所述开关管的第一连接端为所述开关电路的输入端，所述第二连接端为所述开关电路的输出端，所述开关管的受控端为所述开关电路的受控端。
在一实施例中，所述开关管为P型MOS管，所述P型MOS管的源极为所述开关管的第一连接端，所述P型MOS管的漏极为所述开关管的第二连接端，所述P型MOS管的栅极为所述开关管的受控端。
在一实施例中，所述开关管为N型MOS管，所述N型MOS管的漏极为所述开关管的第一连接端，所述N型MOS管的源极为所述开关管的第二连接端，所述N型MOS管的栅极为所述开关管的受控端。
在一实施例中，所述显示面板中存储器的保护电路还包括第一电阻，所述第一电阻的第一端与所述电源电路的输出端连接，所述第一电阻的第二端与所述开关电路的输入端和所述写保护信号控制端的公共端连接。
在一实施例中，所述时序控制器还用于在接收到所述存储器完成数据写入后的反馈信号时，控制所述开关电路关断。
在一实施例中，所述存储器为电可擦可编程只读存储器。
在一实施例中，所述电源电路为直流电源。
在一实施例中，所述显示面板为液晶显示面板或者有机发光二极管显示面板或者场发射显示面板或者等离子显示面板或者曲面型面板。
本申请技术方案，通过设置时序控制器、存储器、电源电路及开关电路等组成了显示面板中存储器的保护电路，该电路中，将原来的写保护信号WP被去除，由电源电路输出写保护信号至所述存储器，以限制所述存储器的数据被改写，时序控制器控制所述开关电路处于常关断状态，仅在接收到对所述存储器进行数据写入指令时，控制所述开关电路处于开启状态，开关电路则在关断时，控制电源电路输出写保护信号至存储器的写保护信号控制端，开关电路在开启时，将存储器的写保护信号控制端接到地。由于写保护信号为电源电路输出，稳定可靠，不易受到其他电路影响，因此，即使SDA数据线上的读写位因为线长和高频率等原因在存储器识别的时候为写，也不会使得存储器中的软件数据被改写，即实现了降低存储器中软件数据被改写的几率的目的。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板中存储器的保护电路一实施例的电路功能框图；
图2为本申请显示面板中存储器的保护电路一实施例的电路结构示意图；
图3为本申请显示面板中存储器的保护电路另一实施例的电路结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
在显示面板中，时序控制器与存储器通过串行通信单元，例如I2C总线（包括SDA数据线和SCL时钟线）相互连接，以进行数据传输。在刚上电时，时序控制器内部会通过串行通信单元去读取存储器里面存储的时序控制器的软件数据（如输出使能信号OE、锁存信号TP、帧启始信号STV、极性反转信号POL），完成时序控制器的初始化设定。其中，存储器的读写由计算机提供的信号WP进行控制，WP是存储器的写保护信号，WP为高时进行读操作，WP为低时进行读写操作，存储器正常状态下都要处于写保护状态，即正常状态下WP为一直要为高电平H。可是现在比较容易出现的问题是，软件数据写入存储器中一般是在电路板PCBA打件完成之后在打件厂内就已经完成。然后在面板厂内，在绑点完成之后，才进行上电测试，此时因为WP为高，进行的是读操作，但是一旦WP受到干扰而被拉低，就将进行读写操作，此时如果又遇到SDA数据线上的读写位由于线长和高频率等原因在存储器识别的时候为写，就会导致存储器中的软件数据被改写。当时序控制器读取被改写后的软件数据时，就可能会造成读取错误，不能完成时序控制器的初始化设定。进而导致不能正确输出用于驱动所述显示面板的各种控制信号，造成显示画面异常，错误频出，而现今并没有纠错机制，那么就无法防范这种情况。
针对上述问题，本申请提出一种显示面板中存储器的保护电路，参照图1，在本申请一实施例中，显示面板中存储器的保护电路包括存储器100、时序控制器200、电源电路300及开关电路400。
时序控制器200具有信号传输端和写控制信号输出端，存储器100具有信号传输端和写保护信号控制端；所述存储器100的信号传输端与所述时序控制器200的信号传输端连接；所述电源电路300的输出端与所述写保护信号控制端连接，所述开关电路400的输入端与述电源电路300的输出端、所述写保护信号控制端互相连接，所述开关电路400的输出端接地，所述开关电路400的受控端与所述写控制信号输出端连接。
本实施例中，存储器100可以是电可擦可编程只读存储器EEPROM，能够在掉电后存储数据，防止数据遗失。所述存储器100用于存储所述时序控制器200的软件数据，在读状态下时，时序控制器200可以读取存储器100的软件数据，完成相应的初始化设定。时序控制器200完成相应的初始化设定后就可以输出各种控制信号，驱动显示面板工作。
本实施例中，电源电路300可以是直流电源或者是为接入交流电源经电源变换后得到的直流电源。电源电路300用于输出写保护信号WP_O至所述存储器100，以限制所述存储器100的数据被改写。其中，写保护信号WP_O原则上为高电平信号，这样就可以使得存储器100的写保护信号控制端的输入信号一直为高，相当于WP一直为高，使得存储器100一直处于写保护状态，而不被写入数据，这样就可避免造成存储器100中的软件数据被改写。
本实施例中，开关电路400具有关断和开启两种状态，可以采用各种晶体管组成电路实现，例如MOS管、三极管、以及其他由多个晶体管组成的复合型开关电路400。其中，开关电路400在关断时，电源电路300输出写保护信号至存储器100的写保护信号控制端，开关电路400在开启时，将存储器100的写保护信号控制端接到地。
本实施例中，时序控制器200用于控制所述开关电路400处于常关断状态，在接收到对所述存储器100进行数据写入指令时，控制所述开关电路400处于开启状态。
当开关电路400处于常关断状态时，电源电路300输出写保护信号WP_O至存储器100的写保护信号控制端，限制存储器100被写入数据，即原来的写保护信号WP被去除，此信号WP_O相当于原来的写保护信号WP，由于此信号为WP_O电源电路300输出，稳定可靠，不易受到其他信号或电路影响，因此，即使SDA数据线上的读写位因为线长和高频率等原因在存储器100识别的时候为写，但是由于写保护信号WP_O的保护，也不会使得存储器100中的软件数据被改写，即实现了降低存储器100中软件数据被改写的几率的目的，并且采用开关电路400进行切换控制，电路结构简单、容易实现。另外，可以理解的是，由于存储器100的数据不会被改写，废品率降低，进而还能够增加生产良率。
进一步地，所述存储器100还具有电源端，所述电源电路300还与所述存储器100的电源端连接。本实施例中，存储器100采用电源电路300供电，工作电压可为3.3伏，WP为高时也是3.3V，这样只要一个电源即可实现给存储器100供电和写保护控制，这样即使电源出现故障造成掉电，导致输出至存储器100的写保护信号WP_O失效，那么存储器100也由于失电而停止工作，此时不管采用何种方式都不可能对存储器100进行数据写入，如此，便可靠的保护了存储器100的数据被改写，因此，提高了显示面板的抗干扰能力。
在一实施例中，开关电路400采用如下电路结构实现，开关电路400包括开关管，所述开关管具有第一连接端、第二连接端及受控端，所述开关管的第一连接端为所述开关电路400的输入端，所述第二连接端为所述开关电路400的输出端，所述开关管的受控端为所述开关电路400的受控端。
该实施例中，开关管的导通和关断由时序控制器200输出的高低信号进行控制。如果选择开关管为接收到高电平信号时关断，低电平信号时开启，则此处，时序控制器200在正常状态下，输出高电平信号，使开关管处于关断状态，让电源电路300输出的高电平信号给到存储器100的写保护信号控制端，使存储器100处于写保护状态，而要对存储器100写入数据时，则时序控制器200输出低电平信号控制开关管开启，拉低存储器100的写保护信号控制端的信号，以解除或者释放存储器100的写保护状态。如果选择开关管为接收到低电平信号时关断，高电平信号时开启，则此处，时序控制器200在正常状态下，输出低电平信号，使开关管处于关断状态，让电源电路300输出的高电平信号给到存储器100的写保护信号控制端，使存储器100处于写保护状态，而要对存储器100写入数据时，则时序控制器200输出高电平信号控制开关管开启，拉低存储器100的写保护信号控制端的信号，以解除或者释放存储器100的写保护状态。
该实施例中，采用开关管进行开关控制开关响应速度快，可以避免响应延迟，造成保护失效，并且，由于仅采用一个开关管实现，电路结构简单，实现成本相对复合型开关成本较低。
该实施例中，开关管可以采用三极管或者MOS管实现，具体不限，以下以MOS管为例详细说明。
在一实施例中，参照图2，所述开关管为P型MOS管Q1，所述P型MOS管Q1的源极为所述开关管的第一连接端，所述P型MOS管Q1的漏极为所述开关管的第二连接端，所述P型MOS管Q1的栅极为所述开关管的受控端。P型MOS管Q1为栅极接收到低电平信号时导通（对应开关管开启状态），接收到高电平时关断，也就是说，要让使存储器100处于写入保护状态，则时序控制器200的写控制信号输出端输出的信号TC需要设置为高，使P型MOS管Q1关断。若时序控制器200要对存储器100进行写操作，则时序控制器200的写控制信号输出端输出的信号TC需要设置为低，使P型MOS管Q1打开。当P型MOS管Q1关断时，电源电路300输出的高电平信号给到存储器100，使存储器100处于写保护状态，当P型MOS管Q1打开时，则存储器100的写保护信号控制端WP_O与地相接，WP_O为低，存储器100就可以被进行写操作。
在另一实施例中，参照图3，所述开关管为N型MOS管Q2，所述N型MOS管Q2的漏极为所述开关管的第一连接端，所述N型MOS管Q2的源极为所述开关管的第二连接端，所述N型MOS管Q2的栅极为所述开关管的受控端。N型MOS管Q2为栅极接收到高电平信号时导通（对应开关管开启状态），接收到低电平时关断，也就是说，要让使存储器100处于写入保护状态，则时序控制器200的写控制信号输出端输出的信号TC需要设置为低，使N型MOS管Q2关断。若时序控制器200要对存储器100进行写操作，则时序控制器200的写控制信号输出端输出的信号TC设置为高，使N型MOS管Q2打开。当N型MOS管Q2关断时，电源电路300输出的高电平信号给到存储器100，使存储器100处于写保护状态，当N型MOS管Q2打开时，则存储器100的写保护信号控制端WP_O与地相接，WP_O为低，存储器100就可以被进行写操作。
进一步地，参照图2或图3，所述显示面板中存储器的保护电路还包括第一电阻R1，所述第一电阻R1的第一端与所述电源电路300的输出端连接，所述第一电阻R1的第二端与所述开关电路400的输入端和所述写保护信号控制端的公共端连接。
该实施例中，电源电路300为直流电源VDD，第一电阻R1为存储器100的上拉电阻，能够在直流电源VDD输出的电源信号异常时也能将其输出信号钳位为高电平，保证输出稳定、可靠，避免写保护信号WP_O失效。
该实施例中，进一步地，所述时序控制器200还用于在接收到所述存储器100完成数据写入后的反馈信号时，控制所述开关电路400关断。当存储器100完成数据写入后，会发送反馈或应答信号至所述时序控制器200，时序控制器200在收到反馈或应答信号时即可知晓存储器100已经完成数据写入，此时控制开关电路400关断，不仅可以使存储器100进入写保护状态而且可以防止第一电阻R1消耗能量。可以理解的是，由于第一电阻R1的存在，若在对存储器100完成写入数据后，开关电路400仍被被开启，则会通过第一电阻R1消耗能量，造成不必要的损耗，本实施例中，在对存储器100完成写入数据后，控制开关电路400关断，则很好地避免了此问题。
此外，本申请还提供一种显示面板，该显示面板包括上述的显示面板中存储器的保护电路，可以理解的是，由于在显示面板中使用了上述显示面板中存储器的保护电路，因此，该显示面板的实施例包括上述显示面板中存储器的保护电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
本实施例中，显示面板包括但不限于液晶显示面板、有机发光二极管显示面板、场发射显示面板、等离子显示面板、曲面型面板，所述液晶面板包括薄膜晶体管液晶显示面板、TN面板、VA类面板、IPS面板等。
此外，本申请还提供一种显示装置，该显示装置包括上述的显示面板，而显示面板包含上述的显示面板中存储器的保护电路，因此，也具有上述显示面板中存储器的保护电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。需要说明的是，该显示装置可以是一般的显示器或者平板电视等，当然也可以是液晶显示器或者液晶电视。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (19)

  1. 一种显示面板中存储器的保护电路，其中，所述显示面板中存储器的保护电路包括：
    时序控制器，具有信号传输端和写控制信号输出端；
    存储器，具有信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
    电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
    开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
    所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
  2. 如权利要求1所述的显示面板中存储器的保护电路，其中，所述开关电路包括开关管，所述开关管具有第一连接端、第二连接端及受控端，所述开关管的第一连接端为所述开关电路的输入端，所述第二连接端为所述开关电路的输出端，所述开关管的受控端为所述开关电路的受控端。
  3. 如权利要求2所述的显示面板中存储器的保护电路，其中，所述开关管为P型MOS管，所述P型MOS管的源极为所述开关管的第一连接端，所述P型MOS管的漏极为所述开关管的第二连接端，所述P型MOS管的栅极为所述开关管的受控端。
  4. 如权利要求2所述的显示面板中存储器的保护电路，其中，所述开关管为N型MOS管，所述N型MOS管的漏极为所述开关管的第一连接端，所述N型MOS管的源极为所述开关管的第二连接端，所述N型MOS管的栅极为所述开关管的受控端。
  5. 如权利要求1所述的显示面板中存储器的保护电路，其中，所述显示面板中存储器的保护电路还包括第一电阻，所述第一电阻的第一端与所述电源电路的输出端连接，所述第一电阻的第二端与所述开关电路的输入端和所述写保护信号控制端的公共端连接。
  6. 如权利要求5所述的显示面板中存储器的保护电路，其中，所述时序控制器还用于在接收到所述存储器完成数据写入后的反馈信号时，控制所述开关电路关断。
  7. 如权利要求1所述的显示面板中存储器的保护电路，其中，所述存储器为电可擦可编程只读存储器。
  8. 如权利要求1所述的显示面板中存储器的保护电路，其中，所述电源电路为直流电源。
  9. 一种显示面板中存储器的保护电路，其中，所述显示面板中存储器的保护电路包括：
    时序控制器，具有信号传输端和写控制信号输出端；
    存储器，具有电源端、信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
    电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路还与所述存储器的电源端连接；所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
    开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
    所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
  10. 一种显示面板，其中，所述显示面板包括显示面板中存储器的保护电路，所述显示面板中存储器的保护电路包括：
    时序控制器，具有信号传输端和写控制信号输出端；
    存储器，具有信号传输端和写保护信号控制端，所述存储器的信号传输端与所述时序控制器的信号传输端连接；所述存储器，用于存储所述时序控制器的软件数据；
    电源电路，所述电源电路的输出端与所述写保护信号控制端连接，所述电源电路，用于输出写保护信号至所述存储器，以限制所述存储器的数据被改写；以及
    开关电路，所述开关电路的输入端与述电源电路的输出端、所述写保护信号控制端互连，所述开关电路的输出端接地，所述开关电路的受控端与所述写控制信号输出端连接；
    所述时序控制器，用于控制所述开关电路处于常关断状态，在接收到对所述存储器进行数据写入指令时，控制所述开关电路开启。
  11. 如权利要求10所述的显示面板，其中，所述存储器还具有电源端，所述电源电路还与所述存储器的电源端连接。
  12. 如权利要求10所述的显示面板，其中，所述开关电路包括开关管，所述开关管具有第一连接端、第二连接端及受控端，所述开关管的第一连接端为所述开关电路的输入端，所述第二连接端为所述开关电路的输出端，所述开关管的受控端为所述开关电路的受控端。
  13. 如权利要求12所述的显示面板，其中，所述开关管为P型MOS管，所述P型MOS管的源极为所述开关管的第一连接端，所述P型MOS管的漏极为所述开关管的第二连接端，所述P型MOS管的栅极为所述开关管的受控端。
  14. 如权利要求12所述的显示面板，其中，所述开关管为N型MOS管，所述N型MOS管的漏极为所述开关管的第一连接端，所述N型MOS管的源极为所述开关管的第二连接端，所述N型MOS管的栅极为所述开关管的受控端。
  15. 如权利要求10所述的显示面板，其中，所述显示面板中存储器的保护电路还包括第一电阻，所述第一电阻的第一端与所述电源电路的输出端连接，所述第一电阻的第二端与所述开关电路的输入端和所述写保护信号控制端的公共端连接。
  16. 如权利要求15所述的显示面板，其中，所述时序控制器还用于在接收到所述存储器完成数据写入后的反馈信号时，控制所述开关电路关断。
  17. 如权利要求10所述的显示面板，其中，所述存储器为电可擦可编程只读存储器。
  18. 如权利要求10所述的显示面板，其中，所述电源电路为直流电源。
  19. 如权利要求10所述的显示面板，其中，所述显示面板为液晶显示面板或者有机发光二极管显示面板或者场发射显示面板或者等离子显示面板或者曲面型面板。
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