WO2022057372A1 - 一种基于pca9511芯片的iic挂死的链路恢复电路及方法 - Google Patents

一种基于pca9511芯片的iic挂死的链路恢复电路及方法 Download PDF

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WO2022057372A1
WO2022057372A1 PCT/CN2021/103368 CN2021103368W WO2022057372A1 WO 2022057372 A1 WO2022057372 A1 WO 2022057372A1 CN 2021103368 W CN2021103368 W CN 2021103368W WO 2022057372 A1 WO2022057372 A1 WO 2022057372A1
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chip
pac9511
mos transistor
clock line
iic
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PCT/CN2021/103368
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French (fr)
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江博
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苏州浪潮智能科技有限公司
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Priority to US18/012,937 priority Critical patent/US11990895B2/en
Publication of WO2022057372A1 publication Critical patent/WO2022057372A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Definitions

  • the invention belongs to the technical field of IIC (Inter-Integrated Circuit, integrated circuit bus) bus, and in particular relates to a link recovery circuit and method for hanging IIC based on a PAC9511 chip.
  • IIC Inter-Integrated Circuit, integrated circuit bus
  • PCA9511 full name Hot swappable I2C-bus and SMBus bus buffer, a chip, hot-swappable I2C and SMBus bus buffer
  • PCIE peripheral component interconnect express
  • SMBus bus buffer a chip, hot-swappable I2C and SMBus bus buffer
  • the enable pin is generally directly pulled up to the power supply voltage, and then the UIC enters the initialization stage.
  • the internal reference voltage and precharge circuit in this stage have already worked.
  • the bus "STOP BIT ANND BUS IDLE" detection starts. If STOP BIT (stop bit) or BUS IDLE (bus idle) is detected, the bus will send data
  • the internal switches of the line input interface and the data line output interface are set to be closed, and the internal switches of the clock line input interface and the clock line output interface are set to be closed.
  • Scenario 1 Hot-swap controller, BBU (Battery Back-Up unit, battery module) is always charged during the whole process, then BBU will pull the IIC bus interconnected with MCU (Microcontroller Unit, micro control unit);
  • MCU Microcontroller Unit, micro control unit
  • Scenario 2 The controller is hot-swapped, and the controller at the other end is always powered, then the BMC IIC bus that interacts with the dual controllers will hang up (the whole storage controller has 2 controllers, and the dual controllers are mirror images of each other);
  • the PCA9511 will also be pulled out and powered off, and will be powered on again when the IIC bus master is inserted. It is detected that the data line level on the bus slave side is low, and the PCA9511 The switch inside it will never be turned on. Under such conditions, because the link between the master and the slave is disconnected, the repair method of 9 CLOCKs will not work, and the fault repair will be difficult.
  • the present invention provides a link recovery circuit and method for IIC hang-up based on a PAC9511 chip, so as to solve the above-mentioned technical problems.
  • the present invention provides a link recovery circuit based on a PAC9511 chip for IIC hang-up, including: a PAC9511 chip, an inversion circuit and an external MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviation for MOSFET, metal -oxide semiconductor field effect transistor) Q1,
  • the IIC bus inside the PAC9511 chip includes: a clock line; one end of the PAC9511 chip is connected to the master of the IIC bus, and the other end of the PAC9511 chip is connected to the slave of the IIC bus; so
  • the PAC9511 chip is provided with clock line input, output interface and ready signal interface, one end of the inversion circuit is connected to the ready signal interface, and the other end of the inversion circuit is connected to the G pole of the external MOS tube Q1; the external MOS tube
  • the S pole and D pole of Q1 are respectively connected to the input and output interfaces of the clock line of the PAC9511 chip.
  • the inversion circuit includes a MOS transistor Q2, the G pole of the MOS transistor Q2 is connected to the ready signal interface, and the S pole of the MOS transistor Q2 is connected to the G pole of the external MOS transistor Q1;
  • the input interface of the clock line of the S pole PAC9511 chip of the external MOS transistor Q1 is connected; the output interface of the clock line of the D pole PAC9511 chip of the external MOS transistor Q1 is connected.
  • a pull-up resistor is connected to the ready signal interface, and the pull-up resistor is connected to a 3.3V power supply.
  • the S pole of the MOS transistor Q2 is connected with a protection resistor, and the protection resistor is grounded.
  • the D pole of the MOS transistor Q2 is connected with a pull-up resistor, and the pull-up resistor is connected with the 3.3V power supply.
  • the present invention provides a link recovery method based on the PAC9511 chip that hangs up the IIC, including:
  • the internal switch of the PCA9511 chip is open, and the ready signal is low;
  • the ready signal is inverted and becomes a high level, thereby turning on the external MOS transistor Q1;
  • the method further includes: when the IIC bus service is normal, the ready signal is high, the external MOS transistor Q1 is not turned on, and there is only the original clock line channel inside the PCA9511 between the input and output interfaces of the clock line.
  • the method further includes: when the internal switch of the clock line of the PCA9511 chip is set to be closed, the ready signal output is high; otherwise, the ready signal is low.
  • the method further includes: a method of sending 9 CLOCKs on the new clock line channel by the host of the IIC bus to perform fault recovery.
  • the beneficial effect of the present invention is that,
  • the invention provides a link recovery circuit and method for IIC hang-up based on the PAC9511 chip. After the IIC hang-up occurs, a clock line channel is set outside the PCA9511 chip to restore the connection between the host and the slave, so that the host can connect to the clock line.
  • the method of sending 9 CLOCKs above is used for troubleshooting.
  • the present invention has reliable design principle and simple structure, and has a very wide application prospect.
  • FIG. 1 is an internal circuit structure diagram of a PCA9511 chip in the prior art of the present invention.
  • FIG. 2 is a schematic diagram of a master-slave pulse of an IIC bus in the prior art of the present invention.
  • FIG. 3 is a schematic structural diagram of a circuit according to an embodiment of the present invention.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • This embodiment provides a link recovery circuit based on a PAC9511 chip that hangs up an IIC, including: a PAC9511 chip, an inversion circuit and an external MOS transistor Q1, and the IIC bus inside the PAC9511 chip includes: a data line and a clock line; One end of the PAC9511 chip is connected to the host of the IIC bus, and the other end of the PAC9511 chip is connected to the slave of the IIC bus; the PAC9511 chip is provided with input and output interfaces for data lines and input and output interfaces for clock lines; the PAC9511 The chip is provided with a ready signal interface, one end of the inversion circuit is connected to the ready signal interface, and the other end of the inversion circuit is connected to the G pole of the external MOS transistor Q1; the S pole and the D pole of the external MOS transistor Q1 are respectively PAC9511 chips The input and output interfaces of the clock line are connected; the data line is the data transmission channel of the IIC bus, when SCL is high, SDA jump
  • the inversion circuit includes a MOS transistor Q2, the G pole of the MOS transistor Q2 is connected to the ready signal interface, and the S pole of the MOS transistor Q2 is connected to the G pole of the external MOS transistor Q1;
  • the input interface of the clock line of the S pole PAC9511 chip of the external MOS transistor Q1 is connected; the output interface of the clock line of the D pole PAC9511 chip of the external MOS transistor Q1 is connected.
  • a pull-up resistor is connected to the ready signal interface, and the pull-up resistor is connected to a 3.3V power supply.
  • the S pole of the MOS transistor Q2 is connected with a protection resistor, and the protection resistor is grounded.
  • the D pole of the MOS transistor Q2 is connected with a pull-up resistor, and the pull-up resistor is connected with the 3.3V power supply.
  • This embodiment provides a link recovery method based on the PAC9511 chip that hangs the IIC, including:
  • the ready signal is inverted and becomes a high level, thereby turning on the external MOS tube Q1; after the external MOS tube Q1 is turned on, a new clock line channel is formed outside the PCA9511 chip;
  • the host of the IIC bus performs fault repair by sending 9 CLOCKs on the new clock line channel.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Logic Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)

Abstract

一种基于PCA9511芯片的IIC挂死的链路恢复电路，包括：PCA9511芯片、取反电路和外部MOS管（Q1），PCA9511芯片内部的IIC总线包括：时钟线；PCA9511芯片一端连接IIC总线的主机，且PCA9511芯片的另一端连接IIC总线的从机；PCA9511芯片设置有时钟线的输入、输出接口和就绪信号接口，取反电路一端连接就绪信号接口，取反电路的另一端连接外部MOS管（Q1）的G极；外部MOS管（Q1）的S极和D极分别与PCA9511芯片的时钟线的输入、输出接口连接。还公开了一种基于PCA9511芯片的IIC挂死的链路恢复方法。在发生IIC挂死后，在PCA9511芯片外部设置时钟线的通道，恢复主机和从机的连通，方便主机在时钟线上发送9个CLOCK进行故障修复。

Description

[根据细则37.2由ISA制定的发明名称]　一种基于PCA9511芯片的IIC挂死的链路恢复电路及方法
本申请要求于2020年09月18日提交中国专利局、申请号为202010990345.1、发明名称为“一种基于PAC9511芯片的IIC挂死的链路恢复电路及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于IIC(Inter-Integrated Circuit，集成电路总线)总线技术领域，具体涉及一种基于PAC9511芯片的IIC挂死的链路恢复电路及方法。
背景技术
PCA9511(全称为Hot swappable I2C-bus and SMBus bus buffer，一款芯片，热插拔型I2C与SMBus总线缓存器)只应用于热插拔IIC SLAVE的场景，比如热插入某PCIE(peripheral component interconnect express，一种高速串行计算机扩展总线标准)卡到正在正常运行的服务器上。因为热插拔将在PCIE卡与服务器之间的信号上造成可预见的短时间高脉冲，如果所插入的总线中IIC主机与某IIC从机(IIC总线可以挂在多个从机)正在通信，此插入造成的高脉冲将扰乱正常通信的数据，导致数据错误。
当PCA9511上电过程中，其“低压与初始化”电路(下文简称“UIC”,under voltage and initialization circuit)将数据线输入接口、数据线输出接口、时钟线输入接口、时钟线输出接口置为高阻态；则时钟线和数据线的上的开关均为开路；此时数据线输入接口与数据线输出接口内部开关为开路，时钟线输入接口与时钟线输出接口内部开关为开路。随着供电电压爬升到满足芯片电压电平要求，即UIC的低压检测，并且芯片的使能接口变高,使用中，使能pin一般是直接上拉到供电电压的，然后UIC进入初始化阶段。此阶段内部的参考电压和预充电电路已经工作，阶段的最后步骤，总线 “STOP BIT ANND BUS IDLE”检测开始，如果检测到STOP BIT(停止位)或者BUS IDLE(总线空闲)后，总线将数据线输入接口与数据线输出接口内部开关设为闭合，时钟线输入接口与时钟线输出接口内部开关设为闭合。除非发生芯片断电，否则此内部开发将一直处于闭合状态。在图2中：箭头处发生热拔事件，从机的时钟线突然消失，从机内部逻辑需要在每个时钟线的跳变沿上推新数据，时钟线消失导致从机没内逻辑没有跳变沿触发，从而从机维持一拍的数据不变。如果前一拍数据为低电平，则从机将一直将数据线拉低，造成总线挂死。
此种现象尤其在存储控制器中是很常见的，例如：
场景1：热拔插控制器，BBU(Battery Back-Up unit，电池模块)在全程一直带电，则BBU将拉死其与MCU(Microcontroller Unit，微控制单元)互联的IIC总线；
场景2：热插拔控制器，另一端控制器一直带电，则双控间交互的BMC IIC总线将挂死(存储控整机有2个控制器，双控制器之间互为镜像)；
遇到IIC总线发生挂死后，一般采用主机在SCL上发送9个CLOCK的方法修复。
但是当拔出IIC总线主机的过程中PCA9511也会一起拔出并掉电，并随IIC总线主机插入而一起再次上电，检测到总线从机一侧的数据线电平为低电平，PCA9511将一直不会打开其内部的开关。在这样的条件下，因主机与从机之间的链路是断开的，则9个CLOCK的修复方法将不能奏效，故障修复遇到困难。
发明内容
针对现有技术的上述不足，本发明提供一种基于PAC9511芯片的IIC挂死的链路恢复电路及方法，以解决上述技术问题。
第一方面，本发明提供一种基于PAC9511芯片的IIC挂死的链路恢复电路，包括：PAC9511芯片、取反电路和外部MOS管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET的缩写，金属-氧化物半导体场效应晶体管)Q1，所述PAC9511芯片内部的IIC总线包括： 时钟线；所述PAC9511芯片一端连接IIC总线的主机，且所述PAC9511芯片的另一端连接IIC总线的从机；所述PAC9511芯片设置有时钟线的输入、输出接口以及就绪信号接口，所述取反电路一端连接就绪信号接口，所述取反电路的另一端连接外部MOS管Q1的G极；所述外部MOS管Q1的S极和D极分别PAC9511芯片的时钟线的输入、输出接口连接。
进一步的，所述取反电路包括MOS管Q2，所述MOS管Q2的G极与就绪信号接口连接，所述MOS管Q2的S极与外部MOS管Q1的G极连接；
进一步的，所述外部MOS管Q1的S极PAC9511芯片的时钟线的输入接口连接；所述外部MOS管Q1的D极PAC9511芯片的时钟线的输出接口连接。
进一步的，所述就绪信号接口连接有上拉电阻，所述上拉电阻与3.3V电源连接。
进一步的，所述MOS管Q2的S极连接有保护电阻，所述保护电阻接地。
进一步的，所述MOS管Q2的D极连接有上拉电阻，所述上拉电阻与3.3V电源连接。
第二方面，本发明提供一种基于PAC9511芯片的IIC挂死的链路恢复方法，包括：
当IIC总线挂死后，PCA9511芯片插入IIC总线主机重新上电；
PCA9511芯片内部开关开路，就绪信号为低电平；
就绪信号取反变为高电平，从而导通外部MOS管Q1；
外部MOS管Q1导通后在PCA9511芯片外部形成新的时钟线通道。
进一步的，所述方法还包括：当IIC总线业务正常时，就绪信号为高电平，外部MOS管Q1不导通，时钟线的输入、输出接口之间只有PCA9511内部的原时钟线通道。
进一步的，所述方法还包括：PCA9511芯片的时钟线的内部开关设为闭合时，就绪信号输出为高；反之，就绪信号为低。
进一步的，所述方法还包括：所述IIC总线的主机在所述新的时钟线通道上发送9个CLOCK的方法来进行故障修复。
本发明的有益效果在于，
本发明提供的一种基于PAC9511芯片的IIC挂死的链路恢复电路及方 法，在发生IIC挂死后，在PCA9511芯片外部设置时钟线的通道，恢复连通主机和从机，方便主机在时钟线上发送9个CLOCK的方法进行故障修复。
此外，本发明设计原理可靠，结构简单，具有非常广泛的应用前景。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明现有技术PCA9511芯片的内部电路结构图。
图2是本发明现有技术IIC总线主从机脉冲示意图。
图3是本发明一个实施例的电路的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以通过具体情况理解上述术语 在本发明中的具体含义。
实施例1
本实施例提供一种基于PAC9511芯片的IIC挂死的链路恢复电路，包括：PAC9511芯片、取反电路和外部MOS管Q1，所述PAC9511芯片内部的IIC总线包括：数据线和时钟线；所述PAC9511芯片一端连接IIC总线的主机，且所述PAC9511芯片的另一端连接IIC总线的从机；所述PAC9511芯片设置有数据线的输入、输出接口和时钟线的输入、输出接口；所述PAC9511芯片设置有就绪信号接口，所述取反电路一端连接就绪信号接口，所述取反电路的另一端连接外部MOS管Q1的G极；所述外部MOS管Q1的S极和D极分别PAC9511芯片的时钟线的输入、输出接口连接；所述数据线为IIC总线的数据传输通道，当SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据；当SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据，即当时钟线连通时，数据线才能连通。
进一步的，所述取反电路包括MOS管Q2，所述MOS管Q2的G极与就绪信号接口连接，所述MOS管Q2的S极与外部MOS管Q1的G极连接；
进一步的，所述外部MOS管Q1的S极PAC9511芯片的时钟线的输入接口连接；所述外部MOS管Q1的D极PAC9511芯片的时钟线的输出接口连接。
进一步的，所述就绪信号接口连接有上拉电阻，所述上拉电阻与3.3V电源连接。
进一步的，所述MOS管Q2的S极连接有保护电阻，所述保护电阻接地。
进一步的，所述MOS管Q2的D极连接有上拉电阻，所述上拉电阻与3.3V电源连接。
实施例2
本实施例提供一种基于PAC9511芯片的IIC挂死的链路恢复方法，包括：
S1、当IIC总线业务正常时，就绪信号为高电平，外部MOS管Q1不 导通，时钟线的输入、输出接口之间只有PCA9511内部的原时钟线通道；
S2、当IIC总线挂死后，PCA9511芯片插入IIC总线主机重新上电；
S3、PCA9511芯片的时钟线的内部开关设为闭合时，就绪信号输出为高；反之，就绪信号为低；当IIC总线挂死后，PCA9511芯片内部开关开路，就绪信号为低电平；
S4、就绪信号取反变为高电平，从而导通外部MOS管Q1；外部MOS管Q1导通后在PCA9511芯片外部形成新的时钟线通道；
S5、所述IIC总线的主机在所述新的时钟线通道上发送9个CLOCK的方法来进行故障修复。
尽管通过参考附图并结合优选实施例的方式对本发明进行了详细描述，但本发明并不限于此。在不脱离本发明的精神和实质的前提下，本领域普通技术人员可以对本发明的实施例进行各种等效的修改或替换，而这些修改或替换都应在本发明的涵盖范围内/任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (10)

  1. 一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，包括：PAC9511芯片、取反电路和外部MOS管Q1，所述PAC9511芯片内部的IIC总线包括：时钟线；所述PAC9511芯片一端连接IIC总线的主机，且所述PAC9511芯片的另一端连接IIC总线的从机；所述PAC9511芯片设置有时钟线的输入、输出接口以及绪信号接口，所述取反电路一端连接就绪信号接口，所述取反电路的另一端连接外部MOS管Q1的G极；所述外部MOS管Q1的S极和D极分别PAC9511芯片的时钟线的输入、输出接口连接。
  2. 根据权利要求1所述的一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，所述取反电路包括MOS管Q2，所述MOS管Q2的G极与就绪信号接口连接，所述MOS管Q2的S极与外部MOS管Q1的G极连接；
  3. 根据权利要求1所述的一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，所述外部MOS管Q1的S极PAC9511芯片的时钟线的输入接口连接；所述外部MOS管Q1的D极PAC9511芯片的时钟线的输出接口连接。
  4. 根据权利要求1所述的一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，所述就绪信号接口连接有上拉电阻，所述上拉电阻与3.3V电源连接。
  5. 根据权利要求1所述的一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，所述MOS管Q2的S极连接有保护电阻，所述保护电阻接地。
  6. 根据权利要求1所述的一种基于PAC9511芯片的IIC挂死的链路恢复电路，其特征在于，所述MOS管Q2的D极连接有上拉电阻，所述上拉电阻与3.3V电源连接。
  7. 一种如权利要求1至6任一项所述的基于PAC9511芯片的IIC挂死的链路恢复电路的链路恢复方法，其特征在于，包括：
    当IIC总线挂死后，PCA9511芯片插入IIC总线主机重新上电；
    PCA9511芯片内部开关开路，就绪信号为低电平；
    就绪信号取反变为高电平，从而导通外部MOS管Q1；
    外部MOS管Q1导通后在PCA9511芯片外部形成新的时钟线通道并基于新的时钟线进行链路恢复。
  8. 根据权利要求7所述的一种基于PAC9511芯片的IIC挂死的链路恢复方法，其特征在于，所述方法还包括：当IIC总线业务正常时，就绪信号为高电平，外部MOS管Q1不导通，时钟线的输入、输出接口之间只有PCA9511内部的原时钟线通道。
  9. 根据权利要求7所述的一种基于PAC9511芯片的IIC挂死的链路恢复方法，其特征在于，所述方法还包括：PCA9511芯片的时钟线的内部开关设为闭合时，就绪信号输出为高；反之，就绪信号为低。
  10. 根据权利要求7所述的一种基于PAC9511芯片的IIC挂死的链路恢复方法，其特征在于，所述链路恢复方法包括：所述IIC总线的主机在所述新的时钟线通道上发送9个CLOCK的方法来进行故障修复。
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