WO2020056932A1 - 一种三维非易失性铁电存储器 - Google Patents

一种三维非易失性铁电存储器 Download PDF

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WO2020056932A1
WO2020056932A1 PCT/CN2018/119974 CN2018119974W WO2020056932A1 WO 2020056932 A1 WO2020056932 A1 WO 2020056932A1 CN 2018119974 W CN2018119974 W CN 2018119974W WO 2020056932 A1 WO2020056932 A1 WO 2020056932A1
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ferroelectric memory
ferroelectric
memory cell
layer
bit line
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French (fr)
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江安全
柴晓杰
张岩
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Fudan University
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Fudan University
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Priority to US16/760,581 priority patent/US10971204B2/en
Publication of WO2020056932A1 publication Critical patent/WO2020056932A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/10—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2255—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2257—Word-line or row circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array

Definitions

  • the invention belongs to the technical field of ferroelectric storage, and particularly relates to a three-dimensional nonvolatile ferroelectric memory.
  • Ferroelectric Random Access Memory uses two different polarization orientations of ferroelectric domains (or “electric domains”) in the electric field as logical information (“0" or "1") to store them.
  • Non-volatile memory of data which can also be referred to as “ferroelectric memory”.
  • such a ferroelectric memory device with a domain-wall conductive storage mechanism has an on-state (ON state) read current of 10 -7 A to 10 -6 A and a large read current; on the other hand, ON-state current and off-state (Off state)
  • ON state ON-state current and off-state
  • the current ratio ie, the switching ratio
  • the data retention performance is good; therefore, it has attracted much attention from the industry.
  • 3D NAND is a revolutionary semiconductor storage technology that achieves storage density growth by increasing storage stacks instead of reducing the two-dimensional size of the device, bringing the development space of semiconductor memory into the third dimension, and becoming the key to achieving sustainable growth in memory chip capacity in the future. .
  • a three-dimensional non-volatile ferroelectric memory which includes a ferroelectric memory array structure, the ferroelectric memory array structure including a multi-layer ferroelectric memory cell array arranged in a stack, each layer
  • the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns;
  • substantially orthogonal word lines and bit lines are respectively arranged opposite to two sides corresponding to the ferroelectric memory cell, and a reference ferroelectric body is arranged adjacent to the ferroelectric memory cell;
  • a polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and applying the between the word line and the bit line
  • an electric domain of the ferroelectric memory cell can be inverted and a domain wall conductive channel can be established between the ferroelectric memory cell and the adjacent reference ferroelectric body.
  • the domain wall conductive channel can be electrically connected to the domain wall conductive channel.
  • the three-dimensional non-volatile ferroelectric memory wherein the ferroelectric memory unit and the reference ferroelectric body are integrally formed by a same ferroelectric single crystal layer or a ferroelectric thin film layer.
  • each of the bit lines is correspondingly arranged by the multilayer ferroelectric memory cell array in a stacking direction thereof.
  • Multiple ferroelectric memory cells are shared; each bit line of each layer of the ferroelectric memory cell array is shared by multiple ferroelectric memory cells of the ferroelectric memory cell array correspondingly arranged in the column / row direction.
  • the three-dimensional non-volatile ferroelectric memory according to another embodiment of the present invention or any one of the foregoing embodiments, further comprising:
  • a bit line layer which is arranged on a top layer and / or a bottom layer of the multilayer ferroelectric memory cell array, wherein each of the bit line layers and a plurality of the bits arranged in a row / column direction in sequence Electrical connection.
  • the three-dimensional non-volatile ferroelectric memory according to another embodiment of the present invention or any one of the foregoing embodiments, wherein two sides of the word line in a row / column direction are respectively two columns / rows of the ferroelectric memory cell.
  • the coupling is shared by the two column / row ferroelectric memory cells; and / or
  • the two sides of the bit line in the row / column direction are respectively coupled with the two in-line ferroelectric memory cells arranged correspondingly in the stacking direction and shared by the two in-line ferroelectric memory cells.
  • the three-dimensional non-volatile ferroelectric memory according to another embodiment of the present invention or any one of the foregoing embodiments, wherein the ferroelectric memory cell of the multilayer ferroelectric memory cell array and the corresponding reference ferroelectric body Both are integrally formed by the same ferroelectric single crystal layer or ferroelectric thin film layer.
  • the three-dimensional non-volatile ferroelectric memory wherein the ferroelectric single crystal layer or the ferroelectric thin film layer is patterned to form a first layer extending in the stacking direction.
  • a deep groove and a second deep groove the bit line is formed in the first deep groove, a plurality of the word lines are formed in the same second deep groove and the corresponding word lines pass through the second deep groove
  • the dielectric layer in the tank is isolated;
  • the ferroelectric memory cell of the multilayer ferroelectric memory cell array and the corresponding reference ferroelectric body are formed in the ferroelectric body between the first deep groove and the second deep groove,
  • the ferroelectric portion corresponding to the dielectric layer in the second deep trench is the reference ferroelectric, and the ferroelectric portion corresponding to the word line in the second deep trench is the ferroelectric storage. unit.
  • the three-dimensional non-volatile ferroelectric memory according to another embodiment of the present invention or any one of the foregoing embodiments, wherein a plurality of the word lines and a plurality of dielectric layers in the same second deep trench are in the stacking direction.
  • a plurality of the reference ferroelectrics and a plurality of the ferroelectric memory cells are sequentially staggered in the stacking direction.
  • the three-dimensional non-volatile ferroelectric memory wherein each layer of the ferroelectric memory cell array includes:
  • a plurality of ferroelectric memory cells arranged in rows and columns protruding from the ferroelectric base layer;
  • a word line layer including a plurality of word lines arranged on the ferroelectric base layer
  • bit line extends through the ferroelectric base layer of the multilayer ferroelectric memory cell array in the stacking direction.
  • the three-dimensional non-volatile ferroelectric memory wherein each layer of the ferroelectric memory cell array includes:
  • a bit line layer / word line layer for forming a plurality of bit lines / word lines
  • a word line layer / bit line layer on the ferroelectric layer for forming a plurality of word lines / bit lines;
  • a ferroelectric layer corresponding to the intersection of the word line and the bit line is used to form the ferroelectric memory cell, and the remaining portion of the ferroelectric layer is used to form the reference ferroelectric body.
  • each of the ferroelectric memory cells has a unidirectional conduction characteristic in an on state.
  • the read voltage of the three-dimensional non-volatile ferroelectric memory is greater than that of the ferroelectric memory cell to make it unidirectional.
  • the turn-on voltage is less than the coercive voltage of the ferroelectric memory cell.
  • ferroelectric material used in the ferroelectric single crystal layer or the ferroelectric thin film layer is selected from one or more of the following: Species:
  • the ferroelectric material is lithium tantalate LiTaO 3 , lithium niobate LiNbO 3 or bismuth ferrite BiFeO 3 ,
  • Doping selected from MgO, Mn 2 O 5, Fe 2 O 3 or La salt of lithium tantalate 2 O 3 is LiTaO 3, lithium niobate LiNbO 3 or bismuth ferrate BiFeO 3,
  • the three-dimensional non-volatile ferroelectric memory according to another embodiment of the present invention or any one of the foregoing embodiments, wherein the polarization direction of the electric domain of the ferroelectric memory cell and the word line and bit line on both sides thereof are There is an included angle in the connection direction and the electric domains have a component in the connection direction.
  • FIG. 1 is a schematic diagram of a ferroelectric memory array structure and an operating principle of a three-dimensional nonvolatile ferroelectric memory according to a first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a second embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a ferroelectric memory array structure and an operating principle of a three-dimensional nonvolatile ferroelectric memory according to a third embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a fourth embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a fifth embodiment of the present invention.
  • FIG. 6 (a) is an IV characteristic curve diagram of a single ferroelectric memory cell formed on the surface of a single crystal lithium niobate (LiNbO3) and performing read and write operations by a voltage scanning method according to an embodiment of the present invention
  • FIG. 6 (b) ) Is a schematic diagram showing that the turn-on voltage Von of the ferroelectric memory cell according to an embodiment of the invention changes with the gap g between the right electrode and the ferroelectric memory cell.
  • FIG. 7 is an I-V characteristic curve of a single ferroelectric memory cell formed on a surface of a lithium niobate (LiNbO3) single crystal thin film according to an embodiment of the present invention by performing a voltage scanning method for reading and writing.
  • LiNbO3 lithium niobate
  • the domain direction or polarization direction is exemplarily given, but it should be understood that the domain direction or polarization direction of the ferroelectric memory is not limited to the embodiment shown in the figure. Out direction.
  • a ferroelectric single crystal refers to a single crystal structure or a single crystal-like structure that does not have a "crystal boundary" within the polycrystalline structure; the memory cell of the memory cell array formed thereon is also a single crystal structure, and the size of the memory cell does not vary. limit.
  • the ferroelectric single crystal may be a ferroelectric single crystal thin film layer or a ferroelectric single crystal substrate, and the ferroelectric single crystal thin film layer may be a single crystal thin film formed by epitaxial single crystal growth, or separated from a ferroelectric single crystal substrate or The formed thin film layer is cut.
  • the non-volatile memory includes a ferroelectric memory array, and a plurality of ferroelectric memory cells in the ferroelectric memory array are arranged in a row and a column manner. Circuits, corresponding rows and columns of ferroelectric memory cells can be selected for corresponding write or read operations. It should be noted that the specific number and arrangement of the ferroelectric memory cells in the ferroelectric memory array are not limitative.
  • FIG. 1 is a schematic diagram showing a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a first embodiment of the present invention.
  • FIG. 1 (a) schematically illustrates the three-dimensional structure of the ferroelectric memory array structure 40 of this embodiment
  • FIG. 1 (b) is a top view of the ferroelectric memory array structure 40 without a top bit line layer.
  • FIG. 1 (c) is a cross-sectional view taken along IJ in FIG. 1 (a).
  • FIG. 1 (d) illustrates the operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 40.
  • FIG. 1 (a) schematically illustrates the three-dimensional structure of the ferroelectric memory array structure 40 of this embodiment
  • FIG. 1 (b) is a top view of the ferroelectric memory array structure 40 without a top bit line layer.
  • FIG. 1 (c) is a cross-sectional view taken along IJ in FIG. 1 (a).
  • FIG. 1 (e) illustrates the operation principle of writing data “0” to a ferroelectric memory cell of the ferroelectric memory array structure 40
  • FIG. 1 (f) illustrates a ferroelectric to the ferroelectric memory array structure 40. Operation principle of reading data "1" from the memory cell.
  • the z direction is defined as the stacking direction of the multilayer ferroelectric memory cell array, which is generally perpendicular to the substrate
  • the x direction is defined as each layer of ferroelectric The direction in which the rows of the memory cell array are located
  • the y direction is defined as the direction in which the columns of each layer of the ferroelectric memory cell array are located.
  • the ferroelectric memory array structure 40 is included in a three-dimensional non-volatile ferroelectric memory, and corresponding peripheral read-write circuits can be configured.
  • the specific structure of the peripheral read-write circuits is not restrictive. The present invention is clearly described, and the description of the peripheral read-write circuit is omitted here.
  • the ferroelectric memory array structure 40 may include a plurality of ferroelectric base layers 401 (for example, ferroelectric base layers 401a, 401b, and 401c which are sequentially stacked from bottom to top), and a multi-layer memory cell array 402 (for example, stacked from bottom to top) Ground memory cell array 402a, 402b, and 402c), a plurality of word line layers 403 (for example, word line layers 403a, 403b, and 403c arranged in order from bottom to top), a bit line array 404, and a top bit line layer 405 And multilayer insulation layer 406.
  • ferroelectric base layers 401 for example, ferroelectric base layers 401a, 401b, and 401c which are sequentially stacked from bottom to top
  • a multi-layer memory cell array 402 for example, stacked from bottom to top
  • Ground memory cell array 402a, 402b, and 402c Ground memory cell array 402a, 402b, and 402c
  • the uppermost insulating layer 406 can isolate the top bit line layer 405 from the ferroelectric base layer 401 and the like, and the intermediate insulating layer 406 can isolate multiple word line layers 403 from each other; other gaps can be insulated Material filling.
  • the ferroelectric memory array structure 40 includes a multilayer ferroelectric memory cell array arranged in a stack, which are sequentially stacked in the z direction, that is, their stacking direction is the z direction; each layer of the ferroelectric memory cell array includes A ferroelectric base layer 401, a memory cell array 402 arranged on the ferroelectric base layer 401, and a word line layer 403 provided on the ferroelectric base layer 401.
  • each word line of the word line layer 403 extends in the y direction, and a plurality of word lines are sequentially arranged in parallel in the x direction.
  • the word lines 403a1 and 403a2 of the word line layer 403a are arranged in parallel.
  • the word lines 403b1 and 403b2 are arranged in parallel, and the word lines 403c1 and 403c2 of the word line layer 403c are arranged in parallel; a plurality of each of the memory cell arrays 402 (such as the memory cell array 402a, the memory cell array 402b, or the memory cell array 402c)
  • the ferroelectric memory cells are arranged in the row and column directions, for example, in a dot matrix in the x direction and the y direction, and each ferroelectric base layer 401 is arranged in the xy plane.
  • a plurality of ferroelectric memory cells of the memory cell array 402 on each layer of the ferroelectric base layer 401 may be arranged in the form of bumps with respect to them, for example, a plurality of ferroelectric memory cells are convexly arranged relative to the ferroelectric base layer 401.
  • the size of each ferroelectric memory cell (for example, the specific size of the dimension L in the x direction and the dimension W in the y direction) is not limited.
  • the top bit line layer 405 is disposed at a top position, for example, above the word line layer 403 c.
  • the bit line array 404 is arranged substantially perpendicular to the plurality of ferroelectric base layers 401 and is aligned with the top bit
  • the line layer 405 is electrically connected; the bit lines of the top bit line layer 405 may extend in the x direction, and a plurality of bit lines may be arranged substantially in parallel in the y direction.
  • the bit line can be coupled to a read / write circuit outside the ferroelectric memory array structure 40 through the bit line of the top bit line layer 405.
  • each bit line of the bit line array 404 extends in the z direction (for example, it extends downward from its connection position with the top bit line layer 405), and is connected to multiple word line layers.
  • the word lines are spatially orthogonal. In this way, each bit line can be shared by a plurality of ferroelectric memory cells of a multilayer ferroelectric memory cell array correspondingly arranged in a stacking direction thereof.
  • each ferroelectric memory cell two sides in the x direction are adjacent to a word line of a word line layer 403 and a bit line in the bit line array 404, that is, each ferroelectric memory cell is disposed at At the orthogonal positions of the word line and the bit line, they form a crossbar structure according to an example of the present invention.
  • the ferroelectric base layer 401 and a plurality of ferroelectric memory cells thereon can be formed by patterning a ferroelectric single crystal layer or a ferroelectric thin film material layer using a method such as etching.
  • the ferroelectric base layer 401 can be used To form a reference ferroelectric body of a ferroelectric memory cell (for example, it may also be referred to as a “reference cell”), it is adjacent to each ferroelectric memory cell, and a domain wall conductive channel can be established at their approximate adjacencies.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell can be defined as having a component in the x direction. It can also be understood that the initial polarization direction of the electric domain of the memory cell has a certain angle with the ferroelectric base layer 401 but There is a component on the ferroelectric base layer 401, but it cannot be perpendicular to the ferroelectric base layer 401 (for example, not in the z direction). In this way, the polarization direction of the electric domain in the ferroelectric memory cell is not perpendicular to the direction of the electric field of the write voltage signal applied to the word and bit lines on both sides thereof. As shown in FIG.
  • the solid line arrows indicate the initial polarization directions of the electric domains in the ferroelectric memory cell and the ferroelectric base layer 401, which may be parallel to the x direction, for example. It will be understood that the initial polarization direction of the electric domain of each ferroelectric memory cell and its corresponding reference ferroelectric body (such as the ferroelectric base layer 401) is not limited to the direction shown in FIG. The direction is at an angle but is not perpendicular to the x direction, so there is a component in the x direction.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell also has a component in the x direction. It can also be understood that the initial polarization direction has a projection in the x direction.
  • the word line layer 403 may have, but is not limited to, three levels, which are sequentially formed on the ferroelectric base layer 401.
  • the word lines of each level have a plurality of word lines that are substantially parallel to each other and extend along the y direction, and sequentially fill the gaps between adjacent ferroelectric memory cell columns in the x direction.
  • the word line layer 403 may be vertically aligned in the z direction, that is, the word line in each of a plurality of levels may be positioned at the same position in each level so that the word lines of different layers are in the z direction alignment.
  • each ferroelectric memory cell of the memory cell array 402 has a unidirectional conduction characteristic in the on state (ON state). Therefore, when a current is read in the on state (ON state), the ferroelectric The memory cell appears to have a switching characteristic and has a relatively measurable turn-on voltage V on .
  • the ferroelectric memory cell selected by the word line 403b1 and the bit line 4053 as shown in FIG. 1 (f) the polarization direction of the domain of the ferroelectric memory cell is the polarization direction of the reference ferroelectric adjacent to the lower part.
  • conductive domain walls are easily formed at their interfaces, that is, domain wall conductive channels; if the voltage applied to the ferroelectric memory cell is less than the coercive voltage V c and greater than the turn-on voltage V on , if there is a large on-state When the current flows, the stored data can be read as "1"; otherwise, the stored data can be read as "0".
  • the word line 403b1 and the bit line 4053 are selected.
  • the word line 403b1 is configured as a high voltage V write1 , and the value of V write1 is greater than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2, and the bit line 4053 is configured to be grounded.
  • the other bit lines are left floating or configured as a semi-high level V c / 2; in this way, the selected ferroelectric memory cell will be applied with an electric field opposite to its initial polarization direction, and the electric domain of the ferroelectric memory cell is in the x direction
  • the positive direction of is reversed, and the data "1" is written.
  • the direction shown by the hollow arrow is the polarization direction after the domain is reversed.
  • the word line 403b1 and the bit line 4053 may be left floating or configured to a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 40 is continuously selected for writing data "0", for example, the word line 403b1 and the bit line 4053 are selected.
  • the word line 403b1 is configured as ground, and other word lines are left floating or configured as a semi-high level V c / 2;
  • the top bit line 4053 is configured with a high voltage V write0 , and the value of V write0 is greater than the coercive voltage V c of the ferroelectric memory cell; In this way, the selected ferroelectric memory cell will be applied with the same electric field as the initial polarization direction.
  • the electric domain of the ferroelectric memory cell will be reversed in the opposite direction of the x direction, and the data "0" will be written.
  • the direction is the polarization direction after the electric domain is reversed.
  • the word line 403b1 and the bit line 4053 may be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 40 is continuously selected for a read operation (for example, a read operation for reading data "1"), such as a word line 403b1 and a bit line 4053 was selected.
  • the word line 403b1 is configured as a voltage V read1 .
  • the value of V read1 is greater than the turn-on voltage V on and less than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a half-high level V c / 2;
  • the element line 4053 is grounded, and other bit lines are left floating or configured as a half-high level V c / 2.
  • FIG. 2 is a schematic diagram showing a ferroelectric memory array structure and an operating principle of a three-dimensional nonvolatile ferroelectric memory according to a second embodiment of the present invention.
  • FIG. 2 (a) illustrates a three-dimensional structure diagram of the ferroelectric memory array structure 50 of this embodiment
  • FIG. 2 (b) is a top view of the ferroelectric memory array structure 50 without a top bit line layer.
  • FIG. 2 (c) is a cross-sectional view taken along IJ in FIG. 2 (a).
  • FIG. 2 (d) illustrates the operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 50.
  • FIG. 2 (d) illustrates the operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 50.
  • FIG. 2 (e) illustrates the operation principle of writing data “0” to a ferroelectric memory cell of the ferroelectric memory array structure 50
  • FIG. 2 (f) illustrates a ferroelectric to the ferroelectric memory array structure 50. Operation principle of reading data "1" from the memory cell.
  • the ferroelectric memory array structure 50 is included in a three-dimensional non-volatile ferroelectric memory, and corresponding peripheral read-write circuits can be configured accordingly.
  • the specific structure of the peripheral read-write circuits is not restrictive. The present invention is clearly described, and the description of the peripheral read-write circuit is omitted here.
  • the ferroelectric memory array structure 50 may include a plurality of ferroelectric base layers 501 (for example, ferroelectric base layers 501a, 501b, and 501c which are sequentially stacked and stacked from bottom to top), and a multi-layer memory cell array 502 (for example, sequentially stacked from bottom to top) Ground cell arrays 502a, 502b, and 502c), multiple word line layers 503 (e.g., word line layers 503a, 503b, and 503c arranged sequentially stacked from bottom to top), bit line arrays 504 (e.g., bit line arrays 504a and 504b), a top bit line layer 505a, a bottom bit line layer 505b, and a multilayer insulation layer 506.
  • ferroelectric base layers 501 for example, ferroelectric base layers 501a, 501b, and 501c which are sequentially stacked and stacked from bottom to top
  • a multi-layer memory cell array 502 for example, sequentially stacked from bottom to top
  • the uppermost insulating layer 506 can isolate the top bit line layer 505 from the ferroelectric base layer 501 and the like, and the intermediate insulating layer 506 (such as the dielectric layer in the second deep trench) can make multiple word line layers. 503 are isolated from each other; other gaps can be filled with insulating materials.
  • the ferroelectric memory array structure 50 includes a multi-layer ferroelectric memory cell array arranged in a stack, which are sequentially stacked in the z direction, that is, their stacking direction is the z direction; each layer of the ferroelectric memory cell array includes A ferroelectric base layer 501, a memory cell array 502 arranged on the ferroelectric base layer 501, and a word line layer 503 arranged on the ferroelectric base layer 501.
  • Each word line of the word line layer 503 extends in the y direction, and a plurality of word lines are arranged in parallel in the x direction.
  • the word lines 503a1 and 503a2 of the word line layer 503a are arranged in parallel.
  • the word lines 503b1 and 503b2 are arranged in parallel, and the word lines 503c1 and 503c2 of the word line layer 503c are arranged in parallel; a plurality of each of the memory cell arrays 502 (for example, the memory cell array 502a, the memory cell array 502b, or the memory cell array 502c)
  • the ferroelectric memory cells are arranged in the row and column directions, for example, in a lattice pattern in the x and y directions, and each ferroelectric base layer 501 is arranged in the xy plane.
  • a plurality of ferroelectric memory cells of the memory cell array 502 on each layer of the ferroelectric base layer 501 may be arranged in the form of bumps relative to the ferroelectric memory cells.
  • a plurality of ferroelectric memory cells are convexly arranged relative to the ferroelectric base layer 501.
  • the middle word line of the word line array of the word line layer 503 is arranged between two ferroelectric memory cells. In this way, two sides of the word line in the x direction are coupled to two columns of ferroelectric memory cells, respectively, and are shared by the two columns of ferroelectric memory cells. Therefore, compared with the embodiment of FIG. 1, the ferroelectric memory array structure 50 of the three-dimensional nonvolatile ferroelectric memory of the embodiment shown in FIG. 2 can reduce word lines and further increase the storage density.
  • the top bit line layer 505 a is disposed at a top position, for example, above the word line layer 503 c.
  • the bit line array 504 a is disposed substantially perpendicular to the plurality of ferroelectric base layers 501 and is aligned with the top bit
  • the line layer 505a is electrically connected;
  • the bottom bit line layer 505a is disposed at the bottom position, for example, the bottom ferroelectric memory cell array is arranged (for example, under the ferroelectric base layer 501a), and the bit line array 504b is arranged substantially perpendicular to
  • the plurality of ferroelectric base layers 501 are electrically connected to the bottom bit line layer 505b.
  • the bit lines of the top bit line layer 505a and the bottom bit line layer 505b may extend in the x direction, and a plurality of bit lines may be arranged substantially in parallel in the y direction.
  • the bit line can be coupled to a read / write circuit outside the ferroelectric memory array structure 50 through the bit line of the top bit line layer 505a or the bottom bit line layer 505b.
  • the bit line array 504 includes a bit line array 504 a and a bit line array 504 b.
  • Each bit line of the bit line array 504 extends in the z direction.
  • Each bit line of the bit line array 504 a is from Its connection position with the top bit line layer 505a extends downward, and each bit line of the bit line array 504b extends downward from its connection position with the bottom bit line layer 505b; and each bit line is connected to a different word line
  • the multiple word lines of a layer are spatially orthogonal. In this way, each bit line can be shared by a plurality of ferroelectric memory cells of a multilayer ferroelectric memory cell array correspondingly arranged in a stacking direction thereof.
  • each ferroelectric memory cell two sides in the x direction are adjacent to a word line of a word line layer 503 and a bit line in the bit line array 504, that is, each ferroelectric memory cell is disposed at At the orthogonal positions of the word line and the bit line, they form a crossbar structure according to an example of the present invention.
  • the ferroelectric memory cell is arranged adjacent to both sides of the bit line in the x direction.
  • the two sides of the bit line in the x direction are respectively coupled with two in-line ferroelectric memory cells arranged correspondingly on z and shared by the two in-line ferroelectric memory cells. Therefore, compared with the embodiment in FIG. 1, the ferroelectric memory array structure 50 of the three-dimensional nonvolatile ferroelectric memory in the embodiment shown in FIG. 2 can reduce bit lines and further increase the storage density.
  • the ferroelectric base layer 501 and a plurality of ferroelectric memory cells thereon can be formed by patterning a ferroelectric single crystal layer or a ferroelectric thin film material layer using a method such as etching.
  • the ferroelectric base layer 501 can be used To form a reference ferroelectric body of a ferroelectric memory cell (for example, it may also be referred to as a “reference cell”), it is adjacent to each ferroelectric memory cell, and a domain wall conductive channel can be established at their approximate adjacencies.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell can be defined as having a component in the x direction. It can also be understood that the initial polarization direction of the electric domain of the memory cell has a certain angle with the ferroelectric base layer 501 but There is a component on the ferroelectric base layer 501, but it cannot be perpendicular to the ferroelectric base layer 501 (for example, not in the z direction). In this way, the polarization direction of the electric domain in the ferroelectric memory cell is not perpendicular to the direction of the electric field of the write voltage signal applied to the word and bit lines on both sides thereof. As shown in FIG.
  • the solid line arrows indicate the initial polarization directions of the electric domains in the ferroelectric memory cell and the ferroelectric base layer 501, which may be parallel to the x direction, for example. It will be understood that the initial polarization direction of the electric domain of each ferroelectric memory cell and its corresponding reference ferroelectric body (such as the ferroelectric base layer 501) is not limited to the direction shown in FIG. The direction is at an angle but is not perpendicular to the x direction, so there is a component in the x direction.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell also has a component in the x direction. It can also be understood that the initial polarization direction has a projection in the x direction.
  • the word line layer 503 may have, but is not limited to, three levels, which are sequentially formed on the ferroelectric base layer 501.
  • the word lines of each level have a plurality of word lines extending substantially in parallel with each other along the y-direction, and sequentially fill gaps between adjacent ferroelectric memory cell columns in the x-direction.
  • the word line layer 503 may be vertically aligned in the z direction, that is, the word line in each of a plurality of levels may be positioned at the same position in each level so that the word lines of different layers are in the z direction Alignment (for example, the word lines 503a2, 503b2, and 503c2 are substantially aligned with each other in the z direction).
  • each ferroelectric memory cell of the memory cell array 502 has a unidirectional conduction characteristic in the on state (ON state). Therefore, when a current is read in the on state (ON state), the ferroelectric The memory cell appears to have a switching characteristic and has a relatively measurable turn-on voltage V on .
  • the domain polarization direction of the ferroelectric memory cell is the polarization direction of the reference ferroelectric adjacent to the lower part.
  • conductive domain walls are easily formed at their interfaces, that is, domain wall conductive channels; if the voltage applied to the ferroelectric memory cell is less than the coercive voltage V c and greater than the turn-on voltage V on , if there is a large on-state When the current flows, the stored data can be read as "1"; otherwise, the stored data can be read as "0".
  • the word line 503b1 and the bit line 505b3 are selected.
  • the word line 503b1 is configured as a high voltage V write1 , and the value of V write1 is greater than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2.
  • the bit line 505b3 is configured to be grounded.
  • the other bit lines are left floating or configured as a semi-high level V c / 2; in this way, the selected ferroelectric memory cell will be applied with an electric field opposite to its initial polarization direction, and the electric domain of the ferroelectric memory cell is in the x direction
  • the positive direction of is reversed, and the data "1" is written.
  • the direction shown by the hollow arrow is the polarization direction after the domain is reversed.
  • the word line 503b1 and the bit line 505b3 may be left floating or configured to a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 50 is continuously selected for writing data "0", for example, the word line 503b1 and the bit line 505b3 are selected.
  • the word line 503b1 is configured to be grounded, and other word lines are left floating or configured to a half-high level V c / 2;
  • the top bit line 505b3 is configured to have a high voltage V write0 , and the value of V write0 is greater than the coercive voltage V c of the ferroelectric memory cell; In this way, the selected ferroelectric memory cell will be applied with the same electric field as the initial polarization direction.
  • the electric domain of the ferroelectric memory cell will be reversed in the opposite direction of the x direction, and the data "0" will be written.
  • the direction is the polarization direction after the electric domain is reversed.
  • the word line 503b1 and the bit line 505b3 can be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 50 continues to be selected for a read operation (for example, a read operation for reading data "1"), such as a word line 503b1 and a bit line 505b3 was selected.
  • the configuration word line 503b1 is a voltage V read1 , and the value of V read1 is greater than the turn-on voltage V on and less than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a half-high level V c / 2;
  • the element line 505b3 is grounded, and the other bit lines are left floating or configured as a half-high level V c / 2.
  • FIG. 3 is a schematic diagram showing a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a third embodiment of the present invention.
  • FIG. 3 (a) illustrates a three-dimensional structure diagram of the ferroelectric memory array structure 60 of this embodiment
  • FIG. 3 (b) is a top view of the ferroelectric memory array structure 60 without a top bit line layer.
  • 3 (c) is a cross-sectional view taken along IJ in FIG. 3 (a)
  • FIG. 3 (d) illustrates the operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 60.
  • FIG. 3 (d) illustrates the operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 60.
  • FIG. 3 (e) illustrates the operation principle of writing data “0” to a ferroelectric memory cell of the ferroelectric memory array structure 60
  • FIG. 3 (f) illustrates a ferroelectric to the ferroelectric memory array structure 60. Operation principle of reading data "1" from the memory cell.
  • the ferroelectric memory array structure 60 is included in a three-dimensional non-volatile ferroelectric memory, and corresponding peripheral read-write circuits can be configured accordingly.
  • the specific structure of the peripheral read-write circuits is not restrictive. The present invention is clearly described, and the description of the peripheral read-write circuit is omitted here.
  • the ferroelectric memory array structure 60 may include: a ferroelectric base layer 601, a multi-layer memory cell array 602, and a plurality of word line layers 603 (for example, word line layers 603a, 603b, 603c, and 603d that are sequentially stacked from bottom to top) , A bit line array 604, a top bit line layer 605, and a multilayer insulation layer 606.
  • the uppermost insulating layer 606 can isolate the top bit line layer 605 from the ferroelectric base layer 601 and the like, and the intermediate insulating layer 606 can isolate the upper and lower adjacent word line layers 603 from each other; other gaps can be Fill with insulating material.
  • a ferroelectric base layer 601 and a multi-layer memory cell array 602 may be integrally formed by the same ferroelectric single crystal layer or a ferroelectric thin film layer, thereby forming a multi-layer ferroelectric memory cell with a 3D structure.
  • arraying it can greatly reduce the number of depositions of ferroelectric single crystal layers or ferroelectric thin film layers, simplify the process and reduce costs; for example, thicker ferroelectric single crystal layers or ferroelectric thin film layers are formed by one deposition or growth.
  • the electric single crystal layer or the ferroelectric thin film layer is patterned to form a plurality of deep grooves; the ferroelectric body between the deep grooves can be operated to form a plurality of ferroelectric memory cells of the multi-layer memory cell array 602.
  • the ferroelectric body between the ferroelectric memory cells can be used to form a reference ferroelectric body.
  • the ferroelectric memory cell can be programmed to form a left-right domain wall conductive channel with the reference ferroelectric body.
  • the domain wall conductive channel can be used to electrically Connect the word and bit lines on its left and right sides.
  • At least the ferroelectric single crystal layer or the ferroelectric thin film layer used to form the ferroelectric base layer 601 may be patterned with a first deep groove (or deep hole) and a second deep groove extending in the stacking direction. Deep grooves.
  • the bit lines of the bit line array 604 are formed in the first deep groove.
  • Multiple word lines (for example, bit lines 603a1, 603b1, 603c1, and 603d1) that belong to different word line layers 603 are formed in the same second deep groove.
  • a dielectric layer for isolating multiple word lines is formed in the second deep groove. In this way, the upper and lower adjacent word lines in the second deep groove are separated by the dielectric layer in the second deep groove.
  • the dielectric layer can A part of the functions of the insulating layer 606 is realized.
  • the ferroelectric memory array structure 60 can also include a multilayer ferroelectric memory cell array arranged in a stack (although there is no substantial physical layered interface between the multilayer memory cell array 602), they are stacked in the z direction; each layer of the ferroelectric memory cell array corresponds to It includes a layer of memory cell array 602 at a certain height in the z direction, and a word line layer 603 corresponding to the height.
  • each word line of the word line layer 603 extends in the y direction, and a plurality of word lines are arranged in parallel in the x direction in sequence; a plurality of ferroelectric memory cells in each layer of the memory cell array 602 are arranged in rows in the xy plane. Aligned with the column direction, each layer of reference ferroelectrics is also arranged in the row and column directions in the xy plane.
  • the top bit line layer 605 is disposed at the top position, for example, above the word line layer 603d, and the bit line array 604 is arranged substantially perpendicular to the plurality of ferroelectric base layers 601 and is aligned with the top bit
  • the line layer 605 is electrically connected.
  • a plurality of bit lines (for example, bit lines 6051, 6052, 6053, 6054, and 6055) of the top bit line layer 605 may extend in the x direction, and the plurality of bit lines may be arranged substantially in parallel in the y direction.
  • the bit line can be coupled to the read / write circuit outside the ferroelectric memory array structure 60 through the bit line of the top bit line layer 605.
  • each bit line of the bit line array 604 extends downward from its connection position with the top bit line layer 605 and is formed in a first deep trench between the memory cell arrays 602; and, each The bit lines are spatially orthogonal to multiple word lines of different word line layers. In this way, each bit line can be shared by a plurality of ferroelectric memory cells of a multilayer ferroelectric memory cell array correspondingly arranged in a stacking direction thereof.
  • each ferroelectric memory cell two sides in the x direction are adjacent to a word line of a word line layer 603 and a bit line in the bit line array 604, that is, corresponding to an orthogonal word line and a
  • the ferroelectric body between the bit lines forms a ferroelectric memory cell according to an embodiment of the present invention; similarly, each ferroelectric memory cell is disposed on a word line and At the orthogonal positions of the bit lines, they form an exemplary Crossbar structure of the present invention.
  • the corresponding ferroelectric body between the orthogonal bit line and the dielectric layer forms a reference ferroelectric body according to an embodiment of the present invention.
  • the reference ferroelectric body is adjacent to the ferroelectric storage unit in the vertical direction.
  • the plurality of reference ferroelectrics and the plurality of ferroelectric memory cells which are alternately arranged in the up-down direction are all formed by a unified ferroelectric body between the first deep groove and the second deep groove;
  • the adjacent ferroelectric portion of the dielectric layer in the slot corresponds to the reference ferroelectric, and the adjacent ferroelectric portion corresponding to the word line in the second deep slot is a ferroelectric memory cell.
  • the bit lines are adjacently arranged with ferroelectric memory cells on both sides in the x direction.
  • the two sides of the bit line in the x direction are respectively coupled with two in-line ferroelectric memory cells arranged correspondingly on z and shared by the two in-line ferroelectric memory cells. Therefore, compared with the embodiment of FIG. 1, the ferroelectric memory array structure 60 of the three-dimensional nonvolatile ferroelectric memory of the embodiment shown in FIG. 3 can reduce bit lines and further increase the storage density.
  • the middle word line of the word line array of the word line layer 603 is arranged between two ferroelectric memory cells In this way, two sides of the word line in the x direction are respectively coupled to two columns of ferroelectric memory cells and shared by the two columns of ferroelectric memory cells. Therefore, compared with the embodiment of FIG. 1, the ferroelectric memory array structure 60 of the three-dimensional nonvolatile ferroelectric memory of the embodiment shown in FIG. 3 can reduce word lines and further increase the storage density.
  • the ferroelectric memory array structure 60 can reduce the number of ferroelectric base layers 601; at the same time, a thicker ferroelectric single crystal layer can be generated or deposited at one time. Or ferroelectric thin film layers.
  • the ferroelectric memory cells in different layers of ferroelectric memory cell arrays and the reference ferroelectric body are more consistent in terms of performance (such as ferroelectric performance, etc.).
  • Good consistency on the other hand, can greatly reduce defects in ferroelectric memory cells and reference ferroelectrics, reduce invalid memory cells, and improve memory yield.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell can be defined as having a component in the x direction, and it can also be understood that the initial polarization direction of the electric domain of the memory cell exists with the ferroelectric base layer 601. A certain included angle has a component on the ferroelectric base layer 601, but may not be perpendicular to the ferroelectric base layer 601 (for example, not in the z direction). In this way, the polarization direction of the electric domain in the ferroelectric memory cell is not perpendicular to the direction of the electric field of the write voltage signal applied to the word and bit lines on both sides thereof. As shown in FIG.
  • the solid-line arrows indicate the initial polarization directions of the electric domains in the ferroelectric memory cell and the ferroelectric base layer 601, which may be parallel to the x direction, for example. It will be understood that the initial polarization direction of the electric domain of each ferroelectric memory cell and its corresponding reference ferroelectric body (such as the ferroelectric base layer 601) is not limited to the direction shown in FIG. The direction is at an angle but is not perpendicular to the x direction, so there is a component in the x direction.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell also has a component in the x direction. It can also be understood that the initial polarization direction has a projection in the x direction.
  • each ferroelectric memory cell of the memory cell array 602 has a unidirectional conduction characteristic in the on state (ON state). Therefore, when the current is read in the on state (ON state), the ferroelectric The memory cell appears to have a switching characteristic and has a relatively measurable turn-on voltage V on .
  • the ferroelectric memory cell selected by the word line 603b1 and the bit line 6055 as shown in FIG. 3 (f) the ferroelectric memory cell has a domain polarization direction that is adjacent to the reference ferroelectric body below and / or above.
  • the polarization direction is opposite, and it is easy to form conductive domain walls (such as two) at their interfaces, that is, domain wall conductive channels; the voltage applied to the ferroelectric memory cell is less than the coercive voltage V c and greater than the turn-on voltage V on Next, if a large on-state current flows, the stored data can be read as "1", otherwise, the stored data is read as "0".
  • the word line 603b1 and the bit line 6055 are selected.
  • the word line 603b1 is configured as a high voltage V write1 , and the value of V write1 is greater than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2.
  • the bit line 6055 is configured to be grounded.
  • the other bit lines are left floating or configured as a semi-high level V c / 2; in this way, the selected ferroelectric memory cell will be applied with an electric field opposite to its initial polarization direction, and the electric domain of the ferroelectric memory cell is in the x direction The positive direction of is reversed, and the data "1" is written. The direction shown by the hollow arrow is the polarization direction after the domain is reversed. After the writing of the data “1”, the word line 603b1 and the bit line 6055 can be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 60 is continuously selected for writing data "0", for example, the word line 603b1 and the bit line 6055 are selected.
  • the word line 603b1 is configured as ground, and other word lines are left floating or configured as a half-high level V c / 2;
  • the top bit line 6055 is configured with a high voltage V write0 , and the value of V write0 is greater than the coercive voltage V c of the ferroelectric memory cell; In this way, the selected ferroelectric memory cell will be applied with the same electric field as the initial polarization direction.
  • the electric domain of the ferroelectric memory cell will be reversed in the opposite direction of the x direction, and the data "0" will be written.
  • the direction is the polarization direction after the electric domain is reversed.
  • the word line 603b1 and the bit line 6055 can be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 60 is continuously selected for a read operation (for example, a read operation for reading data "1"), such as a word line 603b1 and a bit line 6055 is selected.
  • the configuration word line 603b1 is a voltage V read1 , and the value of V read1 is greater than the turn-on voltage V on and less than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2;
  • the element line 6055 is grounded, and the other bit lines are left floating or configured as a half-high level V c / 2.
  • FIG. 4 is a schematic diagram showing a ferroelectric memory array structure and an operation principle of a three-dimensional nonvolatile ferroelectric memory according to a fourth embodiment of the present invention.
  • FIG. 4 (a) schematically illustrates the three-dimensional structure of the ferroelectric memory array structure 70 of this embodiment
  • FIG. 4 (b) is a top view of the ferroelectric memory array structure 70 without a top bit line layer.
  • 4 (c) is a cross-sectional view taken along IJ in FIG. 4 (a)
  • FIG. 4 (d) illustrates an operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 70.
  • FIG. 4 (d) illustrates an operation of writing data "1" to a ferroelectric memory cell of the ferroelectric memory array structure 70.
  • FIG. 4 (e) illustrates the operation principle of writing data “0” to a ferroelectric memory cell of the ferroelectric memory array structure 70
  • FIG. 4 (f) illustrates a ferroelectric to the ferroelectric memory array structure 70. Operation principle of reading data "1" from the memory cell.
  • the ferroelectric memory array structure 70 is included in a three-dimensional nonvolatile ferroelectric memory, and corresponding peripheral read-write circuits can be configured accordingly.
  • the specific structure of the peripheral read-write circuits is not restrictive. The present invention is clearly described, and the description of the peripheral read-write circuit is omitted here.
  • the ferroelectric memory array structure 70 may include: a ferroelectric base layer 701, a multi-layer memory cell array 702, and a plurality of word line layers 703 (for example, word line layers 703a, 703b, 703c, and 703d, which are sequentially stacked from bottom to top) , A bit line array 704 (eg, bit line arrays 704a and 704b), a top bit line layer 705a, a bottom bit line layer 705ab, and a multilayer insulation layer 706.
  • the uppermost insulating layer 706 can isolate the top bit line layer 705a from the ferroelectric base layer 701 and the like, and the intermediate insulating layer 706 (such as a dielectric layer) can make the upper and lower adjacent word line layers 703 each other. Isolation; other gaps can be filled with insulating material.
  • a ferroelectric base layer 701 and a multi-layer memory cell array 702 may be integrally formed by the same ferroelectric single crystal layer or a ferroelectric thin film layer, thereby forming a multi-layer ferroelectric memory cell with a 3D structure.
  • arraying it can greatly reduce the number of depositions of ferroelectric single crystal layers or ferroelectric thin film layers, simplify the process and reduce costs; for example, thicker ferroelectric single crystal layers or ferroelectric thin film layers are formed by one deposition or growth.
  • the electric single crystal layer or the ferroelectric thin film layer is patterned to form a plurality of deep grooves; the ferroelectric body between the deep grooves can be operated to form a plurality of ferroelectric memory cells of the multilayer memory cell array 702, which are adjacent to each other
  • the ferroelectric body between the ferroelectric memory cells can be used to form a reference ferroelectric body.
  • the ferroelectric memory cell can be programmed to form a left-right domain wall conductive channel with the reference ferroelectric body.
  • the domain wall conductive channel can be used to electrically Connect the word and bit lines on its left and right sides.
  • At least the ferroelectric single crystal layer or the ferroelectric thin film layer used to form the ferroelectric base layer 701 may be patterned with a first deep groove (or deep hole) and a second deep groove extending in the stacking direction. Deep grooves.
  • the bit lines of the bit line array 704 are formed in the first deep groove.
  • Multiple word lines (for example, bit lines 703a1, 703b1, 703c1, and 703d1) that belong to different word line layers 704 are formed in the same second deep groove.
  • a dielectric layer for isolating multiple word lines is formed in the second deep groove. In this way, the upper and lower adjacent word lines in the second deep groove are separated by the dielectric layer in the second deep groove.
  • the dielectric layer can A part of the functions of the insulating layer 706 is realized.
  • the ferroelectric memory array structure 70 can also include a multilayer ferroelectric memory cell array arranged in a stack (although there is no substantial physical layered interface between the multilayer memory cell arrays 702), they are stacked in the z direction; each layer of the ferroelectric memory cell array corresponds to It includes a layer of memory cell array 702 at a certain height in the z direction, and a word line layer 703 corresponding to the height.
  • each word line of the word line layer 703 extends in the y direction, and a plurality of word lines are arranged in parallel in the x direction in sequence; a plurality of ferroelectric memory cells in each layer of the memory cell array 702 are arranged in rows in the xy plane. Aligned with the column direction, each layer of reference ferroelectrics is also arranged in the row and column directions in the xy plane.
  • the top bit line layer 705 a is disposed at a top position, for example, above the word line layer 703 d.
  • the bit line array 704 a is disposed substantially perpendicular to the plurality of ferroelectric base layers 701 and is aligned with the top bit
  • the wire layer 705a is electrically connected;
  • the bottom bit line layer 705 a is disposed at a bottom position, for example, the bottom ferroelectric memory cell array is arranged (eg, below the ferroelectric base layer 701), and the bit line array 704 b is arranged substantially perpendicular to the plurality of ferroelectric base layers 501. And is electrically connected to the bottom bit line layer 705b.
  • bit lines of the top bit line layer 705a can extend in the x direction
  • multiple bit lines of the bottom bit line layer 705b can extend in the x direction, where a plurality of bit lines can be arranged in parallel in the y direction in order.
  • the bit line can be coupled to the read / write circuit outside the ferroelectric memory array structure 70 through the bit line of the top bit line layer 705a or the bottom bit line layer 705b.
  • each bit line of the bit line array 704 a extends downward from its connection position with the top bit line layer 705 a and is formed in a first deep trench between the memory cell arrays 702.
  • Each bit line of 704b extends upward from its connection position with the bottom bit line layer 705b and is formed in a first deep groove between the memory cell arrays 702; the bit lines of the bit line array 704a and the bits of the bit line array 704b
  • the lines are alternately arranged in the x direction; and each bit line is spatially orthogonal to a plurality of word lines of different word line layers.
  • each bit line can be shared by a plurality of ferroelectric memory cells of a multilayer ferroelectric memory cell array correspondingly arranged in a stacking direction thereof.
  • two sides in the x direction are adjacent to a word line of a word line layer 703 and a bit line in the bit line array 704, that is, corresponding to an orthogonal word line and a
  • the ferroelectric body between the bit lines forms a ferroelectric memory cell according to an embodiment of the present invention; similarly, each ferroelectric memory cell is disposed on a word line and At the orthogonal positions of the bit lines, they form an exemplary Crossbar structure of the present invention.
  • the corresponding ferroelectric body between the orthogonal bit line and the dielectric layer forms a reference ferroelectric body according to an embodiment of the present invention.
  • the reference ferroelectric body is adjacent to the ferroelectric storage unit in the vertical direction.
  • the plurality of reference ferroelectrics and the plurality of ferroelectric memory cells which are alternately arranged in the up-down direction are all formed by a unified ferroelectric body between the first deep groove and the second deep groove;
  • the adjacent ferroelectric portion of the dielectric layer in the slot corresponds to the reference ferroelectric, and the adjacent ferroelectric portion corresponding to the word line in the second deep slot is a ferroelectric memory cell.
  • the ferroelectric memory array structure 70 of the three-dimensional nonvolatile ferroelectric memory of the embodiment shown in FIG. 4 can reduce word lines and bit lines, and further increase the storage density.
  • the ferroelectric memory array structure 70 can reduce the number of ferroelectric base layers 701; at the same time, a thicker ferroelectric single crystal layer can be generated or deposited at one time. Or ferroelectric thin film layers.
  • the ferroelectric memory cells in different layers of ferroelectric memory cell arrays and the reference ferroelectric body are more consistent in terms of performance (such as ferroelectric performance, etc.).
  • Good consistency on the other hand, can greatly reduce defects in ferroelectric memory cells and reference ferroelectrics, reduce invalid memory cells, and improve memory yield.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell can be defined as having a component in the x direction, and it can also be understood that the initial polarization direction of the electric domain of the memory cell and the ferroelectric base layer 701 exist A certain included angle has a component on the ferroelectric base layer 701, but cannot be perpendicular to the ferroelectric base layer 701 (for example, not in the z direction). In this way, the polarization direction of the electric domain in the ferroelectric memory cell is not perpendicular to the direction of the electric field of the write voltage signal applied to the word and bit lines on both sides thereof. As shown in FIG.
  • the solid line arrows indicate the initial polarization directions of the electric domains in the ferroelectric memory cell and the ferroelectric base layer 701, which may be parallel to the x direction, for example.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell and its corresponding reference ferroelectric body is not limited to the direction shown in FIG. 4, for example, it may also be related to x
  • the direction is at an angle but is not perpendicular to the x direction, so there is a component in the x direction.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell also has a component in the x direction. It can also be understood that the initial polarization direction has a projection in the x direction.
  • each ferroelectric memory cell of the memory cell array 702 has a unidirectional conduction characteristic in the on state (ON state). Therefore, when a current is read in the on state (ON state), the ferroelectric The memory cell appears to have a switching characteristic and has a relatively measurable turn-on voltage V on .
  • the ferroelectric memory cell For the ferroelectric memory cell selected by the word line 703b1 and the bit line 705a5 as shown in FIG. 4 (f), the ferroelectric memory cell has the domain polarization direction of the reference ferroelectric adjoining below and / or above.
  • the polarization direction is opposite, and it is easy to form conductive domain walls (such as two) at their interfaces, that is, domain wall conductive channels; the voltage applied to the ferroelectric memory cell is less than the coercive voltage V c and greater than the turn-on voltage V on Next, if a large on-state current flows, the stored data can be read as "1", otherwise, the stored data is read as "0".
  • the word line 703b1 and the bit line 705a5 are selected.
  • the word line 703b1 is configured as a high voltage V write1 , and the value of V write1 is greater than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2.
  • the bit line 705a5 is configured to be grounded.
  • the other bit lines are left floating or configured as a semi-high level V c / 2; in this way, the selected ferroelectric memory cell will be applied with an electric field opposite to its initial polarization direction, and the electric domain of the ferroelectric memory cell is in the x direction
  • the positive direction of is reversed, and the data "1" is written.
  • the direction shown by the hollow arrow is the polarization direction after the domain is reversed.
  • the word line 703b1 and the bit line 705a5 may be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 70 is continuously selected for writing data "0", for example, the word line 703b1 and the bit line 705a5 are selected.
  • the word line 703b1 is configured as ground, and other word lines are left floating or configured as a half-high level V c / 2;
  • the top bit line 705a5 is configured with a high voltage V write0 , and the value of V write0 is greater than the coercive voltage V c of the ferroelectric memory cell; In this way, the selected ferroelectric memory cell will be applied with the same electric field as the initial polarization direction.
  • the electric domain of the ferroelectric memory cell will be reversed in the opposite direction of the x direction, and the data "0" will be written.
  • the direction is the polarization direction after the electric domain is reversed.
  • the word line 703b1 and the bit line 705a5 may be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 70 is continuously selected for a read operation (for example, a read operation for reading data "1"), such as a word line 703b1 and a bit line 705a5 was selected.
  • the configuration word line 703b1 is a voltage V read1 , and the value of V read1 is greater than the turn-on voltage V on and less than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2;
  • the element line 705a5 is grounded, and the other bit lines are left floating or configured as a half-high level V c / 2.
  • the selected ferroelectric memory cell Due to the existence of domain-wall conductive channels between the selected ferroelectric memory cell and the reference ferroelectric body (such as the ferroelectric base layer 701b) (as indicated by the solid black line in Figure 4 (f)), there is a large on-state current (for example, It can reach 10 -7 A to 10 -6 A), so that the data stored in the selected ferroelectric memory cell can be read as "1".
  • the word line 703b1 and the bit line 705a5 may be left floating or configured as a half-high level V c / 2.
  • the data state corresponding to the disappearance of the domain wall can be read, for example, the data "0".
  • a very small off-state current is read, that is, the stored data "0" is read.
  • FIG. 5 is a schematic diagram showing a ferroelectric memory array structure and its operating principle of a three-dimensional nonvolatile ferroelectric memory according to a fifth embodiment of the present invention.
  • FIG. 5 (a) illustrates a three-dimensional structure diagram of the ferroelectric memory array structure 80 of this embodiment
  • FIG. 5 (b) is a cross-sectional view taken along IJ in FIG. 5 (a).
  • FIG. 5 (c) illustrates the operation principle of writing data “1” to a ferroelectric memory cell of the ferroelectric memory array structure 80
  • FIG. 5 (d) illustrates a ferroelectric memory cell of the ferroelectric memory array structure 80
  • FIG. 5 (e) illustrates the operation principle diagram of reading data “1” to a ferroelectric memory cell of the ferroelectric memory array structure 80.
  • the ferroelectric memory array structure 80 is included in a three-dimensional non-volatile ferroelectric memory, and corresponding peripheral read-write circuits can be configured.
  • the specific structure of the peripheral read-write circuits is not restrictive. The present invention is clearly described, and the description of the peripheral read-write circuit is omitted here.
  • the ferroelectric memory array structure 80 may include a plurality of ferroelectric thin film layers 801 (for example, ferroelectric thin film layers 801a, 801b, and 801c which are sequentially stacked from bottom to top), and correspondingly formed in the multilayer ferroelectric thin film layers 801, respectively.
  • Multi-layer memory cell array 802 multiple word line layers 803 (e.g., word line layers 803a, 803b, and 803c sequentially stacked from bottom to top), multiple bit line layers 804 (e.g., bits stacked sequentially from bottom to top Line layers 804a, 804b, and 804c) and a plurality of insulating layers 806.
  • the ferroelectric memory array structure 80 includes a multilayer ferroelectric memory cell array arranged in a stack, which are sequentially stacked in the z direction, that is, their stacking direction is the z direction; each layer of the ferroelectric memory cell array correspondingly includes A bit line layer 804, a ferroelectric thin film layer 801, a word line layer 803, and an insulating layer 806.
  • each word line of each word line layer 803 extends in the y direction, and a plurality of word lines are sequentially arranged in parallel in the x direction, for example, the word lines 803a1, 803a2, 803a3, and 803a4 of the word line layer 803a are arranged in parallel.
  • the word lines 803c1, 803c2, 803c3, and 803c4 of the word line layer 803c are arranged in parallel; each bit line of each bit line layer 804 extends in the x direction, and multiple bit lines are arranged in parallel in the y direction, for example
  • the bit lines 804a1, 804a2, 804a3, and 804a4 of the bit line layer 804a are arranged in parallel, and the bit lines 804c1, 804c2, 804c3, and 804c4 of the bit line layer 804c are arranged in parallel.
  • the bit line and the word line are spatially orthogonal, and at corresponding orthogonal positions of the word line and the bit line, the ferroelectric memory in the ferroelectric thin film layer 801 forms the memory cell array 802.
  • Cells and ferroelectric memory cells may be formed in the ferroelectric thin film layer 801 in rows and columns.
  • the word lines, ferroelectric memory cells, and bit lines form an example Crossbar structure of the present invention.
  • a plurality of ferroelectric memory cells in each layer of the memory cell array 802 are arranged in the row and column directions, for example, a dot matrix is arranged in the x direction and the y direction, and each ferroelectric thin film layer 801 is arranged in the xy plane.
  • the part other than the ferroelectric memory cell in the ferroelectric thin film layer 801 may be used as a reference ferroelectric body (for example, it may also be referred to as a “reference cell”), which is adjacent to each ferroelectric memory cell.
  • Their approximate adjacencies can establish domain wall conductive channels.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell can be defined as having a component in the x direction. It can also be understood that the initial polarization direction of the electric domain of the memory cell has a certain angle with the ferroelectric thin film layer 801, but There is a component on the ferroelectric thin film layer 801, but it cannot be perpendicular to the ferroelectric thin film layer 801 (for example, not in the z direction). In this way, the polarization direction of the electric domain in the ferroelectric memory cell is not perpendicular to the direction of the electric field of the write voltage signal applied to the word and bit lines on both sides thereof. As shown in FIG.
  • the solid line arrows indicate the initial polarization directions of the electric domains in the ferroelectric memory cell and the ferroelectric thin film layer 801, which may be parallel to the z direction, for example.
  • the initial polarization direction of the electric domain of each ferroelectric memory cell and its corresponding reference ferroelectric body is not limited to the direction shown in FIG. 5, for example, it may also be related to z The direction is at an angle but is not perpendicular to the z direction, so that there is a component in the z direction.
  • the ferroelectric thin film layer 801, the word line layer 803, and the bit line layer 804 may have, but are not limited to, three levels.
  • the word line layer 803 may be vertically aligned in the z direction, that is, the word line in each of a plurality of levels may be positioned at the same position in each level so that the word lines of different layers are in the z direction Alignment;
  • the bit line layer 804 may be vertically aligned in the z direction, that is, the bit line in each of a plurality of levels may be positioned at the same position in each level so that the bit lines of different layers are at Aligned in the z direction.
  • each ferroelectric memory cell of the memory cell array 802 has a unidirectional conduction characteristic in an on state (ON state). Therefore, when a current is read in the on state (ON state), the ferroelectric The memory cell appears to have a switching characteristic and has a relatively measurable turn-on voltage V on .
  • the polarization direction of the domain of the ferroelectric memory cell is the polarization direction of the reference ferroelectric adjacent to the lower part.
  • conductive domain walls are easily formed at their interfaces, that is, domain wall conductive channels; if the voltage applied to the ferroelectric memory cell is less than the coercive voltage V c and greater than the turn-on voltage V on , if there is a large on-state When the current flows, the stored data can be read as "1"; otherwise, the stored data can be read as "0".
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 80 is selected for writing data "1", for example, a word line 803b1 and a bit line 804c4 are selected.
  • the word line 803b1 is configured as a high voltage V write1 , and the value of V write1 is greater than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a semi-high level V c / 2, and the bit line 804c4 is configured to be grounded.
  • the other bit lines are left floating or configured as a semi-high level V c / 2; in this way, the selected ferroelectric memory cell will be applied with an electric field opposite to its initial polarization direction, and the electric domain of the ferroelectric memory cell is in the x direction The positive direction of is reversed, and the data "1" is written. The direction shown by the hollow arrow is the polarization direction after the domain is reversed. After the writing of the data “1”, the word line 803b1 and the bit line 804c4 can be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 80 is continuously selected for writing data "0", for example, the word line 803b1 and the bit line 804c4 are selected.
  • the word line 803b1 is configured as ground, and other word lines are left floating or configured as a half-high level V c / 2;
  • the top bit line 804c4 is configured with a high voltage V write0 , and the value of V write0 is greater than the coercive voltage V c of the ferroelectric memory cell; In this way, the selected ferroelectric memory cell will be applied with the same electric field as the initial polarization direction.
  • the electric domain of the ferroelectric memory cell will be reversed in the opposite direction of the x direction, and the data "0" will be written.
  • the direction is the polarization direction after the electric domain is reversed.
  • the word line 803b1 and the bit line 804c4 may be left floating or configured as a half-high level V c / 2.
  • a certain ferroelectric memory cell of the ferroelectric memory array structure 80 is continuously selected for a read operation (for example, a read operation for reading data "1"), such as a word line 803b1 and a bit line 804c4 was selected.
  • the configuration word line 803b1 is a voltage V read1 , and the value of V read1 is greater than the turn-on voltage V on and less than the coercive voltage V c of the ferroelectric memory cell.
  • the other word lines are left floating or configured as a half-high level V c / 2;
  • the element line 804c4 is grounded, and the other bit lines are left floating or configured as a half-high level V c / 2.
  • the unidirectional conduction characteristics of the ferroelectric memory cells of the 3D non-volatile ferroelectric memory of the above embodiments of the present invention greatly reduce the proximity storage of the selected ferroelectric memory cells, especially during read operations. Units generate crosstalk and have low leakage power consumption; therefore, for ferroelectric memory cells, gates or switches can be directly omitted, and the Crossbar structure becomes simpler and lower in cost.
  • ferroelectric memory array structure 40-80 using the Crossbar structure in the above embodiments can completely realize the three-dimensional stacking of the multi-layer ferroelectric memory cell array, which greatly improves the storage density and significantly reduces the manufacturing cost per unit storage capacity.
  • the number of layers of the ferroelectric memory cell array stacked in the ferroelectric memory array structure 40 is not limitative. Yes, those skilled in the art can select the number of layers of the ferroelectric memory cell array according to requirements such as storage density; of course, two or more ferroelectric memory array structures 40 can also be stacked in the z direction to improve storage. density.
  • the ferroelectric material used in the ferroelectric memory cell and / or the ferroelectric single crystal layer or ferroelectric thin film layer of the reference ferroelectric body is selected as follows One or more of:
  • the ferroelectric material is lithium tantalate LiTaO 3 , lithium niobate LiNbO 3 or bismuth ferrite BiFeO 3 ,
  • Doping selected from MgO, Mn 2 O 5, Fe 2 O 3, La 2 O 3 is one kind or more of salts of lithium tantalate LiTaO 3, lithium niobate LiNbO 3 or bismuth ferrate BiFeO 3,
  • a single ferroelectric memory cell having a size of 200 ⁇ 200 nm 2 was successfully prepared on an X-cut 5% Mg-doped lithium niobate (LiNbO 3 ) single crystal surface; FIG.
  • FIG a shows that the size is 200 Atomic force morphology of ⁇ 200nm 2 memory cell, with the left and right electrodes (L and R) connected at both ends of the device;
  • Figure 9b is an in-plane piezoelectric imaging, by applying a write greater than the coercive voltage (Vc) on the L and R electrodes
  • Vc coercive voltage
  • Fig. 6 (a) shows the SEM image of two other ferroelectric memory cells prepared on the surface of the LiNbO 3 single crystal.
  • the gaps (g) between the right electrode and the ferroelectric memory cell are 0nm (Fig. 6 ( (a) top left) and 49nm (bottom left of Figure 6 (a)).
  • FIG. 6 (a) shows the current-voltage (IV) curve measured by writing "1" (black curve) and "0" (gray curve) information of the above two devices at +/- 12V, respectively.
  • the above research results prove that the turn-on voltage V on is adjustable, and the measurement results in Fig. 6 (b) prove that V on changes linearly with the gap g. V on is adjustable to facilitate the selection of the read voltage in the Crossbar array.
  • a 300-nm-thick LN single-crystal thin film is prepared on a silicon single-crystal substrate by ion bonding at low temperature, and then a 200 ⁇ 200 nm 2 ferroelectric memory cell is prepared on the surface of the film.
  • the components of various embodiments described using directional terms and the like indicate directions shown in the drawings or directions that can be understood by those skilled in the art. These directional terms are used for relative description and clarification, and are not intended to limit the orientation of any embodiment to a specific direction or orientation.
  • the direction corresponding to the above “column” may also be transformed into the direction corresponding to “row”, and the direction corresponding to the above “row” may also be transformed into the direction corresponding to “column”.

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Abstract

一种三维非易失性铁电存储器，包括铁电存储器阵列结构，铁电存储器阵列结构包括堆叠式地布置的多层铁电存储单元阵列，每层铁电存储器单元阵列包括按行和列排列的铁电存储单元；其中，对应铁电存储单元的两侧分别相对地布置有基本正交的字线和位线，对应所述铁电存储单元邻接地布置参考铁电体；铁电存储单元中的电畴的极化方向与施加在字线和位线上的写电压信号的电场方向不垂直；并且，在字线和位线之间施加所述写电压信号时，能够使所述铁电存储单元的电畴发生反转并与其邻接的所述参考铁电体之间建立畴壁导电通道，其中，畴壁导电通道能电连接所述铁电存储单元的两侧的字线和位线。该三维非易失性铁电存储器密度高、成本低。

Description

一种三维非易失性铁电存储器 技术领域
本发明属于铁电存储技术领域，具体涉及一种三维非易失性铁电存储器。
背景技术
传统的铁电随机存储器FRAM(Ferroelectric Random Access Memory)是利用铁电畴(或称为“电畴”)在电场中两种不同极化取向作为逻辑信息(“0”或“1”)来存储数据的非易失性存储器(Non-volatile Memory)，其也可以称为“铁电存储器”。
江安全(Anquan JIANG)等人已经提出了基于畴壁导电的铁电存储器件，例如，在美国发明专利号US9685216B2、美国专利公开号US2016/0358639A1等的专利中已经描述了这种铁电存储器的存储机制，其存储机制明显区别于传统的铁电存储器，并且，可以实现基于电流读取方式非破坏性读出数据。目前，这种畴壁导电存储机制的铁电存储器件，一方面开态(ON态)读电流可达到10 -7A至10 -6A，读电流大；另一方面ON态电流和关态(Off态)电流比(即开关比)能够大于10 6，数据的保持性能好；因此，备受业界关注。
随着全球物联网、大数据中心、智能家居、便携设备等应用的发展，对存储器的存储容量、存储密度的要求不断提高。传统半导体存储器芯片通过提高单位面积的存储能力实现存储容量增长，但在后摩尔时代已不可避免地面临存储器单元间串扰加剧、单字位成本增加等瓶颈。因此，在存储密度、容量、成本和功耗等方面寻求存储技术的突破和创新。
3D NAND是革新性的半导体存储技术，通过增加存储叠层而非缩小器件二维尺寸实现存储密度增长，将半导体存储器的发展空间带入第三维度，成为未来实现存储器芯片容量可持续增长的关键。
发明内容
按照本发明的一方面，提供一种三维非易失性铁电存储器，其包括铁电存储器阵列结构，所述铁电存储器阵列结构包括堆叠式地布置 的多层铁电存储单元阵列，每层铁电存储器单元阵列包括按行和列排列的铁电存储单元；
其中，对应所述铁电存储单元的两侧分别相对地布置有基本正交的字线和位线，对应所述铁电存储单元邻接地布置参考铁电体；
所述铁电存储单元中的电畴的极化方向与施加在所述字线和位线上的写电压信号的电场方向不垂直；并且，在所述字线和位线之间施加所述写电压信号时，能够使所述铁电存储单元的电畴发生反转并与其邻接的所述参考铁电体之间建立畴壁导电通道，其中，所述畴壁导电通道能电连接所述铁电存储单元的两侧的字线和位线。
根据本发明一实施例的三维非易失性铁电存储器，其中，所述铁电存储单元和所述参考铁电体通过同一铁电单晶层或铁电薄膜层一体地形成。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，每条所述位线被所述多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用；每层所述铁电存储单元阵列的每条位线被该铁电存储单元阵列的在列/行方向上对应排列的多个铁电存储单元共用。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，还包括：
位元线层，其被布置在所述多层铁电存储单元阵列的顶层和/或底层，其中所述位元线层的每条与在行/列方向上依次排列的多条所述位线电连接。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述字线在行/列方向上的两侧分别与两列/行所述铁电存储单元耦合被所述两列/行铁电存储单元共用；和/或
所述位线在行/列方向上的两侧分别与在所述堆叠方向上对应排列的两直列所述铁电存储单元耦合被所述两直列铁电存储单元共用。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述多层铁电存储单元阵列的所述铁电存储单元以及相应的所述参考铁电体均通过同一铁电单晶层或铁电薄膜层一体地形成。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述铁电单晶层或铁电薄膜层被构图形成有在所述堆叠 方向上延伸的第一深槽和第二深槽，所述位线形成在所述第一深槽中，多条所述字线形成在同一所述第二深槽中并且相应的所述字线通过第二深槽中的介质层隔离；
其中，所述多层铁电存储单元阵列的所述铁电存储单元以及相应的所述参考铁电体被形成在所述第一深槽和第二深槽之间的铁电体之中，与所述第二深槽中的介质层对应邻接的铁电体部分为所述参考铁电体，与所述第二深槽中的字线对应邻接的铁电体部分为所述铁电存储单元。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，同一所述第二深槽中的多条所述字线和多个介质层在所述堆叠方向上依次交错设置，多个所述参考铁电体和多个所述铁电存储单元在所述堆叠方向上依次交错设置。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，每层所述铁电存储单元阵列包括：
作为所述参考铁电体的铁电基底层；
相对所述铁电基底层凸起设置的按行和列排列的多个铁电存储单元；以及
在所述铁电基底层上布置的包括多条字线的字线层；
其中，所述位线在所述堆叠方向上延伸穿过多层所述铁电存储单元阵列的铁电基底层。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，每层所述铁电存储单元阵列包括：
用于形成多条位线/字线的位线层/字线层；
在所述位线层上的铁电体层；
在所述铁电体层上的用于形成多条字线/位线的字线层/位线层；
其中，对应所述字线和所述位线的交接位置的铁电体层用于形成所述铁电存储单元，铁电体层的剩余部分用于形成所述参考铁电体。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，每个所述铁电存储单元在开态下具有单向导通特性。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述三维非易失性铁电存储器的读电压大于所述铁电存储单元的使其单向导通的开启电压且小于所述铁电存储单元的矫顽电 压。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述铁电单晶层或铁电薄膜层所使用的铁电材料选择以下的一种或多种：
铁电材料为钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
掺杂选自MgO、Mn 2O 5、Fe 2O 3或La 2O 3的钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
锆钛酸铅(Pb,Zr)TiO 3或BaTiO 3，
黑化钽酸锂盐LiTaO 3或铌酸锂盐LiNbO 3。
根据本发明又一实施例或前述任一实施例的三维非易失性铁电存储器，其中，所述铁电存储单元的电畴的极化方向与其两侧的所述字线和位线的连线方向存在夹角并且使所述电畴在该连线方向上有分量。
附图说明
从结合附图的以下详细说明中，将会使本发明的上述和其他目的及优点更加完整清楚，其中，相同或相似的要素采用相同的标号表示。
图1是按照本发明第一实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。
图2是按照本发明第二实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。
图3是按照本发明第三实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。
图4是按照本发明第四实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。
图5是按照本发明第五实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。
图6(a)是按照本发明一实施例的在单晶铌酸锂(LiNbO3)表面形成的单个铁电存储单元及其通过电压扫描方式进行读写操作的I-V特性曲线图；图6(b)是发明一实施例的铁电存储单元的开启电压Von随右电极与铁电存储单元的间隙g而变化的示意图。
图7是按照本发明一实施例的在铌酸锂(LiNbO3)单晶薄膜表面 形成的单个铁电存储单元通过电压扫描方式进行读写操作的I-V特性曲线图。
具体实施方式
下面介绍的是本发明的多个可能实施例中的一些，旨在提供对本发明的基本了解，并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。
在附图中，为了清楚起见，夸大了层和区域的厚度，图示中的各部分之间的尺寸比例关系并不反映实际的尺寸比例关系。
在以下实施例中，为了描述的清楚，示例性地给出了电畴方向或者极化方向，但是应当理解到，铁电存储器的电畴方向或极化方向并不限于如图所示实施例示出的方向。
在本文中，铁电单晶体是指内部不存在多晶结构的“晶界”的单晶结构或类单晶结构；其上形成的存储单元阵列的存储单元也是一个单晶体结构，存储单元的尺寸不限。所述铁电单晶体可以是铁电单晶薄膜层或铁电单晶基片，铁电单晶薄膜层可以是外延单晶生长所形成的单晶薄膜、或者从铁电单晶基片分离或切割所形成的薄膜层。
在以下实施例中，非易失性存储器非易失性铁电存储器包括铁电存储器阵列，铁电存储器阵列中的多个铁电存储器单元是按行和列的方式排列；这样，通过读写电路，相应行相应列的铁电存储器单元可以被选中进行相应的写操作或读操作。需要说明的是，铁电存储器阵列中的铁电存储器单元具体数量、排列方式等不是限制性的。
图1所示为按照本发明第一实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。为清楚及方便说明起见，图1(a)示意出该实施例的铁电存储器阵列结构40的三维结构示意图，图1(b)为无顶位元线层的铁电存储器阵列结构40的俯视图，图1(c)为在图1(a)中沿着I-J所绘制的剖面图，图1(d)示意对铁电存储器阵列结构40的一铁电存储单元写入数据“1”的操作原理图，图1(e)示意对铁电存储器阵列结构40的一铁电存储单元写入数据“0”的操作原理图，图1(f)示意对铁电存储器阵列结构40的一铁电存储单元读数据“1”的操作原理图。为方便示意说明，在图1至图5示意的铁电存储器阵列结构中，z方向定义为多层铁电存储单元阵列的堆叠方向，其 一般地垂直于基底，x方向定义为每层铁电存储单元阵列的行所在的方向，y方向定义为每层铁电存储单元阵列的列所在的方向。
如图1所示，铁电存储器阵列结构40被包含在三维非易失性铁电存储器中，对应其可以配置有相应的外围读写电路，外围读写电路的具体结构不是限制性的，为清楚描述本发明，在此省略对外围读写电路的描述。
铁电存储器阵列结构40可以包括：多个铁电基底层401(例如由下至上依次堆叠地布置的铁电基底层401a、401b和401c)、多层存储单元阵列402(例如由下至上依次堆叠地布置的存储单元阵列402a、402b和402c)、多个字线层403(例如由下至上依次堆叠地布置的字线层403a、403b和403c)、位线阵列404、顶位元线层405以及多层绝缘层406。其中，最上层的绝缘层406可以使顶位元线层405与铁电基底层401等相隔离，中间位置的绝缘层406可以使多个字线层403之间彼此隔离；其他空隙可以用绝缘材料填充。
这样，铁电存储器阵列结构40包括有堆叠式地布置的多层铁电存储单元阵列，它们在z方向上依次层叠，也即它们的堆叠方向为z方向；每层铁电存储单元阵列对应包括一铁电基底层401、在该铁电基底层401上布置的存储单元阵列402、在该铁电基底层401上设置的一字线层403。其中，字线层403的每条字线在y方向上延伸，多条字线在x方向上依次平行地排列，例如字线层403a的字线403a1和403a2平行地排列、字线层403b的字线403b1和403b2平行地排列、字线层403c的字线403c1和403c2平行地排列；每层存储单元阵列402(例如存储单元阵列402a、存储单元阵列402b或存储单元阵列402c)中的多个铁电存储单元按行和列的方向排列，例如在x方向和y方向上点阵排列，每层铁电基底层401在xy平面内布置。具体地，每层铁电基底层401上的存储单元阵列402的多个铁电存储单元可以相对其以凸块的形式布置，例如多个铁电存储单元相对铁电基底层401凸起设置，每个铁电存储单元的大小(例如在x方向的尺寸L、在y方向的尺寸W的具体大小)不是限制性的。
继续如图1所示，顶位元线层405设置在顶层位置，例如布置在字线层403c的上方，位线阵列404被布置成基本垂直于多个铁电基底层401并与顶位元线层405电性连接；顶位元线层405的位元线可以在x 方向延伸，其中多条位元线可以在y方向依次基本平行排列。位线通过顶位元线层405的位元线，可以与铁电存储器阵列结构40外部的读写电路耦接。
继续如图1所示，位线阵列404的每条位线是在z方向上延伸(例如从其与顶位元线层405的连接位置向下延伸)，并与不同字线层的多条字线在空间上正交。这样，每条位线可以被多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用。对于每个铁电存储单元来说，其x方向的两侧分别邻接一字线层403的一字线和位线阵列404中的一位线，也即，每个铁电存储单元被设置在字线和位线的正交位置处，它们形成了本发明一示例的Crossbar结构。
需要说明的是，铁电基底层401及其上的多个铁电存储单元可以通过对铁电单晶层或铁电薄膜材料层使用例如刻蚀等方法构图形成，铁电基底层401可以用来形成铁电存储单元的参考铁电体(例如也可以称为“参考单元”)，其与每个铁电存储单元邻接，在它们大致的邻接位置可以建立畴壁导电通道。
每个铁电存储单元的电畴的初始极化方向可以限定为在x方向上有分量，也可以理解为存储单元的电畴的初始极化方向与铁电基底层401存在一定的夹角但在铁电基底层401上有分量，但不可以与铁电基底层401垂直(例如不在z方向)。这样，铁电存储单元中的电畴的极化方向与施加在其两侧的字线和位线上的写电压信号的电场方向不垂直。如图1(c)所示，实线箭头所指为铁电存储单元和铁电基底层401中的电畴的初始极化方向，其例如可以平行于x方向。将理解，每个铁电存储单元和其对应的参考铁电体(例如铁电基底层401)的电畴的初始极化方向不限于为图1中示出的方向，例如其还可以与x方向呈一定夹角但不垂直于x方向，这样，在x方向上有分量。
需要说明的是，每个铁电存储单元的电畴的初始极化方向在x方向也有分量也可以理解为该初始极化方向在x方向上有投影。
如图1(a)所示，字线层403可具有但不限于为三个层级，它们依次形成在铁电基底层401上。每个层级的字线具有沿着y方向延伸的彼此基本平行的多条字线，并且依次填充在x方向的相邻的铁电存储单元列之间的间隙中。字线层403可以在z方向上垂直对准，即，在多个层级中的每一者中的字线可定位于每一层级的相同位置处，以便 于不同层的字线在z方向上对准。
继续如图1所示，存储单元阵列402的每个铁电存储单元在开态(ON态)下具有单向导通特性，因此，在开态(ON态)下读出电流时，该铁电存储单元表现为具有开关特性，并具有相对可测的开启电压V on。对如图1(f)所示的字线403b1和位元线4053所选中的铁电存储单元中，该铁电存储单元的电畴极化方向与下方邻接的参考铁电体的极化方向相反，在它们界面处容易形成导电的畴壁，即畴壁导电通道；对该铁电存储单元施加的电压小于矫顽电压V c并大于开启电压V on条件下，如果有较大的开态电流流过，可以读出存储的数据为“1”，反之，则读出存储的数据为“0”。
以下进一步结合图1(d)至图1(f)示例说明本发明一实施例的三维非易失性铁电存储器的读写工作原理。
如图1(d)所示，假设铁电存储器阵列结构40的某个铁电存储单元被选中进行写数据“1”的操作，例如字线403b1和位元线4053被选中。配置字线403b1为高电压V write1，V write1值大于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2，同时，配置位元线4053接地，其他位元线悬空或者配置为半高电平V c/2；这样，被选中的铁电存储单元将被施加与其初始极化方向相反的电场，该铁电存储单元的电畴沿x方向的正方向发生反转，写入数据“1”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“1”结束后，可以将字线403b1和位元线4053悬空或者配置为半高电平V c/2。
如图1(e)所示，假设铁电存储器阵列结构40的某个铁电存储单元继续被选中进行写数据“0”的操作，例如字线403b1和位元线4053被选中。配置字线403b1为接地，将其他字线悬空或者配置为半高电平V c/2；配置顶位元线4053高电压V write0，V write0值大于铁电存储单元的矫顽电压V c；这样，被选中的铁电存储单元将被施加与初始极化方向相同的电场，该铁电存储单元的电畴沿x方向的反方向发生翻转，写入数据“0”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“0”结束后，可以将字线403b1和位元线4053悬空或者配置为半高电平V c/2。
如图1(f)所示，假设铁电存储器阵列结构40的某个铁电存储单元继续被选中进行读操作(例如读取数据“1”的读操作)，例如字线 403b1和位元线4053被选中。配置字线403b1为电压V read1，V read1值大于开启电压V on且小于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2；同时配置位元线4053接地，其他位元线悬空或者配置为半高电平V c/2。由于选中的铁电存储单元与参考铁电体(例如铁电基底层401b)之间存在畴壁导电通道(如图1(f)中黑色实线示意)，有较大的开态电流(例如可达到10 -7A至10 -6A)流过，从而可以读出该选中的铁电存储单元所存储的数据为“1”。读取结束后，可以将字线403b1和位元线4053悬空或者配置为半高电平V c/2。同理，可以读出畴壁消失对应的数据状态，例如数据“0”，此时读出非常小的关态电流，即读出存储数据“0”。需要说明的是，读取信息过程中所选择的读电压V read是可调的。
图2所示为按照本发明第二实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。为清楚及方便说明起见，图2(a)示意出该实施例的铁电存储器阵列结构50的三维结构示意图，图2(b)为无顶位元线层的铁电存储器阵列结构50的俯视图，图2(c)为在图2(a)中沿着I-J所绘制的剖面图，图2(d)示意对铁电存储器阵列结构50的一铁电存储单元写入数据“1”的操作原理图，图2(e)示意对铁电存储器阵列结构50的一铁电存储单元写入数据“0”的操作原理图，图2(f)示意对铁电存储器阵列结构50的一铁电存储单元读数据“1”的操作原理图。
如图2所示，铁电存储器阵列结构50被包含在三维非易失性铁电存储器中，对应其可以配置有相应的外围读写电路，外围读写电路的具体结构不是限制性的，为清楚描述本发明，在此省略对外围读写电路的描述。
铁电存储器阵列结构50可以包括：多个铁电基底层501(例如由下至上依次堆叠地布置的铁电基底层501a、501b和501c)、多层存储单元阵列502(例如由下至上依次堆叠地布置的存储单元阵列502a、502b和502c)、多个字线层503(例如由下至上依次堆叠地布置的字线层503a、503b和503c)、位线阵列504(例如位线阵列504a和504b)、顶位元线层505a、底位元线层505b以及多层绝缘层506。其中，最上层的绝缘层506可以使顶位元线层505与铁电基底层501等相隔离，中间位置的绝缘层506(例如第二深槽中的介质层)可以使多个字线层 503之间彼此隔离；其他空隙可以用绝缘材料填充。
这样，铁电存储器阵列结构50包括有堆叠式地布置的多层铁电存储单元阵列，它们在z方向上依次层叠，也即它们的堆叠方向为z方向；每层铁电存储单元阵列对应包括一铁电基底层501、在该铁电基底层501上布置的存储单元阵列502、在该铁电基底层501上布置的一字线层503。其中，字线层503的每条字线在y方向上延伸，多条字线在x方向上依次平行地排列，例如字线层503a的字线503a1和503a2平行地排列、字线层503b的字线503b1和503b2平行地排列、字线层503c的字线503c1和503c2平行地排列；每层存储单元阵列502(例如存储单元阵列502a、存储单元阵列502b或存储单元阵列502c)中的多个铁电存储单元按行和列的方向排列，例如在x方向和y方向上点阵排列，每层铁电基底层501在xy平面内布置。具体地，每层铁电基底层501上的存储单元阵列502的多个铁电存储单元可以相对其以凸块的形式布置，例如多个铁电存储单元相对铁电基底层501凸起设置。相比于图1中示出的字线与铁电存储单元的布置方式，在图2中，字线层503的字线阵列的中间的字线被布置在两个铁电存储单元之间，这样，字线在x方向上的两侧分别与两列铁电存储单元耦合被该两列铁电存储单元共用。因此，相比于图1实施例，图2所示实施例的三维非易失性铁电存储器的铁电存储器阵列结构50可以减少字线，存储密度可以进一步提高。
继续如图2所示，顶位元线层505a设置在顶层位置，例如布置在字线层503c的上方，位线阵列504a被布置成基本垂直于多个铁电基底层501并与顶位元线层505a电性连接；底位元线层505a设置在底层位置，例如布置底层铁电存储单元阵列的下方(例如在铁电基底层501a的下方)，位线阵列504b被布置成基本垂直于多个铁电基底层501并与底位元线层505b电性连接。顶位元线层505a和底位元线层505b的位元线可以在x方向延伸，其中多条位元线可以在y方向依次基本平行排列。位线通过顶位元线层505a或底位元线层505b的位元线，可以与铁电存储器阵列结构50外部的读写电路耦接。
继续如图2所示，位线阵列504包括位线阵列504a和位线阵列504b，位线阵列504的每条位线是在z方向上延伸，其中，位线阵列504a的每条位线从其与顶位元线层505a的连接位置向下延伸，位线阵列504b 的每条位线从其与底位元线层505b的连接位置向下延伸；并且，每条位线与不同字线层的多条字线在空间上正交。这样，每条位线可以被多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用。对于每个铁电存储单元来说，其x方向的两侧分别邻接一字线层503的一字线和位线阵列504中的一位线，也即，每个铁电存储单元被设置在字线和位线的正交位置处，它们形成了本发明一示例的Crossbar结构。
继续如图2所示，相比于图1中示出的字线与铁电存储单元的布置方式，在图2中，位线在x方向的两侧均邻接地布置有铁电存储单元，这样，位线在x方向上的两侧分别与在z上对应排列的两直列铁电存储单元耦合被该两直列铁电存储单元共用。因此，相比于图1实施例，图2所示实施例的三维非易失性铁电存储器的铁电存储器阵列结构50可以减少位线，存储密度可以进一步提高。
需要说明的是，铁电基底层501及其上的多个铁电存储单元可以通过对铁电单晶层或铁电薄膜材料层使用例如刻蚀等方法构图形成，铁电基底层501可以用来形成铁电存储单元的参考铁电体(例如也可以称为“参考单元”)，其与每个铁电存储单元邻接，在它们大致的邻接位置可以建立畴壁导电通道。
每个铁电存储单元的电畴的初始极化方向可以限定为在x方向上有分量，也可以理解为存储单元的电畴的初始极化方向与铁电基底层501存在一定的夹角但在铁电基底层501上有分量，但不可以与铁电基底层501垂直(例如不在z方向)。这样，铁电存储单元中的电畴的极化方向与施加在其两侧的字线和位线上的写电压信号的电场方向不垂直。如图2(c)所示，实线箭头所指为铁电存储单元和铁电基底层501中的电畴的初始极化方向，其例如可以平行于x方向。将理解，每个铁电存储单元和其对应的参考铁电体(例如铁电基底层501)的电畴的初始极化方向不限于为图2中示出的方向，例如其还可以与x方向呈一定夹角但不垂直于x方向，这样，在x方向上有分量。
需要说明的是，每个铁电存储单元的电畴的初始极化方向在x方向也有分量也可以理解为该初始极化方向在x方向上有投影。
如图2(a)所示，字线层503可具有但不限于为三个层级，它们依次形成在铁电基底层501上。每个层级的字线具有沿着y方向延伸的 彼此基本平行的多条字线，并且依次填充在x方向的相邻的铁电存储单元列之间的间隙中。字线层503可以在z方向上垂直对准，即，在多个层级中的每一者中的字线可定位于每一层级的相同位置处，以便于不同层的字线在z方向上对准(例如字线503a2、503b2、503c2彼此在z方向上基本对准)。
继续如图2所示，存储单元阵列502的每个铁电存储单元在开态(ON态)下具有单向导通特性，因此，在开态(ON态)下读出电流时，该铁电存储单元表现为具有开关特性，并具有相对可测的开启电压V on。对如图2(f)所示的字线503b1和位元线505b3所选中的铁电存储单元中，该铁电存储单元的电畴极化方向与下方邻接的参考铁电体的极化方向相反，在它们界面处容易形成导电的畴壁，即畴壁导电通道；对该铁电存储单元施加的电压小于矫顽电压V c并大于开启电压V on条件下，如果有较大的开态电流流过，可以读出存储的数据为“1”，反之，则读出存储的数据为“0”。
以下进一步结合图2(d)至图2(f)示例说明本发明一实施例的三维非易失性铁电存储器的读写工作原理。
如图2(d)所示，假设铁电存储器阵列结构50的某个铁电存储单元被选中进行写数据“1”的操作，例如字线503b1和位元线505b3被选中。配置字线503b1为高电压V write1，V write1值大于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2，同时，配置位元线505b3接地，其他位元线悬空或者配置为半高电平V c/2；这样，被选中的铁电存储单元将被施加与其初始极化方向相反的电场，该铁电存储单元的电畴沿x方向的正方向发生反转，写入数据“1”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“1”结束后，可以将字线503b1和位元线505b3悬空或者配置为半高电平V c/2。
如图2(e)所示，假设铁电存储器阵列结构50的某个铁电存储单元继续被选中进行写数据“0”的操作，例如字线503b1和位元线505b3被选中。配置字线503b1为接地，将其他字线悬空或者配置为半高电平V c/2；配置顶位元线505b3高电压V write0，V write0值大于铁电存储单元的矫顽电压V c；这样，被选中的铁电存储单元将被施加与初始极化方向相同的电场，该铁电存储单元的电畴沿x方向的反方向发生翻转，写入数据“0”，空心箭头所示的方向即为电畴的发生反转后的极化方向。 写入数据“0”结束后，可以将字线503b1和位元线505b3悬空或者配置为半高电平V c/2。
如图2(f)所示，假设铁电存储器阵列结构50的某个铁电存储单元继续被选中进行读操作(例如读取数据“1”的读操作)，例如字线503b1和位元线505b3被选中。配置字线503b1为电压V read1，V read1值大于开启电压V on且小于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2；同时配置位元线505b3接地，其他位元线悬空或者配置为半高电平V c/2。由于选中的铁电存储单元与参考铁电体(例如铁电基底层501b)之间存在畴壁导电通道(如图2(f)中黑色实线示意)，有较大的开态电流(例如可达到10 -7A至10 -6A)流过，从而可以读出该选中的铁电存储单元所存储的数据为“1”。读取结束后，可以将字线503b1和位元线505b3悬空或者配置为半高电平V c/2。同理，可以读出畴壁消失对应的数据状态，例如数据“0”，此时读出非常小的关态电流，即读出存储数据“0”。需要说明的是，读取信息过程中所选择的读电压V read是可调的。
图3所示为按照本发明第三实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。为清楚及方便说明起见，图3(a)示意出该实施例的铁电存储器阵列结构60的三维结构示意图，图3(b)为无顶位元线层的铁电存储器阵列结构60的俯视图，图3(c)为在图3(a)中沿着I-J所绘制的剖面图，图3(d)示意对铁电存储器阵列结构60的一铁电存储单元写入数据“1”的操作原理图，图3(e)示意对铁电存储器阵列结构60的一铁电存储单元写入数据“0”的操作原理图，图3(f)示意对铁电存储器阵列结构60的一铁电存储单元读数据“1”的操作原理图。
如图3所示，铁电存储器阵列结构60被包含在三维非易失性铁电存储器中，对应其可以配置有相应的外围读写电路，外围读写电路的具体结构不是限制性的，为清楚描述本发明，在此省略对外围读写电路的描述。
铁电存储器阵列结构60可以包括：一个铁电基底层601、多层存储单元阵列602、多个字线层603(例如由下至上依次堆叠地布置的字线层603a、603b、603c和603d)、位线阵列604、顶位元线层605以及多层绝缘层606。其中，最上层的绝缘层606可以使顶位元线层605与 铁电基底层601等相隔离，中间位置的绝缘层606可以使上下相邻的字线层603之间彼此隔离；其他空隙可以用绝缘材料填充。
继续如图3所示，一个铁电基底层601和多层存储单元阵列602可以通过同一铁电单晶层或铁电薄膜层一体地形成，从而，在形成3D结构的多层铁电存储单元阵列时，可以大大减少铁电单晶层或铁电薄膜层的沉积次数，简化工艺过程并降低成本；例如，一次沉积或生长形成较厚的铁电单晶层或铁电薄膜层，对铁电单晶层或铁电薄膜层进行构图，形成多个深槽；深槽之间的铁电体可以被操作用来形成多层存储单元阵列602的多个铁电存储单元，上下相邻的铁电存储单元之间的铁电体可以用来形成参考铁电体，铁电存储单元可以被编程来与参考铁电体形成大致左右方向的畴壁导电通道，该畴壁导电通道可以用来电连接其左右两侧的字线和位线。
具体如图3所示，至少用于形成铁电基底层601的铁电单晶层或铁电薄膜层可以被构图形成有在堆叠方向上延伸的第一深槽(或深孔)和第二深槽，位线阵列604的位线形成在第一深槽中，分别属于不同字线层603的多条字线(例如位线603a1、603b1、603c1、603d1)形成在同一第二深槽中，并且，该第二深槽中还形成用于隔离多条字线的介质层，这样，第二深槽中的上下相邻字线通过第二深槽中的介质层隔离，该介质层可以实现绝缘层606的部分功能。
这样，尽管多层存储单元阵列602中形成的多个铁电存储单元以及相应的多个参考铁电体均通过同一铁电单晶层或铁电薄膜层一体地形成，铁电存储器阵列结构60也可以包括有堆叠式地布置的多层铁电存储单元阵列(尽管多层存储单元阵列602之间没有实质的物理分层界面)，它们在z方向上层叠；每层铁电存储单元阵列对应包括在z方向的某一高度上的一层存储单元阵列602、该高度上对应的一字线层603。其中，字线层603的每条字线在y方向上延伸，多条字线在x方向上依次平行地排列；每层存储单元阵列602中的多个铁电存储单元在xy平面内按行和列的方向排列，每层参考铁电体也在xy平面内按行和列的方向布置。
继续如图3所示，顶位元线层605设置在顶层位置，例如布置在字线层603d的上方，位线阵列604被布置成基本垂直于多个铁电基底层601并与顶位元线层605电性连接。顶位元线层605的多条位元线(例 如位元线6051、6052、6053、6054和6055)可以在x方向延伸，其中多条位元线可以在y方向依次基本平行排列。位线通过顶位元线层605的位元线，可以与铁电存储器阵列结构60外部的读写电路耦接。
继续如图3所示，位线阵列604的每条位线从其与顶位元线层605的连接位置向下延伸并形成在存储单元阵列602之间的第一深槽中；并且，每条位线与不同字线层的多条字线在空间上正交。这样，每条位线可以被多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用。对于每个铁电存储单元来说，其x方向的两侧分别邻接一字线层603的一字线和位线阵列604中的一位线，也即，对应正交的一字线和一位线之间的铁电体(位于第一深槽和第二深槽之间)，形成本发明一实施例的铁电存储单元；同样地，每个铁电存储单元被设置在字线和位线的正交位置处，它们形成了本发明一示例的Crossbar结构。
需要说明的是，对应正交的一位线和介质层之间的铁电体，形成本发明一实施例的参考铁电体，该参考铁电体在上下方向上与铁电存储单元邻接，并且，在上下方向上交替布置的多个参考铁电体和多个铁电存储单元都是通过在第一深槽和第二深槽之间的统一铁电体形成；这样，与第二深槽中的介质层对应邻接的铁电体部分为参考铁电体，与第二深槽中的字线对应邻接的铁电体部分为铁电存储单元。
继续如图3所示，相比于图1中示出的字线与铁电存储单元的布置方式，在图3中，位线在x方向的两侧均邻接地布置有铁电存储单元，这样，位线在x方向上的两侧分别与在z上对应排列的两直列铁电存储单元耦合被该两直列铁电存储单元共用。因此，相比于图1实施例，图3所示实施例的三维非易失性铁电存储器的铁电存储器阵列结构60可以减少位线，存储密度可以进一步提高。
进一步相比于图1中示出的字线与铁电存储单元的布置方式，在图3中，字线层603的字线阵列的中间的字线被布置在两个铁电存储单元之间，这样，字线在x方向上的两侧分别与两列铁电存储单元耦合被该两列铁电存储单元共用。因此，相比于图1实施例，图3所示实施例的三维非易失性铁电存储器的铁电存储器阵列结构60可以减少字线，存储密度可以进一步提高。
同时相比于图1和图2所示实施例的铁电存储器阵列结构，铁电存 储器阵列结构60可以减少铁电基底层601的数量；同时可以一次生成或沉积较厚的铁电单晶层或铁电薄膜层来实现，从而，一方面，不同层的铁电存储单元阵列中的铁电存储单元以及参考铁电体在性能(例如铁电性能等)方面更一致，因此，可以获得更好的一致性，另一方面，可以大大减少铁电存储单元以及参考铁电体中的缺陷，减少无效存储单元，提高存储器的成品率。
需要说明的是，每个铁电存储单元的电畴的初始极化方向可以限定为在x方向上有分量，也可以理解为存储单元的电畴的初始极化方向与铁电基底层601存在一定的夹角但在铁电基底层601上有分量，但不可以与铁电基底层601垂直(例如不在z方向)。这样，铁电存储单元中的电畴的极化方向与施加在其两侧的字线和位线上的写电压信号的电场方向不垂直。如图3(c)所示，实线箭头所指为铁电存储单元和铁电基底层601中的电畴的初始极化方向，其例如可以平行于x方向。将理解，每个铁电存储单元和其对应的参考铁电体(例如铁电基底层601)的电畴的初始极化方向不限于为图3中示出的方向，例如其还可以与x方向呈一定夹角但不垂直于x方向，这样，在x方向上有分量。
需要说明的是，每个铁电存储单元的电畴的初始极化方向在x方向也有分量也可以理解为该初始极化方向在x方向上有投影。
继续如图3所示，存储单元阵列602的每个铁电存储单元在开态(ON态)下具有单向导通特性，因此，在开态(ON态)下读出电流时，该铁电存储单元表现为具有开关特性，并具有相对可测的开启电压V on。对如图3(f)所示的字线603b1和位元线6055所选中的铁电存储单元中，该铁电存储单元的电畴极化方向与下方和/或上方邻接的参考铁电体的极化方向相反，在它们界面处容易形成导电的畴壁(例如两个)，即畴壁导电通道；对该铁电存储单元施加的电压小于矫顽电压V c并大于开启电压V on条件下，如果有较大的开态电流流过，可以读出存储的数据为“1”，反之，则读出存储的数据为“0”。
以下进一步结合图3(d)至图3(f)示例说明本发明一实施例的三维非易失性铁电存储器的读写工作原理。
如图3(d)所示，假设铁电存储器阵列结构60的某个铁电存储单元被选中进行写数据“1”的操作，例如字线603b1和位元线6055被选中。 配置字线603b1为高电压V write1，V write1值大于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2，同时，配置位元线6055接地，其他位元线悬空或者配置为半高电平V c/2；这样，被选中的铁电存储单元将被施加与其初始极化方向相反的电场，该铁电存储单元的电畴沿x方向的正方向发生反转，写入数据“1”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“1”结束后，可以将字线603b1和位元线6055悬空或者配置为半高电平V c/2。
如图3(e)所示，假设铁电存储器阵列结构60的某个铁电存储单元继续被选中进行写数据“0”的操作，例如字线603b1和位元线6055被选中。配置字线603b1为接地，将其他字线悬空或者配置为半高电平V c/2；配置顶位元线6055高电压V write0，V write0值大于铁电存储单元的矫顽电压V c；这样，被选中的铁电存储单元将被施加与初始极化方向相同的电场，该铁电存储单元的电畴沿x方向的反方向发生翻转，写入数据“0”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“0”结束后，可以将字线603b1和位元线6055悬空或者配置为半高电平V c/2。
如图3(f)所示，假设铁电存储器阵列结构60的某个铁电存储单元继续被选中进行读操作(例如读取数据“1”的读操作)，例如字线603b1和位元线6055被选中。配置字线603b1为电压V read1，V read1值大于开启电压V on且小于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2；同时配置位元线6055接地，其他位元线悬空或者配置为半高电平V c/2。由于选中的铁电存储单元与参考铁电体(例如铁电基底层601b)之间存在畴壁导电通道(如图3(f)中黑色实线示意)，有较大的开态电流(例如可达到10 -7A至10 -6A)流过，从而可以读出该选中的铁电存储单元所存储的数据为“1”。读取结束后，可以将字线603b1和位元线6055悬空或者配置为半高电平V c/2。同理，可以读出畴壁消失对应的数据状态，例如数据“0”，此时读出非常小的关态电流，即读出存储数据“0”。需要说明的是，读取信息过程中所选择的读电压V read是可调的。
图4所示为按照本发明第四实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。为清楚及方便说明起见，图4(a)示意出该实施例的铁电存储器阵列结构70的三维结构示意图， 图4(b)为无顶位元线层的铁电存储器阵列结构70的俯视图，图4(c)为在图4(a)中沿着I-J所绘制的剖面图，图4(d)示意对铁电存储器阵列结构70的一铁电存储单元写入数据“1”的操作原理图，图4(e)示意对铁电存储器阵列结构70的一铁电存储单元写入数据“0”的操作原理图，图4(f)示意对铁电存储器阵列结构70的一铁电存储单元读数据“1”的操作原理图。
如图4所示，铁电存储器阵列结构70被包含在三维非易失性铁电存储器中，对应其可以配置有相应的外围读写电路，外围读写电路的具体结构不是限制性的，为清楚描述本发明，在此省略对外围读写电路的描述。
铁电存储器阵列结构70可以包括：一个铁电基底层701、多层存储单元阵列702、多个字线层703(例如由下至上依次堆叠地布置的字线层703a、703b、703c和703d)、位线阵列704(例如位线阵列704a和704b)、顶位元线层705a、底位元线层705ab以及多层绝缘层706。其中，最上层的绝缘层706可以使顶位元线层705a与铁电基底层701等相隔离，中间位置的绝缘层706(例如介质层)可以使上下相邻的字线层703之间彼此隔离；其他空隙可以用绝缘材料填充。
继续如图4所示，一个铁电基底层701和多层存储单元阵列702可以通过同一铁电单晶层或铁电薄膜层一体地形成，从而，在形成3D结构的多层铁电存储单元阵列时，可以大大减少铁电单晶层或铁电薄膜层的沉积次数，简化工艺过程并降低成本；例如，一次沉积或生长形成较厚的铁电单晶层或铁电薄膜层，对铁电单晶层或铁电薄膜层进行构图，形成多个深槽；深槽之间的铁电体可以被操作用来形成多层存储单元阵列702的多个铁电存储单元，上下相邻的铁电存储单元之间的铁电体可以用来形成参考铁电体，铁电存储单元可以被编程来与参考铁电体形成大致左右方向的畴壁导电通道，该畴壁导电通道可以用来电连接其左右两侧的字线和位线。
具体如图4所示，至少用于形成铁电基底层701的铁电单晶层或铁电薄膜层可以被构图形成有在堆叠方向上延伸的第一深槽(或深孔)和第二深槽，位线阵列704的位线形成在第一深槽中，分别属于不同字线层704的多条字线(例如位线703a1、703b1、703c1、703d1)形成在同一第二深槽中，并且，该第二深槽中还形成用于隔离多条字线 的介质层，这样，第二深槽中的上下相邻字线通过第二深槽中的介质层隔离，该介质层可以实现绝缘层706的部分功能。
这样，尽管多层存储单元阵列702中形成的多个铁电存储单元以及相应的多个参考铁电体均通过同一铁电单晶层或铁电薄膜层一体地形成，铁电存储器阵列结构70也可以包括有堆叠式地布置的多层铁电存储单元阵列(尽管多层存储单元阵列702之间没有实质的物理分层界面)，它们在z方向上层叠；每层铁电存储单元阵列对应包括在z方向的某一高度上的一层存储单元阵列702、该高度上对应的一字线层703。其中，字线层703的每条字线在y方向上延伸，多条字线在x方向上依次平行地排列；每层存储单元阵列702中的多个铁电存储单元在xy平面内按行和列的方向排列，每层参考铁电体也在xy平面内按行和列的方向布置。
继续如图4所示，顶位元线层705a设置在顶层位置，例如布置在字线层703d的上方，位线阵列704a被布置成基本垂直于多个铁电基底层701并与顶位元线层705a电性连接；
底位元线层705a设置在底层位置，例如布置底层铁电存储单元阵列的下方(例如在铁电基底层701的下方)，位线阵列704b被布置成基本垂直于多个铁电基底层501并与底位元线层705b电性连接。顶位元线层705a的多条位元线(例如位元线705a1、705a2、705a3、705a4和705a5)可以在x方向延伸，底位元线层705b的多条位元线(例如位元线705b1、705b2、705b3、705b4和705b5)可以在x方向延伸，其中多条位元线可以在y方向依次基本平行排列。位线通过顶位元线层705a或底位元线层705b的位元线，可以与铁电存储器阵列结构70外部的读写电路耦接。
继续如图4所示，位线阵列704a的每条位线从其与顶位元线层705a的连接位置向下延伸并形成在存储单元阵列702之间的第一深槽中，位线阵列704b的每条位线从其与底位元线层705b的连接位置向上延伸并形成在存储单元阵列702之间的第一深槽中；位线阵列704a的位线与位线阵列704b的位线在x方向上交替地布置；并且，每条位线与不同字线层的多条字线在空间上正交。这样，每条位线可以被多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用。对于每个铁电存储单元来说，其x方向的两侧分别邻接一字线层703 的一字线和位线阵列704中的一位线，也即，对应正交的一字线和一位线之间的铁电体(位于第一深槽和第二深槽之间)，形成本发明一实施例的铁电存储单元；同样地，每个铁电存储单元被设置在字线和位线的正交位置处，它们形成了本发明一示例的Crossbar结构。
需要说明的是，对应正交的一位线和介质层之间的铁电体，形成本发明一实施例的参考铁电体，该参考铁电体在上下方向上与铁电存储单元邻接，并且，在上下方向上交替布置的多个参考铁电体和多个铁电存储单元都是通过在第一深槽和第二深槽之间的统一铁电体形成；这样，与第二深槽中的介质层对应邻接的铁电体部分为参考铁电体，与第二深槽中的字线对应邻接的铁电体部分为铁电存储单元。
继续如图4所示，与图3所示的铁电存储阵列结构类似，位线在x方向上的两侧分别与在z上对应排列的两直列铁电存储单元耦合被该两直列铁电存储单元共用，字线在x方向上的两侧分别与两列铁电存储单元耦合被该两列铁电存储单元共用。因此，相比于图1实施例，图4所示实施例的三维非易失性铁电存储器的铁电存储器阵列结构70可以减少字线和位线，存储密度可以进一步提高。
同时相比于图1和图2所示实施例的铁电存储器阵列结构，铁电存储器阵列结构70可以减少铁电基底层701的数量；同时可以一次生成或沉积较厚的铁电单晶层或铁电薄膜层来实现，从而，一方面，不同层的铁电存储单元阵列中的铁电存储单元以及参考铁电体在性能(例如铁电性能等)方面更一致，因此，可以获得更好的一致性，另一方面，可以大大减少铁电存储单元以及参考铁电体中的缺陷，减少无效存储单元，提高存储器的成品率。
需要说明的是，每个铁电存储单元的电畴的初始极化方向可以限定为在x方向上有分量，也可以理解为存储单元的电畴的初始极化方向与铁电基底层701存在一定的夹角但在铁电基底层701上有分量，但不可以与铁电基底层701垂直(例如不在z方向)。这样，铁电存储单元中的电畴的极化方向与施加在其两侧的字线和位线上的写电压信号的电场方向不垂直。如图4(c)所示，实线箭头所指为铁电存储单元和铁电基底层701中的电畴的初始极化方向，其例如可以平行于x方向。将理解，每个铁电存储单元和其对应的参考铁电体(例如铁电基底层701)的电畴的初始极化方向不限于为图4中示出的方向，例如 其还可以与x方向呈一定夹角但不垂直于x方向，这样，在x方向上有分量。
需要说明的是，每个铁电存储单元的电畴的初始极化方向在x方向也有分量也可以理解为该初始极化方向在x方向上有投影。
继续如图4所示，存储单元阵列702的每个铁电存储单元在开态(ON态)下具有单向导通特性，因此，在开态(ON态)下读出电流时，该铁电存储单元表现为具有开关特性，并具有相对可测的开启电压V on。对如图4(f)所示的字线703b1和位元线705a5所选中的铁电存储单元中，该铁电存储单元的电畴极化方向与下方和/或上方邻接的参考铁电体的极化方向相反，在它们界面处容易形成导电的畴壁(例如两个)，即畴壁导电通道；对该铁电存储单元施加的电压小于矫顽电压V c并大于开启电压V on条件下，如果有较大的开态电流流过，可以读出存储的数据为“1”，反之，则读出存储的数据为“0”。
以下进一步结合图4(d)至图4(f)示例说明本发明一实施例的三维非易失性铁电存储器的读写工作原理。
如图4(d)所示，假设铁电存储器阵列结构70的某个铁电存储单元被选中进行写数据“1”的操作，例如字线703b1和位元线705a5被选中。配置字线703b1为高电压V write1，V write1值大于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2，同时，配置位元线705a5接地，其他位元线悬空或者配置为半高电平V c/2；这样，被选中的铁电存储单元将被施加与其初始极化方向相反的电场，该铁电存储单元的电畴沿x方向的正方向发生反转，写入数据“1”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“1”结束后，可以将字线703b1和位元线705a5悬空或者配置为半高电平V c/2。
如图4(e)所示，假设铁电存储器阵列结构70的某个铁电存储单元继续被选中进行写数据“0”的操作，例如字线703b1和位元线705a5被选中。配置字线703b1为接地，将其他字线悬空或者配置为半高电平V c/2；配置顶位元线705a5高电压V write0，V write0值大于铁电存储单元的矫顽电压V c；这样，被选中的铁电存储单元将被施加与初始极化方向相同的电场，该铁电存储单元的电畴沿x方向的反方向发生翻转，写入数据“0”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“0”结束后，可以将字线703b1和位元线705a5悬空或者配置 为半高电平V c/2。
如图4(f)所示，假设铁电存储器阵列结构70的某个铁电存储单元继续被选中进行读操作(例如读取数据“1”的读操作)，例如字线703b1和位元线705a5被选中。配置字线703b1为电压V read1，V read1值大于开启电压V on且小于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2；同时配置位元线705a5接地，其他位元线悬空或者配置为半高电平V c/2。由于选中的铁电存储单元与参考铁电体(例如铁电基底层701b)之间存在畴壁导电通道(如图4(f)中黑色实线示意)，有较大的开态电流(例如可达到10 -7A至10 -6A)流过，从而可以读出该选中的铁电存储单元所存储的数据为“1”。读取结束后，可以将字线703b1和位元线705a5悬空或者配置为半高电平V c/2。同理，可以读出畴壁消失对应的数据状态，例如数据“0”，此时读出非常小的关态电流，即读出存储数据“0”。
图5所示为按照本发明第五实施例的三维非易失性铁电存储器的铁电存储器阵列结构及其操作原理的示意图。为清楚及方便说明起见，图5(a)示意出该实施例的铁电存储器阵列结构80的三维结构示意图，图5(b)为在图5(a)中沿着I-J所绘制的剖面图，图5(c)示意对铁电存储器阵列结构80的一铁电存储单元写入数据“1”的操作原理图，图5(d)示意对铁电存储器阵列结构80的一铁电存储单元写入数据“0”的操作原理图，图5(e)示意对铁电存储器阵列结构80的一铁电存储单元读数据“1”的操作原理图。
如图5所示，铁电存储器阵列结构80被包含在三维非易失性铁电存储器中，对应其可以配置有相应的外围读写电路，外围读写电路的具体结构不是限制性的，为清楚描述本发明，在此省略对外围读写电路的描述。
铁电存储器阵列结构80可以包括：多个铁电薄膜层801(例如由下至上依次堆叠地布置的铁电薄膜层801a、801b和801c)、对应分别在多层铁电薄膜层801中形成的多层存储单元阵列802、多个字线层803(例如由下至上依次堆叠地布置的字线层803a、803b和803c)、多个位线层804(例如由下至上依次堆叠地布置的位线层804a、804b和804c)以及多层绝缘层806。
这样，铁电存储器阵列结构80包括有堆叠式地布置的多层铁电存 储单元阵列，它们在z方向上依次层叠，也即它们的堆叠方向为z方向；每层铁电存储单元阵列对应包括一位线层804、一铁电薄膜层801、一字线层803和一绝缘层806。
其中，每一字线层803的每条字线在y方向上延伸，多条字线在x方向上依次平行地排列，例如字线层803a的字线803a1、803a2、803a3和803a4平行地排列、字线层803c的字线803c1、803c2、803c3和803c4平行地排列；每一位线层804的每条位线在x方向上延伸，多条位线在y方向上依次平行地排列，例如位线层804a的位线804a1、804a2、804a3和804a4平行地排列、位线层804c的位线804c1、804c2、804c3和804c4平行地排列。这样，每层铁电存储单元阵列中，位线与字线在空间上正交，在对应字线和位线的正交位置处，铁电薄膜层801中形成存储单元阵列802的铁电存储单元，铁电存储单元可以在铁电薄膜层801中按行和列地形成。字线、铁电存储单元和位线形成了本发明一示例的Crossbar结构。每层存储单元阵列802中的多个铁电存储单元按行和列的方向排列，例如在x方向和y方向上点阵排列，每层铁电薄膜层801在xy平面内布置。
需要说明的是，铁电薄膜层801中的铁电存储单元之外的部分可以用作参考铁电体(例如也可以称为“参考单元”)，其与每个铁电存储单元邻接，在它们大致的邻接位置可以建立畴壁导电通道。
每个铁电存储单元的电畴的初始极化方向可以限定为在x方向上有分量，也可以理解为存储单元的电畴的初始极化方向与铁电薄膜层801存在一定的夹角但在铁电薄膜层801上有分量，但不可以与铁电薄膜层801垂直(例如不在z方向)。这样，铁电存储单元中的电畴的极化方向与施加在其两侧的字线和位线上的写电压信号的电场方向不垂直。如图5(b)所示，实线箭头所指为铁电存储单元和铁电薄膜层801中的电畴的初始极化方向，其例如可以平行于z方向。将理解，每个铁电存储单元和其对应的参考铁电体(例如铁电薄膜层801)的电畴的初始极化方向不限于为图5中示出的方向，例如其还可以与z方向呈一定夹角但不垂直于z方向，这样，在z方向上有分量。
如图5(a)所示，铁电薄膜层801、字线层803和位线层804可具有但不限于为三个层级。字线层803可以在z方向上垂直对准，即，在多个层级中的每一者中的字线可定位于每一层级的相同位置处，以 便于不同层的字线在z方向上对准；位线层804可以在z方向上垂直对准，即，在多个层级中的每一者中的位线可定位于每一层级的相同位置处，以便于不同层的位线在z方向上对准。
继续如图5所示，存储单元阵列802的每个铁电存储单元在开态(ON态)下具有单向导通特性，因此，在开态(ON态)下读出电流时，该铁电存储单元表现为具有开关特性，并具有相对可测的开启电压V on。对如图5(e)所示的字线803b1和位元线804c4所选中的铁电存储单元中，该铁电存储单元的电畴极化方向与下方邻接的参考铁电体的极化方向相反，在它们界面处容易形成导电的畴壁，即畴壁导电通道；对该铁电存储单元施加的电压小于矫顽电压V c并大于开启电压V on条件下，如果有较大的开态电流流过，可以读出存储的数据为“1”，反之，则读出存储的数据为“0”。
以下进一步结合图5(c)至图5(e)示例说明本发明一实施例的三维非易失性铁电存储器的读写工作原理。
如图5(c)所示，假设铁电存储器阵列结构80的某个铁电存储单元被选中进行写数据“1”的操作，例如字线803b1和位元线804c4被选中。配置字线803b1为高电压V write1，V write1值大于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2，同时，配置位元线804c4接地，其他位元线悬空或者配置为半高电平V c/2；这样，被选中的铁电存储单元将被施加与其初始极化方向相反的电场，该铁电存储单元的电畴沿x方向的正方向发生反转，写入数据“1”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“1”结束后，可以将字线803b1和位元线804c4悬空或者配置为半高电平V c/2。
如图5(d)所示，假设铁电存储器阵列结构80的某个铁电存储单元继续被选中进行写数据“0”的操作，例如字线803b1和位元线804c4被选中。配置字线803b1为接地，将其他字线悬空或者配置为半高电平V c/2；配置顶位元线804c4高电压V write0，V write0值大于铁电存储单元的矫顽电压V c；这样，被选中的铁电存储单元将被施加与初始极化方向相同的电场，该铁电存储单元的电畴沿x方向的反方向发生翻转，写入数据“0”，空心箭头所示的方向即为电畴的发生反转后的极化方向。写入数据“0”结束后，可以将字线803b1和位元线804c4悬空或者配置为半高电平V c/2。
如图5(e)所示，假设铁电存储器阵列结构80的某个铁电存储单元继续被选中进行读操作(例如读取数据“1”的读操作)，例如字线803b1和位元线804c4被选中。配置字线803b1为电压V read1，V read1值大于开启电压V on且小于铁电存储单元的矫顽电压V c，将其他字线悬空或者配置为半高电平V c/2；同时配置位元线804c4接地，其他位元线悬空或者配置为半高电平V c/2。由于选中的铁电存储单元与参考铁电体(例如铁电薄膜层801b)之间存在畴壁导电通道(如图5(e)中黑色实线示意)，有较大的开态电流(例如可达到10 -7A至10 -6A)流过，从而可以读出该选中的铁电存储单元所存储的数据为“1”。读取结束后，可以将字线803b1和位元线804c4悬空或者配置为半高电平V c/2。同理，可以读出畴壁消失对应的数据状态，例如数据“0”，此时读出非常小的关态电流，即读出存储数据“0”。
由此可见，利用本发明以上实施例的3D非易失性铁电存储器的铁电存储单元的单向导通特性，使在特别是读操作时，大大降低对选中的铁电存储单元的邻近存储单元的产生串扰，漏电功耗也小；因此，对于铁电存储单元来说，完全可以直接省去选通管或开关管，Crossbar结构也变得更简单、成本更低。
还需要说明的是，以上实施例的使用Crossbar结构的铁电存储器阵列结构40-80完全可以实现多层铁电存储单元阵列的三维堆叠，大大提高存储密度，明显降低单位存储容量的制造成本。
需要理解的是，尽管以上图1至图5中是以3层或4层铁电存储单元阵列来示例说明的，铁电存储器阵列结构40中所堆叠的铁电存储单元阵列层数不是限制性的，本领域技术人员可以根据存储密度等要求来选择铁电存储单元阵列的层数；当然，两个或两个以上的铁电存储器阵列结构40也可以在z方向上堆叠地设置来提高存储密度。
在以上图1至图5实施例的3D非易失性铁电存储器中，铁电存储单元和/或参考铁电体的铁电单晶层或铁电薄膜层所使用的铁电材料选择以下的一种或多种：
铁电材料为钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
掺杂选自MgO、Mn 2O 5、Fe 2O 3、La 2O 3的一种或多种的钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
锆钛酸铅(Pb,Zr)TiO 3或BaTiO 3，
黑化钽酸锂盐LiTaO 3或铌酸锂盐LiNbO 3。
在本发明一具体实施例中，在X切割的掺5％Mg铌酸锂(LiNbO 3)单晶表面成功制备尺寸为200×200nm 2单个铁电存储单元；其中图9a示出了尺寸为200×200nm 2存储单元的原子力形貌像，器件两端连接左右电极(L和R)；图9b为面内压电成像，通过在L和R电极上施加一个大于矫顽电压(Vc)的写电压(+/-10V)，可以实现铁电畴向右或向左的反转，即图中黑色或白色成像区域，从而非挥发地存储逻辑“1”和“0”的数据信息。
需要特别说明的是，每个铁电存储单元的开态电流天然地具有二极管电流单向导通特性，且每个单元中开态电流读电压需大于一个大小可调的V on。通过改变电极和铁电存储单元接触的间距(0-100nm)，可以调节电流读出的开启电压。图6(a)左边显示在LiNbO 3单晶表面所制备的另外两个铁电存储单元的扫描电镜的形貌像，右电极与铁电存储单元的间隙(g)分别为0nm(图6(a)的左上图)和49nm(图6(a)的左下图)。图6(a)的右图显示以上两种器件分别在+/-12V写入“1”(黑色曲线)和“0”(灰色曲线)信息后所测量的电流-电压(I-V)曲线。当写入“1”信息后，铁电存储单元内写入电畴与底部不变的块体电畴反平行，它们之间形成导电畴壁，当I-V曲线测量电压从0V增大时，电流开始为0，但是当电压大于某一开启电压Von时，电流突然增大，而且V on随右电极与铁电存储单元的间隙g变化：当g＝0nm时，Von＝1.8V；当g＝49nm时，V on＝5V。以上研究结果证明，开启电压V on可调，图6(b)的测量结果证明了V on随间隙g线性变化。V on可调为Crossbar阵列中读电压的选择提供便利。
在本发明又一具体实施例中，在硅单晶衬底上通过离子键合低温制备的300nm厚度的LN单晶薄膜，然后在薄膜表面制备的尺寸为200×200nm 2铁电存储单元。
如图7所示，在+/-5V写入“1”(黑色曲线)和“0”(灰色曲线)信息后，器件读出电流分别处于开态和关态。电流-电压曲线测量结果证明，开启电压为2.7V，矫顽电压V c约为4V。
在以上描述中，使用方向性术语以及类似术语描述的各种实施方式的部件表示附图中示出的方向或者能被本领域技术人员理解的方向。这些方向性术语用于相对的描述和澄清，而不是要将任何实施例的定 向限定到具体的方向或定向。示例地，在其他替换实施例中，以上“列”对应的方向也可以变换为“行”对应的方向，同时以上“行”对应的方向也可以变换为“列”对应的方向。
以上例子主要说明了本发明的低功耗3D非易失性铁电存储器。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (14)

  1. 一种三维非易失性铁电存储器，其包括铁电存储器阵列结构，其特征在于，所述铁电存储器阵列结构包括堆叠式地布置的多层铁电存储单元阵列，每层铁电存储器单元阵列包括按行和列排列的铁电存储单元；
    其中，对应所述铁电存储单元的两侧分别相对地布置有基本正交的字线和位线，对应所述铁电存储单元邻接地布置参考铁电体；
    所述铁电存储单元中的电畴的极化方向与施加在所述字线和位线上的写电压信号的电场方向不垂直；并且，在所述字线和位线之间施加所述写电压信号时，能够使所述铁电存储单元的电畴发生反转并与其邻接的所述参考铁电体之间建立畴壁导电通道，其中，所述畴壁导电通道能电连接所述铁电存储单元的两侧的字线和位线。
  2. 如权利要求1所述的三维非易失性铁电存储器，其特征在于，所述铁电存储单元和所述参考铁电体通过同一铁电单晶层或铁电薄膜层一体地形成。
  3. 如权利要求1所述的三维非易失性铁电存储器，其特征在于，每条所述位线被所述多层铁电存储单元阵列的在其堆叠方向上对应排列的多个铁电存储单元共用；每层所述铁电存储单元阵列的每条位线被该铁电存储单元阵列的在列/行方向上对应排列的多个铁电存储单元共用。
  4. 如权利要求3所述的三维非易失性铁电存储器，其特征在于，还包括：
    位元线层，其被布置在所述多层铁电存储单元阵列的顶层和/或底层，其中所述位元线层的每条与在行/列方向上依次排列的多条所述位线电连接。
  5. 如权利要求3所述的三维非易失性铁电存储器，其特征在于，所述字线在行/列方向上的两侧分别与两列/行所述铁电存储单元耦合被所述两列/行铁电存储单元共用；和/或
    所述位线在行/列方向上的两侧分别与在所述堆叠方向上对应排列的两直列所述铁电存储单元耦合被所述两直列铁电存储单元共用。
  6. 如权利要求3所述的三维非易失性铁电存储器，其特征在于，所述多层铁电存储单元阵列的所述铁电存储单元以及相应的所述参考铁电体均通过同一铁电单晶层或铁电薄膜层一体地形成。
  7. 如权利要求6所述的三维非易失性铁电存储器，其特征在于，所述铁电单晶层或铁电薄膜层被构图形成有在所述堆叠方向上延伸的第一深槽和第二深槽，所述位线形成在所述第一深槽中，多条所述字线形成在同一所述第二深槽中并且相应的所述字线通过第二深槽中的介质层隔离；
    其中，所述多层铁电存储单元阵列的所述铁电存储单元以及相应的所述参考铁电体被形成在所述第一深槽和第二深槽之间的铁电体之中，与所述第二深槽中的介质层对应邻接的铁电体部分为所述参考铁电体，与所述第二深槽中的字线对应邻接的铁电体部分为所述铁电存储单元。
  8. 如权利要求6所述的三维非易失性铁电存储器，其特征在于，同一所述第二深槽中的多条所述字线和多个介质层在所述堆叠方向上依次交错设置，多个所述参考铁电体和多个所述铁电存储单元在所述堆叠方向上依次交错设置。
  9. 如权利要求3所述的三维非易失性铁电存储器，其特征在于，每层所述铁电存储单元阵列包括：
    作为所述参考铁电体的铁电基底层；
    相对所述铁电基底层凸起设置的按行和列排列的多个铁电存储单元；以及
    在所述铁电基底层上布置的包括多条字线的字线层；
    其中，所述位线在所述堆叠方向上延伸穿过多层所述铁电存储单元阵列的铁电基底层。
  10. 如权利要求1所述的三维非易失性铁电存储器，其特征在于，每层所述铁电存储单元阵列包括：
    用于形成多条位线/字线的位线层/字线层；
    在所述位线层上的铁电体层；
    在所述铁电体层上的用于形成多条字线/位线的字线层/位线层；
    其中，对应所述字线和所述位线的交接位置的铁电体层用于形成所述铁电存储单元，铁电体层的剩余部分用于形成所述参考铁电体。
  11. 如权利要求1所述的三维非易失性铁电存储器，其特征在于，每个所述铁电存储单元在开态下具有单向导通特性。
  12. 如权利要求11所述的三维非易失性铁电存储器，其特征在于，所述三维非易失性铁电存储器的读电压大于所述铁电存储单元的使其单向导通的开启电压且小于所述铁电存储单元的矫顽电压。
  13. 如权利要求2所述的三维非易失性铁电存储器，其特征在于，所述铁电单晶层或铁电薄膜层所使用的铁电材料选择以下的一种或多种：
    铁电材料为钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
    掺杂选自MgO、Mn 2O 5、Fe 2O 3或La 2O 3的钽酸锂盐LiTaO 3、铌酸锂盐LiNbO 3或铁酸铋BiFeO 3，
    锆钛酸铅(Pb,Zr)TiO 3或BaTiO 3，
    黑化钽酸锂盐LiTaO 3或铌酸锂盐LiNbO 3。
  14. 如权利要求1所述的三维非易失性铁电存储器，其特征在于，所述铁电存储单元的电畴的极化方向与其两侧的所述字线和位线的连线方向存在夹角并且使所述电畴在该连线方向上有分量。
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