WO2021217493A1 - 三维铁电存储器及电子设备 - Google Patents

三维铁电存储器及电子设备 Download PDF

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Publication number
WO2021217493A1
WO2021217493A1 PCT/CN2020/087763 CN2020087763W WO2021217493A1 WO 2021217493 A1 WO2021217493 A1 WO 2021217493A1 CN 2020087763 W CN2020087763 W CN 2020087763W WO 2021217493 A1 WO2021217493 A1 WO 2021217493A1
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storage
layer
block
electrode
connection
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PCT/CN2020/087763
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English (en)
French (fr)
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魏侠
杨喜超
张岩
秦健鹰
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华为技术有限公司
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Priority to CN202080098708.9A priority Critical patent/CN115298826A/zh
Priority to PCT/CN2020/087763 priority patent/WO2021217493A1/zh
Publication of WO2021217493A1 publication Critical patent/WO2021217493A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/10—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout

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  • This application relates to the technical field of storage devices, and in particular to a three-dimensional ferroelectric memory and electronic equipment.
  • three-dimensional ferroelectric memory has a wide range of application prospects due to its faster reading and writing speed and higher storage capacity.
  • a three-dimensional ferroelectric memory includes a substrate and a plurality of storage layers, and the plurality of storage layers are sequentially stacked in a direction perpendicular to the substrate.
  • Each storage layer includes a reference layer and a dielectric layer on the side of the reference layer away from the substrate.
  • the dielectric layer includes a plurality of storage blocks arranged in an array on the reference layer.
  • the storage blocks and the reference layer constitute a storage unit, and the storage blocks and The reference layers are all made of ferroelectric materials.
  • Each memory block is connected with a bit line and a word line, and the reading and writing of information can be realized by using the bit line and the word line.
  • the dielectric layer and the reference layer correspond one-to-one, so that the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate is relatively large, and it is difficult to realize the miniaturization of the three-dimensional ferroelectric memory.
  • the purpose of the embodiments of the present application is to provide a three-dimensional ferroelectric memory and electronic device, by providing a first dielectric layer on the side of each reference layer away from the substrate, and providing a second dielectric layer on the side of the reference layer facing the substrate , The two dielectric layers share a reference layer to reduce the number of reference layers in the three-dimensional ferroelectric memory, thereby reducing the volume of the three-dimensional ferroelectric memory, and realizing the miniaturization of the three-dimensional ferroelectric memory.
  • the embodiment of the application discloses a three-dimensional ferroelectric memory, including: a substrate and a plurality of storage layers stacked on the substrate; each storage layer of the plurality of storage layers includes a reference layer, which is arranged on the side of the reference layer away from the substrate.
  • the first dielectric layer and the second dielectric layer share a reference layer, that is to say, the number of reference layers is half of the number of each dielectric layer.
  • the reference layer is reduced.
  • the size of the three-dimensional ferroelectric memory is reduced in the direction perpendicular to the substrate, thereby reducing the volume of the three-dimensional ferroelectric memory, and realizing the miniaturization of the three-dimensional ferroelectric memory.
  • the plurality of first storage blocks and the plurality of second storage blocks are arranged in an array, and the plurality of first storage blocks and the plurality of second storage blocks correspond to each other in a direction perpendicular to the reference layer;
  • the dielectric layer further includes a first electrode bonded to one side of the first memory block and a second electrode bonded to the other side of the first memory block;
  • the second dielectric layer further includes a third electrode bonded to one side of the second memory block, and The fourth electrode joined to the other side of the second memory block.
  • the data writing and reading of the first memory cell formed between the first memory block and the reference layer can be realized through the first electrode and the second electrode.
  • the third electrode and the fourth electrode can realize the data writing and reading of the first memory cell formed between the first memory block and the reference layer.
  • the three-dimensional ferroelectric memory further includes a first connection layer located on the side of the first storage block away from the substrate and a second connection layer located on the side of the second storage block facing the substrate.
  • the first connection layer includes parallel and spaced apart layers.
  • a plurality of first connecting lines are arranged, each of the plurality of first connecting lines is connected to a first electrode corresponding to a row of first memory blocks;
  • the second connecting layer includes a plurality of second connecting lines arranged in parallel and spaced apart A connecting line, each of the plurality of second connecting lines is connected to a third electrode corresponding to a row of second memory blocks.
  • power can be supplied to the corresponding first electrode through the first connection line, and power can be supplied to the corresponding third electrode through the second connection line, so as to facilitate the reading of data in the first storage unit and the second storage unit, or to the first storage unit and the second storage unit.
  • Data is written in a storage unit and a second storage unit.
  • the three-dimensional ferroelectric memory further includes a third connection layer located on the side of the first storage block away from the substrate and a fourth connection layer located on the side of the second storage block facing the substrate.
  • the third connection layer includes parallel and spaced apart layers.
  • a plurality of third connecting lines are arranged, each of the plurality of third connecting lines is connected to a second electrode corresponding to a row of the first memory block, and the fourth connecting layer includes a plurality of fourth connecting lines arranged in parallel and spaced apart.
  • a connecting line, each fourth connecting line of the plurality of fourth connecting lines is connected to a fourth electrode corresponding to a row of second memory blocks.
  • a first storage block can be uniquely determined through a first connection line and a third connection line, so as to accurately read data in the first storage unit composed of the first storage block and the reference layer, or to Data is written in the first storage unit; similarly, a second storage block can be uniquely determined through a second connection line and a fourth connection line, so that the second storage block and the reference layer can be accurately formed by the second storage block. Read data in the second storage unit, or write data into the second storage unit.
  • the first connection layer is located between the first storage block and the third connection layer
  • the second connection layer is located between the second storage block and the fourth connection layer.
  • each first connection line is located is parallel and spaced apart from the plane where each third connection line is located
  • the plane where each second connection line is located is parallel and spaced apart from the plane where each fourth connection line is located.
  • the wiring is more reasonable, which avoids the interference between the first connection line and the third connection line, and also avoids the interference between the second connection line and the fourth connection line.
  • the second electrode connected to the first memory block and the fourth electrode connected to the second memory block are connected.
  • the second electrode corresponding to the first memory block in each row and the fourth electrode corresponding to the second memory block can share one connection line, so as to reduce the number of conductive layers in the three-dimensional ferroelectric memory and to further reduce the three-dimensional ferroelectric memory. volume of.
  • a through hole is provided on the reference layer, and in the first memory block and the second memory block that are disposed oppositely, the second electrode connected to the first memory block and the fourth electrode connected to the second memory block are between It is connected by a conductive block provided in the through hole.
  • connection between the second electrode bonded to the first memory block and the fourth electrode bonded to the second memory block is realized by the conductive block located in the through hole, and there is no need to arrange a line outside the reference layer to connect to the first memory block.
  • the second electrode and the fourth electrode connected with the second storage block have a simple structure and are easy to manufacture.
  • the conductive block, the second electrode and the fourth electrode corresponding to the conductive block are an integral structure.
  • the conductive block, the second electrode and the fourth electrode corresponding to the conductive block can be formed by one processing, which simplifies the difficulty of manufacturing the three-dimensional ferroelectric memory.
  • the three-dimensional ferroelectric memory includes a third connection layer, and the third connection layer includes a plurality of third connection lines arranged in parallel and spaced apart, and each third connection line of the plurality of third connection lines is connected to a row of first connection lines.
  • a second electrode corresponding to a memory block is connected.
  • each second electrode in a row of the first storage block in the storage layer and each second storage block in a row of the second storage block opposite to the first storage block in the row can be realized through a third connecting line.
  • the connection between the fourth electrode is not limited to.
  • the three-dimensional ferroelectric memory includes a third connection layer, and the third connection layer includes a plurality of third connection lines arranged in parallel and spaced apart, and each third connection line of the plurality of third connection lines is connected to a row of first connection lines.
  • the fourth electrode corresponding to the two storage blocks is connected.
  • a plurality of first conductive lines are arranged between adjacent storage layers, and one end of each first conductive line of the plurality of first conductive lines is connected to a third electrode in the storage layer far from the substrate , The other end of each first conductive line in the plurality of first conductive lines is connected to the corresponding first electrode in the storage layer close to the substrate.
  • the first electrode in the storage layer close to the substrate between the adjacent storage layers is connected to the third electrode in the storage layer far from the substrate through the first conductive line, so that the first electrode in the storage layer close to the substrate among the adjacent storage layers
  • the electrode and the third electrode in the storage layer far from the substrate can be provided with a line corresponding to the external device, and the first electrode in the storage layer close to the substrate in the adjacent storage layer and the third electrode in the storage layer far away from the substrate are separately provided Compared with the conductive layer, the number of conductive layers in the three-dimensional ferroelectric memory can be reduced, thereby reducing the volume of the three-dimensional ferroelectric memory.
  • a plurality of second conductive lines are arranged between two adjacent storage layers, and one end of each second conductive line of the plurality of second conductive lines is connected to the fourth electrode in the storage layer far from the substrate. Connected, the other end of each second conductive line in the plurality of second conductive lines is connected to the corresponding second electrode in the storage layer close to the substrate; the three-dimensional ferroelectric memory further includes a fourth connection layer, and the fourth connection layer includes A plurality of fourth connecting lines are arranged in parallel and spaced apart, and each fourth connecting line of the plurality of fourth connecting lines is connected to a row of second conductive lines.
  • the connection between the fourth electrode in the storage layer far from the substrate and the second electrode in the storage layer close to the substrate in two adjacent storage layers can be realized through the second conductive line.
  • the second electrode and the fourth electrode are connected.
  • each second conductive line also realizes the first memory block and the first memory block and the The connection between each second electrode and the fourth electrode in the second memory block; in the entire three-dimensional ferroelectric memory, each second electrode and the second electrode and the first memory block in the first memory block and the second memory block that are directly opposite in the direction perpendicular to the substrate
  • the four electrodes can be connected to external devices through a connecting line.
  • the number of conductive layers in the three-dimensional ferroelectric memory can be further reduced, thereby reducing the three-dimensional ferroelectric memory volume of.
  • the fourth connection layer is disposed between the substrate and the storage layer close to the substrate, and each fourth connection line in the plurality of fourth connection lines corresponds to a row of second memory blocks in the storage layer close to the substrate.
  • the fourth electrode is connected.
  • the second electrode of the first memory block in the same row and the fourth electrode of the second memory block in the corresponding row are led out through the fourth connection line on the side of the storage layer near the substrate facing the substrate. There is no need to provide a fourth electrode between the storage layers.
  • the connection line further reduces the volume of the three-dimensional ferroelectric memory.
  • the fourth connection layer is disposed on a side of the storage layer away from the substrate away from the substrate, and each fourth connection line in the plurality of fourth connection lines corresponds to a row of first memory blocks in the storage layer away from the substrate.
  • the second electrode is connected.
  • the second electrode of the first memory block in the same row and the fourth electrode of the second memory block in the corresponding row are led out by the fourth connection line located on the side of the storage layer away from the substrate toward the substrate. There is no need to provide a fourth electrode between the storage layers.
  • the connection line further reduces the volume of the three-dimensional ferroelectric memory.
  • an insulating dielectric layer is provided between adjacent storage layers.
  • the isolation between adjacent reference layers can be achieved through the insulating layer.
  • the insulating medium layer can separate the two storage layers to achieve an insulating connection between the two storage layers, so as to avoid mutual interference between the two storage layers.
  • the reference layer, the first memory block, and the second memory block all include a resistive change material, a phase change material, and a resistive change structure.
  • the reference layer, the first memory block, and the second memory block all include ferroelectric materials.
  • the embodiment of the present application also discloses an electronic device, including a circuit board, and a three-dimensional ferroelectric memory connected to the circuit board.
  • the three-dimensional ferroelectric memory is the above-mentioned three-dimensional ferroelectric memory.
  • each storage layer includes a reference layer, and a first dielectric layer is provided on the side of the reference layer away from the substrate.
  • the dielectric layer includes a plurality of first memory blocks arranged at intervals, a second dielectric layer is arranged on the side of the reference layer facing the substrate, and the second dielectric layer includes a plurality of second memory blocks arranged at intervals, the first memory block and the second memory block.
  • the storage blocks are all attached to the reference layer, so that the first storage block and the reference layer are combined to form a first storage unit, and the second storage block is combined with the reference layer to form a second storage unit, and data is stored in each of the first storage unit and the second storage unit.
  • the first dielectric layer and the second dielectric layer share a reference layer, that is to say, the number of reference layers is half of the number of each dielectric layer.
  • the reference layer is reduced The number, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate, thereby reducing the volume of the three-dimensional ferroelectric memory, and realizing the miniaturization of the three-dimensional ferroelectric memory.
  • FIG. 1 is a first structural diagram of a three-dimensional ferroelectric memory provided by the implementation of this application;
  • FIG. 2 is a three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 1;
  • FIG. 3 is a top view of the three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 4 is a schematic diagram of the first polarization direction and the second polarization direction in the three-dimensional ferroelectric memory provided by the implementation of this application;
  • FIG. 5 is a schematic diagram of the first polarization direction and the second polarization direction in the three-dimensional ferroelectric memory provided by the implementation of this application;
  • FIG. 6 is a second structural diagram of the three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 7 is the third structural diagram of the three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 8 is a three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 7;
  • FIG. 9 is a fourth structural diagram of a three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 10 is a fifth structural schematic diagram of a three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 11 is a three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 10.
  • ferroelectric memory With the gradual development of storage device technology, three-dimensional ferroelectric memory has become a research hotspot due to its higher storage capacity and faster reading and writing speed. Among them, the ferroelectric memory that realizes data reading and writing through the ferroelectric polarization characteristics of ferroelectric materials has been widely used.
  • a three-dimensional ferroelectric memory includes a substrate and a plurality of stacked storage layers disposed on the substrate.
  • Each storage layer includes a reference layer and a dielectric layer disposed on the side of the reference layer away from the substrate.
  • the dielectric layer is included in the reference layer.
  • the multiple memory blocks set up in the upper array, the memory block and the reference layer are made of ferroelectric materials, the memory block and the reference layer constitute the memory cell; each memory block is connected to a bit line and a word line, word line and bit line Vertically set up, read or write memory cell data through word lines and bit lines.
  • each dielectric layer is correspondingly provided with a reference layer, so that the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate is large, which makes the volume of the three-dimensional ferroelectric memory larger, and it is difficult to realize the miniaturization of the three-dimensional ferroelectric memory. change.
  • the embodiment of the present application provides a three-dimensional ferroelectric memory.
  • the number of reference layers in the three-dimensional ferroelectric memory is reduced, thereby reducing the three-dimensional ferroelectric memory along the perpendicular to the substrate.
  • the size of the direction realizes the miniaturization of the three-dimensional ferroelectric memory.
  • FIG. 1 is a first structural diagram of a three-dimensional ferroelectric memory provided by the implementation of this application
  • FIG. 2 is a three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 1, as shown in FIGS. 1 and 2.
  • the three-dimensional storage provided by the embodiment of the present application includes a substrate 1 and a plurality of storage layers 2 stacked on the substrate 1, wherein the substrate 1 is used to carry each storage layer 2, and the material of the substrate 1 can be monocrystalline silicon or silicon germanium. Or one or more of germanium.
  • the storage layer 2 includes a reference layer 20, a first dielectric layer disposed on the side of the reference layer 20 away from the substrate 1, and a second dielectric layer disposed on the side of the reference layer 20 facing the substrate 1,
  • the first medium layer includes a plurality of first storage blocks 30 arranged at intervals
  • the second medium layer includes a plurality of second storage blocks 40 arranged at intervals. Both the first storage block 30 and the second storage block 40 are attached to the reference layer 20.
  • the first storage block 30 and the reference layer 20 are combined to form a first storage unit
  • the second storage block 40 and the reference layer 20 are combined to form a second storage unit.
  • Data can be stored on the first storage unit and the second storage unit. Read and write.
  • multiple first memory blocks 30 can be arranged in an array on the side of the reference layer 20 facing away from the substrate 1.
  • multiple second memory blocks 40 can also be arranged on the side of the reference layer 20 facing the substrate 1.
  • the arrangement of the array makes the arrangement of the first storage block 30 and the second storage block 40 relatively regular.
  • the number of the first storage block 30 and the second storage block 40 may be the same, and the first storage block 30 and the second storage block 40 have a one-to-one correspondence in the direction perpendicular to the reference layer 20, that is, the first storage block
  • the projection of 30 on the reference layer 20 coincides with the projection of the second memory block 40 on the reference layer 20.
  • FIG. 1 A schematic diagram of the first polarization direction and the second polarization direction of the ferroelectric memory are opposite.
  • FIG. 5 is a schematic diagram of the first polarization direction and the second polarization direction of the three-dimensional ferroelectric memory provided by the implementation of this application.
  • a domain wall channel may be formed between the first memory block 30 and the reference layer 20, the reference layer 20 has a first polarization direction, and the first memory block 30 has a second polarization direction; in data read During the process, when the first polarization direction is the same as the second polarization direction, no domain wall channel is formed between the first memory block 30 and the reference layer 20, and the first memory block 30 is in a high-resistance state.
  • the data read on the first storage unit may be "0".
  • the first polarization direction is opposite to the second polarization direction, a domain wall channel is formed between the first storage block 30 and the reference layer 20, The first memory block 30 is in a low resistance state.
  • the data read on the first memory cell may be "1"; of course, in this embodiment, when the first polarization direction is the same as the second polarization direction, No domain wall channel is formed between the first memory block 30 and the reference layer 20, and the first memory block 30 is in a high resistance state. At this time, the data read on the first memory cell may be "1".
  • the first memory block 30 is When the first polarization direction is opposite to the second polarization direction, a domain wall channel is formed between the first memory block 30 and the reference layer 20, and the first memory block 30 is in a low resistance state.
  • the read data can be "0".
  • the second storage unit is formed between the second storage block 40 and the reference layer 20, and the data reading principle of the second storage unit may be the same as that of the first storage unit, which will not be repeated here.
  • a preset voltage is applied to the first memory block 30.
  • the second polarization direction of the first memory block 30 is reversed due to the reversal of the second polarization direction.
  • the first memory block 30 changes from a high-impedance state to a low-impedance state, and writes data "1" into the first memory cell.
  • the first memory block 30 changes from a low-impedance state to a high-impedance state, The data "0" is written to the first storage unit.
  • the second polarization direction of the first memory block 30 is reversed.
  • the first memory block 30 changes from a high resistance state to a low resistance state. , The data "0" is written to the first memory cell. On the contrary, when the first memory block 30 changes from the low resistance state to the high resistance state, the data "1" is written to the first memory cell.
  • the data writing process of the second storage unit is substantially the same as the data writing process of the first storage unit, and will not be repeated here.
  • this embodiment does not limit the preset voltage, as long as the second polarization direction of the first storage block 30 is reversed when the voltage on the first storage block 30 rises to the preset voltage.
  • This embodiment does not limit the materials of the first storage block 30, the second storage block 40, and the reference layer 20, as long as it can be ensured that a domain wall channel can be formed between the first storage block 30, the second storage block 40 and the reference layer 20.
  • the first memory block 30, the second memory block 40 and the reference layer 20 can all have similar resistive switching characteristics.
  • the reference layer 20, the first memory block 30, and the second memory block 40 may all include a resistive change material, a phase change material, and a resistive change structure; wherein the resistive material may be nickel oxide (NiO), titanium oxide ( TiOx), hafnium oxide (HfOx), etc.
  • the phase change material can be mGeTe ⁇ nSb2Te3 (GST), vanadium dioxide (VO 2 ), etc.
  • the resistive change structure can be a PN junction, a magnetic tunnel junction, a ferroelectric tunnel junction, and the like.
  • the reference layer 20, the first memory block 30, and the second memory block 40 are all made of ferroelectric materials.
  • a connection line connecting the block 30 and the second storage block 40 In order to obtain data in the first storage unit and the second storage unit, or to write data into the first storage unit and the second storage unit; A connection line connecting the block 30 and the second storage block 40.
  • the current flowing through the first storage block 30 and the second storage block 40 can be obtained through the connecting line to determine the resistance state of the first storage block 30 and the second storage block 40, thereby realizing the first storage unit And the reading of data in the second storage unit; during data writing, a voltage can be applied to the first storage unit and the second storage unit through the connecting line, and when the voltage reaches the preset voltage, the first storage block 30 and the second storage unit The polarization direction of the second memory block 40 is changed to realize data writing.
  • a plurality of storage layers 2 are stacked on a substrate 1, and the storage layer 2 includes a reference layer 20.
  • a first dielectric layer is provided on the side of the reference layer 20 away from the substrate 1.
  • the layer includes a plurality of first memory blocks 30 arranged at intervals, a second dielectric layer is arranged on the side of the reference layer 20 facing the substrate 1, and the second media layer includes a plurality of second memory blocks 40 arranged at intervals.
  • Both the second storage block 30 and the second storage block 40 are attached to the reference layer 20, so that the first storage block 30 and the reference layer 20 are combined to form a first storage unit, and the second storage block 40 is combined with the reference layer 20 to form a second storage unit.
  • the first medium layer and the second medium layer share a reference layer 20, that is to say, the number of reference layers 20 is half of the number of each medium layer, and a reference layer 20 Compared with a corresponding dielectric layer, the number of reference layers 20 is reduced, and the size of the three-dimensional ferroelectric memory is reduced in the direction perpendicular to the substrate 1, thereby reducing the volume of the three-dimensional ferroelectric memory and realizing the three-dimensional ferroelectric Miniaturization of memory.
  • the first dielectric layer further includes a first electrode 301 arranged on one side of the first memory block 30 and a first electrode 301 arranged on the first memory block 30.
  • the second electrode 302 on the other side of 30, the first electrode 301 and the second electrode 302 are all joined to the first memory block 30, and the data in the first memory cell can be read through the first electrode 301 and the second electrode 302.
  • the second dielectric layer also includes a third electrode 401 arranged on one side of the second memory block 40 and a fourth electrode 402 arranged on the other side of the second memory block 40.
  • the third electrode 401 and the fourth electrode 402 are both It is connected to the second memory block 40, and the data in the second memory cell can be read through the third electrode 401 and the fourth electrode 402. Of course, the data in the second memory cell can also be read through the third electrode 401 and the fourth electrode 402. data input.
  • the first electrode 301 and the second electrode 302 may both be made of metal materials such as copper and silver.
  • the first electrode 301 and the second electrode 302 may also be made of other non-metallic conductive materials.
  • the third electrode 401 and the fourth electrode 402 can both be made of metal materials such as copper, silver, etc.
  • the third electrode 401 and the fourth electrode 402 can also be made of other non-metal conductive materials.
  • the three-dimensional ferroelectric memory in this embodiment may be a bipolar memory, that is, the readout direction of the three-dimensional ferroelectric memory does not depend on the polarization direction of the reference layer 20, that is to say, the polarization direction of the reference layer 20 and the flow through the first
  • the current direction of a memory block 30 is the same or opposite
  • data can be read.
  • the first electrode 301 is higher than the voltage of the second electrode 302
  • the voltage of the first electrode 301 is lower than the voltage of the second electrode 302
  • the first storage block 30 corresponding to the first storage The cells can read data.
  • the voltage of the third electrode 401 is higher than the voltage of the fourth electrode 402
  • the second memory block The second storage unit corresponding to 40 can read data.
  • the three-dimensional ferroelectric memory in this embodiment can also be a unipolar memory, that is, the readout direction of the three-dimensional ferroelectric memory depends on the polarization direction of the reference layer 20, that is, the polarization direction of the reference layer 20 and Data can be read only when the direction of current flowing through the first memory block 30 is opposite. Similarly, when the polarization direction of the reference layer 20 is opposite to the direction of current flowing through the second memory block 40, data can be read.
  • the polarization direction of the reference layer 20 is that the first electrode 301 points to the second electrode 302, and only when the voltage of the first electrode 301 is lower than the voltage of the second electrode 302, the first memory block 30 corresponds to the first
  • the memory cell can read data; when the polarization direction of the reference layer is that the second electrode 302 points to the first electrode 301, only when the voltage of the first electrode 301 is higher than the voltage of the second electrode 302, the first memory block 30 corresponds to In the same way, the polarization direction of the reference layer 20 is that the third electrode 401 points to the fourth electrode 402, and only when the voltage of the third electrode 401 is lower than the voltage of the fourth electrode 402, The first memory cell corresponding to the first memory block 40 can read data; the polarization direction of the reference layer 20 is that the fourth electrode 402 points to the third electrode 401, only when the voltage of the third electrode 401 is higher than that of the fourth electrode 402 When the voltage is applied, the first memory cell corresponding to the first memory block 30 can read
  • the relative first storage In the block 30 and the second memory block 40 the first electrode 301 and the third electrode 401 may be directly opposite, and the corresponding second electrode 302 and the fourth electrode 402 may be arranged directly opposite to each other.
  • an insulating dielectric layer 5 is provided between adjacent storage layers 2.
  • the insulating dielectric layer 5 can separate the two storage layers 2 to achieve a gap between the two storage layers 2. Insulation connection, so as to avoid mutual interference between the two storage layers 2.
  • FIG. 3 is a top view of the three-dimensional ferroelectric memory provided by the implementation of this application, and continue to refer to FIGS. 1 to 3.
  • the three-dimensional ferroelectric memory includes a first connection layer disposed on the side of the first storage block 30 away from the substrate 1 and a second connection layer disposed on the first side of the second storage block 40 facing the substrate 1.
  • the connection layer includes a plurality of first connection lines 50 arranged in parallel and spaced apart.
  • Each first connection line 50 of the plurality of first connection lines 50 is connected to a row of first electrodes 301 corresponding to the first memory blocks 30, and the second connection layer includes A plurality of second connecting wires 60 are arranged in parallel and spaced apart, and each second connecting wire 60 of the plurality of second connecting wires 60 is electrically connected to the third electrodes 401 of a row of second memory blocks 40.
  • power can be supplied to the corresponding first electrode 301 through the first connection line 50, and power can be supplied to the corresponding third electrode 401 through the second connection line 60, so as to facilitate the reading of data in the first storage unit and the second storage unit , Or write data to the first storage unit and the second storage unit.
  • the three-dimensional ferroelectric memory further includes a third connection layer disposed on the side of the first storage block 30 away from the substrate 1 and a fourth connection layer disposed on the side of the second storage block 40 facing the substrate 1.
  • the third connection layer It includes a plurality of third connection lines 70 arranged in parallel and spaced apart. Each third connection line 70 of the plurality of third connection lines 70 is connected to the second electrode 302 corresponding to a row of the first memory block 30, and the fourth connection layer includes A plurality of fourth connecting lines 80 are arranged in parallel and spaced apart, and each fourth connecting line 80 of the plurality of fourth connecting lines 80 is connected to a row of fourth electrodes 402 corresponding to the second memory blocks 40.
  • the data reading or writing corresponding to the first storage unit can be realized through the first connection line 50 and the third connection line 70.
  • the corresponding second connection line 60 and the fourth connection line 80 can be realized. 2. Data reading or writing of the storage unit.
  • first connection line 50, the second connection line 60, the third connection line 70, and the fourth connection line 80 may all be metal lines mainly composed of metal materials such as copper, silver, etc., of course, the first connection line 50.
  • the second connection line 60, the third connection line 70, and the fourth connection line 80 may also be mainly composed of other non-metal conductive materials.
  • the extending direction of the first connection line 50 and the second connection line 60 may be parallel to the column direction of the first storage block 30 and the second storage block 40, and the third connection line 70 and the fourth connection may be connected to the first storage block 30 and the first storage block 30 and the second storage block 40.
  • the row directions of the two memory blocks 40 are parallel.
  • the first connection line 50 and the second connection line 60 can be word lines
  • the third connection line 70 and the fourth connection line 80 are bit lines
  • the first connection line 50 and the second connection line 60 can be They are bit lines.
  • the third connection line 70 and the fourth connection line 80 are word lines.
  • One first memory block 30 can be selected uniquely among the plurality of first memory blocks 30 arranged in the array through a first connection line 50 and a third connection line 70; that is, one first connection line 50 and one first connection line 50 can be selected arbitrarily.
  • the third connection line 70, the position where the first connection line 50 and the third connection line 70 cross is the selected first memory block 30, and the first electrode 301 of the selected first memory block 30 is connected to the first connection line 50, the second electrode 302 of the selected first memory block 30 is connected to the third connection line 70.
  • the first connection line 50 and the third connection line 70 can realize the second electrode 302 corresponding to the selected first memory block 30.
  • a storage unit data reading and writing.
  • a second connecting line 60 and a fourth connecting line 80 it is possible to uniquely select a second memory block 40 among the plurality of second memory blocks 40 arranged in the array, and the second connecting line 60 is connected to the fourth The line 80 can implement data reading and writing of the second memory cell corresponding to the selected second memory block 40.
  • the first connecting line 50 may be arranged on a side of the corresponding column of first memory blocks 30 away from the substrate 1, and the first connecting line 50 may be connected to the corresponding column of first memory blocks 30.
  • Each first electrode 301 is attached to a side away from the substrate 1 so that the first connection line 50 can make good contact with each first electrode 301 of a corresponding row of first memory blocks 30.
  • the second connection line 60 may be arranged on the side of the corresponding column of the second memory block 40 facing the substrate 1, and the second connection line 60 and each third electrode 401 of the corresponding column of the second memory block 40 may face the substrate 1.
  • the third connection line 70 may be arranged on the side of each corresponding first memory block 30 away from the substrate 1, and the third connection line 70 is attached to the side of each second electrode 302 of the corresponding row of first memory block 30 away from the substrate. combine.
  • the fourth connecting line 80 may be arranged on the side of the corresponding row of the second memory block 40 facing the substrate 1, and the fourth connecting line 80 and the fourth electrode 402 of the corresponding row of the second memory block 40 may be attached to the side facing the substrate 1. Together, so that the fourth connection line 80 is in good contact with the fourth electrode 402 of the corresponding row of the second memory block 40.
  • first connection layer may be located between the first storage block 30 and the third connection layer
  • second connection layer may be located between the second storage block 40 and the fourth connection layer.
  • first connecting line 50 is located and the plane where each third connecting line 70 is located are parallel and spaced apart
  • second connecting line 60 is located and each fourth connecting line 80 are located
  • the planes are arranged in parallel and spaced apart; the wiring is more reasonable, which avoids the interference between the first connection line 50 and the third connection line 70, and at the same time prevents the second connection line 60 and the fourth connection line 80 from interfering with each other.
  • each third connection line 70 may be provided with a first contact block extending to the corresponding first storage block 30.
  • the third connection line 70 is connected to each third electrode 401 through the first contact block; the same, the distance between the fourth connection layer and the second memory block 40 is relatively large, at this time, the direction can be set on the fourth connection line 80
  • the second contact block extending from the second storage block 40 realizes the connection between the fourth connection line 80 and the fourth electrode 402 through the second contact block; wherein the first contact block and the third connection line 70 are formed by one processing
  • the fourth connecting line 80 and the second contact block may also be an integrated structure formed by one processing.
  • the three-dimensional ferroelectric memory includes multiple stacked storage layers 2, and the structure of each storage layer 2 may be the same as the structure of the storage layer 2 in the foregoing implementation manner; or the three-dimensional ferroelectric memory of this embodiment Part of the storage layer 2 in is the same structure as the storage layer 2 in the above implementation.
  • the first connection line 50 and the second connection line 60 may be word lines, and the corresponding third connection line 70 and the fourth connection line 80 are bit lines; or the first connection line 50 and the second connection line 60 may be a bit line, and the corresponding third connection line 70 and fourth connection line 80 are word lines.
  • the corresponding voltage configuration can include: floating mode, ground mode, 1/2 bias voltage mode and 1/3 bias voltage mode.
  • the floating mode can be unselected word line and bit line without voltage configuration, selected word line configuration Certain voltage; grounding mode can be unselected word line and bit line grounding, selected word line is configured with a certain voltage; 1/2 bias voltage mode can be unselected word line and bit line configuration voltage is 1 of the selected word line /2; 1/3 bias voltage mode can be that the voltage of the unselected word line configuration is 1/3 of the selected word line, and the voltage of the unselected bit line configuration is 2/3 of the selected word line.
  • FIG. 6 is the second structural diagram of the three-dimensional ferroelectric memory provided by the implementation of this application, and continue to refer to FIG. 6; since electrodes are provided on both sides of the reference layer 20, in order to prevent the current in the electrodes on one side of the reference layer 20 from reaching the reference layer 20
  • the electrode on the other side of the layer 20, that is, in order to avoid leakage between the electrodes on both sides of the reference layer 20, the opposing first memory block 30 and the second memory block 40 may have a predetermined distance L along the direction parallel to the reference layer 20 .
  • a reasonable setting of the predetermined distance L can reduce the leakage current between the electrodes on both sides of the reference layer 20, thereby reducing the leakage current and crosstalk between the electrodes on both sides of the reference layer 20.
  • FIG. 7 is the third structural diagram of the three-dimensional ferroelectric memory provided by the implementation of this application.
  • FIG. 8 is the three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 7, as shown in FIGS. 7 and 8;
  • the plurality of first storage blocks 30 and the plurality of second storage blocks 40 are in one-to-one correspondence, and one side of each first storage block 30 is provided with a first electrode 301 ,
  • Each first memory block 30 is provided with a second electrode 302 on the other side, correspondingly, each second memory block 40 is provided with a third electrode 401 on one side, and each second memory block 40 is provided on the other side
  • a fourth electrode 402 is provided.
  • the second electrode 302 joined to the first memory block 30 and the fourth electrode 402 joined to the second memory block 40 are connected.
  • connection lines connected to the second electrode 302 and the fourth electrode 402 and the connection lines connected to the first electrode 301 and the second electrode 302 are It can realize the data reading and writing of the first storage unit and the second storage unit; that is, the second electrode 302 and the fourth electrode 402 can share a connection line, thereby reducing the number of conductive layers in the three-dimensional ferroelectric memory , In order to further reduce the volume of the three-dimensional ferroelectric memory.
  • the first electrode 301 may be arranged directly opposite to the second electrode 302, and the corresponding third electrode 401 may be arranged directly opposite to the fourth electrode 402;
  • the layer 20 is provided with a through hole.
  • the second electrode 302 connected to the first memory block 30 and the fourth electrode 402 connected to the second memory block 40 The connection is made by a conductive block 201 provided in the through hole.
  • the conductive block 201 and the second electrode 302 and the fourth electrode 402 corresponding to the conductive block 201 may be an integral structure; such a configuration can form the conductive block 201 and the second electrode corresponding to the conductive block 201 through one processing.
  • the second electrode 302 and the fourth electrode 402 simplify the manufacturing difficulty of the three-dimensional ferroelectric memory; for example, the conductive block 201 and the second electrode 302 and corresponding second electrode 302 and the conductive block 201 may be formed by evaporation, deposition or electroplating.
  • the conductive block 201 and the second electrode 302 and the fourth electrode 402 corresponding to the conductive block 201 may also be of a split structure. In this case, the conductive block 201 and the corresponding second electrode 302 is in contact with the fourth electrode 402.
  • the three-dimensional ferroelectric memory includes a first connection layer disposed on the side of the first memory block 30 away from the substrate 1, and a second connection layer disposed on the side of the second memory block 40 away from the substrate 1.
  • the first connection The layer includes a plurality of first connecting lines 50 arranged in parallel and spaced apart. The extending direction of the first connecting lines 50 is parallel to the column direction of the first memory blocks 30 arranged in the array, and the first connecting lines 50 are connected to a row of first memory blocks 30.
  • the corresponding first electrodes 301 are connected;
  • the second connection layer includes a plurality of second connection wires 60 arranged in parallel and spaced apart. The extension direction of the second connection wires 60 is parallel to the column direction of the second memory blocks 40 arranged in the array.
  • a second connecting line 60 is connected to each third electrode 401 of a row of second memory blocks 40.
  • the three-dimensional ferroelectric memory further includes a third connection layer.
  • the third connection layer includes a plurality of third connection lines 70 arranged in parallel and spaced apart. Each third connection line 70 of the plurality of third connection lines 70 is connected to one row.
  • the second electrode 302 corresponding to the first memory block 30 is connected.
  • the second electrode 302 and the fourth electrode 402 can be connected to the outside through the third connection line 70 connected to the second electrode 302 corresponding to the first memory block 30 Connection; at this time, a first memory block 30 can be uniquely selected through the first connection line 50 and the third connection line 70, and the selected first memory block can be selected through the first connection line 50 and the third connection line 70
  • the first storage unit corresponding to 30 performs data reading or writing; similarly, a second storage block 40 can be uniquely selected through the second connection line 60 and the third connection line 70, and the second storage block 40 can be selected through the second connection line 60
  • the third connecting line 70 can read or write data to the second memory cell corresponding to the selected second memory block 40.
  • the third connection line 70 may be disposed on the side of the first storage block 30 away from the substrate 1, and the first connection line 50 is located between the first storage block 30 and the third connection line 70.
  • the third connection layer may also be provided on the side of the second storage block 40 facing the substrate 1, and the second connection layer is located between the third connection layer and the second storage block 40; correspondingly
  • the third connection layer may include a plurality of third connection lines 70 arranged in parallel and spaced apart.
  • the extension direction of the third connection lines 70 may be parallel to the row direction of the plurality of second memory blocks 40 arranged in the array, and each third connection The line 70 is connected to the fourth electrode 402 corresponding to the second memory block 40 in a row.
  • the three-dimensional ferroelectric memory includes a plurality of stacked storage layers 2.
  • the structure of each storage layer 2 may be the same as the structure of the storage layer 2 in the above implementation; or, part of the storage layer 2 is the same as the above implementation.
  • the storage layer 2 in the structure is the same.
  • FIG. 9 is the fourth structural diagram of the three-dimensional ferroelectric memory provided by the implementation of this application, and continue to refer to FIG. 9.
  • the plurality of first storage blocks 30 and the plurality of second storage blocks 40 have a one-to-one correspondence, and each first storage block 30 A first electrode 301 is provided on one side of each first memory block 30, and a second electrode 302 is provided on the other side of each first memory block 30.
  • a third electrode 401 is provided on one side of each second memory block 40, and each A fourth electrode 402 is provided on the other side of the second memory block 40.
  • the second electrode 302 joined to the first memory block 30 and the fourth electrode 402 joined to the second memory block 40 are connected.
  • a plurality of first conductive wires 3 are arranged between adjacent storage layers 2, and one end of each first conductive wire 3 of the plurality of first conductive wires 3 is connected to one of the first conductive wires 3 in the storage layer 2 far away from the substrate 1.
  • the three electrodes 401 are connected, and the other end of each first conductive wire 3 of the plurality of first conductive wires 3 is connected to the corresponding first electrode 301 in the storage layer 2 close to the substrate 1.
  • the first electrode 301 in the storage layer 2 close to the substrate 1 between the adjacent storage layers 2 is connected to the third electrode 401 in the storage layer 2 far away from the substrate 1 through the first conductive line 3, so that the adjacent storage layer 2
  • the first electrode 301 in the storage layer 2 close to the substrate 1 and the third electrode 401 in the storage layer 2 far from the substrate 1 can be provided with a corresponding line to connect to external devices, and to the storage layer of the adjacent storage layer 2 close to the substrate 1.
  • the number of conductive layers in the three-dimensional ferroelectric memory can be reduced, thereby reducing the volume of the three-dimensional ferroelectric memory.
  • the first conductive lines 3 between two adjacent storage layers 2 are arranged in an array, and an intermediate conductive layer may be arranged between two adjacent storage layers 2.
  • the intermediate conductive layers include parallel and spaced arrangements.
  • a plurality of intermediate connecting lines, each intermediate connecting line is connected to a row of first conductive lines 3.
  • the storage layer 2 is provided with a first connection layer and a second connection layer, the first connection layer is disposed on the side of the first storage block 30 away from the substrate 1, and the first connection layer includes a plurality of first connection layers arranged in parallel and spaced apart.
  • a connecting line 50, the extending direction of the first connecting line 50 is the same as the column direction of the first memory block 30, the first connecting line 50 is connected to the first electrode 301 corresponding to a column of the first memory block 30; the second connecting layer is located here
  • the second storage block 40 in the storage layer 2 faces the side of the substrate 1.
  • the second connection layer includes a plurality of second connection lines 60 arranged in parallel and spaced apart.
  • each second connection line 60 is connected to the third electrode 401 of the second memory block 40; each storage layer 2 is also provided with a third connection layer, and each third connection layer is located where The first storage block 30 of the storage layer 2 is on the side facing away from the substrate 1.
  • the third connection layer includes a plurality of third connection lines 70 arranged in parallel and spaced apart. The extension direction of the third connection lines 70 corresponds to the first storage block 30 The row directions of are parallel, and each third connecting line 70 is connected to the second electrode 302 corresponding to a row of the first memory block 30.
  • the third connection line 70 in the two storage layers 2 connected by the intermediate connection line and the intermediate connection line can be selected from the two storage layers 2 close to the substrate 1
  • a first storage block 30 in the storage layer 2 and a second storage block 40 in the storage layer 2 far from the substrate 1 further realize the reading or writing of corresponding storage cell data.
  • the third connection line 70 and the second connection line 60 in the storage layer 2 can be used to uniquely select a second storage block 40 in the storage layer 2 to realize the first Reading or writing of data in the second storage unit corresponding to the second storage block 40.
  • a first storage block 30 can be uniquely selected through the first connection line 50 and the third connection line 70, and then the data of the first storage unit corresponding to the first storage block 30 can be read. Fetch or write.
  • each storage layer 2 may not be provided with a third connection layer, and correspondingly, a fourth connection layer is provided on the side of the second storage block 40 facing the substrate 1 in each storage layer 2.
  • the four connecting layers include a plurality of fourth connecting lines 80 arranged in parallel and spaced apart. The extending direction of the fourth connecting lines 80 is parallel to the row direction of the second memory blocks 40, and each fourth connecting line 80 is connected to a row of the second memory blocks 40.
  • the corresponding fourth electrode 402 is connected; since the second electrode 302 and the fourth electrode 402 are connected between the opposing first memory block 30 and the second memory block 40, the fourth connection line 80 and the third connection line 70 Has the same effect.
  • FIG. 10 is a schematic diagram 5 of the structure of the three-dimensional ferroelectric memory provided by the implementation of this application
  • FIG. 11 is a three-dimensional structure diagram of the three-dimensional ferroelectric memory in FIG. 10, and continue to refer to FIG. 10 and FIG. 11.
  • the plurality of first storage blocks 30 and the plurality of second storage blocks 40 have a one-to-one correspondence, and each first storage block 30
  • a first electrode 301 is provided on one side of each first memory block 30, and a second electrode 302 is provided on the other side of each first memory block 30.
  • a third electrode 401 is provided on one side of each second memory block 40, and each The other side of the second memory block 40 is provided with a fourth electrode 402; among them, opposite to the first memory block 30 and the second memory block 40, the second electrode 302 connected to the first memory block 30 and the second memory block 40 is connected between the fourth electrodes 402 joined.
  • a plurality of second conductive wires 4 are arranged between two adjacent storage layers 2, and one end of each second conductive wire 4 of the plurality of second conductive wires 4 is connected to the storage layer 2 far away from the substrate 1.
  • the fourth electrode 402 is connected, and the other end of each second conductive wire 4 of the plurality of second conductive wires 4 is connected to the corresponding second electrode 302 in the storage layer 2 close to the substrate 1;
  • the three-dimensional ferroelectric memory includes a fourth connection
  • the fourth connection layer includes a plurality of fourth connection lines 80 arranged in parallel and spaced apart, and each fourth connection line 80 of the plurality of fourth connection lines 80 is connected to a row of second conductive lines 4.
  • each second conductive line 4 also realizes the entire three-dimensional ferroelectric memory
  • Each of the second electrode 302 and the fourth electrode 402 in the first memory block 30 and the second memory block 40 that are directly opposite to each other can be connected to an external device through a connecting line, and each memory layer 2 is provided with a second electrode 302 Compared with the connecting wires, the number of conductive layers in the three-dimensional ferroelectric memory can be further reduced, thereby reducing the volume of the three-dimensional ferroelectric
  • each storage layer 2 may also have a first connection layer and a second connection layer.
  • the first connection layer may be disposed on the side of the storage layer 2 where the first storage block 30 faces away from the substrate 1.
  • a connecting layer includes a plurality of first connecting lines 50 arranged in parallel and spaced apart. The extending direction of the first connecting lines 50 is parallel to the column direction of the first memory blocks 30, and each first connecting line 50 is connected to a row of first memory blocks 30.
  • the corresponding first electrode 301 is connected; the second connection layer can be arranged on the side of the storage layer 2 where the second memory block 40 faces the substrate 1.
  • the second connection layer includes a plurality of second connection lines 60 arranged in parallel and spaced apart, The extending direction of the second connecting lines 60 is parallel to the column direction of the second memory blocks 40, and each second connecting line 60 is connected to a row of third electrodes 401 corresponding to the second memory blocks 40.
  • the three-dimensional ferroelectric memory includes a fourth connection layer.
  • the fourth connection layer includes a plurality of fourth connection lines 80 arranged in parallel and spaced apart. Each fourth connection line 80 of the plurality of fourth connection lines 80 is connected to a row of second conductive lines. 4Connect.
  • a first storage block 30 can be selected uniquely, so as to realize the reading and writing of data in the first storage unit corresponding to the first storage block 30;
  • the fourth connection line 80 and the second connection line 60 can uniquely select a second storage block 40 to realize the reading and writing of data in the second storage unit corresponding to the second storage block 40.
  • the fourth connection layer may be disposed between the substrate 1 and the storage layer 2 close to the substrate 1, and each fourth connection line 80 of the plurality of fourth connection lines 80 is connected to one row in the storage layer 2 close to the substrate 1.
  • the fourth electrode 402 corresponding to the second memory block 40 is connected.
  • the second electrode 302 of the first memory block 30 in the same row and the fourth electrode 402 of the second memory block 40 in the corresponding row pass through the fourth connection line 80 located on the side of the memory layer 2 near the substrate 1 facing the substrate 1. It is concluded that there is no need to provide a fourth connection line 80 between the storage layers 2 to further reduce the volume of the three-dimensional ferroelectric memory.
  • the fourth connection layer may also be disposed on the side of the storage layer 2 away from the substrate 1 away from the substrate 1.
  • Each fourth connection line 80 of the plurality of fourth connection lines 80 is connected to the storage layer 2 away from the substrate 1.
  • the second electrode 302 corresponding to the row of the first memory block 30 in layer 2 is connected. In this way, the second electrode 302 of the first memory block 30 in the same row and the fourth electrode 402 of the second memory block 40 in the corresponding row pass through the fourth connecting line 80 located on the side of the memory layer 2 away from the substrate 1 facing the substrate 1. It is concluded that there is no need to provide a fourth connection line 80 between the storage layers 2 to further reduce the volume of the three-dimensional ferroelectric memory.
  • an embodiment of the present application also provides an electronic device, including a circuit board and a three-dimensional ferroelectric memory connected to the circuit board.
  • the three-dimensional ferroelectric memory may be the three-dimensional ferroelectric memory described in the above embodiment.
  • the circuit board may be a printed circuit board (PCB), of course, the circuit board may also be a flexible circuit board (FPC), etc.
  • PCB printed circuit board
  • FPC flexible circuit board
  • a plurality of storage layers 2 are stacked on the substrate 1 of the three-dimensional ferroelectric memory.
  • the storage layer 2 includes a reference layer 20, and a first A dielectric layer, the first dielectric layer includes a plurality of first memory blocks 30 arranged at intervals, a second dielectric layer is arranged on the side of the reference layer 20 facing the substrate 1, and the second dielectric layer includes a plurality of second memory blocks arranged at intervals 40.
  • Both the first storage block 30 and the second storage block 40 are attached to the reference layer 20, so that the first storage block 30 is combined with the reference layer 20 to form a first storage unit, and the second storage block 40 is combined with the reference layer 20 to form The second storage unit, data is stored in each of the first storage unit and the second storage unit; the first medium layer and the second medium layer share a reference layer 20, that is to say, the number of reference layers 20 is half of the number of each medium layer Compared with a dielectric layer corresponding to a reference layer 20, the number of reference layers 20 is reduced, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate 1, thereby reducing the volume of the three-dimensional ferroelectric memory , Realizing the miniaturization of three-dimensional ferroelectric memory.

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Abstract

本申请实施例属于存储设备技术领域，具体涉及一种三维铁电存储器及电子设备。本申请实施例旨在解决相关技术中三维铁电存储器的尺寸较大，难以实现三维铁电存储器的小型化的问题。本申请实施的三维铁电存储器及电子设备，存储层包括参考层，在参考层背离基底的一侧设置有第一介质层，第一介质层包括多个间隔设置的第一存储块，在参考层朝向基底的一侧设置有第二介质层，第二介质层包括多个间隔设置的第二存储块；第一介质层和第二介质层共用一个参考层，与一个参考层对应设置一个介质层相比，减少了参考层的数量，进而在垂直于基底的方向减小了三维铁电存储器的尺寸，进而减小了三维铁电存储器的体积，实现了三维铁电存储器的小型化。

Description

三维铁电存储器及电子设备 技术领域
本申请涉及存储设备技术领域，尤其涉及一种三维铁电存储器及电子设备。
背景技术
随着存储设备技术的逐渐发展，三维铁电存储器以其较快的读写速度以及较高的存储能力，具有广泛的应用前景。
相关技术中，三维铁电存储器包括基底以及多个存储层，多个存储层沿垂直于基底方向依次层叠设置。每个存储层包括参考层、位于参考层背离基底一侧的介质层，介质层包括在参考层上阵列排布的多个存储块，存储块均与参考层共同构成存储单元，且存储块和参考层均由铁电材料构成。每个存储块连接有一条位线和一条字线，利用位线和字线可以实现信息的读取和写入。
然而，相关技术中，介质层与参考层一一对应，使得沿垂直于基底的方向上三维铁电存储器的尺寸较大，难以实现三维铁电存储器的小型化。
发明内容
本申请实施例的目的在于提供一种三维铁电存储器及电子设备，通过在每一参考层背离基底的一侧设置第一介质层，并且在该参考层朝向基底的一侧设置第二介质层，两个介质层共用一个参考层，以减少三维铁电存储器中参考层的数量，进而缩小三维铁电存储器的体积，实现了三维铁电存储器的小型化。
本申请实施例公开了一种三维铁电存储器，包括：基底和在基底上层叠设置的多个存储层；多个存储层中的每个存储层包括参考层、设置在参考层背离基底一侧的第一介质层、设置在参考层朝向基底一侧的第二介质层，第一介质层包括间隔设置的多个第一存储块，第二介质层包括间隔设置的多个第二存储块，多个第一存储块中每一第一存储块和多个第二存储块中每一第二存储块均与参考层贴合，每一第一存储块与参考层组合形成一个第一存储单元，每一第二存储块与参考层组合形成一个第二存储单元。
基于上述技术内容，第一介质层和第二介质层共用一个参考层，也就说参考层的数量是各介质层数量的一半，与一个参考层对应设置一个介质层相比，减少了参考层的数量，进而在垂直于基底的方向减小了三维铁电存储器的尺寸，进而减小了三维铁电存储器的体积，实现了三维铁电存储器的小型化。
在一个实现方式中，多个第一存储块以及多个第二存储块均阵列设置，且多个第一存储块和多个第二存储块在垂直于参考层的方向一一对应；第一介质层还包括与第一存储块一侧接合的第一电极以及与第一存储块另一侧接合的第二电极；第二介质层还包括与第二存储块一侧接合的第三电极以及与第二存储块另一侧接合的第四电极。
如此设置，通过第一电极和第二电极可以实现第一存储块与参考层之间构成的第一存储单元的数据写入和读取，相同的，通过第三电极和第四电极可以实现第二存储块与参考层之间构成的第二存储单元的数据写入和读取。
在一个实现方式中，三维铁电存储器还包括位于第一存储块背离基底一侧的第一连接层和位于第二存储块朝向基底一侧的第二连接层，第一连接层包括平行且间隔设置的多个第一连接线，多个第一连接线中的每一第一连接线与一列第一存储块对应的第一电极连接；第二连接层包括平行且间隔设置的多个第二连接线，多个第二连接线中的每一第二连接线与一列第二存储块对应的第三电极连接。
如此设置，可以通过第一连接线向对应的第一电极供电，通过第二连接线向对应的第三电极供电，以便于第一存储单元和第二存储单元内数据的读取、或者向第一存储单元和第二存储单元内写入数据。
在一个实现方式中，三维铁电存储器还包括位于第一存储块背离基底一侧的第三连接层以及位于第二存储块朝向基底一侧的第四连接层，第三连接层包括平行且间隔设置的多个第三连接线，多个第三连接线中的每一第三连接线与一行第一存储块对应的第二电极连接，第四连接层包括平行且间隔设置的多个第四连接线，多个第四连接线中的每一第四连接线与一行第二存储块对应的第四电极连接。
如此设置，通过一个第一连接线和一个第三连接线可以唯一确定一个第一存储块，以便于准确的由该第一存储块和参考层构成的第一存储单元内读取数据，或者向该第一存储单元内写入数据；相同的，通过一个第二连接线和一个第四连接线可以唯一确定一个第二存储块，以便于准确的由该第二存储块和参考层构成的第二存储单元内读取数据，或者向该第二存储单元内写入数据。
在一个实现方式中，第一连接层位于第一存储块和第三连接层之间，第二连接层位于第二存储块和第四连接层之间。
如此设置，各第一连接线所处的平面和各第三连接线所处的平面平行且间隔的设置，各第二连接线所处的平面和各第四连接线所处的平面平行且间隔的设置；布线较为合理，避免了第一连接线和第三连接线互相干扰，同时也避免了第二连接线和第四连接线互相干扰。
在一个实现方式中，相对的第一存储块和第二存储块中，与第一存储块接合的第二电极和与第二存储块接合的第四电极之间连接。
如此设置，每一行第一存储块对应的第二电极以及第二存储块对应的第四电极可以共用一个连接线，以减少三维铁电存储器中导电层的数目，以进一步减小三维铁电存储器的体积。
在一个实现方式中，参考层上设置贯通孔，相对设置的第一存储块和第二存储块中，与第一存储块接合的第二电极和与第二存储块接合的第四电极之间通过设置在贯通孔内的导电块连接。
通过位于贯通孔内的导电块实现与第一存储块接合的第二电极和与第二存储块接合的第四电极之间的连接，无需在参考层外设置线路以连接与第一存储块接合的第二电极和与第二存储块接合的第四电极，结构简单，便于制作。
在一个实现方式中，导电块、与该导电块对应的第二电极和第四电极为一体结构。
如此设置，可以通过一次加工形成导电块、与该导电块对应的第二电极和第四电极，简化了三维铁电存储器的制作难度。
在一个实现方式中，三维铁电存储器包括第三连接层，第三连接层包括平行且间隔设置的多个第三连接线，多个第三连接线中的每一第三连接线与一行第一存储块对应的第二电极连接。
如此设置，同一存储层中，可以通过一个第三连接线实现该存储层中一行第一存储块中的各第二电极、以及与该行第一存储块相对的一行第二存储块中的各第四电极之间的连接。
在一个实现方式中，三维铁电存储器包括第三连接层，第三连接层包括平行且间隔设置的多个第三连接线，多个第三连接线中的每一第三连接线与一行第二存储块对应的第四电极连接。
在一个实现方式中，相邻存储层之间设置有多个第一导电线，多个第一导电线中的每一第一导电线的一端与远离基底的存储层中的一个第三电极连接，多个第一导电线中的每一第一导电线的另一端与靠近基底的存储层中的相应的第一电极连接。
如此设置，相邻存储层之间靠近基底的存储层中第一电极与远离基底的存储层中第三电极通过第一导电线连接，使得相邻的存储层中靠近基底的存储层中第一电极与远离基底的存储层中第三电极可以对应设置一个线路与外界设备连接，与相邻的存储层中靠近基底的存储层中第一电极与远离基底的存储层中第三电极均单独设置导电层相比，可以减少三维铁电存储器中导电层的数量，进而减小三维铁电存储器的体积。
在一个实现方式中，相邻两个存储层之间设置有多个第二导电线，多个第二导电线中的每一第二导电线的一端与远离基底的存储层中的第四电极连接，多个第二导电线中的每一第二导电线的另一端与靠近基底的存储层中的相应的第二电极连接；三维铁电存储器还包括第四连接层，第四连接层包括平行且间隔设置的多个第四连接线，多个第四连接线中的每一第四连接线与一行第二导电线连接。
如此设置，通过第二导电线可以实现相邻两个存储层中远离基底的存储层中的第四电极和靠近基底的存储层中的第二电极之间的连接，由于每一存储层中相对的第一存储块和第二存储块中，第二电极和第四电极连接，此时各第二导电线还实现了整个三维铁电存储器中沿垂直于基底方向正对的第一存储块和第二存储块中各第二电极和第四电极之间的连接；整个三维铁电存储器中，沿垂直于基底方向正对的第一存储块和第二存储块中的各第二电极和第四电极可以通过一个连接线与外界设备连接，与每一存储层均设置与第二电极连接的连接线相比，可以进一步减少三维铁电存储器中导电层的数量，进而减小三维铁电存储器的体积。
在一个实现方式中，第四连接层设置在基底和靠近基底的存储层之间，多个第四连接线中的每一第四连接线与靠近基底的存储层中一行第二存储块对应的第四电极连接。
同一行第一存储块的第二电极和对应行的第二存储块的第四电极，通过位于靠近基底的存储层朝向基底一侧的第四连接线引出，各存储层之间无需设置第四连接线，进一步减小三维铁电存储器的体积。
在一个实现方式中，第四连接层设置在远离基底的存储层背离基底的一侧，多个 第四连接线中的每一第四连接线与远离基底的存储层中一行第一存储块对应的第二电极连接。
同一行第一存储块的第二电极和对应行的第二存储块的第四电极，通过位于远离基底的存储层朝向基底一侧的第四连接线引出，各存储层之间无需设置第四连接线，进一步减小三维铁电存储器的体积。
在一个实现方式中，相邻存储层之间设置有绝缘介质层。
通过绝缘层可以实现相邻参考层之间的隔离。绝缘介质层可以将两个存储层分隔开，实现两个存储层之间的绝缘连接，以免两个存储层之间互相干扰。
在一个实现方式中，参考层、第一存储块以及第二存储块均包括阻变材料、相变材料、阻变结构。
在一个实现方式中，参考层、第一存储块以及第二存储块均包括铁电材料。
本申请实施例还公开了一种电子设备，包括电路板，以及与电路板连接的三维铁电存储器，三维铁电存储器为如上所述的三维铁电存储器。
本申请实施例提供的电子设备，三维铁电存储器中基底上层叠的设置有多个存储层，每个存储层包括参考层，在参考层背离基底的一侧设置有第一介质层，第一介质层包括多个间隔设置的第一存储块，在参考层朝向基底的一侧设置有第二介质层，第二介质层包括多个间隔设置的第二存储块，第一存储块和第二存储块均与参考层贴合，以使第一存储块与参考层组合形成第一存储单元，第二存储块与参考层组合形成第二存储单元，数据存储在各第一存储单元和第二存储单元内；第一介质层和第二介质层共用一个参考层，也就说参考层的数量是各介质层数量的一半，与一个参考层对应设置一个介质层相比，减少了参考层的数量，进而在垂直于基底的方向减小了三维铁电存储器的尺寸，进而减小了三维铁电存储器的体积，实现了三维铁电存储器的小型化。
附图说明
图1为本申请实施提供的三维铁电存储器的结构示意图一；
图2为图1中三维铁电存储器的立体结构图；
图3为本申请实施提供的三维铁电存储器的俯视图；
图4为本申请实施提供的三维铁电存储器的中第一极化方向与第二极化方向相反的示意图；
图5为本申请实施提供的三维铁电存储器的中第一极化方向与第二极化方向相同的示意图；
图6为本申请实施提供的三维铁电存储器的结构示意图二；
图7为本申请实施提供的三维铁电存储器的结构示意图三；
图8为图7中三维铁电存储器的立体结构图；
图9为本申请实施提供的三维铁电存储器的结构示意图四；
图10为本申请实施提供的三维铁电存储器的结构示意图五；
图11为图10中三维铁电存储器的立体结构图。
附图标记说明：
1：基底；
2：存储层；
3：第一导电线；
4：第二导电线；
5：绝缘介质层；
20：参考层；
30：第一存储块；
40：第二存储块；
50：第一连接线；
60：第二连接线；
70：第三连接线；
80：第四连接线；
201：导电块；
301：第一电极；
302：第二电极；
401：第三电极；
402：第四电极；
L：预定距离。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请，下面将结合附图对本申请实施例的实施方式进行详细描述。
随着存储设备技术的逐渐发展，三维铁电存储器以其具有较高的存储能力以及较快的读写速度成为研究的热点。其中，通过铁电材料的铁电极化特性，实现数据读写的铁电存储器已经得到广泛的应用。
相关技术中，三维铁电存储器包括基底以及层叠的设置在基底上的多个存储层，每一存储层包括参考层，以及设置在参考层背离基底一侧的介质层，介质层包括在参考层上阵列设置的多个存储块，存储块和参考层均由铁电材料构成，存储块和参考层构成存储单元；每一存储块对应连接有一条位线和一条字线，字线和位线垂直设置，通过字线和位线可以实现对存储单元数据的读取或者写入。
然而，相关技术中，每一介质层对应设置一个参考层，使得沿垂直于基底方向上三维铁电存储器的尺寸较大，使得三维铁电存储器的体积较大，难以实现三维铁电存储器的小型化。
本申请实施例提供一种三维铁电存储器，通过使相邻的两个介质层共用一个参考层，减少了三维铁电存储器中参考层的数量，进而减小了三维铁电存储器沿垂直于基底方向的尺寸，实现了三维铁电存储器的小型化。
图1为本申请实施提供的三维铁电存储器的结构示意图一，图2为图1中三维铁电存储器的立体结构图，如图1和图2所示。本申请实施例提供的三维存储，包括基底1以及层叠的设置在基底1上的多个存储层2，其中基底1用于承载各存储层2，基 底1的材质可以为单晶硅、硅锗或锗中的一种或者多种。
数据存储在各存储层2内，存储层2包括参考层20、设置在参考层20背离基底1一侧的第一介质层，以及设置在参考层20朝向基底1一侧的第二介质层，其中第一介质层包括间隔设置的多个第一存储块30，第二介质层包括间隔设置的多个第二存储块40，第一存储块30和第二存储块40均与参考层20贴合，使得第一存储块30和参考层20组合形成第一存储单元，第二存储块40和参考层20组合形成第二存储单元，可以在第一存储单元和第二存储单元上实现数据的读取和写入。
在上述实现方式中，多个第一存储块30在参考层20背离基底1的一侧可以阵列的设置，相同的，多个第二存储块40在参考层20朝向基底1的一侧也可以阵列的设置，使得各第一存储块30和第二存储块40的排列较为规则。进一步地，第一存储块30和第二存储块40的数量可以相同，并且第一存储块30和第二存储块40在垂直于参考层20的方向一一对应，也就是说第一存储块30在参考层20上的投影与第二存储块40在参考层20上的投影重合。
本实施例中，第一存储块30和参考层20组合形成第一存储单元，第二存储块40和参考层20组合形成第二存储单元，示例性的，图4为本申请实施提供的三维铁电存储器的中第一极化方向与第二极化方向相反的示意图，图5为本申请实施提供的三维铁电存储器的中第一极化方向与第二极化方向相同的示意图，继续参照图4和图5；第一存储块30与参考层20之间可以形成畴壁通道，参考层20具有第一极化方向，第一存储块30具有第二极化方向；在数据读取的过程中，当第一极化方向与第二极化方向相同时，第一存储块30与参考层20之间未形成畴壁通道，第一存储块30处于高阻状态，此时，在第一储存单元上读取的数据可以为“0”，相反，当第一极化方向与第二极化方向的方向相反时，第一存储块30与参考层20之间形成畴壁通道，第一存储块30处于低阻状态，此时在第一存储单元上的读取的数据可以为“1”；当然本实施例中，当第一极化方向与第二极化方向相同时，第一存储块30与参考层20之间未形成畴壁通道，第一存储块30处于高阻状态，此时，在第一储存单元上读取的数据可以为“1”，相反，当第一极化方向与第二极化方向的方向相反时，第一存储块30与参考层20之间形成畴壁通道，第一存储块30处于低阻状态，此时在第一存储单元上的读取的数据可以为“0”。本实施例中，第二存储块40与参考层20之间组成第二存储单元，第二存储单元的数据读取原理可以与第一存储单元相同，在此不再赘述。
在数据写入时，在第一存储块30上施加预设电压，当电压达到预设电压时，第一存储块30的第二极化方向发生反转，由于第二极化方向的反转，使得第一存储块30由高阻状态变为低阻状态，将数据“1”写入到第一存储单元，相反，当第一存储块30由低阻状态变为的高阻状态时，将数据“0”写入到第一存储单元。或者，当电压达到预设电压时，第一存储块30的第二极化方向发生反转，由于第二极化方向的反转，使得第一存储块30由高阻状态变为低阻状态，将数据“0”写入到第一存储单元，相反，当第一存储块30由低阻状态变为的高阻状态时，将数据“1”写入到第一存储单元。第二存储单元的数据写入与第一存储单元的数据写入过程大体相同，在此不在赘述。
值得说明的是，本实施例对预设电压不作限制，只要在第一存储块30上的电压升 高至预设电压时，第一存储块30的第二极化方向发生反转即可。
本实施例对第一存储块30、第二存储块40以及参考层20的材质不作限制，只要能够保证第一存储块30和第二存储块40与参考层20之间均可以形成畴壁通道、或者第一存储块30和第二存储块40与参考层20之间均可以形成类似的阻变特性即可。示例性的，参考层20、第一存储块30以及第二存储块40可以均包括阻变材料、相变材料、阻变结构；其中，阻变材料可以为氧化镍(NiO)、氧化钛(TiOx)、氧化铪(HfOx)等，相变材料可以为mGeTe·nSb2Te3(GST)、二氧化钒(VO 2)等，阻变结构可以为PN结、磁性隧道结、铁电隧道结等。进一步地，本实施例中参考层20、第一存储块30以及第二存储块40均由铁电材料构成。
在上述实现方式中，为了获取第一存储单元和第二存储单元内的数据，或者向第一存储单元和第二存储单元内写入数据；在参考层20的外部还设置有与第一存储块30和第二存储块40连接的连接线。在数据读取时，通过连接线可以获得流经第一存储块30和第二存储块40的电流，以判断第一存储块30和第二存储块40的电阻状态，进而实现第一存储单元和第二存储单元内数据的读取；在数据写入时，可以通过连接线向第一存储单元和第二存储单元施加电压，在电压达到预设电压时，使第一存储块30和第二存储块40的极化方向改变，以实现数据的写入。
本实施提供的三维铁电存储器，基底1上层叠的设置有多个存储层2，存储层2包括参考层20，在参考层20背离基底1的一侧设置有第一介质层，第一介质层包括多个间隔设置的第一存储块30，在参考层20朝向基底1的一侧设置有第二介质层，第二介质层包括多个间隔设置的第二存储块40，第一存储块30和第二存储块40均与参考层20贴合，以使第一存储块30与参考层20组合形成第一存储单元，第二存储块40与参考层20组合形成第二存储单元，数据存储在各第一存储单元和第二存储单元内；第一介质层和第二介质层共用一个参考层20，也就说参考层20的数量是各介质层数量的一半，与一个参考层20对应设置一个介质层相比，减少了参考层20的数量，进而在垂直于基底1的方向减小了三维铁电存储器的尺寸，进而减小了三维铁电存储器的体积，实现了三维铁电存储器的小型化。
继续参照图1和图2，本实施例中，为了便于与第一存储块30连接，第一介质层还包括设置在第一存储块30一侧的第一电极301以及设置在第一存储块30另一侧的第二电极302，第一电极301和第二电极302均与第一存储块30接合，进而通过第一电极301和第二电极302可以读取第一存储单元内的数据，当然，也可以通过第一电极301和第二电极302向第一存储单元内写入数据。相同的，第二介质层还包括设置在第二存储块40一侧的第三电极401以及设置在第二存储块40另一侧的第四电极402，第三电极401和第四电极402均与第二存储块40接合，进而通过第三电极401和第四电极402可以读取第二存储单元内的数据，当然，也可以通过第三电极401和第四电极402向第二存储单元内写入数据。
示例性的，第一电极301、第二电极302可以均由铜、银等金属材质构成块，当然第一电极301和第二电极302还可以由其他的非金属导电材质构成。相同的，第三电极401和第四电极402可以均由铜、银等金属材质构成，当然第三电极401和第四电极402还可以由其他的非金属导电材质构成。
本实施例中的三维铁电存储器可以为双极性存储器，即三维铁电存储器的读出方向不依赖于参考层20的极化方向，也就是说参考层20的极化方向与流经第一存储块30的电流方向相同和相反时，均可以进行数据的读取，相同的，参考层20的极化方向与流经第二存储块40的电流方向相同和相反时，均可以进行数据的读取；相应的，在第一电极301的电压高于第二电极302的电压、以及第一电极301的电压低于第二电极302的电压时，第一存储块30对应的第一存储单元均可以进行数据的读取，相同的，在第三电极401的电压高于第四电极402的电压、以及在第三电极401的电压低于第四电极402的电压时，第二存储块40对应的第二存储单元均可以进行数据的读取。
当然，本实施例中的三维铁电存储器还可以为单极性存储器，即三维铁电存储器的读出方向依赖于参考层20的极化方向，也就是说，参考层20的极化方向与流经第一存储块30的电流方向相反时，才可以进行数据的读取，相同的，参考层20的极化方向与流经第二存储块40的电流方向相反时，才可以进行数据的读取；相应的，参考层20极化方向为第一电极301指向第二电极302，仅当第一电极301的电压低于第二电极302的电压时，第一存储块30对应的第一存储单元才能进行数据的读取；参考层极化方向为第二电极302指向第一电极301时，仅当第一电极301的电压高于第二电极302的电压时，第一存储块30对应的第一存储单元才能进行数据的读取；相同的，参考层20极化方向为第三电极401指向第四电极402，仅当第三电极401的电压低于第四电极402的电压时，第一存储块40对应的第一存储单元才能进行数据的读取；参考层20极化方向为第四电极402指向第三电极401，仅当第三电极401的电压高于第四电极402的电压时，第一存储块30对应的第一存储单元才能进行数据的读取。如此设置，三维铁电存储器适应的范围更广泛。
在多个第一存储块30和多个第二存储块40均阵列设置，且同一存储层2内第一存储块30和第二存储块40一一对应的实现方式中，相对的第一存储块30和第二存储块40中，第一电极301可以与第三电极401正对，相应的第二电极302与第四电极402正对设置。
继续参照图1和图2，本实施例中，相邻的存储层2之间设置绝缘介质层5，绝缘介质层5可以将两个存储层2分隔开，实现两个存储层2之间的绝缘连接，以免两个存储层2之间互相干扰。
图3为本申请实施提供的三维铁电存储器的俯视图，继续参照图1-图3。在一些实施例中，三维铁电存储器包括设置在第一存储块30背离基底1一侧的第一连接层和设置在第二存储块40朝向基底1第一侧的第二连接层，第一连接层包括平行且间隔设置多个第一连接线50，多个第一连接线50中每一第一连接线50与一列第一存储块30对应的第一电极301连接，第二连接层包括平行且间隔设置的多个第二连接线60，多个第二连接线60中每一第二连接线60与一列第二存储块40的第三电极401电连接。如此设置，可以通过第一连接线50向对应的第一电极301供电，通过第二连接线60向对应的第三电极401供电，以便于第一存储单元和第二存储单元内数据的读取、或者向第一存储单元和第二存储单元内写入数据。
进一步地，三维铁电存储器还还包括设置在第一存储块30背离基底1一侧的第三连接层以及设置在第二存储块40朝向基底1一侧的第四连接层，第三连接层包括平行 且间隔设置的多个第三连接线70，多个第三连接线70中的每一第三连接线70与一行第一存储块30对应的第二电极302连接，第四连接层包括平行且间隔设置的多个的第四连接线80，多个第四连接线80中的每一第四连接线80与一行第二存储块40对应的第四电极402连接。
如此设置，可以通过第一连接线50和第三连接线70实现对应第一存储单元的数据读取或者写入，相同的，可以通过第二连接线60和第四连接线80实现对应的第二存储单元的数据读取或者写入。
在上述实现方式中，第一连接线50、第二连接线60、第三连接线70以及第四连接线80均可以为主要由铜、银等金属材质构成的金属线，当然第一连接线50、第二连接线60、第三连接线70以及第四连接线80也可以主要由其他的非金属导电材质构成。
第一连接线50和第二连接线60的延伸方向可以与第一存储块30和第二存储块40的列方向平行，第三连接线70和第四连接可以与第一存储块30和第二存储块40的行方向平行。其中，第一连接线50和第二连接线60可以为字线，相应的，第三连接线70和第四连接线80为位线；当然，第一连接线50和第二连接线60可以为位线，相应的，第三连接线70和第四连接线80为字线。通过一个第一连接线50和一个第三连接线70可以在阵列设置的多个第一存储块30中唯一选中一个第一存储块30；也就是说，任意选取一个第一连接线50和一个第三连接线70，该第一连接线50和第三连接线70交叉的位置即为选中的第一存储块30，选中的第一存储块30的第一电极301连接在该第一连接线50上，选中的第一存储块30的第二电极302连接在该第三连接线70上，通过该第一连接线50和第三连接线70可以实现选中的第一存储块30对应的第一存储单元数据的读取和写入。相同的，通过一个第二连接线60和一个第四连接线80可以在阵列设置的多个第二存储块40中唯一选中一个第二存储块40，通过该第二连接线60和第四连接线80可以实现选中的第二存储块40对应的第二存储单元的数据读取和写入。
继续参照图1和图2，进一步地，第一连接线50可以设置在对应的一列第一存储块30背离基底1的一侧，并且第一连接线50与对应的一列第一存储块30的各第一电极301背离基底1的一侧贴合，以使第一连接线50可以与对应的一列第一存储块30的各第一电极301接触良好。相同的，第二连接线60可以设置在对应的一列第二存储块40朝向基底1的一侧，并且第二连接线60与对应的一列第二存储块40的各第三电极401朝向基底1的一侧贴合，以使第二连接线60可以与对应的一列第二存储块40的各第三电极401接触良好。第三连接线70可以设置在各对应的第一存储块30背离基底1的一侧，并且第三连接线70与对应的一行第一存储块30的各第二电极302背离基底的一侧贴合。第四连接线80可以设置在对应的一行第二存储块40朝向基底1的一侧，并且第四连接线80与对应的一行第二存储块40的第四电极402朝向基底1的一侧贴合，以使第四连接线80与对应的一行第二存储块40的第四电极402接触良好。
进一步地，第一连接层可以位于第一存储块30和第三连接层之间，第二连接层位于第二存储块40和第四连接层之间。如此设置，各第一连接线50所处的平面和各第 三连接线70所处的平面平行且间隔的设置，各第二连接线60所处的平面和各第四连接线80所处的平面平行且间隔的设置；布线较为合理，避免了第一连接线50和第三连接线70互相干扰，同时也避免了第二连接线60和第四连接线80互相干扰。值得说明的是，由于第三连接层与第一存储块30之间的距离较大，此时可以在各第三连接线70上设置向对应的第一存储块30延伸的第一接触块，第三连接线70通过第一接触块与各第三电极401连接；相同的，第四连接层与第二存储块40之间的距离较大，此时可以在第四连接线80上设置向第二存储块40延伸的第二接触块，通过第二接触块实现第四连接线80与第四电极402之间的连接；其中第一接触块与第三连接线70为通过一次加工形成的一体结构，第四连接线80和第二接触块也可以为通过一次加工形成的一体结构。
上述实现方式中，三维铁电存储器包括多个层叠设置的多个存储层2，每一存储层2的结构可以与上述实现方式中的存储层2结构相同；或者本实施例的三维铁电存储器中的部分存储层2与上述实现方式中的存储层2结构相同。
在一些实施例中，第一连接线50和第二连接线60可以为字线，相应的第三连接线70和第四连接线80为位线；或者第一连接线50和第二连接线60可以为位线，相应的第三连接线70和第四连接线80为字线。对应的电压配置可以为包括：悬空模式，接地模式，1/2偏置电压模式以及1/3偏置电压模式，其中悬空模式可以为非选中字线和位线不配置电压，选中字线配置一定的电压；接地模式可以为非选中字线和位线接地，选中字线配置一定的电压；1/2偏置电压模式可以为非选中字线和位线配置的电压为选中字线的1/2；1/3偏置电压模式可以为非选中字线配置的电压为选中字线的1/3，非选中位线配置的电压为选中字线的2/3。
图6为本申请实施提供的三维铁电存储器的结构示意图二，继续参照图6；由于参考层20两侧均设置有电极，为了避免参考层20一侧电极中的电流经参考层20到达参考层20另一侧的电极，即为了避免参考层20两侧的电极之间发生漏电，可以使相对的第一存储块30和第二存储块40沿平行于参考层20的方向具有预定距离L。合理的设置预定距离L可以减小参考层20两侧的电极之间发生的漏电，进而减小参考层20两侧的电极之间的漏电电流和串扰。
图7为本申请实施提供的三维铁电存储器的结构示意图三，图8为图7中三维铁电存储器的立体结构图，如图7和图8所示；在多个第一存储块30和多个第二存储块40均阵列设置的实现方式中，多个第一存储块30和多个第二存储块40一一对应，每一第一存储块30的一侧设置有第一电极301，每一第一存储块30的另一侧设置有第二电极302，相应的，每一第二存储块40的一侧设置有第三电极401，每一第二存储块40的另一侧设置有第四电极402。其中，相对的第一存储块30和第二存储块40中，与第一存储块30接合的第二电极302和与第二存储块40接合的第四电极402之间连接。
如此设置，相对的第一存储块30和第二存储块40中，通过与第二电极302和第四电极402连接的连接线、以及与第一电极301、第二电极302连接的连接线即可实现第一存储单元和第二存储单元的数据读取和写入；也就是说，第二电极302和第四电极402可以共用一个连接线，进而减少了三维铁电存储器中导电层的数目，以进一 步减小三维铁电存储器的体积。
进一步地，相对的第一存储块30和第二存储块40中，第一电极301可以正对第二电极302设置，相应的第三电极401正对第四电极402设置；此时可以在参考层20上设置贯通孔，相对设置的第一存储块30和第二存储块40中，与第一存储块30接合的第二电极302和与第二存储块40接合的第四电极402之间通过设置在贯通孔内的导电块201连接。如此设置，通过位于贯通孔内的导电块201实现与第一存储块30接合的第二电极302和与第二存储块40接合的第四电极402之间的连接，无需设置额外的线路，结构简单，且便于制作。
在上述实现方式中，导电块201、以及该导电块201对应的第二电极302和第四电极402可以为一体结构；如此设置可以通过一次加工形成导电块201、与该导电块201对应的第二电极302和第四电极402，简化了三维铁电存储器的制作难度；示例性的，可以通过蒸镀、沉积或者电镀等方式形成导电块201、以及该导电块201对应的第二电极302和第四电极402。当然，在其他的实现方式在中，导电块201、以及该导电块201对应的第二电极302和第四电极402也可以为分体式结构，此时需要使导电块201与对应的第二电极302和第四电极402接触。
本实施例中，三维铁电存储器包括设置在第一存储块30背离基底1一侧的第一连接层、以及设置在第二存储块40背离基底1一侧的第二连接层，第一连接层包括平行且间隔设置的多个第一连接线50，第一连接线50的延伸方向与阵列设置的第一存储块30的列方向平行，并且第一连接线50与一列第一存储块30对应的各第一电极301连接；第二连接层包括平行且间隔设置的多个第二连接线60，第二连接线60的延伸方向与阵列设置的第二存储块40的列方向平行，每一第二连接线60与一列第二存储块40的各第三电极401连接。
进一步地，三维铁电存储器还包括第三连接层，第三连接层包括平行且间隔设置的多个第三连接线70，多个第三连接线70中的每一第三连接线70与一行第一存储块30对应的第二电极302连接。如此设置，相对的第一存储块30和第二存储块40中，第二电极302和第四电极402可以通过与第一存储块30对应的第二电极302连接的第三连接线70与外界连接；此时，通过第一连接线50和第三连接线70可以唯一的选中一个第一存储块30，并通过该第一连接线50和第三连接线70可以对选中的第一存储块30对应的第一存储单元进行数据的读取或写入；相同的，通过第二连接线60和第三连接线70可以唯一的选中一个第二存储块40，并通过该第二连接线60和第三连接线70可以对选中的第二存储块40对应的第二存储单元进行数据的读取或写入。
其中，第三连接线70可设置在第一存储块30背离基底1的一侧，并且第一连接线50位于第一存储块30和第三连接线70之间。
当然，在其他的实现方式中，第三连接层还可以设置在第二存储块40朝向基底1的一侧，并且第二连接层位于第三连接层和第二存储块40之间；相应的，第三连接层可以包括多个平行且间隔设置的第三连接线70，第三连接线70的延伸方向可以与阵列设置的多个第二存储块40中行方向平行，并且每一第三连接线70与一行第二存储块40对应的第四电极402连接。
在上述实现方式中，三维铁电存储器包括多个层叠设置的存储层2，每一存储层2 的结构可以与上述实现方式中的存储层2结构相同；或者，部分存储层2与上述实现方式中的存储层2结构相同。
图9为本申请实施提供的三维铁电存储器的结构示意图四，继续参照图9。
在多个第一存储块30和多个第二存储块40均阵列设置的实现方式中，多个第一存储块30和多个第二存储块40一一对应，每一第一存储块30的一侧设置有第一电极301，每一第一存储块30的另一侧设置有第二电极302，相应的，每一第二存储块40的一侧设置有第三电极401，每一第二存储块40的另一侧设置有第四电极402。其中，相对第一存储块30和第二存储块40中，与第一存储块30接合的第二电极302和与第二存储块40接合的第四电极402之间连接。进一步地，相邻存储层2之间设置有多个第一导电线3，多个第一导电线3中的每一第一导电线3的一端与远离基底1的存储层2中的一个第三电极401连接，多个第一导电线3中的每一第一导电线3的另一端与靠近基底1的存储层2中的相应的第一电极301连接。
如此设置，相邻存储层2之间靠近基底1的存储层2中第一电极301与远离基底1的存储层2中第三电极401通过第一导电线3连接，使得相邻的存储层2中靠近基底1的存储层2中第一电极301与远离基底1的存储层2中第三电极401可以对应设置一个线路与外界设备连接，与相邻的存储层2中靠近基底1的存储层2中第一电极301与远离基底1的存储层2中第三电极401均单独设置导电层相比，可以减少三维铁电存储器中导电层的数量，进而减小三维铁电存储器的体积。
在上述实现方式中，相邻的两个存储层2之间的各第一导电线3阵列设置，相邻的两个存储层2之间可以设置中间导电层，中间导电层包括平行且间隔设置的多个中间连接线，每一中间连接线与一列第一导电线3连接。
进一步地，存储层2中设置有第一连接层和第二连接层，第一连接层设置在第一存储块30背离基底1的一侧，第一连接层包括平行且间隔设置的多个第一连接线50，第一连接线50的延伸方向与第一存储块30的列方向相同，第一连接线50与一列第一存储块30对应的第一电极301连接；第二连接层位于该存储层2中第二存储块40朝向基底1的一侧，第二连接层包括平行且间隔设置的多个第二连接线60，第二连接线60的延伸方向与对应的第二存储块40的列方向平行，每一第二连接线60与一列第二存储块40的第三电极401连接；在每一存储层2中还设置有第三连接层，每一第三连接层设置在所在的存储层2第一存储块30背离基底1的一侧，第三连接层包括平行且间隔设置的多个第三连接线70，第三连接线70的延伸方向与对应的第一存储块30的行方向平行，且每一第三连接线70与一行第一存储块30对应的第二电极302连接。
在使用时，相邻的两个存储层中，通过中间连接线以及该中间连接线连接的两个存储层2中的第三连接线70可以在这两个存储层2中选中靠近基底1的存储层2中的一个第一存储块30、以及远离基底1的存储层2中的一个第二存储块40，进而实现对应存储单元数据的读取或写入。在靠近基底1的存储层2中，可以通过该存储层2中的第三连接线70以及第二连接线60，唯一的选中该存储层2中的一个第二存储块40，进而实现该第二存储块40对应的第二存储单元数据的读取或写入。在远离基底1的存储层2中，可以通过第一连接线50和第三连接线70唯一的选中一个第一存储块30，进而实现该第一存储块30对应的第一存储单元数据的读取或写入。
当然，在上述实现方式中，每一存储层2中还可以不设置第三连接层，相应的在每一存储层2中第二存储块40朝向基底1的一侧设置第四连接层，第四连接层包括平行且间隔设置的多个第四连接线80，第四连接线80的延伸方向与第二存储块40的行方向平行，每一第四连接线80与一行第二存储块40对应的第四电极402连接；由于相对的第一存储块30和第二存储块40中，第二电极302和第四电极402之间连接，此时第四连接线80与第三连接线70的作用相同。
图10为本申请实施提供的三维铁电存储器的结构示意图五，图11为图10中三维铁电存储器的立体结构图，继续参照图10和图11。
在多个第一存储块30和多个第二存储块40均阵列设置的实现方式中，多个第一存储块30和多个第二存储块40一一对应，每一第一存储块30的一侧设置有第一电极301，每一第一存储块30的另一侧设置有第二电极302，相应的，每一第二存储块40的一侧设置有第三电极401，每一第二存储块40的另一侧设置有第四电极402；其中，相对第一存储块30和第二存储块40中，与第一存储块30接合的第二电极302和与第二存储块40接合的第四电极402之间连接。进一步地，相邻两个存储层2之间设置有多个第二导电线4，多个第二导电线4中的每一第二导电线4的一端与远离基底1的存储层2中的第四电极402连接，多个第二导电线4中的每一第二导电线4的另一端与靠近基底1的存储层2中相应的第二电极302连接；三维铁电存储器包括第四连接层，第四连接层包括平行且间隔设置的多个第四连接线80，多个第四连接线80中的每一第四连接线80与一行第二导电线4连接。
如此设置，通过第二导电线4可以实现相邻两个存储层2中远离基底1的存储层2中的第四电极402和靠近基底1的存储层2中的第二电极302之间的连接，由于每一存储层2中相对的第一存储块30和第二存储块40中，第二电极302和第四电极402连接，此时各第二导电线4还实现了整个三维铁电存储器中沿垂直于基底1方向正对的第一存储块30和第二存储块40中，各第二电极302和第四电极402之间的连接；整个三维铁电存储器中，沿垂直于基底1方向正对的第一存储块30和第二存储块40中的各第二电极302和第四电极402可以通过一个连接线与外界设备连接，与每一存储层2均设置与第二电极302连接的连接线相比，可以进一步减少三维铁电存储器中导电层的数量，进而减小三维铁电存储器的体积。
在上实现方式中，每个存储层2中还可以具有第一连接层和第二连接层，第一连接层可以设置在该存储层2中第一存储块30背离基底1的一侧，第一连接层包括平行且间隔设置的多个第一连接线50，第一连接线50的延伸方向与第一存储块30的列方向平行，每一第一连接线50与一列第一存储块30对应的第一电极301连接；第二连接层可以设置在该存储层2中第二存储块40朝向基底1的一侧，第二连接层包括平行且间隔设置的多个第二连接线60，第二连接线60的延伸方向与第二存储块40的列方向平行，每一第二连接线60与一列第二存储块40对应的第三电极401连接。
三维铁电存储器包括第四连接层，第四连接层包括平行且间隔设置的多个第四连接线80，多个第四连接线80中的每一第四连接线80与一行第二导电线4连接。如此设置，根据第四连接线80以及第一连接线50可以唯一的选中一个第一存储块30，以实现该第一存储块30对应的第一存储单元中数据的读取和写入；根据第四连接线80 和第二连接线60可以唯一的选中一个第二存储块40，以实现该第二存储块40对应的第二存储单元中数据的读取和写入。
示例性的，第四连接层可以设置在基底1和靠近基底1的存储层2之间，多个第四连接线80中的每一第四连接线80与靠近基底1的存储层2中一行第二存储块40对应的第四电极402连接。如此设置，同一行第一存储块30的第二电极302和对应行的第二存储块40的第四电极402，通过位于靠近基底1的存储层2朝向基底1一侧的第四连接线80引出，各存储层2之间无需设置第四连接线80，进一步减小三维铁电存储器的体积。
在一些实施例中，第四连接层还可以设置在远离基底1的存储层2背离基底1的一侧，多个第四连接线80中的每一第四连接线80与远离基底1的存储层2中一行第一存储块30对应的第二电极302连接。如此设置，同一行第一存储块30的第二电极302和对应行的第二存储块40的第四电极402，通过位于远离基底1的存储层2朝向基底1一侧的第四连接线80引出，各存储层2之间无需设置第四连接线80，进一步减小三维铁电存储器的体积。
继续参照图1-图11，本申请实施例还提供一种电子设备，包括电路板以及与电路板连接的三维铁电存储器，三维铁电存储器可以为如上实施例所述的三维铁电存储器。其中，电路板可以为印制电路板(PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。
本申请实施例提供的电子设备，其中三维铁电存储器的基底1上层叠的设置有多个存储层2，存储层2包括参考层20，在参考层20背离基底1的一侧设置有第一介质层，第一介质层包括多个间隔设置的第一存储块30，在参考层20朝向基底1的一侧设置有第二介质层，第二介质层包括多个间隔设置的第二存储块40，第一存储块30和第二存储块40均与参考层20贴合，以使第一存储块30与参考层20组合形成第一存储单元，第二存储块40与参考层20组合形成第二存储单元，数据存储在各第一存储单元和第二存储单元内；第一介质层和第二介质层共用一个参考层20，也就说参考层20的数量是各介质层数量的一半，与一个参考层20对应设置一个介质层相比，减少了参考层20的数量，进而在垂直于基底1的方向减小了三维铁电存储器的尺寸，进而减小了三维铁电存储器的体积，实现了三维铁电存储器的小型化。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种三维铁电存储器，其特征在于，包括：
    基底和在所述基底上层叠设置的多个存储层；
    所述多个存储层中的每个存储层包括参考层、设置在所述参考层背离所述基底一侧的第一介质层、设置在所述参考层朝向所述基底一侧的第二介质层，所述第一介质层包括间隔设置的多个第一存储块，所述第二介质层包括间隔设置的多个第二存储块，所述多个第一存储块中每一第一存储块和所述多个第二存储块中每一第二存储块均与所述参考层贴合，每一所述第一存储块与所述参考层组合形成一个第一存储单元，每一所述第二存储块与所述参考层组合形成一个第二存储单元。
  2. 根据权利要求1所述的三维铁电存储器，其特征在于，
    所述多个第一存储块以及所述多个第二存储块均阵列设置，且所述多个第一存储块和所述多个第二存储块在垂直于所述参考层的方向一一对应；
    所述第一介质层还包括与所述第一存储块一侧接合的第一电极以及与所述第一存储块另一侧接合的第二电极；
    所述第二介质层还包括与所述第二存储块一侧接合的第三电极以及与所述第二存储块另一侧接合的第四电极。
  3. 根据权利要求2所述的三维铁电存储器，其特征在于，
    所述三维铁电存储器还包括位于所述第一存储块背离所述基底一侧的第一连接层和位于所述第二存储块朝向所述基底一侧的第二连接层，所述第一连接层包括平行且间隔设置的多个第一连接线，所述多个第一连接线中的每一所述第一连接线与一列所述第一存储块对应的所述第一电极连接；所述第二连接层包括平行且间隔设置的多个第二连接线，所述多个第二连接线中的每一所述第二连接线与一列所述第二存储块对应的所述第三电极连接。
  4. 根据权利要求3所述的三维铁电存储器，其特征在于，
    所述三维铁电存储器还包括位于所述第一存储块背离所述基底一侧的第三连接层以及位于所述第二存储块朝向所述基底一侧的第四连接层，所述第三连接层包括平行且间隔设置的多个第三连接线，所述多个第三连接线中的每一所述第三连接线与一行所述第一存储块对应的所述第二电极连接，所述第四连接层包括平行且间隔设置的多个第四连接线，所述多个第四连接线中的每一所述第四连接线与一行所述第二存储块对应的所述第四电极连接。
  5. 根据权利要求4所述的三维铁电存储器，其特征在于，
    所述第一连接层位于所述第一存储块和所述第三连接层之间，所述第二连接层位于所述第二存储块和所述第四连接层之间。
  6. 根据权利要求2所述的三维铁电存储器，其特征在于，
    相对的所述第一存储块和所述第二存储块中，与所述第一存储块接合的所述第二电极和与所述第二存储块接合的所述第四电极之间连接。
  7. 根据权利要求6所述的三维铁电存储器，其特征在于，所述参考层上设置贯通孔，相对设置的所述第一存储块和所述第二存储块中，与所述第一存储块接合的所述 第二电极和与所述第二存储块接合的所述第四电极之间通过设置在所述贯通孔内的导电块连接。
  8. 根据权利要求7所述的三维铁电存储器，其特征在于，所述导电块、与该导电块对应的所述第二电极和所述第四电极为一体结构。
  9. 根据权利要求6-8任一项所述的三维铁电存储器，其特征在于，
    所述三维铁电存储器包括第三连接层，所述第三连接层包括平行且间隔设置的多个第三连接线，所述多个第三连接线中的每一所述第三连接线与一行所述第一存储块对应的第二电极连接。
  10. 根据权利要求6-8任一项所述的三维铁电存储器，其特征在于，
    所述三维铁电存储器包括第三连接层，所述第三连接层包括平行且间隔设置的多个第三连接线，所述多个第三连接线中的每一所述第三连接线与一行所述第二存储块对应的第四电极连接。
  11. 根据权利要求9或10所述的三维铁电存储器，其特征在于，
    相邻所述存储层之间设置有多个第一导电线，所述多个第一导电线中的每一所述第一导电线的一端与远离所述基底的所述存储层中的一个所述第三电极连接，所述多个第一导电线中的每一所述第一导电线的另一端与靠近所述基底的所述存储层中的相应的所述第一电极连接。
  12. 根据权利要求6-8任一项所述的三维铁电存储器，其特征在于，
    相邻两个所述存储层之间设置有多个第二导电线，所述多个第二导电线中的每一所述第二导电线的一端与远离所述基底的所述存储层中的所述第四电极连接，所述多个第二导电线中的每一所述第二导电线的另一端与靠近所述基底的所述存储层中的相应的所述第二电极连接；
    所述三维铁电存储器还包括第四连接层，所述第四连接层包括平行且间隔设置的多个第四连接线，所述多个第四连接线中的每一所述第四连接线与一行所述第二导电线连接。
  13. 根据权利要求12所述的三维铁电存储器，其特征在于，
    所述第四连接层设置在所述基底和靠近所述基底的所述存储层之间，所述多个第四连接线中的每一所述第四连接线与靠近所述基底的所述存储层中一行所述第二存储块对应的所述第四电极连接。
  14. 根据权利要求12所述的三维铁电存储器，其特征在于，
    所述第四连接层设置在远离所述基底的所述存储层背离所述基底的一侧，所述多个第四连接线中的每一所述第四连接线与远离所述基底的所述存储层中一行所述第一存储块对应的所述第二电极连接。
  15. 根据权利要求1-14任一项所述的三维铁电存储器，其特征在于，相邻所述存储层之间设置有绝缘介质层。
  16. 根据权利要求1-15任一项所述的三维铁电存储器，其特征在于，所述参考层、所述第一存储块以及所述第二存储块均包括阻变材料、相变材料、或者阻变结构。
  17. 根据权利要求16所述的三维铁电存储器，其特征在于，所述参考层、所述第一存储块以及所述第二存储块均包括铁电材料。
  18. 一种电子设备，包括电路板，以及与所述电路板连接的三维铁电存储器，所述三维铁电存储器为如权利要求1-17任一项所述的三维铁电存储器。
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CN101350360A (zh) * 2008-08-29 2009-01-21 中国科学院上海微系统与信息技术研究所 一种三维堆叠非相变所致电阻转换存储装置及其制造方法
CN101878529A (zh) * 2007-11-29 2010-11-03 松下电器产业株式会社 非易失性存储装置及其制造方法
US20110018043A1 (en) * 2009-07-22 2011-01-27 Kabushiki Kaisha Toshiba Semiconductor memory device
CN109378313A (zh) * 2018-09-23 2019-02-22 复旦大学 一种低功耗三维非易失性存储器及其制备方法

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CN101878529A (zh) * 2007-11-29 2010-11-03 松下电器产业株式会社 非易失性存储装置及其制造方法
CN101350360A (zh) * 2008-08-29 2009-01-21 中国科学院上海微系统与信息技术研究所 一种三维堆叠非相变所致电阻转换存储装置及其制造方法
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CN109378313A (zh) * 2018-09-23 2019-02-22 复旦大学 一种低功耗三维非易失性存储器及其制备方法

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