WO2021104411A1 - 一种集成电路和电子设备 - Google Patents

一种集成电路和电子设备 Download PDF

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WO2021104411A1
WO2021104411A1 PCT/CN2020/132019 CN2020132019W WO2021104411A1 WO 2021104411 A1 WO2021104411 A1 WO 2021104411A1 CN 2020132019 W CN2020132019 W CN 2020132019W WO 2021104411 A1 WO2021104411 A1 WO 2021104411A1
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source line
integrated circuit
source
line
lines
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PCT/CN2020/132019
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English (en)
French (fr)
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沈鼎瀛
相奇
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厦门半导体工业技术研发有限公司
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Priority to US17/796,166 priority Critical patent/US20230110795A1/en
Publication of WO2021104411A1 publication Critical patent/WO2021104411A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Definitions

  • the present invention relates to integrated circuits, in particular to an integrated circuit and electronic equipment.
  • Resistive Random Access Memory is a new type of technology.
  • RRAM combines the advantages of static random access memory (SRAM, Static Random-Access Memory), dynamic random access memory (DRAM, Dynamic Random Access Memory), and FLASH, which can achieve non-volatile and ultra-high density.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • FLASH FLASH
  • NVM Non-Volatile Memory
  • Low power consumption, low cost and high scale reduction characteristics is considered by the industry to be a promising candidate for the next generation of non-volatile memory (NVM, Non-Volatile Memory).
  • NVM Non-Volatile Memory
  • the emerging NVM due to its relatively large bandwidth and rapidly growing capacity, can play a vital role in the integrated storage and computing technology of (AI, Artificial Intelligence) chips.
  • the basic structure of a typical RRAM is composed of a bottom electrode, a resistance transition layer and a top electrode, forming a metal-insulator-metal (MIM, Metal-Insulator-Metal) laminated structure, and the resistance transition layer serves as a medium for ion transmission and storage.
  • MIM Metal-insulator-metal
  • the conductive filament model that is, dendritic conductive filaments are formed in the insulating dielectric film.
  • the memory setting (SET, writing 1 is the transition process from high resistance to low resistance) and reset (RESET, writing 0 is the transition process from low resistance to high resistance) cause the connection and breakage of the conductive filaments, causing the resistance of the film to occur
  • the conversion between low resistance and high resistance forms a data storage with a logic "0" data bit or a logic "1" data bit.
  • FIG. 1 it is a plan view of a partial structure of an existing resistive random access memory.
  • the variable impedance cells of the same column corresponding to the bit line share the corresponding source line, and the bit line and the source line have symmetry that can be replaced with each other.
  • the purpose of the present invention is to provide an integrated circuit with better area efficiency.
  • the present invention also provides a resistive random access memory.
  • the resistive random access memory includes a plurality of resistive memory cells arranged in a row and column direction, and each of the resistive memory cells includes a variable impedance.
  • the first source line is located on the first wiring layer, and the second source line is located on the second wiring layer above the first wiring layer;
  • the first source line and the second source line are respectively coupled to variable impedance units on different sides;
  • the first source line and the second source line are located between two adjacent rows of variable impedance units, and the projections of at least one first source line and the corresponding second source line in the vertical direction overlap at least partly
  • Each of the source lines is perpendicular to the direction of the word line space, and each of the source lines is parallel to the direction of the bit line space; the bit lines are located in the third wiring layer above the second wiring layer;
  • the first source line is electrically connected to the substrate through the N groups of contact plugs and the bottom connection platform of the N-1 group
  • the second source line is electrically connected to the substrate through the M group of contact plugs and the bottom connection platform of the M-1 group, where M is greater than N.
  • the variable impedance unit may be one or more of RRAM, MRAM, FRAM or PRAM.
  • the resistive random access memory can achieve the following effects: because the source line includes the first source line and the second source line, and the second source line is located above the vertical space of the first source line Therefore, the spacing between the variable impedance units can be reduced, which can improve the area efficiency of the memory array compared with the case where the source lines are located on the same side of the variable impedance unit in the prior art.
  • FIG. 1 is a plan view of a partial structure of a conventional resistive random access memory.
  • FIG. 2 is a plan view of a partial structure of a resistive random access memory according to an embodiment of the invention.
  • 3A is a cross-sectional view of a resistive random access memory in the direction of A-A' according to an embodiment of the present invention.
  • 3B is a cross-sectional view of a resistive random access memory in the direction of B-B' according to an embodiment of the present invention.
  • 3C is a cross-sectional view of a resistive random access memory in the direction of C-C' according to an embodiment of the present invention.
  • Fig. 3D is a cross-sectional view in the direction D-D' of a resistive random access memory according to an embodiment of the present invention.
  • variable impedance unit 106, 107, 206, 207 ⁇ variable impedance unit
  • An embodiment of the present invention provides an integrated circuit, including: a plurality of integrated circuit units and a plurality of source lines, wherein the plurality of source lines include a first source line and a second source line located in different layers, The first source line and the second source line are located in different wiring layers, and the integrated circuit unit is coupled to the first source line or the second source line.
  • the first source line is located on the first wiring layer, and the second source line is located on the second wiring layer above the first wiring layer.
  • Another embodiment of the present invention further provides a memory including: a plurality of memory cells and a plurality of source lines, wherein the plurality of source lines include first source lines and second source lines located in different layers, The first source line and the second source line are located in different wiring layers, and the memory cell is coupled to the first source line or the second source line.
  • the first source line is located in the first wiring layer
  • the second source line is located in the second wiring layer above the first wiring layer
  • the first source line and the second source line The projections in the vertical direction overlap at least partly, and they are respectively coupled to the memory cells located on different sides of the first source line and the second source line.
  • FIG. 2 is a plan view of a partial structure of a resistive random access memory according to an embodiment of the present invention.
  • FIG. 3A is a cut along the line A-A' in FIG. 2
  • Fig. 3B is a cross-sectional view taken along the line B-B' of Fig. 2
  • Fig. 3C is a cross-sectional view taken along the line C-C’ of Fig. 2
  • Fig. 3D is a cross section taken along the line D-D’ of Fig. 2 Figure.
  • the memory array has a multilayer wiring structure on a silicon substrate.
  • the substrate has a metal layer and a control gate.
  • the control gate electrode can be a high-k metal gate, a fin field effect transistor (FiNFET), or a conductive polysilicon layer.
  • a bit line BL is formed in a direction orthogonal to the word line WL.
  • the bit line BL is located on the third wiring layer above the second wiring layer.
  • the bit line BL is made of metal such as aluminum (Al) or copper (Cu).
  • the source lines SL1/SL2 are formed in a spatial direction parallel to the bit line BL, and the source lines SL1/SL2 are perpendicular to the word line WL in the spatial direction.
  • the source line SL1 is located in the first wiring layer, and the same metal layer 1 (M1) as the bottom bonding platform 112 is used for wiring.
  • the source line SL2 is located on the second wiring layer, and is wired using the same metal layer (M2) as the bottom bonding platform 113.
  • the variable impedance unit is located in the insulating layer between the second wiring layer and the third wiring layer.
  • variable impedance unit in this embodiment may be any one of resistive change memory (RRAM), magnetic memory (MRAM), ferroelectric memory (FRAM), or phase change memory (PRAM), or a combination of several.
  • RRAM resistive change memory
  • MRAM magnetic memory
  • FRAM ferroelectric memory
  • PRAM phase change memory
  • Figures 3A, 3B, 3C and 3D respectively show the A-A' line cross-sectional view, the B-B' line cross-sectional view, and the C-C' line cross-sectional view and the D-D' line of the area of the array shown in Figure 2 Sectional view.
  • an insulating layer 101 is formed on the surface of the substrate 100 to define the active area of the access transistor.
  • the material of the insulating layer 101 is silicon oxide film or the like.
  • the source line SL1 is located on the insulating layer 102, is wired by the metal layer 1 (M1 ), and is coupled to the column where the variable impedance unit 106 is located.
  • the metal layer 1 may be made of metal such as aluminum (Al) or copper (Cu).
  • the source line SL1 is perpendicular to the word line WL in the spatial direction and parallel to the bit line BL in the spatial direction. The figure shows the connection part between the source line SL1 and the contact plug, so this spatial relationship cannot be directly observed.
  • a contact hole is formed in the interlayer insulating layer 101, and a contact plug 120 is formed, and the source line SL1 is electrically connected to the surface of the substrate 100 through the contact plug 120.
  • the variable impedance unit 106 is formed on the insulating layer 104 and is electrically connected to the metal layer 2 through the contact plug 110 in the insulating layer 104.
  • the bit line BL is wired using the metal layer 3 (M3), and is electrically connected to the variable impedance unit 106 through the contact plug 111.
  • an insulating region 101 is formed on the surface of the substrate 100 to define the active region of the access transistor.
  • the source line SL2 is wired using the metal layer 2 (M2) located on the metal layer 1 (M1), and the source line SL2 is coupled to the column where the variable impedance unit 206 is located.
  • the metal layer 2 may be made of metal such as aluminum (Al) or copper (Cu).
  • the source line SL2 and the word line WL are perpendicular to the space direction and parallel to the bit line BL in the space direction.
  • Figure 3C shows a cross-sectional view in the CC' direction. It can be seen that the source line SL1 and the source line SL2 are in different metal layers, and the source line SL1 and the source line SL2 are different from the memory cell on the side. Are coupled and the projections in the vertical direction overlap.
  • the figure shows the connection part with the source line SL1 and the source line SL2 and the contact plug.
  • the source line SL1 and the source line SL2 themselves and the bit line BL are in Parallel in space.
  • the source line SL1 is electrically connected to the surface of the substrate 100 through the contact plug 120
  • the source line SL2 is electrically connected to the surface of the substrate 100 through the contact plug 220, the bottom connection platform 221, and the contact plug 222.

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Abstract

一种集成电路和电子设备，能够提供一种具有较佳面积效率的集成电路。此集成电路可以为电阻式随机存取存储器，其包括以行列方向排列的多个电阻式存储记忆胞，所述的电阻式存储记忆胞包括可变阻抗单元（106）和与上述可变阻抗单元（106）耦接的开关单元；每列方向的可变阻抗单元（106）分别与对应的源极线（SL1、SL2）耦接，所述源极线（SL1、SL2）包括第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层。

Description

一种集成电路和电子设备 技术领域
本发明涉及集成电路，尤其涉及一种集成电路和电子设备。
背景技术
在集成电路领域中，集成电路向着更小、更紧密且更拥挤的方向发展。给定面积里所能形成及安置的电子组件愈来愈多，以致装置有可能更小，即包括更小的存储单元、及用于操作该存储单元的互连件。然而，随着电子组件以更靠近的方式安置在一起，紧密靠近会导致不期望的效应。因此，希望提供一种使集成电路在可用空间的使用上更有效率的设计方案。
其中，电阻式随机存取存储器(RRAM，Resistive Random Access Memory)是一种新型技术。RRAM由于结合了静态随机存取存储器(SRAM，Static Random-Access Memory)，动态随机存取存储器(DRAM，Dynamic Random Access Memory)，和FLASH的优点于一身，可以实现非易失性、超高密度、低功耗、低成本和高比例缩小的特点，被产业界认为是下一代非易失性存储器(NVM，Non-Volatile Memory)有前景的候选。新兴的NVM由于具有相对较大的带宽和迅速增长的容量，可以在(AI，Artificial Intelligence)芯片的存算一体技术中发挥至关重要的作用。
典型的RRAM的基本结构由底电极、电阻转态层及顶电极构成，组成金属-绝缘体-金属(MIM，Metal-Insulator-Metal)叠层结构，电阻转态层作为离子传输和存储的介质。在RRAM多种阻变原理模型中，最为广泛接受的是导电细丝模型，即在绝缘介质膜中形成了树枝状的导电细丝。存储器的置位(SET，写l即高阻到低阻的转变过程)和复位(RESET，写0即低阻到高阻的转变过程)引起导电细丝的连接和断裂，使薄膜的电阻发生低 阻和高阻间的转化，形成逻辑“0”数据位或逻辑“1”数据位的数据存储。
如图1所示，其为现有的电阻式随机存取存储器部分结构的平面图。在此双极性类型中，对应位线的同一列可变阻抗单元共用相应源极线，并且位线和源极线之间具有可以相互置换的对称性。
然而在这种存储器阵列结构中，由于对于每个位线配置专用的源极线，所以在形成高积体密度存储器的情况下，源极线就成了存储器阵列在AA(active area or diffusion)宽度方向上尺寸微缩的障碍，因此将影响电阻式随机存取存储器积体密度(integration density)的提高。
本发明的目的，即在于提供一种具有较佳面积效率的集成电路。
发明内容
本发明提供一种集成电路，包括：多个集成电路单元和多条源极线，其中，所述多条源极线包括位于不同层的第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层，所述集成电路单元耦接至所述第一源极线或所述第二源极线。
本发明还提供一种存储器，所述的存储器包括：多个存储单元和多条源极线，其中，多条源极线包括位于不同层的第一源极线与第二源极线，第一源极线与第二源极线位于不同配线层，存储单元耦接至第一源极线或第二源极线；所述第一源极线与所述第二源极线在垂直方向上的投影至少有一部分相重叠，其分别耦接至位于所述第一源极线与所述第二源极线的不同侧的所述存储单元。
本发明还提供一种电阻式随机存取存储器，所述电阻式随机存取存储器包括：以行列方向排列的多个电阻式存储记忆胞，所述的每一电阻式存储记忆胞包括可变阻抗单元和与上述可变阻抗单元耦接的开关单元；所述源极线包括第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层；
所述的第一源极线位于第一配线层，所述的第二源极线位于上述第一配线层上层的第二配线层；
所述第一源极线及第二源极线分别与不同侧的可变阻抗单元耦接；
第一源极线与第二源极线位于相邻两列可变阻抗单元之间，且至少一条第一源极线与对应的第二源极线在垂直方向上的投影至少有一部分相重叠；每条所述源极线与字线空间方向上垂直，每条所述源极线与位线空间方向上平行；所述位线位于第二配线层上层的第三配线层；
第一源极线通过N组接触栓塞及N-1组底联结平台与基板电连接，第二源极线通过M组接触栓塞及M-1组底联结平台与基板电连接，其中，M大于N。
所述可变阻抗单元可为RRAM、MRAM、FRAM或PRAM中的一种或几种。
依据本发明，此电阻式随机存取存储器可以实现的效果有：由于源极线包含第一源极线与第二源极线，并且第二源极线位于第一源极线垂直空间的上方，便能够将可变阻抗单元间的间距缩小，相较于已知技术中源极线分别位于可变阻抗单元同侧的情况，可以改善存储器阵列的面积效率。
附图说明
图1为现有的电阻式随机存取存储器部分结构的平面图。
图2为本发明一实施例的电阻式随机存取存储器部分结构的平面图。
图3A为本发明一实施例的电阻式随机存取存储器A-A’方向的剖面图。
图3B为本发明一实施例的一电阻式随机存取存储器B-B’方向的剖面图。
图3C为本发明一实施例的一电阻式随机存取存储器C-C’方向的剖面图。
图3D为本发明一实施例的一电阻式随机存取存储器D-D’方向的剖面 图。
附图标号：
100～基板
101、102、103、104、105～绝缘层
108、109、110、111、120、208、209、210、211、220、222～接触栓塞112(M1)、113(M2)、212(M1)、213(M2)～底联结平台
106、107、206、207～可变阻抗单元
SL0、SL0’、SL1、SL2～源极线
WL0、WL0’、WL1、WL2～字线
BL0、BL0’、BL～位线
具体实施方式
为使本发明的目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而非全部实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的一个实施例提供一种集成电路，包括：多个集成电路单元和多条源极线，其中，多条源极线包括位于不同层的第一源极线与第二源极线，第一源极线与第二源极线位于不同配线层，集成电路单元耦接至第一源极线或所述第二源极线。
第一源极线位于第一配线层，所述的第二源极线位于上述第一配线层上层的第二配线层。
本发明的另一个实施例还提供一种存储器，包括：多个存储单元和多条源极线，其中，多条源极线包括位于不同层的第一源极线与第二源极线，第一源极线与第二源极线位于不同配线层，存储单元耦接至第一源极线或 第二源极线。
第一源极线位于第一配线层，所述的第二源极线位于上述第一配线层上层的第二配线层；所述第一源极线与所述第二源极线在垂直方向上的投影至少有一部分相重叠，其分别耦接至位于所述第一源极线与所述第二源极线的不同侧的所述存储单元。
本发明的另一个实施例提供一种电阻式随机存取存储器，图2为本发明一个实施例的一电阻式随机存取存储器部分结构的平面图，图3A为沿图2的A-A’切线的剖面图，图3B为沿图2的B-B’切线的剖面图,图3C为沿图2的C-C’切线的剖面图，图3D为沿图2的D-D’切线的剖面图。
图2为本发明本实施例的一电阻式随机存取存储器部分结构的概略平面图。存储器阵列在硅基板上具有多层配线结构，在此实施例中，基板上具有金属层以及控制栅电极(control gate)。控制栅电极可以为高介电常数金属栅极(high K metal gate)、鳍式场效电晶体(Fin Field Effect Transistor，FiNFET)或导电性多晶硅层的一种。在与字线WL正交的方向上，形成位线BL。为更清晰的表示源极线与可变阻抗单元的位置，图2中未示出位线BL。位线BL位于第二配线层上层的第三配线层。位线BL是由例如铝(Al)或铜(Cu)等金属所构成。
源极线SL1/SL2是以空间方向上平行于位线BL的方式所形成，源极线SL1/SL2与所述的字线WL空间方向上垂直。在本实施例中，源极线SL1位于第一配线层，利用与底联结平台112同样的金属层1(M1)进行配线。源极线SL2位于第二配线层，利用与底联结平台113同样的金属层(M2)进行配线。可变阻抗单元位于所述第二配线层与所述第三配线层之间的绝缘层。
本实施例中的可变阻抗单元可以为阻变存储器(RRAM)、磁存储器(MRAM)、铁电存储器(FRAM)或相变存储器(PRAM)中的任一一种，或者几种的组合。
图3A、图3B、图3C和图3D分别表示在图2所示阵列的区域的A-A’线剖面图、B-B’线剖面图C-C’线剖面图和D-D’线剖面图。
在图3A中，例如在基板100的表面上形成绝缘层101，用来界定存取晶体管的主动区，绝缘层101材料为氧化硅膜等。在基板100上，源极线SL1位于绝缘层102，是利用金属层1(M1)进行配线，与可变阻抗单元106所在的列耦接。金属层1可以由例如铝(Al)或铜(Cu)等金属所构成。源极线SL1与字线WL空间方向上垂直，与位线BL空间方向上平行。图中示出的为源极线SL1与接触栓塞的连接部分，因此无法直接观察到此空间关系。层间绝缘层101中形成接触孔，并形成接触栓塞120，源极线SL1通过在接触栓塞120电连接至基板100表面上。可变阻抗单元106形成在绝缘层104之上，通过绝缘层104中的接触栓塞110与金属层2导通。位线BL是利用金属层3(M3)进行配线，通过接触栓塞111与可变阻抗单元106导通。
如图3B所示，在基板100的表面上形成绝缘区101，用来界定存取晶体管的主动区。在基板100上，源极线SL2是利用位于金属层1(M1)之上的金属层2(M2)进行配线，源极线SL2与可变阻抗单元206所在的列耦接。金属层2可以由例如铝(Al)或铜(Cu)等金属所构成。源极线SL2与字线WL空间方向上垂直与位线BL空间方向上平行。同样的，源极线SL2通过在氧化硅膜等层间绝缘膜所形成的两个接触孔内的接触栓塞220、222及一个底联结平台221，分别电连接至基板100表面上。在源极线SL2之上，位线BL是利用金属层3(M3)进行配线。
如图3C示出了在C-C’方向上的剖面图，可以看到，源极线SL1与源极线SL2在不同金属层，源极线SL1与源极线SL2与不同侧的存储单元耦接，且在垂直方向上的投影重叠，图中示出的为与源极线SL1及源极线SL2与接触栓塞的连接部分，源极线SL1及源极线SL2本身与位线BL在空间 方向上平行。源极线SL1通过接触栓塞120电连接至基板100表面上，源极线SL2通过接触栓塞220、底联结平台221、接触栓塞222电连接至基板100表面上。
如图3D示出了在D-D’方向上的剖面图，源极线SL1位于第一配线层，利用金属层1(M1)形成；源极线SL2位于第二配线层，利用金属层2(M2)形成。金属层2(M1)位于金属层1(M2)上方。源极线SL1耦接于第一可变阻抗单元106，源极线SL2耦接于第二可变阻抗单元206。图中可见的为源极线SL1与源极线SL2的截面，其在垂直方向上的投影至少有一部分重叠，并且源极线SL1与源极线SL2与位线BL空间方向上平行。
本发明的另一个实施例为一种电子设备，其采用上述实施例的集成电路。其集成电路包括多个集成电路单元和多条源极线，其中，多条源极线包括位于不同层的第一源极线与第二源极线，第一源极线与第二源极线位于不同配线层，集成电路单元耦接至第一源极线或所述第二源极线。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局 限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种集成电路，包括：多个集成电路单元和多条源极线，其中，所述多条源极线包括位于不同层的第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层，所述集成电路单元耦接至所述第一源极线或所述第二源极线。
  2. 根据权利要求1所述的集成电路，所述的集成电路为存储器，所述的存储器包括：多个存储单元和多条源极线，其中，所述多条源极线包括位于不同层的第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层，所述存储单元耦接至所述第一源极线或所述第二源极线。
  3. 根据权利要求2所述的集成电路，其中，所述的存储器为电阻式随机存取存储器，所述存储单元为以行列方向排列的多个电阻式存储记忆胞，所述的电阻式存储记忆胞包括可变阻抗单元和与所述可变阻抗单元耦接的开关单元，所述源极线包括第一源极线与第二源极线，所述第一源极线与所述第二源极线位于不同配线层。
  4. 根据权利要求3所述的集成电路，所述的第一源极线位于第一配线层，所述的第二源极线位于所述第一配线层上层的第二配线层。
  5. 根据权利要求1至4任一项所述的集成电路，其中，至少一条所述第一源极线与对应的所述第二源极线在垂直方向上的投影至少有一部分相重叠。
  6. 根据权利要求2-4任一项所述的集成电路，其中，在垂直方向上的投影至少有一部分相重叠的所述第一源极线与所述第二源极线分别耦接至位于所述第一源极线与所述第二源极线的不同侧的所述存储单元。
  7. 根据权利要求1至4任一项所述的集成电路，其中，各个所述源极线与字线空间方向上垂直，各个所述的源极线与位线在空间方向上平行。
  8. 根据权利要求4所述的集成电路，位线位于所述第二配线层上层的第三配线层。
  9. 根据权利要求1至4任一项所述的集成电路，其中，所述第一源极线通过N组接触栓塞及N-1组底联结平台与基板电连接，所述第二源极线通过M组接触栓塞及M-1组底联结平台与基板电连接，其中，M大于N。
  10. 一种电子设备，包括权利要求1-9任一项所述的集成电路。
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